Method for automatically generating multi-level model in real time
By automatically generating multi-level model methods in real-time, the problem of untimely model updates and slow simulation speed in digital-analog hybrid chip simulation is solved, the model and circuit schematic matching is achieved, the simulation speed and accuracy are improved, the diverse verification needs are met, and the R&D costs are reduced.
Patent Information
- Application Number
- CN202510403074.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-01
- Publication Date
- 2025-07-18
AI Technical Summary
In the large-scale digital-to-analog hybrid chip simulation, the existing technology has problems such as slow simulation speed, untimely model updates, mismatch between the model and the circuit schematic, and difficulty in meeting the needs of variable verification.
Provide a real-time automatic generation of multi-level models. By configuring the hierarchy type of the model for the object selected by the user, setting the modeling time node, checking the pin range and accuracy, and generating the model for simulation as needed, ensuring that the model matches the latest circuit schematic, and dynamically adjusting the model type and accuracy to meet different simulation needs.
Significantly improve simulation speed, ensure model accuracy, reduce R&D costs, meet diversified verification needs, and shorten R&D cycle.
Smart Images
Figure CN120337853A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of Electronic Design Automation (EDA) technology, and particularly to a method for real-time automatic generation of multi-level models. Background Art
[0002] With the rapid development of technology, the rise of emerging technologies such as artificial intelligence, 5G communication, data centers, autonomous driving, biomedicine, and humanoid robots has led to an increasingly diverse demand for integrated circuits, and the complexity of their design has also been continuously increasing. This trend not only greatly increases the design difficulty but also poses more stringent requirements for large-scale simulation.
[0003] Especially in the fields of mixed-signal chips, large-scale storage chips, and analog chips such as high-precision and high-speed, as the chip scale expands day by day, the speed problem of mixed-signal simulation becomes increasingly prominent. Especially when the circuit contains high-frequency oscillation modules such as OSC (oscillator) and PLL (phase-locked loop), the simulation process becomes extremely slow. In addition, the design complexity of modern chips is extremely high. The number of MOS transistors in some modules even exceeds 10k, and it may take hundreds or even about 20k simulation cycles to complete a specific function. At the same time, various modes such as the control, calibration, and DFT (Design for Testability) of mixed-signal interaction make the chip configuration modes reach more than a hundred, or even 300 - 400. Such complex mixed-signal configurations are extremely likely to cause errors in chip design.
[0004] In the current mixed-signal simulation method, if the analog part is completely simulated using circuit schematics, the simulation speed will be severely affected; if the Model Based verification method is used, an accurate model needs to be established and it is necessary to ensure that the model can accurately reflect the behavior of the circuit schematic. However, in actual operation, the following problems exist:
[0005] 1. In large mixed-signal SOCs, modules such as OSC, PLL, and GPIO are common modules, but they seriously slow down the simulation speed. In addition, the current Verilog models (.v files), VerilogAMS models (.vams files), and SystemVerilog simulations (.sv files) are usually generated manually, making it difficult to ensure complete matching with the circuit schematic (Schematic). When the circuit design is updated, the model (Model) often cannot be updated in a timely manner. As a result, it may not even meet the matching of Schematic and Model; when the circuit design is updated, the Model may not be updated accordingly; even problems such as mismatches between the pins of the circuit diagram (pin) and the pins of the model (Model Pin) may occur.
[0006] 2. Due to the different contents to be verified, for the content to be established by the Model, in different simulations, the concerned parameters are also different. Currently, only a single type of Model is established, which is difficult to meet the changing verification requirements and changes, and to cope with various simulation challenges. Summary of the Invention
[0007] To solve the defects of the prior art, the purpose of this application is to provide a method for real-time automatic generation of multi-level models. Aiming at the defects existing in the prior art, by real-time automatic generation of multi-level models, the simulation speed is improved and diverse verification requirements are met.
[0008] To achieve the above purpose, the method for real-time automatic generation of multi-level models provided by this application is used for modeling, simulation, formal verification and hardware acceleration of general analog chips, mixed-signal chips, multi-core heterogeneous chips or panels, and includes the following steps:
[0009] Configure the hierarchical type of the model for the object selected by the user, where the object is a functional module of a chip or a panel;
[0010] Set the start and end time nodes required for object modeling;
[0011] Check the input and output ranges or accuracies of the power supply, input and output pins of the selected object, and perform a pre-set behavior selection for the power supply, input and output pins that exceed the set range or accuracy;
[0012] Generate the model of the object according to the selected hierarchical type, at the start and end time nodes of modeling, and perform object simulation.
[0013] Further, the chip includes: general analog chips, mixed-signal chips, multi-core heterogeneous chips.
[0014] Further, the hierarchical type of the model includes: Verilog-A model, Verilog-AMS model, SystemVerilog model, Real Number Model model, Verilog model, simplified circuit diagram, C model, Protocol model, Critical Part Model.
[0015] Further, the simulation includes the simulation of the object itself, the simulation of the subsystem where the object is located, the simulation of the TOP circuit where the object is located, and the simulation of the test cases of the object;
[0016] Set the start and end time nodes required for object modeling.
[0017] Further, the step of configuring the hierarchical type of the model for the object selected by the user further includes configuring the hierarchical type of the model for the object selected by the user through the hierarchical type variable.
[0018] Further, the step of setting the start and end time nodes required for object modeling further includes
[0019] setting the start time node and end time node of the waveform required for modeling according to the start time variable and stop time variable set by the user;
[0020] when the start time variable is 1, start recording the waveform values of each pin;
[0021] when the end time variable is 1, stop recording the waveform values of each pin.
[0022] Further, the step of checking the input / output range or accuracy of the power supply, input pins, and output pins of the selected object further includes
[0023] checking the input range or accuracy of the power supply pin according to the model power check variable set by the user;
[0024] checking the input range or accuracy of the input signal according to the model input check variable set by the user;
[0025] determining the normal operating range of the output signal according to the model output requirement variable set by the user.
[0026] Even further, the step of performing a pre-set behavior selection on the power supply pins, input pins, and output pins that exceed the set range or accuracy further includes
[0027] setting the behavior selection when the input / output range or accuracy of the power supply pins, input pins, and output pins is not within the normal operating range according to the model constraint variable set by the user;
[0028] The behavior selection includes outputting a warning, an error, and / or terminating.
[0029] To achieve the above object, the present application further provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor is configured to execute the computer program stored in the memory to implement the steps of the real-time automatic generation of a multi-level model method as described above.
[0030] To achieve the above object, the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is loaded and executed by a processor to implement the steps of the real-time automatic generation of a multi-level model method as described above.
[0031] The method for real-time automatic generation of multi-level models provided by this application has the following advantages and positive effects compared with the prior art:
[0032] 1) Meeting the needs of diversified automatic modeling: By generating a Model that matches the simulation requirements in real time, the time-consuming process of manually generating models is avoided. By generating models of different levels and types, various changing verification requirements and various simulation challenges can be met.
[0033] 2) Ensuring model accuracy: Since the model is generated based on the latest circuit schematic diagrams and simulation data, the accuracy of the model can be ensured.
[0034] 3) Significantly improving simulation speed: Through the method for real-time automatic generation of multi-level models, the model type and accuracy can be dynamically adjusted according to requirements, thereby accelerating the simulation speed.
[0035] 4) Reducing R & D costs: By accelerating the simulation speed and ensuring model accuracy, the R & D cycle can be shortened and the R & D costs can be reduced.
[0036] Other features and advantages of this application will be described in the subsequent specification, and partly will be obvious from the specification, or will be understood by implementing this application. Brief Description of the Drawings
[0037] The drawings are used to provide a further understanding of this application, and constitute a part of the specification. Together with the embodiments of this application, they are used to explain this application and do not constitute a limitation to this application. In the drawings:
[0038] Figure 1 It is a flowchart of the method for real-time automatic generation of multi-level models according to an embodiment of this application;
[0039] Figure 2 It is a schematic diagram of the start and end time nodes of the waveform required for setting modeling configuration according to an embodiment of this application;
[0040] Figure 3 It is a schematic diagram of the variables and configuration of real-time automatic generation of multi-level Model according to an embodiment of this application;
[0041] Figure 4 It is a schematic diagram of the table configuration of real-time automatic generation of multi-level Model according to an embodiment of this application;
[0042] Figure 5 It is a schematic diagram of modeling the LDO low-dropout linear regulator circuit according to an embodiment of this application;
[0043] Figure 6 It is a schematic diagram of modeling the OSC oscillator circuit according to an embodiment of this application;
[0044] Figure 7 Schematic diagram for modeling when there is a state machine inside the chip according to an embodiment of the present application;
[0045] Figure 8 Schematic diagram of Model table configuration when there is a state machine inside the chip according to an embodiment of the present application;
[0046] Figure 9 Schematic diagram of the structure of an electronic device according to an embodiment of the present application. Detailed implementation manners
[0047] The preferred embodiments of the present application will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application.
[0048] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to more thoroughly and completely understand the present application. It should be understood that the drawings and embodiments of the present application are only for exemplary purposes and are not used to limit the protection scope of the present application.
[0049] The term "including" and its variations used herein are open-ended, that is, "including but not limited to". The term "based on" is "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.
[0050] It should be noted that the concepts such as "first" and "second" that may be mentioned in the present application are only used to distinguish different devices, components or parts, and are not used to limit the order or interdependence of the functions performed by these devices, components or parts.
[0051] It should be noted that the modifications of "one" and "multiple" that may be mentioned in the present application are illustrative rather than restrictive. Those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more". "Multiple" should be understood as two or more.
[0052] It should be noted that the chips mentioned in the present application can be analog chips, general analog chips, digital-analog hybrid chips, multi-core heterogeneous chips, etc.
[0053] Embodiment 1
[0054] In the method for real-time automatic generation of a multi-level model according to an embodiment of the present application, for a digital-analog hybrid chip, if all analog parts adopt a power supply schematic diagram, it will lead to very slow simulation. If a Model is adopted, it may lead to insufficient accuracy within the concerned range, or errors caused by untimely update of the Model itself. In the present application, each time a Model is automatically generated, the most direct and latest circuit schematic diagram and its corresponding simulation are used, and the data obtained is used to generate the Model. Then the Model will be very correct, and there is no need to perform Model Validation (model verification) on the circuit schematic diagram and the Model. The Model can always be updated following the latest design, making the Schematic and the Model match, and improving the accuracy of the simulation.
[0055] In the method for real-time automatic generation of a multi-level model according to an embodiment of the present application, different levels of Models are established according to different verification purposes. For example, for OSC / PLL / GPIO, etc., the establishment and generation of Models at different levels are solved. A dynamic Netlist simulation system is established, enabling different config views to be used in the same simulation. Thus, within the concerned range, the most accurate schematic view is adopted; when speed needs to be improved, other Models are adopted, such as.v model,.vams model,.sv model, real number model (RNM), etc. Different Models are automatically generated according to different verification purposes, forming Models with different parameters and accuracies, thereby greatly improving the simulation efficiency, significantly reducing the R & D cost, effectively shortening the R & D cycle, and improving the R & D quality.
[0056] Figure 1 For the flowchart of the method for real-time automatic generation of a multi-level model according to an embodiment of the present application, the method for real-time automatic generation of a multi-level model of the present application will be described in detail below with reference to Figure 1 ...
[0057] First, in step 101, the level type of the model is configured for the object selected by the user.
[0058] In the embodiment of the present application, the object selected by the user is a functional module of a chip or a panel, such as a functional module of a chip or a panel like an analog chip, a general analog chip, a digital-analog hybrid chip, a multi-core heterogeneous chip, etc.
[0059] It is understandable that the user can select one or more objects simultaneously, configure the hierarchical types of the model for multiple objects, or configure multiple hierarchical types of the model for a selected object, forming Models with different parameters and precisions, and dynamically adjust the model type and precision according to requirements, thereby accelerating the simulation speed. In the embodiments of the present application, the functional modules of the chip or panel may be: functional modules related to power-on, functional modules related to power supply, functional modules related to clock, functional modules related to signal processing, functional modules related to data processing, functional modules related to signal conversion, functional modules related to storage, functional modules related to communication, functional safety modules, monitoring and protection functional modules, etc., and also include any other functional modules in SOC, general simulation, digital-analog hybrid, and multi-core heterogeneous,
[0060] It also includes any other functional modules in SOC, general simulation, digital-analog hybrid, and multi-core heterogeneous.
[0061] In the embodiments of the present application, the functional modules selected by the user are received, and the hierarchical type of the model is configured through the hierarchical type variable $emy_model_type.
[0062] In the embodiments of the present application, the hierarchical types of the model include: Verilog-A model, Verilog-AMS model, SystemVerilog model, Real Number Model model, Verilog model, simplified circuit diagram, C model, Protocol model, Critical Part Model.
[0063] In step 102, the start and end time nodes required for object modeling are set.
[0064] In the embodiments of the present application, the start and end time nodes required for object modeling are set by setting the start and end time nodes of the waveform required for modeling. As Figure 2 shown, the start and end time nodes required for object modeling are controlled by setting the start time variable $emy_model_start and the end time variable $emy_model_stop respectively. When these variables are set to 1, it means starting or stopping recording the waveform values of each pin. Through this setting, the waveform of the time period required for actual simulation can be established, and for other non-essential waveforms, there is no need to pay attention. For periodic or modules that need to depend on the previous moment / previous input, by reasonably configuring this parameter and controlling the start and end time nodes, various internal requirements such as the corresponding time period and state machine can be ensured to be transmitted to the final output waveform of the modeling.
[0065] In step 103, check the input / output range or accuracy of the power pins, input pins, and output pins of the selected object.
[0066] In the embodiment of the present application, first, set the input / output normal operating range requirements or accuracy of the power supply VDD and ground GND through the model power check variable $emy_model_supply_check to ensure that the model outputs signals normally when it meets the specifications.
[0067] In the embodiment of the present application, set the input range requirements or accuracy of all input signals through the model input check variable $emy_model_input_check to ensure that input signals such as the En signal, Vref voltage, and lbias current meet the model specifications.
[0068] In the embodiment of the present application, set the normal operating range requirements or accuracy of the output signal through the model output requirement variable $emy_model_output_requirement, such as the lout output range of the LDO module, to ensure that Vout can output normally under specific conditions.
[0069] In step 104, perform a preset behavior selection for the power pins, input pins, and output pins that exceed the set range or accuracy.
[0070] In the embodiment of the present application, it is also set through the model constraint variable $emy_model_violation_option to determine the behavior selection when the power supply, input signal, or output signal does not meet the normal operating range requirements, including options such as "output warning", "error", or "terminate". In the embodiment of the present application, according to the variables $emy_model_supply_check, $emy_model_input_check, and $emy_model_output_requirement set by the user, check whether the power supply, input signal, or output signal is within the normal operating range or accuracy. If not, then generate "output warning", "error", or "terminate" behavior actions according to the variable $emy_model_violation_option set by the user.
[0071] Figure 3 For real-time automatic generation of a multi-level Model variable and configuration schematic diagram according to the embodiment of the present application, Figure 4 For real-time automatic generation of a multi-level Model table configuration schematic diagram according to the embodiment of the present application, such as Figure 3 and 4As shown, to ensure the rapid establishment of a Model, for modules that need to establish Models of types such as.vams and.sv, when setting the Model, it is necessary to fill in the relevant pin modeling information (if only establishing a.va model, since it is all of the electrical type, there is no need to fill in the Port Type column; if only establishing a.v model, since it is all of the digital type, there is also no need to fill in the Port Type column); especially for signals that are intended to be established as digital, special definitions need to be made. At the same time, through the "Range" module, the Spec of this Block is converted into code; or some requirements are converted into conditions. For example Figure 4 As described, if the module for which the model is being established has "parameter", etc. in the circuit diagram, then during modeling, just "copy" it over. If there is any other information that needs to be specially explained, fill it in at the bottom of the table. The EDA tool will incorporate this information during the automatic modeling process.
[0072] In step 105, a model of the object is generated for object simulation.
[0073] In the embodiment of the present application, in chip simulation, according to the user's settings, Models with different parameters and precisions can be automatically generated in different hierarchical simulations, enabling the Model to be updated following the latest design.
[0074] Embodiment 2
[0075] In the embodiment of the present application, taking the modeling of an LDO low-dropout linear regulator circuit as an example, the method for real-time automatic generation of multi-level models of the present application will be described in detail.
[0076] Figure 5 For the modeling schematic diagram of an LDO low-dropout linear regulator circuit according to the embodiment of the present application, as Figure 5 shown, the LDO low-dropout linear regulator circuit mainly includes 7 Pin pins: VDD, GND, EN, Vref, Ibias, Trim_v[3:0], and Vout. Since the establishment of the LDO low-dropout linear regulator circuit Model is mainly used after the POC signal of the entire SOC and the complex analog circuit power supply arrives, the power supply voltage is no longer 0V, and the Model does not need to model the power-on stage process, but focuses on modeling the stable state.
[0077] (1) Information of power supply and ground
[0078] VDD (Supply), voltage range: 1.62V to 1.98V. If outside this range, a Warning will be generated or the simulation will be terminated according to the configuration of $emy_model_violation_option.
[0079] GND (Ground), ground voltage, range: -10mV to 10mV. If outside this range, a Warning will be generated or the simulation will be terminated according to the configuration of $emy_model_violation_option.
[0080] (2) Information of input ports:
[0081] EN (Enable), digital enable terminal, will be established as a digital signal in.v,.vams,.sv in the future, controlling the LDO switch: the input when off is reasonably within -10mV to 40mV; or when enabling the LDO, it should be in the range of 1.5V to 1.98V. If outside this range, a Warning will be generated or the simulation will be terminated according to the configuration of $emy_model_violation_option.
[0082] Vref (Voltage Reference) reference input voltage: electrical type, typical value is 1.2V, allowing a fluctuation of ±0.5%. If outside this range, a Warning will be generated or the simulation will be terminated according to the configuration of $emy_model_violation_option.
[0083] Ibias (Current Bias), bias current, electrical type, typical value: 1uA. Allowing a fluctuation of ±0.5%. If outside this range, a Warning will be generated or the simulation will be terminated according to the configuration of $emy_model_violation_option.
[0084] Trim_v[3:0] (Trimming), Trim signal, so it is set to Digital type; its input range is the same as that of the EN signal, and the adjustment range is -10mV to 40mV or 1.5V to 1.98V. If outside this range, a Warning will be generated or the simulation will be terminated according to the configuration of $emy_model_violation_option.
[0085] (3) Output information:
[0086] Vout (Output Voltage), which is of the electrical type; the output voltage Vout is determined by the input but affected by the output current Iout. When Iout is within the range of 0 to 50 mA, the Vout output is normal. If it exceeds this range, a Warning will be generated or the simulation will be terminated according to the configuration of $emy_model_violation_option. When the circuit is being simulated, it can obtain the output voltage value of Vout, and this simulation result serves as the waveform generated by automatic modeling.
[0087] The power consumption of the entire module will be determined by the average value of the power consumption generated between $emy_model_start and $emy_model_stop or by the value obtained after determining the config values such as the final Trim_v code, and this value will be used as the numerical value for the power consumption modeling of the entire module.
[0088] Embodiment 3
[0089] In the embodiments of the present application, taking the modeling of the OSC oscillator circuit as an example, the method for real-time automatic generation of multi-level models of the present application will be described in detail.
[0090] Figure 6 It is a schematic diagram of the modeling of the OSC oscillator circuit according to the embodiments of the present application. As Figure 6 shown, the OSC oscillator circuit includes 7 main Pin pins: VDD, GND, EN, Vref, Ibias, and Trim_v[3:0], and CLK_O. Since the establishment of the OSC oscillator circuit Model is mainly used after the arrival of the power-on POC signal of the entire SOC / complex analog circuit, the power supply voltage is no longer 0V, and the Model does not need to model the power-on stage process, but focuses on modeling the stable state. Moreover, since the oscillator is a periodic square wave after power-on and stabilization, it is necessary to set $emy_model_start and $emy_model_stop to an integer number of cycles.
[0091] (1) Information about power supply and ground
[0092] VDD (Supply), voltage range: 1.62V to 1.98V. If it exceeds this range, a Warning will be generated or the simulation will be terminated according to the configuration of $emy_model_violation_option.
[0093] GND (Ground), the ground voltage, range: -10 mV to 10 mV. If it exceeds this range, a Warning will be generated or the simulation will be terminated according to the configuration of $emy_model_violation_option.
[0094] (2) Information of the input port:
[0095] EN (Enable), the digital enable terminal, which will be established as a digital signal in.v,.vams,.sv in the future to control the LDO switch: the input when it is off is reasonably within -10 mV to 40 mV; or when the LDO is enabled, it should be in the range of 1.5 V to 1.98 V. If it exceeds this range, a Warning will be generated or the simulation will be terminated according to the configuration of $emy_model_violation_option.
[0096] Vref (Voltage Reference), the reference input voltage: electrical type, the typical value is 1.2 V, allowing a fluctuation of ±0.5%. If it exceeds this range, a Warning will be generated or the simulation will be terminated according to the configuration of $emy_model_violation_option.
[0097] Ibias (Current Bias), the bias current bias, electrical type, the typical value is: 1 μA. Allowing a fluctuation of ±0.5%. If it exceeds this range, a Warning will be generated or the simulation will be terminated according to the configuration of $emy_model_violation_option.
[0098] Trim_clk[3:0] (Trimming), the Trim signal, so it is set to the Digital type; its input range is the same as the EN signal, and the adjustment range is -10mV to 40mV or 1.5V to 1.98V. If it exceeds this range, a Warning will be generated or the simulation will be terminated according to the configuration of $emy_model_violation_option. Since different Trim_clk values will generate different CLK_O output clocks, there are two ways during modeling. One is to traverse Trim_clk between $emy_model_start and $emy_model_stop to obtain the steady-state frequency of CLK under different Trim codes; the other approach is to refer to the Block-level simulation results, establish a mathematical expression between Trim_clk and the output CLK_O, and finally add the mathematical expression based on the actual simulation results to obtain the true value of the output CLK_O to complete the modeling. This operation can be done by writing the corresponding expression in the "Other" column of the last row of the table.
[0099] (3) Output information:
[0100] CLK_O (Output CLK), which is of the Digital type; the output voltage Vout is determined by the input but affected by the output current Iout. When Iout is within the range of 0 to 1mA, the CLK_O output is normal. If it exceeds this range, a Warning will be generated or the simulation will be terminated according to the configuration of $emy_model_violation_option. During the circuit simulation, it can obtain the output voltage and frequency information values of CLK_O, and this simulation result is used as the waveform generated by automatic modeling.
[0101] (4) Other information such as module power consumption:
[0102] The power consumption of the entire module will be the average value of the power consumption generated between $emy_model_start and $emy_model_stop or the value obtained after determining the config values such as the final Trim_v code as the value for modeling the power consumption of the entire module.
[0103] Example 4
[0104] In the embodiments of this application, if there is other information that needs to be specifically explained, the user needs to fill it in at the bottom of the table as shown in Figure 4 The EDA tool will incorporate this information during the automatic modeling process.
[0105] Figure 7Schematic diagram for modeling when there is a state machine inside the chip according to an embodiment of the present application Figure 8 Schematic diagram for configuring the Model table when there is a state machine inside the chip according to an embodiment of the present application, as Figure 8 shown, in some modules, just having the input Pin information still cannot determine the output signal information, because there is a state machine designed inside the chip, etc. By storing the signals related to the state machine, converting them into digital signals, writing the states as expressions, and filling them in the Figure 3 "Other" part. As Figure 7 shown, in this module, there are four states: State0, State1, State2, and State3; when State0 encounters the signal M3, it enters State1; when it encounters the signal M1, it enters State3; when it encounters the signal M2, it enters State2, etc. And State3 remains in the State3 state after encountering the M1 signal. Therefore, when processing these modules, it is necessary to save these state information State0, State1, State2, State3 and the M1, M2, M3 signals; M1 is generated when node0 is at a low level and node1 is at a high level, M2 is generated when node0 is at a high level and node1 is at a low level, and M3 is generated when node0 and node1 are both at a high level. The description is established as Figure 8 shown and filled in the Figure 4 "Other" and then used during modeling.
[0106] Embodiment 5
[0107] In an embodiment of the present application, an electronic device is further provided. Figure 9 Schematic diagram of the structure of the electronic device according to an embodiment of the present application, as Figure 9 shown, the electronic device of the present application includes a processor 901 and a memory 902, where
[0108] the memory 902 stores a computer program, and when the computer program is read and executed by the processor 901, it executes the steps in the above-mentioned embodiment of the method for real-time automatic generation of multi-level models.
[0109] Embodiment 6
[0110] In an embodiment of the present application, a computer-readable storage medium is further provided. The computer-readable storage medium stores a computer program, where the computer program is configured to execute the steps in the above-mentioned embodiment of the method for real-time automatic generation of multi-level models when running.
[0111] In this embodiment, the computer-readable storage medium may include, but is not limited to: various media such as USB flash drives, read-only memory (ROM for short), random access memory (RAM for short), mobile hard disks, magnetic disks, or optical discs that can store computer programs.
[0112] Those of ordinary skill in the art can understand that the foregoing is only a preferred embodiment of the present application and is not used to limit the present application. Although the present application has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A method for real-time automatic generation of a multi-level model, which is used for modeling, simulation, formal verification and hardware acceleration of general simulation chips, mixed-signal chips, multi-core heterogeneous chips or panels, characterized in that Including the following steps: Configuring the hierarchical type of the model for the object selected by the user, where the object is a functional module of a chip or a panel; Setting the start and end time nodes required for object modeling; Checking the input / output range or accuracy of the power supply, input, and output pins of the selected object, and performing a preset behavior selection on the power supply, input, and output pins whose range or accuracy exceeds the set values; Generating the model of the object according to the selected hierarchical type at the start and end time nodes of modeling, and performing object simulation.
2. The method for real-time automatic generation of a multi-level model according to claim 1, wherein The chip includes: general analog chip, mixed-signal chip, multi-core heterogeneous chip.
3. The method for real-time automatic generation of a multi-level model according to claim 1, wherein The hierarchical types of the model include: Verilog-A model, Verilog-AMS model, SystemVerilog model, RealNumber Model model, Verilog model, simplified circuit diagram, C model, Protocolmodel, CriticalPart Model.
4. The method for real-time automatic generation of a multi-level model according to claim 1, wherein The simulation includes the simulation of the object itself, the simulation of the subsystem where the object is located, the simulation of the TOP circuit where the object is located, and the simulation of the test cases of the object; Setting the start and end time nodes required for object modeling.
5. The method for real-time automatic generation of a multi-level model according to claim 1, characterized in that The step of configuring the hierarchical type of the model for the object selected by the user further includes configuring the hierarchical type of the model for the object selected by the user through a hierarchical type variable.
6. The method for real-time automatic generation of a multi-level model according to claim 1, wherein The step of setting the start and end time nodes required for object modeling further includes Setting the start time node and end time node of the waveform required for modeling according to the start time variable and stop time variable set by the user; When the start time variable is 1, start recording the waveform values of each pin; When the end time variable is 1, stop recording the waveform values of each pin.
7. The method for real-time automatic generation of a multi-level model according to claim 1, wherein The step of checking the input / output range or accuracy of the power supply, input pins, and output pins of the selected object further includes Checking the input range or accuracy of the power supply pin according to the model power check variable set by the user; Checking the input range or accuracy of the input signal according to the model input check variable set by the user; Determining the normal operating range of the output signal according to the model output requirement variable set by the user.
8. The method for real-time automatic generation of a multi-level model according to claim 1, wherein The step of performing a preset behavior selection on the power supply pins, input pins, and output pins whose range or accuracy exceeds the set values further includes Setting the behavior selection when the input / output range or accuracy of the power supply pins, input pins, and output pins is not within the normal operating range according to the model constraint variable set by the user; The behavior selection Includes outputting warnings, errors, and / or terminating.
9. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor is used to execute the computer program stored in the memory to implement the steps of the real-time automatic generation of multi-level model method according to any one of claims 1-8.
10. A computer-readable storage medium, characterized in that, The computer program is stored in the storage medium, and the computer program is loaded and executed by the processor to implement the steps of the real-time automatic generation of multi-level model method according to any one of claims 1-9.