A memristor neural network circuit based on a competitive learning mechanism

Abstract

The application discloses a kind of memristor neural network circuit based on competition learning mechanism, it includes forward calculation module and reverse adjustment module.Wherein, forward calculation module is composed of memristor cross array module and leakage integral and discharge module, and reverse adjustment module is composed of weight adjustment module.Forward calculation module realizes the transverse inhibition and competition activation between two neurons by winner-takes-all algorithm, and only one neuron competes successfully and then generates output signal for each input.Reverse adjustment module carries out neuron weight adjustment by Hebb learning rule, realizes self-learning, it receives the output signal of forward calculation module, then generates adjustment signal to forward calculation module, and adjusts the weight of winning neuron.Therefore, the memristor neural network circuit based on competition learning mechanism proposed in the application can learn input data, and classify input data after learning is completed.

Description

Technical Field

[0001] This invention relates to the field of memristor neural network circuit design, and particularly to a memristor neural network circuit based on a competitive learning mechanism. Background Technology

[0002] As an important branch of artificial neural networks, competitive learning neural networks simulate the competitive activation and self-learning behavior of neurons in biological neural networks. Competitive learning consists of two parts: forward computation and backward adjustment. The forward computation part achieves competitive activation through a winner-takes-all algorithm, while the backward adjustment part adjusts neuron weights using the Hebbian learning rule to achieve self-learning. Through these competitive activation and self-learning characteristics, competitive neural networks can effectively reveal hidden structures in data and are applicable to applications such as data classification, pattern recognition, and feature compression.

[0003] The winner-takes-all algorithm borrows from the lateral inhibition and competitive activation mechanisms in biological neural networks. The algorithm's working principle is as follows: Figure 1 As shown, neurons in the competitive layer possess lateral inhibition, which suppresses the output of other neurons, allowing only one neuron to win and output at a time. Because each input data point contains different features and the weights of the synapses vary, the responses of each neuron differ. For example, for the same input, if neuron 2's response speed is higher than neuron 4's, neuron 2 will reach its firing threshold first and suppress neuron 4's output through lateral inhibition; therefore, only neuron 2 will successfully compete and produce an output. Conversely, if neuron 4's response speed is higher than neuron 2's, only neuron 4 will successfully compete and produce an output.

[0004] The Hebb learning rule applies to weight adjustment in neural networks. The rule is as follows: two neurons are connected by a synapse, and the synapse has a weight. When both neurons are active, the weight increases; when the first neuron is inactive and the second neuron is active, the weight decreases; when the second neuron is inactive, the weight remains unchanged regardless of whether the first neuron is active.

[0005] Traditional computers employ the von Neumann architecture, which separates in-memory computing from storage. Frequent data transfers between storage and computing units result in high latency and high power consumption. Furthermore, current semiconductor technology is approaching its physical limits, slowing the rate of increase in computer performance. Therefore, neural networks implemented in computer software face limitations. Neural network hardware circuits that simulate the biological brain can achieve in-memory computing, enabling efficient information processing and adaptive learning. They offer advantages such as low power consumption, high parallelism, and real-time processing, overcoming the von Neumann bottleneck.

[0006] Memristor is an ideal device for constructing neural network circuit to simulate the brain of living beings. The resistance of the memristor is plastic, and its resistance changes with the applied electric field. When the direction of the applied electric field is opposite, the resistance of the memristor changes in the opposite direction. The memristor also has the characteristics of nanometer size, low power consumption and compatibility with CMOS transistor, and can be applied to large-scale integrated circuits. Therefore, the neural network circuit based on the memristor has wide application prospects in improving the performance of computers and promoting the development of artificial intelligence.

[0007] The competitive learning mechanism has been widely used in data classification, pattern recognition and feature compression, but most of the current researches use computer software to construct neural networks, and few use hardware circuits to construct neural networks. The hardware of the competitive learning neural network can be realized by the memristor, which can improve the computing efficiency and reduce the energy consumption.

[0008] The present application is based on the plasticity of the resistance of the memristor, and proposes a memristor neural network circuit based on the competitive learning mechanism. Unlike previous researches that realize the competitive learning neural network through software algorithms, the present application realizes the competitive learning neural network through memristor hardware circuit and applies it to data classification, providing a certain reference for the hardware of the memristor neural network circuit. SUMMARY

[0009] The present application proposes a memristor neural network circuit based on the competitive learning mechanism. The plasticity of the resistance of the memristor is used to construct a neural network circuit to simulate the competitive learning mechanism in neurons, and the circuit is used for data classification.

[0010] The present application is realized by the following technical scheme: a memristor neural network circuit based on the competitive learning mechanism, which comprises a forward calculation module and a reverse adjustment module. The forward calculation module is composed of a memristor cross array module and a leaky integration and discharge module, and the reverse adjustment module is composed of a weight adjustment module, as shown in Figure 2 .

[0011] The memristor cross array module receives the output current of the backward leaky integration and discharge module. The memristor cross array module is composed of eight memristors M a1 -M a4 and M b1 -M b4 , and the memristors are arranged in four rows and two columns. Four input signals V in1 -V in4 are connected to the four rows of memristors respectively, and the memristors in the same row receive the same input signal. The memristors generate current after receiving the input signal, and the end current of each column of memristors is the sum of the currents of the four memristors in the column. The resistance of each memristor is different, so the end current of each column is different. The first column of memristors and the leaky integration and discharge module 1 constitute neuron 1, and the second column of memristors and the leaky integration and discharge module 2 constitute neuron 2.

[0012] The leaky integrate-and-fire and spike module includes module 1 and module 2, two modules corresponding to two competing neurons, and their circuit structures are the same, which receive the output current of the crossbar array module of the synaptic weight and then generate output signals V O1 and V O2 . The leaky integrate-and-fire and spike module is composed of NMOS tubes N1-N6, voltage-controlled switches S1, S2, resistors R1-R12, capacitors C1, C2, operational amplifiers A1-A4, voltage comparators COMP1, COMP2 and voltage sources. For module 1, V f and V f1 come from the weight adjustment module and do not participate in the process of forward calculation, and in the forward calculation, V f and V f1 are 0, so NMOS tubes N1 and N2 are turned off, and the 5V voltage source is applied to the positive control end of the voltage-controlled switch S1 through the resistor R1, so that the voltage-controlled switch S1 is turned on, and the end current of the first column of the crossbar array module of the synaptic weight acts on the amplification circuit composed of operational amplifiers A1 and A2, and then a voltage is generated at the output end of the operational amplifier A2, so that an integral voltage is generated on the capacitor C1. Similarly, for module 2, an integral voltage is generated on the capacitor C2. The output of the voltage comparator COMP1 is connected to the gate of the NMOS tube N6 in module 2, and the output of the voltage comparator COMP2 is connected to the gate of the NMOS tube N3 in module 1. If the integral voltage of the capacitor C1 reaches the threshold voltage V th faster than the integral voltage of the capacitor C2, the voltage comparator COMP1 outputs a high level first, so that module 1 generates a high level output signal V O1 and the NMOS tube N6 is turned on, and then the integral voltage of the capacitor C2 is discharged to the ground through the NMOS tube N6, and the voltage comparator COMP2 can only output a low level, that is, the output signal V O2 of module 2 is inhibited to a low level by module 1, which is the process of module 1 winning the competition and generating the output signal V O1 , simulating the mechanism of lateral inhibition and competitive activation of neurons. Similarly, if the integral voltage of the capacitor C2 reaches the threshold voltage V th faster than the integral voltage of the capacitor C1, the voltage comparator COMP2 outputs a high level first, so that module 2 wins the competition and generates the output signal V O2 , and the output signal V O1 of module 1 is inhibited to a low level by module 2.

[0013] The weight adjustment module consists of module 1 and module 2, both of which have the same circuit structure, and they receive the output signals of the leaky integration and discharge module, and then generate the adjustment signals. The weight adjustment module is composed of monostable trigger 74121A-74121F, resistors R13-R24, capacitors C3-C8, voltage-controlled switch S3-S6, summing device SUM1-SUM3, voltage source and absolute value module ABS. In the weight adjustment module 1, monostable trigger 74121A receives the output signal V O1 of the leaky integration and discharge module 1, and it is triggered at the rising edge of V O1 and generates the delay signal V Q1 with the pulse width of t1=0.7*R13*C3. Monostable trigger 74121B receives V Q1 , and it is triggered at the falling edge of V Q1 , and generates the delay signal V Q2 with the amplitude of 6V and the pulse width of t2=0.7*R14*C4 through voltage-controlled switch S3. Monostable trigger 74121C receives V Q2 , and it is triggered at the falling edge of V Q2 , and generates the delay signal V Q3 with the amplitude of -6V and the pulse width of t3=0.7*R15*C5 through voltage-controlled switch S4. V Q2 and V Q3 generate the adjustment signal V f1 after passing through the summing device SUM1. Similarly, the weight adjustment module 2 generates the adjustment signal V f2 . V f1 and V f2 generate the signal V f after passing through the summing device SUM3 and the absolute value module ABS. The signal V f is shared by the leaky integration and discharge modules 1 and 2. If the leaky integration and discharge module 1 wins, the weight adjustment module 1 will generate the output signal V f1 while the weight adjustment module 2 has no output signal V f2 , V f causes the NMOS tubes N1, N2, N4 and N5 in the leaky integration and discharge module to be turned on, and then the voltage-controlled switches S1 and S2 are turned off, so that the leaky integration and discharge modules 1 and 2 stop receiving the input signals from the memristive crossbar array module, the NMOS tubes N2 and N5 provide the discharge channels for the capacitors C1 and C2, and the adjustment signal V f1The negative end of the first column of memristors is applied with the adjustment signal, thus the voltage across the memristors changes. The inverse of the resistance of the memristor represents the weight, and when the voltage exceeds the positive threshold of the memristor, the resistance of the memristor decreases, i.e. the weight increases; when the voltage exceeds the negative threshold of the memristor, the resistance of the memristor increases, i.e. the weight decreases. The negative end of the second column of memristors is not applied with the adjustment signal, thus the memristors do not change, i.e. the weights do not change. Similarly, if the leaky integrate-and-fire module 2 wins, the weight adjustment module 2 will generate an output signal V f2 and the weight adjustment module 1 does not generate an output signal V f1 Thus, only the resistance of the memristors in the second column changes. When the resistance of all the memristors reaches a steady state, i.e. the resistance reaches a maximum or a minimum, it means that the learning of the memristive neural network circuit is completed. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 The schematic diagram of the winner-takes-all algorithm.

[0015] Figure 2 The memristive neural network circuit based on the competitive learning mechanism.

[0016] Figure 3 The shape diagram of two iris flowers.

[0017] Figure 4 The data distribution diagram of two iris flowers.

[0018] Figure 5 The initial resistance diagram of the memristor.

[0019] Figure 6 The simulation diagram of the input signal.

[0020] Figure 7 The simulation diagram of the capacitor voltage and the output signal.

[0021] Figure 8 The voltage simulation diagram of the second column of memristors.

[0022] Figure 9 The resistance change diagram of the second column of memristors.

[0023] Figure 10 The memristor resistance diagram after the training is completed.

[0024] Figure 11 The simulation diagram of the capacitor voltage and the output signal after the iris virginica data is input.

[0025] Figure 12 The simulation diagram of the capacitor voltage and the output signal after the iris virginica data is input. DETAILED DESCRIPTION

[0026] In order to make the technical solutions, objectives and advantages of the present application clearer and more explicit, the present application will be further described in detail below with reference to the drawings.

[0027] As shown in Figure 2 , the present application provides a memristor neural network circuit based on a competitive learning mechanism, which comprises a forward calculation module and a backward adjustment module. The forward calculation module is composed of a memristor cross array module and a leaky integration and discharge module, and the backward adjustment module is composed of a weight adjustment module. The circuit can be used for data classification after training.

[0028] As shown in Figure 2 , the memristor cross array module is composed of memristors M a1 -M a4 and M b1 -M b4 . The positive terminals of the memristors M a1 and M b1 are connected in parallel and connected to node 1 with the input signal V in1 , the positive terminals of the memristors M a2 and M b2 are connected in parallel and connected to node 2 with the input signal V in2 , the positive terminals of the memristors M a3 and M b3 are connected in parallel and connected to node 3 with the input signal V in3 , the positive terminals of the memristors M a4 and M b4 are connected in parallel and connected to node 4 with the input signal V in4 , the negative terminals of the memristors M a1 -M a4 are connected in parallel and connected to node 5 with the input end of the voltage-controlled switch S1, and the negative terminals of the memristors M b1 -M b4 are connected in parallel and connected to node 6 with the input end of the voltage-controlled switch S2. The adjustment signal V f1 is connected to node 5, and the adjustment signal V f2 is connected to node 6.

[0029] As shown in Figure 2 , the leaky integration and discharge module is composed of NMOS tubes N1-N6, voltage-controlled switches S1 and S2, resistors R1-R12, capacitors C1 and C2, operational amplifiers A1-A4, voltage comparators COMP1 and COMP2, and a voltage source. The source of the NMOS tube N1 is grounded, the gate of the NMOS tube N1 is connected to the signal V f , one end of the resistor R1 and the positive control end of the voltage-controlled switch S1 are connected in parallel to node 7 and connected to the drain of the NMOS tube N1, the other end of the resistor R1 is connected to the positive end of the 5V voltage source, the negative end of the 5V voltage source is grounded, and the negative control end of the voltage-controlled switch S1 is grounded. The memristor Ma1 The negative end of the voltage source V a4 is connected to node 5 in parallel with the input end of the voltage-controlled switch S1, the output end of the voltage-controlled switch S1 and one end of the resistor R2 are connected to node 8 in parallel and connected to the inverting input end of the operational amplifier A1, the non-inverting input end of the operational amplifier A1 is grounded, the other end of the resistor R2 and one end of the resistor R3 are connected to node 9 in parallel and connected to the output end of the operational amplifier A1. The other end of the resistor R3 and one end of the resistor R4 are connected to node 10 in parallel and connected to the inverting input end of the operational amplifier A2, the non-inverting input end of the operational amplifier A2 is grounded. The other end of the resistor R4, one end of the resistor R5 and the drain of the NMOS transistor N2 are connected to node 11 in parallel and connected to the output end of the operational amplifier A2. The source of the NMOS transistor N2 is grounded, the gate of the NMOS transistor N2 is connected to the signal V f . The source of the NMOS transistor N3 is grounded, the gate of the NMOS transistor N3 is connected to node 20 with one end of the resistor R12; the other end of the resistor R5, the drain of the NMOS transistor N3 and one end of the capacitor C1 are connected to node 12 in parallel and connected to the non-inverting input end of the voltage comparator COMP1; the inverting input end of the voltage comparator COMP1 is connected to the voltage source V th , the positive power supply pin of the voltage comparator COMP1 is connected to the 6V voltage source, the negative power supply pin of the voltage comparator COMP1 is grounded, one end of the resistor R6 and the gate of the NMOS transistor N6 are connected to node 13 in parallel and connected to the output end of the voltage comparator COMP1, the output end of the voltage comparator COMP1 outputs the signal V O1 . The source of the NMOS transistor N4 is grounded, the gate of the NMOS transistor N4 is connected to the signal V f , one end of the resistor R7 and the positive control end of the voltage-controlled switch S2 are connected to node 14 in parallel and connected to the drain of the NMOS transistor N4, the other end of the resistor R7 is connected to the positive end of the 5V voltage source, the negative end of the 5V voltage source is grounded, and the negative control end of the voltage-controlled switch S2 is grounded. The memristor M b1 -M b4the negative end of the voltage source V f is connected to the node 6, the output end of the voltage-controlled switch S2 and one end of the resistor R8 are connected to the node 15 in parallel and are connected to the inverting input end of the operational amplifier A3, the non-inverting input end of the operational amplifier A3 is grounded, the other end of the resistor R8 and one end of the resistor R9 are connected to the node 16 in parallel and are connected to the output end of the operational amplifier Al. The other end of the resistor R9 and one end of the resistor R10 are connected to the node 17 in parallel and are connected to the inverting input end of the operational amplifier A4, the non-inverting input end of the operational amplifier A4 is grounded, the other end of the resistor R10, one end of the resistor R11 and the drain of the NMOS transistor N5 are connected to the node 18 in parallel and are connected to the output end of the operational amplifier A4. The source of the NMOS transistor N5 is grounded, the gate of the NMOS transistor N5 is connected to the signal V th . O2 .

[0030] As shown in Figure 2 , the weight adjustment module is composed of monostable trigger 74121A-74121F, resistors R13-R24, capacitors C3-C8, voltage-controlled switches S3-S6, summing devices SUM1-SUM3, voltage sources and absolute value module ABS. The signal V O1 is connected to the B pin of the monostable trigger 74121A, the Al and A2 pins of 74121A are grounded, the V cc pin of 74121A and one end of the resistor R13 are connected to the positive end of the 5V voltage source in parallel to the node 21, the negative end of the 5V voltage source is grounded, the other end of the resistor R13 and one end of the capacitor C3 are connected to the R ext / C ext pin of 74121A to the node 22, the other end of the capacitor C3 is connected to the C extThe Q pin of 74121 A is connected to the positive control terminal of voltage-controlled switch S2, the negative control terminal of voltage-controlled switch S2 is grounded, the input terminal of voltage-controlled switch S2 is connected to the positive terminal of 6V voltage source, the negative terminal of 6V voltage source is grounded, the output terminal of voltage-controlled switch S2 and one end of resistor R13 are connected to the 2-port of summer SUM1 at node 22 in parallel, the other end of resistor R13 is grounded. The A1 and A2 pins of 74121 B are connected to node 22, the B pin of 74121 B is connected to the positive terminal of 5V voltage source, the negative terminal of 5V voltage source is grounded, the V cc The B pin of 74121 B is connected to the positive terminal of 5V voltage source, the negative terminal of 5V voltage source is grounded, the V ext / C ext The C pin of 74121 B is connected to node 23, the other end of capacitor C4 is connected to the C ext The Q pin of 74121 B is connected to the positive control terminal of voltage-controlled switch S3, the negative control terminal of voltage-controlled switch S3 is grounded, the input terminal of voltage-controlled switch S3 is connected to the positive terminal of 6V voltage source, the negative terminal of 6V voltage source is grounded, the output terminal of voltage-controlled switch S3 and one end of resistor R17 are connected to the 2-port of summer SUM1 at node 26 in parallel, the other end of resistor R17 is grounded. The A1 and A2 pins of 74121 C are connected to node 26, the B pin of 74121 C is connected to the positive terminal of 5V voltage source, the negative terminal of 5V voltage source is grounded, the V cc The B pin of 74121 C is connected to the positive terminal of 5V voltage source, the negative terminal of 5V voltage source is grounded, the V ext / C ext The C pin of 74121 C is connected to node 28, the other end of capacitor C5 is connected to the C ext The Q pin of 74121 C is connected to the positive control terminal of voltage-controlled switch S4, the negative control terminal of voltage-controlled switch S4 is grounded, the input terminal of voltage-controlled switch S4 is connected to the positive terminal of -6V voltage source, the negative terminal of -6V voltage source is grounded, the output terminal of voltage-controlled switch S4 and one end of resistor R18 are connected to the 1-port of summer SUM1 at node 29 in parallel, the other end of resistor R18 is grounded, the 3-port of summer SUM1 outputs signal V f1 The B pin of 74121 D is connected to signal V O2 The A1 and A2 pins of 74121 D are grounded, the V cc The B pin of 74121 D is connected to the positive terminal of 5V voltage source, the negative terminal of 5V voltage source is grounded, the V ext / C ext The C pin of 74121 D is connected to node 31, the other end of capacitor C6 is connected to the Cext pin Q of 74121D and one end of resistor R22 are connected to node 32 in parallel with A1 and A2 pins of 74121E, the other end of resistor R22 is grounded. B pin of 74121E is connected to the positive terminal of 5V voltage source, the negative terminal of 5V voltage source is grounded, V cc pin and one end of resistor R20 are connected to node 33 in parallel with the positive terminal of 5V voltage source, the negative terminal of 5V voltage source is grounded, the other end of resistor R20 and one end of capacitor C7 are connected to R ext / C ext pin is connected to node 34, the other end of capacitor C7 is connected to C ext pin Q of 74121E and the positive control terminal of voltage-controlled switch S5 are connected, the negative control terminal of voltage-controlled switch S5 is grounded, the input terminal of voltage-controlled switch S5 and the positive terminal of 6V voltage source are connected, the negative terminal of 6V voltage source is grounded, the output terminal of voltage-controlled switch S5 and one end of resistor R23 are connected to node 35 in parallel with the 2-port of summer SUM2, the other end of resistor R23 is grounded. A1 and A2 pins of 74121F are connected to node 35, B pin of 74121F is connected to the positive terminal of 5V voltage source, the negative terminal of 5V voltage source is grounded, V cc pin and one end of resistor R21 are connected to node 36 in parallel with the positive terminal of 5V voltage source, the negative terminal of 5V voltage source is grounded, the other end of resistor R21 and one end of capacitor C8 are connected to R ext / C ext pin is connected to node 37, the other end of capacitor C8 is connected to C ext pin Q of 74121F and the positive control terminal of voltage-controlled switch S6 are connected, the negative control terminal of voltage-controlled switch S6 is grounded, the input terminal of voltage-controlled switch S6 and the positive terminal of -6V voltage source are connected, the negative terminal of -6V voltage source is grounded, the output terminal of voltage-controlled switch S6 and one end of resistor R24 are connected to node 38 in parallel with the 1-port of summer SUM2, the other end of resistor R24 is grounded, the 3-port of summer SUM2 outputs signal V f2 . Signal V f1 and V f2 are connected to the 1-port and 2-port of summer SUM3 respectively, the 3-port of SUM3 is connected to the input terminal of absolute value module ABS, the output terminal of ABS outputs signal V f .

[0031] The proposed memristive neural network circuit is used for classification of two kinds of Iris (Iris Setosa and Iris Virginica), the shapes of Iris Setosa and Iris Virginica are respectively as Figure 3 (a) andFigure 3 As shown in (b), the data distribution (petal length, petal width, sepal length, and sepal width) for the two types of flowers is as follows: Figure 4 As shown, there are 50 sets of data for each. Compared to Virginia iris, mountain iris has smaller petal length, petal width, and sepal length, but a larger sepal width. The initial resistance values ​​of eight memristors were randomly set, as shown below. Figure 5 As shown. Thirty sets of data were taken from each of the two iris varieties to train the memristor neural network circuit. Taking one training iteration as an example, the data for a single Virginia iris flower were: petal length 4.8cm, petal width 1.8cm, sepal length 6cm, sepal width 3cm; these dimensional data were input into the circuit as voltage signals. V in1 (t=20ms, V=4.8V) represents the petal length, V in2 (t=20ms, V=1.8V) represents the petal width, V in3 (t=20ms, V=6V) represents the calyx length, V in4 (t=20ms, V=3V) represents the calyx width, and the input signal is as follows: Figure 6 As shown. Figure 7 The voltages of capacitors C1 and C2 and the output signals V of the two neurons are shown. O1 and V O2 With the input of a voltage signal, the charge accumulation rate on capacitor C1 is less than that on capacitor C2. At 10.4 ms, the integrated voltage of capacitor C2 first reaches the threshold voltage V. th Then neuron 2 outputs a high-level signal V. O2 The integrated voltage of capacitor C1 is discharged to ground, V C1 The voltage drops instantly to 0V, and the output signal V of neuron 1... O1 The voltage is 0V. Neuron 2 wins. The memristor corresponding to neuron 2 includes M. b1 M b2 M b3 and M b4 Starting from 17ms, the system receives feedback voltage signals from the weight adjustment module. After 17ms, the voltage of each memristor is equal to the difference between its input signal and the feedback voltage signal. Figure 8 The voltage across each memristor is displayed. Neuron 1 has no output due to failed competition, so its weight adjustment module does not generate an adjustment signal. Upon receiving the adjustment signal generated by the weight adjustment module, the resistance of neuron 2's memristor changes, as shown... Figure 9 As shown. M b1 M b2 and M b3 When the voltage exceeds its positive threshold voltage, their resistance decreases. b4The voltage of the neuron exceeds its negative threshold, its resistance increases. The above process is the whole process of the learning of the memristor neural network circuit based on the competition learning mechanism for a set of input signals. Each time a set of voltage signals is input, only one neuron wins and only the weight of the winning neuron can change.

[0032] The circuit takes whether the weight characteristics of the memristor after training and the data characteristics of the input signals are consistent as the classification basis. After 1000 training, the resistance of the memristor reaches a steady state, and the circuit completes the learning. The resistance of the memristor is shown in FIG. 6. The resistances of the memristors M Figure 10 a1 , M a2 and M a3 reach the maximum value, and M a4 reaches the minimum value, indicating that the weights of the first three memristors reach the minimum, and the weight of the fourth memristor reaches the maximum. The first three memristors respectively receive the input signals of petal length, petal width and calyx length, and the fourth memristor receives the input signal of calyx width. Compared with the Virginia iris, the data characteristics of the California iris are that the petal length, petal width and calyx length are smaller, and the calyx width is larger. Therefore, the weight characteristics of the neuron 1 are consistent with the data characteristics of the California iris, that is, the neuron 1 corresponds to the California iris. Similarly, the weight characteristics of the neuron 2 are consistent with the data characteristics of the Virginia iris, that is, the neuron 2 corresponds to the Virginia iris. After the training is completed, the circuit can be used for classification. Each time an input is received, only one neuron wins. The output signal of the neuron 1 indicates that the input is classified into the California iris, and the output signal of the neuron 2 indicates that the input is classified into the Virginia iris. For example, the circuit is respectively input with the data of a California iris (petal length 1.4 cm, petal width 0.2 cm, calyx length 5.5 cm, calyx width 4.2 cm) and a Virginia iris (petal length 6.7 cm, petal width 2.2 cm, calyx length 7 cm, calyx width 3.8 cm). Figure 11 Corresponding to the input of the California iris, the integral voltage V C1 of the capacitor C1 exceeds the threshold voltage V C2 faster than the integral voltage V th of the capacitor C2, the neuron 1 wins and outputs a high level V O1 , and the signal V O2 is 0, indicating that the circuit successfully classifies the input into the California iris. Figure 12 Corresponding to the input of the Virginia iris, the integral voltage V C2 of the capacitor C2 exceeds the threshold voltage V C1 faster than the integral voltage V th of the capacitor C1, the neuron 2 wins and outputs a high level V O2 , and V O1 ​A value of 0 indicates that the circuit successfully classified the input as a Virginia iris. After testing with 40 sets of data, one set of data was misclassified, incorrectly classifying a mountain iris (petal length 1.3cm, petal width 0.3cm, sepal length 4.5cm, sepal width 2.3cm) as a Virginia iris. The classification accuracy reached 97.5% (39 / 40), demonstrating that this memristor neural network circuit has a high classification accuracy.

Claims

1. A memristor neural network circuit based on a competitive learning mechanism, characterized in that, It includes a forward calculation module and a reverse adjustment module; the forward calculation module consists of a memristor cross array module and a leakage integration and discharge module, and the reverse adjustment module consists of a weight adjustment module. The memristor cross array module consists of eight memristors M a1 -M a4 and M b1 -M b4 Composition; memristor M a1 and M b1 The positive terminal is connected in parallel with the input signal V. in1 Memristor M connected to node 1 a2 and M b2 The positive terminal is connected in parallel with the input signal V. in2 Memristor M connected to node 2 a3 and M b3 The positive terminal is connected in parallel with the input signal V. in3 Memristor M is connected to node 3. a4 and M b4 The positive terminal is connected in parallel with the input signal V. in4 Memristor M is connected to node 4. a1 -M a4 The negative terminal is connected in parallel with the input terminal of the voltage-controlled switch S1 at node 5, and the memristor M... b1 -M b4 The negative terminal is connected in parallel and then connected to the input terminal of the voltage-controlled switch S2 at node 6; the adjustment signal V f1 Connect to node 5 and adjust signal V f2 Connect to node 6; The leakage integration and discharge module consists of NMOS transistors N1-N6, voltage-controlled switches S1 and S2, resistors R1-R12, capacitors C1 and C2, operational amplifiers A1-A4, voltage comparators COMP1 and COMP2, and a voltage source; the source of NMOS transistor N1 is grounded, and the gate of NMOS transistor N1 is connected to the adjustment signal V. f The resistor R1 is connected in parallel with the positive control terminal of the voltage-controlled switch S1 at node 7 and connected to the drain of the NMOS transistor N1. The other end of the resistor R1 is connected to the positive terminal of the 5V voltage source, the negative terminal of the 5V voltage source is grounded, and the negative control terminal of the voltage-controlled switch S1 is grounded; memristor M a1 -M a4 The negative terminals of the resistors are connected in parallel to the input terminal of the voltage-controlled switch S1 at node 5. The output terminal of the voltage-controlled switch S1 and one end of resistor R2 are connected in parallel to node 8 and to the inverting input terminal of operational amplifier A1. The non-inverting input terminal of operational amplifier A1 is grounded. The other end of resistor R2 and one end of resistor R3 are connected in parallel to node 9 and to the output terminal of operational amplifier A1. The other end of resistor R3 and one end of resistor R4 are connected in parallel to node 10 and to the inverting input terminal of operational amplifier A2. The non-inverting input terminal of operational amplifier A2 is grounded. The other end of resistor R4, one end of resistor R5, and the drain of NMOS transistor N2 are connected in parallel to the output terminal of operational amplifier A2 at node 11. The source of NMOS transistor N2 is grounded, and the gate of NMOS transistor N2 is connected to the adjustment signal V. f The source of NMOS transistor N3 is grounded, and the gate of NMOS transistor N3 and one end of resistor R12 are connected to node 20; the other end of resistor R5, the drain of NMOS transistor N3, and one end of capacitor C1 are connected in parallel to the non-inverting input of voltage comparator COMP1 at node 12; the inverting input of voltage comparator COMP1 is connected to voltage source V. th The positive power supply pin of voltage comparator COMP1 is connected to a 6V voltage source, and the negative power supply pin of voltage comparator COMP1 is grounded. One end of resistor R6 and the gate of NMOS transistor N6 are connected in parallel to the output terminal of voltage comparator COMP1 at node 13. The output terminal of voltage comparator COMP1 outputs a signal V. O1 The source of NMOS transistor N4 is grounded, and the gate of NMOS transistor N4 is connected to the adjustment signal V. f The resistor R7 is connected in parallel with the positive control terminal of the voltage-controlled switch S2 at node 14 and connected to the drain of the NMOS transistor N4. The other end of the resistor R7 is connected to the positive terminal of the 5V voltage source, the negative terminal of the 5V voltage source is grounded, and the negative control terminal of the voltage-controlled switch S2 is grounded; memristor M b1 -M b4 The negative terminals are connected in parallel to the input terminal of voltage-controlled switch S2 at node 6. The output terminal of voltage-controlled switch S2 and one end of resistor R8 are connected in parallel to node 15 and to the inverting input terminal of operational amplifier A3. The non-inverting input terminal of operational amplifier A3 is grounded. The other end of resistor R8 and one end of resistor R9 are connected in parallel to node 16 and to the output terminal of operational amplifier A1. The other end of resistor R9 and one end of resistor R10 are connected in parallel to node 17 and to the inverting input terminal of operational amplifier A4. The non-inverting input terminal of operational amplifier A4 is grounded. The other end of resistor R10, one end of resistor R11, and the drain of NMOS transistor N5 are connected in parallel to the output terminal of operational amplifier A4 at node 18. The source of NMOS transistor N5 is grounded, and the gate of NMOS transistor N5 is connected to the adjustment signal V. f The source of NMOS transistor N6 is grounded, and the gate of NMOS transistor N6 and one end of resistor R6 are connected to node 13. The other end of resistor R11, the drain of NMOS transistor N6, and one end of capacitor C2 are connected in parallel to the non-inverting input of voltage comparator COMP2 at node 19. The inverting input of voltage comparator COMP2 is connected to voltage source V. th The positive power supply pin of voltage comparator COMP2 is connected to a 6V voltage source, and the negative power supply pin of voltage comparator COMP2 is grounded. One end of resistor R12 and the gate of NMOS transistor N3 are connected in parallel to the output terminal of voltage comparator COMP2 at node 20. The output terminal of voltage comparator COMP2 outputs a signal V. O2 ; The weight adjustment module consists of monostable multivibrators 74121A-74121F, resistors R13-R24, capacitors C3-C8, voltage-controlled switches S3-S6, summers SUM1-SUM3, a voltage source, and an absolute value module ABS; signal V O1 It is connected to pin B of the monostable multivibrator 74121A, pins A1 and A2 of the 74121A are grounded, and the V of the 74121A is connected to the ground. cc One end of the pin and resistor R13 are connected in parallel to the positive terminal of the 5V voltage source at node 21. The negative terminal of the 5V voltage source is grounded. The other end of resistor R13 and one end of capacitor C3 are connected in parallel to the R of the 74121A capacitor. ext / C ext The pin is connected to node 22, and the other end of capacitor C3 is connected to the capacitor C of 74121A. ext The pins are connected as follows: the Q pin of the 74121A and one end of resistor R16 are connected in parallel to the A1 and A2 pins of the 74121B at node 23; the other end of resistor R16 is grounded. The B pin of the 74121B is connected to the positive terminal of a 5V voltage source, and the negative terminal of the 5V voltage source is grounded. The V pin of the 74121B... cc One end of the pin and resistor R14 are connected in parallel to the positive terminal of the 5V voltage source at node 24. The negative terminal of the 5V voltage source is grounded. The other end of resistor R14 and one end of capacitor C4 are connected in parallel to the R pin of the 74121B. ext / C ext The pin is connected to node 25, and the other end of capacitor C4 is connected to the capacitor C of the 74121B. ext The pin connections are as follows: The Q pin of the 74121B is connected to the positive control terminal of the voltage-controlled switch S3, the negative control terminal of the voltage-controlled switch S3 is grounded, the input terminal of the voltage-controlled switch S3 is connected to the positive terminal of a 6V voltage source, the negative terminal of the 6V voltage source is grounded, the output terminal of the voltage-controlled switch S3 and one end of resistor R17 are connected in parallel to port 2 of the summer SUM1 at node 26, and the other end of resistor R17 is grounded; the A1 and A2 pins of the 74121C are connected to node 26, the B pin of the 74121C is connected to the positive terminal of a 5V voltage source, the negative terminal of the 5V voltage source is grounded, and the V pin of the 74121C... cc One end of the pin and one end of resistor R15 are connected in parallel to the positive terminal of the 5V voltage source at node 27. The negative terminal of the 5V voltage source is grounded. The other end of resistor R15 and one end of capacitor C5 are connected in parallel to the R of the 74121C. ext / C ext The pin is connected to node 28, and the other end of capacitor C5 is connected to the capacitor C of 74121C. ext The pin connections are as follows: the Q pin of the 74121C is connected to the positive control terminal of the voltage-controlled switch S4, the negative control terminal of the voltage-controlled switch S4 is grounded, the input terminal of the voltage-controlled switch S4 is connected to the positive terminal of the -6V voltage source, and the negative terminal of the -6V voltage source is grounded. The output terminal of the voltage-controlled switch S4 and one end of resistor R18 are connected in parallel to port 1 of the summer SUM1 at node 29. The other end of resistor R18 is grounded. The adjustment signal V is output from port 3 of the summer SUM1. f1 Signal V O2 Connected to pin B of the monostable multivibrator 74121D, pins A1 and A2 of the 74121D are grounded, and the V of the 74121D is connected to the ground. cc One end of the pin and resistor R19 are connected in parallel to the positive terminal of the 5V voltage source at node 30. The negative terminal of the 5V voltage source is grounded. The other end of resistor R19 and one end of capacitor C6 are connected in parallel to the R pin of the 74121D. ext / C ext The pin is connected to node 31, and the other end of capacitor C6 is connected to the capacitor C of 74121D. ext The pins are connected as follows: the Q pin of the 74121D and one end of resistor R22 are connected in parallel to the A1 and A2 pins of the 74121E at node 32; the other end of resistor R22 is grounded. The B pin of the 74121E is connected to the positive terminal of a 5V voltage source, and the negative terminal of the 5V voltage source is grounded. The V pin of the 74121E... cc One end of the pin and resistor R20 are connected in parallel to the positive terminal of the 5V voltage source at node 33. The negative terminal of the 5V voltage source is grounded. The other end of resistor R20 and one end of capacitor C7 are connected in parallel to the R of the 74121E. ext / C ext The pin is connected to node 34, and the other end of capacitor C7 is connected to the capacitor C of 74121E. ext The pin connections are as follows: The Q pin of the 74121E is connected to the positive control terminal of the voltage-controlled switch S5, the negative control terminal of the voltage-controlled switch S5 is grounded, the input terminal of the voltage-controlled switch S5 is connected to the positive terminal of a 6V voltage source, the negative terminal of the 6V voltage source is grounded, the output terminal of the voltage-controlled switch S5 and one end of resistor R23 are connected in parallel to port 2 of the summer SUM2 at node 35, and the other end of resistor R23 is grounded; the A1 and A2 pins of the 74121F are connected to node 35, the B pin of the 74121F is connected to the positive terminal of a 5V voltage source, the negative terminal of the 5V voltage source is grounded, and the V pin of the 74121F... cc One end of the pin and resistor R21 are connected in parallel to the positive terminal of the 5V voltage source at node 36. The negative terminal of the 5V voltage source is grounded. The other end of resistor R21 and one end of capacitor C8 are connected in parallel to the R of the 74121F capacitor. ext / C ext The pin is connected to node 37, and the other end of capacitor C8 is connected to the capacitor C of 74121F. ext The pin connections are as follows: the Q pin of the 74121F is connected to the positive control terminal of the voltage-controlled switch S6, the negative control terminal of the voltage-controlled switch S6 is grounded, the input terminal of the voltage-controlled switch S6 is connected to the positive terminal of the -6V voltage source, and the negative terminal of the -6V voltage source is grounded. The output terminal of the voltage-controlled switch S6 and one end of resistor R24 ​​are connected in parallel to port 1 of the summer SUM2 at node 38. The other end of resistor R24 ​​is grounded. The adjustment signal V is output from port 3 of the summer SUM2. f2 ; Adjustment signal V f1 and V f2 Connect the input signal V to ports 1 and 2 of the summer SUM3, respectively. Connect port 3 of SUM3 to the input of the absolute value module ABS. The output of ABS outputs the adjustment signal V. f .

2. The memristor neural network circuit based on a competitive learning mechanism according to claim 1, characterized in that, The forward calculation module consists of a memristor cross-array module and a leakage integration and discharge module. After receiving the input signal, the memristor cross-array module outputs current to the leakage integration and discharge module. The leakage integration and discharge module receives the output current from the memristor cross-array module and then generates an output signal V. O1 and V O2 The forward computation module uses a winner-takes-all algorithm to achieve lateral inhibition and competitive activation between two neurons. For each input, only one neuron successfully competes and then generates an output signal. The reverse adjustment module consists of a weight adjustment module, which adjusts neuron weights using the Hebbian learning rule to achieve self-learning. It receives the output signal V from the forward calculation module. O1 and V O2 Then, an adjustment signal V is generated. f V f1 and V f2 The weights of the winning neurons are adjusted in the forward calculation module.

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