Resistive random access memory array and storage circuit
Programming the resistive memory array through the current signal, the problem of additional control logic required for memristor voltage driving operations is solved, and low power consumption, low latency data operation and multi-layer matrix vector multiplication cascade expansion are realized.
Patent Information
- Application Number
- CN202510347931.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-24
- Publication Date
- 2025-07-18
AI Technical Summary
In the existing integrated storage and computing architecture, the voltage driving operation of the memristor requires additional control logic design, resulting in increased power consumption and delay, and the large scale of the analog-to-digital conversion circuit, affecting the development of integrated storage and computing technology.
The resistive memory array is programmed using current signals, including a memory-based integrated array, a current mirror circuit, a resistive memory array and an inverting amplifier circuit. The set and reset operation of the memristor is realized through the current signal, eliminating the analog-to-digital conversion process and reducing power consumption.
It realizes data operation with low power consumption and low latency, reduces the scale of peripheral circuits, supports cascade expansion of multi-layer matrix vector multiplication, and reduces circuit power consumption.
Smart Images
Figure CN120340562A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the fields of microelectronics technology and semiconductor integrated circuits, and particularly to a resistive random access memory (RRAM) array and a computing-in-memory circuit, which are applicable to the hardware integration implementation of neural networks. Background Art
[0002] In the context of big data, technologies such as artificial intelligence have developed rapidly. The computing-in-memory architecture realizes storage and in-situ computing functions in storage units, saving the time and power consumption of frequent data transfer between the processor and the memory, and is considered an effective way to break through the current von Neumann bottleneck. As one of the new storage media adopted by the computing-in-memory architecture, memristors have the advantages of high integration density, simple structure, and compatibility with various algorithms. Memristors generally use voltage drive to realize the resistance state adjustment of memristors. However, when performing voltage reset and set operations on memristors, it is necessary to control and limit the current, which requires additional design in the control logic or hardware circuit.
[0003] In the computing-in-memory design, a computing scheme of voltage input and current readout is often adopted. In its circuit, it is usually necessary to perform analog-to-digital conversion to read the computing current and then cache the computing result in an additional register. At the same time, the scale of peripheral circuit components such as analog-to-digital conversion circuits between different arrays is huge, which brings problems such as increased power consumption, delay, and accuracy loss, restricting the further development of the computing-in-memory technology. Memristors can record the historical charge passing through them and can realize different driving methods of voltage and current. Therefore, starting from the driving method of memristors, designing relevant current-driven programming methods and their hardware neural network circuits is of great significance for the development of the computing-in-memory technology and circuit optimization. Summary of the Invention
[0004] Aiming at the defects of the prior art, the present invention provides a resistive random access memory (RRAM) array and a computing-in-memory circuit. This current uses a current signal to program the RRAM array to realize operations such as reading, writing, and erasing of the RRAM array, and has the characteristics of simple structure, high integration density, low power consumption, and low delay.
[0005] To solve the above technical problems, the technical solution adopted in the present invention is as follows: A resistive random access memory (RRAM) array and a computing-in-memory circuit, including a computing-in-memory array, a current mirror circuit, an RRAM array, and an inverting amplifier circuit. The input terminal of the computing-in-memory array is connected to an input voltage, which is used to perform in-situ calculation on the input voltage and the value stored in the computing-in-memory array. The input terminal of the current mirror circuit is connected to the output terminal of the computing-in-memory array, which is used to perform a proportional transformation on the calculation result of the computing-in-memory array and output it. The RRAM array is connected to the output terminal of the current mirror circuit, which is used to store the calculation result of the computing-in-memory array. The input terminal of the inverting amplifier circuit is connected to the output terminal of the current mirror circuit, which is used to perform a negative linear proportional output on the calculation result of the computing-in-memory array. The output terminal of the inverting amplifier circuit is connected to the input terminal of the next-level computing-in-memory array or an analog-to-digital conversion circuit. The RRAM array includes a memristor and a read / write select transistor. One end of the memristor is connected to a programming power supply, and the other end is connected to the output terminal of the current mirror circuit and one signal pole of the read / write select transistor. The control pole of the read / write select transistor is connected to a select signal, and the other signal pole of the read / write select transistor is grounded. The memristor is programmed by a current signal. In the high-resistance state, a current signal with the same polarity as the set voltage is applied to achieve the set operation of the memristor. In the low-resistance state, a current signal with the same polarity as the reset voltage is applied to achieve the reset operation of the memristor. When the memristors form an RRAM array, data read, write, and erase operations are completed by resetting and setting the memristors.
[0006] Further, the process of implementing data write, read, and erase operations on the RRAM array is as follows: Write: The calculation result of the computing-in-memory array is output as a current signal and input to the input terminal of the current mirror circuit. The current mirror circuit proportionally copies the current signal at the input terminal to the output terminal as the programming current for the memristor. The programming current flows from the programming power supply through the memristor, the output terminal of the current mirror circuit to the ground, completing the write operation on the memristor and writing the calculation result of the computing-in-memory array into the memristor. During this process, the read / write select transistor is in the off state. Erase: No signal is input to the computing-in-memory array, and the current mirror circuit is turned off when no signal is input. The inverting amplifier circuit is turned off, and the read / write select transistor is turned on. The programming power supply, the memristor, and the read / write select transistor form a loop, and an erase voltage signal is applied by the programming power supply to perform an erase operation on the memristor. Reading includes two modes: reading during the write operation and independent reading. The implementation process of reading during the write operation is as follows: control the inverting amplifier circuit to turn on. At this time, the memristor and the output terminal of the current mirror form a voltage division relationship. During the writing process, the voltage at the intermediate node between the two is the voltage at the input terminal of the inverting amplifier circuit. There is a linear relationship between the output terminal and the input terminal of the inverting amplifier, and the inverted output voltage signal is used as the reading result of the memristor. During independent reading, there is no signal input to the memory and computing integrated array, and the current mirror circuit has no signal input and is in the off state. Turn on the read / write strobe transistor and the inverting amplifier circuit. At this time, the memristor and the read / write strobe transistor form a series voltage division relationship, and the voltage signal at the intermediate node between the two is input to the input terminal of the inverting amplifier circuit and is inverted and output through the inverting amplifier circuit as the reading result of the memristor.
[0007] Further, when the strobe signal at the control terminal of the read / write strobe transistor is high, the read / write strobe transistor is in the on state; when the strobe signal at the control terminal of the read / write strobe transistor is low, the read / write strobe transistor is in the off state.
[0008] Further, the inverting amplifier circuit is connected with a calculation mode switching signal. When the calculation mode switching signal is high, the inverting amplifier circuit is in the on state; when the calculation mode switching signal is low, the inverting amplifier circuit is in the off state.
[0009] Further, this circuit is applicable to the independent calculation mode. After the memory and computing integrated array completes the calculation, turn on the read / write strobe transistor, generate a read signal using the programming power supply, and read the calculation result at the output terminal of the inverting amplifier circuit.
[0010] Further, this circuit is applicable to the cascaded calculation mode. Multiple resistive random access memory (RRAM) arrays and the memory and computing circuit form a cascaded array. The calculation result of the memory and computing integrated array is written into the RRAM array using the current programming method. At the same time, the inverting amplifier circuit generates the voltage input signal for the next-level memory and computing integrated array, and the final calculation result is obtained at the output terminal of the cascaded array.
[0011] Further, the current programming method does not depend on the structure and material type of the memristor in the resistive random access memory array; and the memristor is generally a two-port sandwich structure, and a high-density cross array can be fabricated through a back-end process compatible with the CMOS process.
[0012] Further, determine the programming power supply based on the I-V curve of the memristor.
[0013] Further, the structure of the current mirror circuit is a simple structure, a cascode structure, or a low-voltage cascode structure.
[0014] Further, the inverting amplifier circuit is a single-stage amplifier circuit, which is composed of a MOS transistor in diode connection and a MOS transistor in common-source connection.
[0015] Furthermore, the stacking mode of the memory - in - computing array is 2D or 3D, and the storage medium is a non - volatile memory.
[0016] Advantages of the present invention: Both the input and output of this circuit are voltage signals, enabling cascaded expansion of multi - layer matrix - vector multiplication. The memristor is programmed with a current signal and stores the intermediate results of the calculation, eliminating the analog - to - digital conversion process between multiple memory - in - computing arrays and reducing the circuit scale. The power consumption of the peripheral circuit is almost 0 under static working conditions, and the current - programmed resistive - random - access - memory array also reduces the corresponding operation power consumption, significantly reducing the power consumption level of the circuit. The memory - in - computing array can control the power supply of the inverting amplifier circuit to achieve an independent calculation mode for a single memory - in - computing array or a cascaded calculation mode for multiple memory - in - computing arrays of different scales. Description of the Drawings
[0017] Figure 1 Schematic diagram of the resistive - random - access - memory array and the memory - in - computing circuit described in Embodiment 1; Figure 2 I - V characteristic curve of the voltage - programmed memristor; Figure 3 I - V characteristic curve and DC readout result schematic diagram of the current - programmed memristor described in Embodiment 1; Figure 4 Schematic diagram of the current - mirror circuit; Figure 5 Schematic diagram of the inverting amplifier circuit; Figure 6 Schematic diagram of the memristor and the read - write select transistor; Figure 7 Working flowchart of the resistive - random - access - memory array and the memory - in - computing circuit described in Embodiment 1; In the figure: 1. Memory - in - computing array, 2. Current - mirror circuit, 3. Memristor, 4. Programming power supply, 5. Read - write select transistor, 6. Inverting amplifier circuit, 7. Read - write control signal, 8. Calculation mode switching signal. Detailed Embodiments
[0018] The present invention will be further described below in conjunction with the drawings and specific embodiments.
[0019] Embodiment 1 This embodiment discloses a resistive - random - access - memory array and a memory - in - computing circuit based on current drive, as Figure 1As shown, it includes an in-memory computing array 1, a current mirror circuit 2, a resistive random access memory (RRAM) array, and an inverting amplifier circuit 6. The input end of the in-memory computing array 1 is connected to an input voltage, which is used to perform in-situ calculation on the input voltage and the value stored in the in-memory computing array 1. The input end of the current mirror circuit 2 is connected to the output end of the in-memory computing array 1, which is used to perform an equal-proportion transformation on the calculation result of the in-memory computing array 1 and output it. The RRAM array is connected to the output end of the current mirror circuit 2, which is used to store the calculation result of the in-memory computing array 1. The input end of the inverting amplifier circuit 6 is connected to the output end of the current mirror circuit 2, which is used to perform a negative linear proportion output on the calculation result of the in-memory computing array 1. The output end of the inverting amplifier circuit 6 is connected to the input end of the next-level in-memory computing array or an analog-to-digital conversion circuit. In this embodiment, the RRAM array includes a memristor 4 and a read / write select transistor 5. One end of the memristor 4 is connected to a programming power supply 4, and the other end is connected to the output end of the current mirror circuit 2 and one signal pole of the read / write select transistor 5. The control pole of the read / write select transistor 5 is connected to a select signal, that is, Figure 1 the read / write control signal 7 in [ ]. The other signal pole of the read / write select transistor 5 is grounded. The memristor 5 is programmed by a current signal. In the high-resistance state, a current signal with the same polarity as the set voltage is applied to achieve the set operation of the memristor. In the low-resistance state, a current signal with the same polarity as the reset voltage is applied to achieve the reset operation of the memristor. In this embodiment, memristors 3 are used to form the RRAM array, and data reading, writing, and erasing operations are completed by resetting and setting the memristors.
[0020] The signal flow of this circuit is as follows: The input voltage vector Vin is applied to the in-memory computing array 1 for matrix-vector multiplication operation. The current at the output end of the in-memory computing array 1 is connected to the input end of the current mirror circuit 2 as the calculation result. The output end of the current mirror circuit 2 is connected to one end of the memristor 3. The output current is scaled down proportionally and used as the programming current of the memristor 3. The magnitude of the programming current determines the resistance state of the memristive memory. At the same time, the other end of the memristor 3 is connected to the programming power supply 4 to cooperate in completing the current setting operation of the memristor 3 and writing the calculation result into the memristor 3. The read / write select transistor 5 is connected to the output end of the current mirror circuit 2 and the power supply ground, and can cooperate with the programming power supply 4 to complete the independent read, write, and erase operations of the memristive memory. The input end of the inverting amplifier circuit 6 is connected to the output end of the current mirror circuit 2, reads out the stored data of the memristor 3, and converts it into an input voltage vector for the next-level in-memory computing array. The inverting amplifier circuit 6 isolates the in-memory computing arrays of the front and back stages, and can start or turn off the power supply of the inverting amplifier according to needs to achieve the independent calculation and cascaded calculation functions of different in-memory computing arrays Bipolar memristors usually have at least two stable resistance states. Among them, the resistance state switching operation from a higher resistance state to a lower resistance state by applying an external excitation is called a set operation; conversely, it is called a reset operation. Usually, bipolar memristors use voltage signals as external excitations to complete the set and reset operations under voltage signals of different polarities. When a memristor is used as a memory, programming operations such as reading, writing, and erasing are all completed by resetting and setting the memristor.
[0021] The current-driven memristive programming method described in this embodiment is a programming method that uses current signals to control the reset and set of memristors to achieve resistance state switching. Similar to the voltage-driven programming method, in the high-resistance state, applying a current signal with the same polarity as the set voltage can achieve the set operation of the memristor at a lower current level. When driven by voltage, in order to prevent excessive current from damaging the device during the set operation, a current limit is usually set. In this current-driven process, the magnitude of the current signal is directly controlled, so there is no need for an additional current (voltage) limiting circuit or control logic, saving control logic resources and additional limiting circuits. Moreover, when the memristor changes from the high-resistance state to the low-resistance state at a lower current level, its own voltage drop becomes smaller, which can prevent the device from failing due to excessive excitation and has a self-protection phenomenon.
[0022] As Figure 2 、 Figure 3 As shown in the I-V curves of voltage-driven and current-driven of the memristor in Fig. a, when driven by voltage, a relatively high current value and additional current limitation occur during the set process. The additional current limitation requires real-time monitoring of the current level in software control and timely limiting of excessive current; or designing a special current-limiting circuit to limit the current value during setting from the hardware level. In these cases, it brings obstacles to the hardware circuit design of the memristive memory. The current level during the set operation in current driving is lower than that in voltage driving, and its operating power consumption is smaller. In the low-resistance state, applying a current signal with the same polarity as the reset voltage can achieve the reset operation of the memristor, and its current level is comparable to that in voltage driving.
[0023] Figure 3 Fig. b shows the comparison of small-voltage read currents after current setting and resetting. Applying current signals of different polarities can set and reset the memristor to switch the memristor between two resistance states. Different from the voltage programming process, during current programming and setting, the set current of the memristive memory is much smaller than that in voltage programming, greatly reducing the power consumption of the set operation of the resistive random access memory array.
[0024] In this embodiment, the resistive random access memory (RRAM) array and the computing-in-memory (CIM) circuit copy the computing result represented by current in the CIM array 1 through the current mirror circuit 2, and write it into the RRAM array by using the current programming method; and the computing result stored in the RRAM array is read out through the inverting amplifier circuit 6 and converted into a voltage signal that can directly drive the next-level CIM array or an output voltage signal for reading the computing result.
[0025] The CIM array 1 includes two groups of signal electrodes as input electrodes and output electrodes. The input electrodes are used to apply input vectors, and the input voltage vectors are calculated in situ with the values stored in the CIM array. According to Ohm's law and Kirchhoff's law, the computing result represented in the form of current can be read out on the output electrodes. The stacking mode of the CIM array is 2D or 3D, and the storage medium is generally a non-volatile memory such as Flash or memristor.
[0026] In this embodiment, the current mirror circuit 2 includes two ports: a current input end and a current output end; among them, the current at the input end of the current mirror circuit and the current at the output end are in a linear proportional relationship, and the current at the output end of the CIM array is scaled proportionally and used as the programming current of the RRAM array. As Figure 4 shown, the current mirror circuit structure includes but is not limited to a simple structure (shown in 4b), a cascode structure (shown in 4a), a low-voltage cascode structure (shown in 4c), etc., which can complete the above functions.
[0027] As Figure 5 shown, the inverting amplifier circuit is a single-stage amplifier circuit, which consists of a MOS transistor connected in diode configuration and a MOS transistor connected in common-source configuration, and can realize the negative linear proportional output of the input and output voltages.
[0028] As Figure 6 shown, one end of the memristor is connected to the programming voltage Vcc, and the other end is connected to the output end of the current mirror. The memristive memory is driven by voltage and current to realize multi-resistance level adjustment, and can store the computing result through current setting; the read / write select tube is used for the reset operation and read operation of the memristive memory. The read / write select tube 5 can control the on / off of the select tube through an external signal, and then control whether the signal is transmitted. Devices such as field effect transistors or triodes can be selected. The read / write select tube includes at least one control electrode and two signal electrodes. Among them, the control electrode is connected to the select signal Vselect, one of the signal electrodes is connected to the output end of the current mirror circuit, and the other signal electrode is grounded to Vpe. The reset operation of the memristive memory is completed through the cooperation of the select signal and the programming power supply; according to the different resistance states of the memristive memory, the voltage division with the read / write select tube is different, and the stored value of the memristive memory can be read out through the inverting amplifier circuit.
[0029] In this embodiment, the process of implementing data writing, reading, and erasing operations on the resistive memory array is as follows: Writing: The calculation result of the memory - in - computing array is output as a current signal and input to the input terminal of the current - mirror circuit. The current - mirror circuit proportionally copies the current signal at the input terminal to the output terminal as the programming current for the memristor. The programming current flows from the programming power supply through the memristor, the output terminal of the current - mirror to the ground, completing the write operation on the memristor and writing the calculation result of the memory - in - computing array into the memristor. During this process, the read - write select transistor is in the off state.
[0030] Erasing: When there is no signal input to the memory - in - computing array, the current - mirror circuit is turned off when there is no signal input; turn off the inverting amplifier circuit and turn on the read - write select transistor. The programming power supply, the memristor, and the read - write select transistor form a loop, and the programming power supply applies an erasing voltage signal to perform an erasing operation on the memristor.
[0031] Reading: It includes two ways: reading during the write operation and independent reading. The implementation process of reading during the write operation is as follows: Control the inverting amplifier circuit to turn on. At this time, the memristor and the output terminal of the current - mirror form a voltage - dividing relationship. The voltage at the intermediate node between the two during the writing process is the voltage at the input terminal of the inverting amplifier circuit. There is a linear relationship between the output terminal and the input terminal of the inverting amplifier, and the inverted output voltage signal is used as the reading result of the memristor. During independent reading, there is no signal input to the memory - in - computing array, the current - mirror circuit is turned off when there is no signal input. Turn on the read - write select transistor and the inverting amplifier circuit. At this time, the memristor and the read - write select transistor form a series voltage - dividing relationship, and the voltage signal at the intermediate node between the two is input to the input terminal of the inverting amplifier circuit and is inverted and output by the inverting amplifier circuit as the reading result of the memristor.
[0032] During the above process, when the gating signal of the control pole of the read - write select transistor is high, the read - write select transistor is in the on state; when the gating signal of the control pole of the read - write select transistor is low, the read - write select transistor is in the off state. The inverting amplifier circuit is connected with a calculation - mode switching signal. When the calculation - mode switching signal is high, the inverting amplifier circuit is in the on state; when the calculation - mode switching signal is low, the inverting amplifier circuit is in the off state.
[0033] In this embodiment, the programming power supply is determined based on the I-V curve of the memristor. There are various types of memristive device materials, and their characteristic current levels are also different. Therefore, the reset and set voltages and currents applied by the circuit should be based on the specific memristive device. In Embodiment 1, according to the typical DC IV characteristics of the memristor, the reset and set voltages of the memristor are set to -2V and 3V respectively, and the reset and set currents are set to -3mA and 4.5uA respectively. The pulse width of the circuit depends on the pulse width of the input voltage signal of the memory and computing integrated array, generally ranging from several hundred nanoseconds to several milliseconds. The programming power supply 4 outputs an amplitude of [-5V, 5V]. Specifically, the range of the programming power supply 4 for writing is from +3V to +5V, with constant voltage output, and the specific value can refer to the limiting voltage of the current Set or Reset; the range of the programming power supply 4 for erasing is from -5V to -3V, with pulse output, and the specific value refers to the voltage value of Reset; the range of the programming power supply 4 for reading is generally below 1V, with pulse reading. Both writing and reading can be output signals by the programming power supply 4 because they are both positive values. Erasing is a negative voltage, and the port of the read / write strobe tube 5 grounded can be connected to a programming power supply that can output a positive voltage. When erasing, the programming power supply 4 outputs 0V, and the programming power supply connected to the grounded end of the read / write strobe tube 5 outputs a positive voltage, which can also complete the erasing and avoid the burden of positive and negative power supplies. At other times, the programming power supply II outputs 0V.
[0034] The resistive random access memory array and the memory and computing circuit described in this embodiment can be divided into an independent computing mode and a cascaded computing mode. The independent computing mode means that multiple memory and computing arrays independently complete their respective computing contents, and the computing results do not participate in the computing of other memory and computing arrays at the same time. The cascaded computing mode is that multiple memory and computing integrated arrays jointly complete the computing task. The output of the previous-level memory and computing integrated array is used as the input signal of the next-level memory and computing integrated array, and a computing task is completed simultaneously. The two modes can be switched or cascaded computing with different scales can be set by controlling the power supply of the inverting amplifier circuit according to the computing mode switching signal. When applicable to the independent computing mode, after the memory and computing integrated array completes the computing, the read / write strobe tube is turned on, and a read signal is generated using the programming power supply, and the computing result is read at the output end of the inverting amplifier circuit. When applicable to the cascaded computing mode, multiple resistive random access memory arrays and memory and computing circuits form a cascaded array. The computing result of the memory and computing integrated array is written into the resistive random access memory array using the current programming method. At the same time, the inverting amplifier circuit generates the voltage input signal of the next-level memory and computing integrated array, and the final computing result is obtained at the output end of the cascaded array.
[0035] As Figure 7 shown, the working process of the resistive random access memory array and the memory and computing circuit in this embodiment is as follows: First, determine the calculation mode and set the overall calculation scale through the calculation mode switching control signal. Then, program the power supply to 0. When the current mirror circuit is in the off state, write matrix data to the memory-in-computation array. Next, select the read / write strobe tube, set the programming power supply to the reset level to reset the resistive random access memory (RRAM) array to the high-resistance state and erase the RRAM array. Finally, set the programming power supply to the set level, start the current mirror circuit, apply the input vector to the input end of the memory-in-computation array, and perform vector-matrix multiplication. The current mirror circuit can then convert the output current into the programming current of the RRAM array to store the calculation result. At this time, the output voltage signal of the inverting amplifier circuit is used as the readout result of the RRAM array. During independent calculation, after the calculation is completed, turn on the read / write strobe tube, generate a read signal using the programming power supply, and read the calculation result at the output end of the inverting amplifier circuit. During cascaded calculation, the calculation result is synchronously programmed and amplified by current to be written into the memristive memory. At the same time, the inverting amplifier circuit generates the input voltage signal for the next stage, and the final calculation result is obtained at the output end of the cascaded array.
[0036] Embodiment 1 shows the circuit structure and design concept of this circuit design. Without conflict, circuit structures with similar functions or structures can be used to replace the circuit of the embodiment of the present disclosure, and new embodiments can be obtained by combining similar features. The above are all specific implementation manners of the present disclosure. Modifications or improvements made without departing from the circuit structure and design mentioned in the present disclosure fall within the scope protected by the claims of the present disclosure.
Claims
1. A resistive random access memory array and a memory - in - computing circuit, characterized in that: It includes a processing-in-memory array, a current mirror circuit, a resistive random access memory (RRAM) array, and an inverting amplifier circuit. The input end of the processing-in-memory array is connected to an input voltage, which is used to perform in-situ calculation on the input voltage and the value stored in the processing-in-memory array. The input end of the current mirror circuit is connected to the output end of the processing-in-memory array, which is used to perform proportional transformation on the calculation result of the processing-in-memory array and output it. The RRAM array is connected to the output end of the current mirror circuit, which is used to store the calculation result of the processing-in-memory array; The input end of the inverting amplifier circuit is connected to the output end of the current mirror circuit, which is used to perform negative linear proportional output on the calculation result of the processing-in-memory array. The output end of the inverting amplifier circuit is connected to the input end of the next-stage processing-in-memory array or an analog-to-digital conversion circuit; The RRAM array includes memristors and read / write select transistors. One end of a memristor is connected to a programming power supply, and the other end is connected to the output end of the current mirror circuit and one signal pole of the read / write select transistor. The control pole of the read / write select transistor is connected to a select signal, and the other signal pole of the read / write select transistor is grounded; The memristor is programmed by a current signal. In the high-resistance state, a current signal with the same polarity as the set voltage is applied to realize the set operation of the memristor; In the low-resistance state, a current signal with the same polarity as the reset voltage is applied to realize the reset operation of the memristor. When the memristors form an RRAM array, data reading, writing, and erasing operations are completed by resetting and setting the memristors.
2. The resistive memory array and computing-in-memory circuit according to claim 1, wherein: The processes of writing, reading, and erasing data in the RRAM array are as follows: Writing: The calculation result of the processing-in-memory array is output as a current signal and input to the input end of the current mirror circuit. The current mirror circuit copies the current signal at the input end to the output end proportionally as the programming current for the memristor. The programming current flows from the programming power supply through the memristor, the output end of the current mirror circuit to the ground, completing the write operation on the memristor and writing the calculation result of the processing-in-memory array into the memristor; In this process, the read / write select transistor is in the off state; Erasing: No signal is input to the processing-in-memory array, and the current mirror circuit is turned off when no signal is input; Turn off the inverting amplifier circuit, turn on the read / write select transistor, and a loop is formed by the programming power supply, the memristor, and the read / write select transistor. The programming power supply applies an erase voltage signal to perform the erase operation on the memristor; Reading: It includes two methods: reading during the write operation and independent reading. The implementation process of reading during the write operation is as follows: Control the inverting amplifier circuit to turn on. At this time, a voltage division relationship is formed between the memristor and the output end of the current mirror circuit. The voltage at the middle node between the two during the write process is the voltage at the input end of the inverting amplifier circuit. The output end and the input end of the inverting amplifier are linearly related, and the inverted output voltage signal is used as the reading result of the memristor; During independent reading, no signal is input to the processing-in-memory array, and the current mirror circuit is turned off when no signal is input. The read / write select transistor and the inverting amplifier circuit are turned on. At this time, a series voltage division relationship is formed between the memristor and the read / write select transistor, and the voltage signal at the middle node between the two is input to the input end of the inverting amplifier circuit and inverted and output by the inverting amplifier circuit as the reading result of the memristor.
3. The resistive memory array and the computing-in-memory circuit according to claim 2, wherein: When the strobe signal of the read / write strobe tube control electrode is high, the read / write strobe tube is in the open state. When the strobe signal of the read / write strobe tube control electrode is low, the read / write strobe tube is in the off state.
4. The resistive memory array and the computing-in-memory circuit according to claim 2, wherein: The inverting amplifier circuit is connected with a calculation mode switching signal. When the calculation mode switching signal is high, the inverting amplifier circuit is in the open state. When the calculation mode switching signal is low, the inverting amplifier circuit is in the off state.
5. The resistive memory array and the computing-in-memory circuit according to claim 1, wherein: This circuit is applicable to the independent calculation mode. After the computing-in-memory array completes the calculation, the read / write strobe tube is turned on, and a read signal is generated by using the programming power supply, and the calculation result is read at the output end of the inverting amplifier circuit.
6. The resistive memory array and computing-in-memory circuit according to claim 1, wherein: This circuit is applicable to the cascaded calculation mode. Multiple resistive random access memory (RRAM) arrays and the computing-in-memory circuits form a cascaded array. The calculation result of the computing-in-memory array is written into the RRAM array by using the current programming method. At the same time, the inverting amplifier circuit generates a voltage input signal for the next-level computing-in-memory array, and the final calculation result is obtained at the output end of the cascaded array.
7. The resistive random access memory array and computing-in-memory circuit according to claim 1, wherein: The programming power supply is determined based on the I-V curve of the memristor.
8. The resistive random access memory array and the memory-computation circuit according to claim 1, wherein: The current mirror circuit structure is a simple structure, a cascode structure, or a low-voltage cascode structure.
9. The resistive memory array and computing-in-memory circuit according to claim 1, wherein: The inverting amplifier circuit is a single-stage amplifier circuit, which is composed of a MOS tube in diode connection and a MOS tube in common-source connection.
10. The resistive random access memory array and the computing-in-memory circuit according to claim 1, wherein: The stacking mode of the computing-in-memory array is 2D or 3D, and the storage medium is a non-volatile memory, including NAND Flash, NOR Flash, ferroelectric memory, magnetic memory, and memristor.