Memory device, operating method of memory device, and memory system including memory device

Abstract

A memory device, an operating method of the memory device, and a memory system including the memory device are provided. The memory device includes: a memory cell array including a plurality of memory cells arranged in a plurality of rows; an erase detector that stores attack-susceptible line data, the attack-susceptible line data including a location of an estimation error corresponding to an attack-susceptible line of the plurality of lines; an error correction code (ECC) engine that decodes first data read from the memory cell array in response to a read command based on the vulnerable row data to generate information about a first error included in the first data, and corrects the first error to generate second data; and a flag generator that generates a decoding flag indicating a decoding state of the ECC engine based on the vulnerable line data, the information about the first error, and the second data.

Description

Technical Field

[0001] The present disclosure relates to a storage device, an operation method of the storage device, and a memory system including the storage device. Background Art

[0002] Storage devices widely used in high-performance electronic systems are increasing in integration and speed, and the manufacturing process of the storage devices is also improving. As the process scale decreases, the bit error rate may increase rapidly, and the yield may decrease. Therefore, a method for improving the reliability of storage devices is needed.

[0003] On the other hand, a dynamic random access memory (DRAM) device includes an error correction code (ECC) circuit to improve the reliability of stored data. The ECC circuit can correct errors in the data stored in the DRAM device. However, if an error in the data exceeds the error correction ability of the ECC circuit, a silent data corruption (SDC) phenomenon may occur in which the error is not detected or corrected from the data. Therefore, it is beneficial to reduce the SDC phenomenon by improving error determination. Summary of the Invention

[0004] According to an embodiment of the present disclosure, a storage device and a memory system having improved reliability will be provided.

[0005] According to an embodiment of the present disclosure, a storage device and a memory system that prevent or reduce a silent data corruption (SDC) phenomenon will be provided.

[0006] A storage device according to an embodiment includes: a memory cell array including a plurality of memory cells arranged in multiple rows; an erasure detector configured to store vulnerable row data including positions of estimated errors corresponding to vulnerable rows among the multiple rows; an error correction code (ECC) engine configured to decode first data read from the memory cell array in response to a read command based on the vulnerable row data to generate information about a first error included in the first data, and correct the first error to generate second data; and a flag generator configured to generate a decoding flag indicating a decoding state of the ECC engine based on the vulnerable row data, the information about the first error, and the second data.

[0007] A method of operating a memory device including a memory cell array, the operating method according to an embodiment comprising: in response to a read command, receiving first data read from the memory cell array including a plurality of memory cells arranged in multiple rows; generating a first syndrome for the first data; generating information about a first error included in the first data based on the first syndrome and vulnerable row data, the vulnerable row data including positions of estimated errors corresponding to vulnerable rows among the multiple rows; generating second data by correcting the first error; and generating a decoding flag indicating a decoding state based on the vulnerable row data, the information about the first error, and the second data.

[0008] A memory system according to an embodiment includes: a memory controller configured to send a read command and receive a decoding flag indicating a decoding state of a memory device in response to the read command; and a memory device including a memory cell array having a plurality of memory cells arranged in multiple rows. The memory device is configured to: read first data from the memory cell array in response to the read command; decode the first data based on vulnerable row data including positions of estimated errors corresponding to vulnerable rows among the multiple rows to generate information about a first error included in the first data; correct the first error to generate second data; and generate the decoding flag indicating the decoding state based on the vulnerable row data, the information about the first error, and the second data. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a view showing a memory system according to an embodiment.

[0010] Figure 2 is a view showing a Figure 1 memory device according to an embodiment.

[0011] Figure 3 is a view showing a Figure 2 ECC engine according to an embodiment.

[0012] Figure 4 is a view showing a Figure 3 ECC decoding circuit according to an embodiment.

[0013] Figure 5 is a view showing a Figure 4 ECC decoding operation of an ECC decoding circuit according to an embodiment.

[0014] Figure 6 is a view showing a Figure 2 flag generator according to an embodiment.

[0015] Figure 7 is a view showing the operation of a flag generator according to an embodiment Figure 6 of the present disclosure.

[0016] Figure 8 is a graph showing the possibility of detecting uncorrectable errors in a storage device according to an embodiment

[0017] Figure 9 is a view showing a computer system according to an embodiment

[0018] Figure 10 is an example block diagram showing a computing device according to an embodiment

[0019] Figure 11 is a block diagram showing a computer system according to an embodiment Detailed Description of the Embodiments

[0020] Hereinafter, embodiments of the present disclosure will be described more fully with reference to the accompanying drawings so that those skilled in the art can easily implement these embodiments. The present disclosure can be modified in various different ways, all of which do not depart from the spirit or scope of the present invention.

[0021] To clearly describe the present disclosure, parts irrelevant to the description of the present disclosure are omitted in the accompanying drawings. The same reference numerals throughout the specification denote the same elements. In the flowcharts described with reference to the accompanying drawings, the order of operations can be changed, various operations can be combined, a certain operation can be divided, and / or a certain operation can be not performed.

[0022] In addition, the singular form may be intended to include the plural form unless an explicit expression such as "one" or "single" is used. Terms including ordinal numbers such as first, second, etc. may be used only to describe various constituent elements and should not be construed as limiting these constituent elements. These terms may be used for the purpose of distinguishing one constituent element from other constituent elements.

[0023] Figure 1 is a view showing a memory system according to an embodiment Figure 2 is a view showing a storage device according to an embodiment Figure 1 of the present disclosure.

[0024] Referring to Figure 1 , the memory system 100 may include a memory controller 10 and a storage device 20.

[0025] The memory controller 10 may access the storage device 20 according to a request from a host. The memory controller 10 may communicate with the host using various protocols. For example, in response to a request from the host, the memory controller 10 may write data in the storage device 20 or may read data from the storage device 20.

[0026] In an embodiment, the memory controller 10 may be connected to the storage device 20 through a memory interface to exchange signals through the memory interface. The memory controller 10 may control the storage operation of the storage device 20 by providing signals to the storage device 20. The signals may include a command CMD and an address ADDR. The command CMD may include an activation command, a read / write command, and a refresh command. The activation command may be a command to activate a target row of the memory cell array 210 to write data into or read data from the memory cell array 210. The read / write command may be a command to perform a read or write operation on a target memory cell of the activated row. The refresh command may be a command to perform a refresh operation in the memory cell array 210.

[0027] The memory controller 10 may provide the command CMD and the address ADDR to the storage device 20 to access the memory cell array 210, and may control storage operations, such as reading data from or writing data into the memory cell array 210. According to the read operation, data DQ may be transferred from the memory cell array 210 to the memory controller 10. According to the write operation, data DQ may be transferred from the memory controller 10 to the memory cell array 210.

[0028] The storage device 20 may be a semiconductor device-based storage device. In an embodiment, the storage device 20 may be a dynamic random access (DRAM) memory including dynamic memory cells, a double data rate 4 (DDR4) synchronous DRAM (SDRAM) memory, a low power DDR4 (LPDDR4) SDRAM memory, an LPDDR5 SDRAM memory, a DDR5 SDRAM memory, or a graphics DDR (GDDR) memory.

[0029] In response to the address ADDR and the command CMD received from the memory controller 10, the storage device 20 may receive or output data DQ through a data line, and may perform a refresh operation. In addition, the storage device 20 may send a decoding flag F_DEC to the memory controller 10. The memory controller 10 may determine the decoding state of the storage device 20 based on the decoding flag F_DEC. For example, if the memory controller 10 receives the decoding flag F_DEC with an enable level, it may determine that the data DQ received from the storage device 20 includes an uncorrectable error. If the memory controller 10 receives the decoding flag F_DEC with a disable level, it may determine that the data DQ received from the storage device 20 does not include an error or includes a corrected error.

[0030] Combined with Figure 1 Refer to Figure 2, the memory device 20 may include a memory cell array 210, sense amplifiers 211, control logic 220, an address register 230, a row decoder 250, a column decoder 260, an input / output (I / O) gating circuit 270, a data I / O buffer 280, and a refresh address generator 290.

[0031] The memory cell array 210 may include a plurality of memory cells MC defined by multiple rows and multiple columns. In an embodiment, the memory cell array 210 may include a plurality of memory banks 210a - 210h. Although Figure 2 eight memory banks (BANK0 - BANK7) 210a - 210h are shown, the number of memory banks is not limited thereto. Each of the memory banks 210a - 210h may include multiple rows, multiple columns, and a plurality of memory cells MC disposed at the intersections (or cross - points) of the multiple rows and multiple columns. In an embodiment, the multiple rows may be defined by multiple word lines WL, and the multiple columns may be defined by multiple bit lines BL.

[0032] The control logic 220 may control the overall operation of the memory device 20. Specifically, the control logic 220 may generate control signals such that the memory device 20 performs a read operation, a write operation, or a refresh operation. In an embodiment, the control logic 220 may include a command decoder for decoding a command CMD and a mode register for setting an operation mode of the memory device 20. The control logic 220 may control the refresh address generator 290 to generate a refresh row address REF_ADDR in response to a refresh command. The control logic 220 may generate an error - correction code (ECC) control signal CTRL_ECC for controlling the ECC engine 300.

[0033] The address register 230 may receive an address ADDR. The address ADDR may include a row address ROW_ADDR indicating a row of the memory cell array 210 and a column address COL_ADDR indicating a column of the memory cell array 210. The address register 230 may provide a bank address BANK_ADDR to the bank control logic 240. The address register 230 may provide the row address ROW_ADDR to the control logic 220 and the row address multiplexer 251. The address register 230 may provide the column address COL_ADDR to the column decoder 260. In an exemplary embodiment, the address register 230 may provide the column address COL_ADDR and the bank address BANK_ADDR to the control logic 220.

[0034] The bank control logic 240 may generate bank control signals based on the bank address BANK_ADDR received from the address register 230. Based on the bank control signals, the row decoder corresponding to the bank address BANK_ADDR among the first to eighth row decoders 250a - 250h may be activated, and the column decoder corresponding to the bank address BANK_ADDR among the first to eighth column decoders 260a - 260h may be activated.

[0035] The refresh address generator 290 may generate a refresh row address REF_ADDR for refreshing the memory cells. The refresh address generator 290 may provide the refresh row address REF_ADDR to the row address multiplexer 251. Accordingly, the memory cells provided at the word lines corresponding to the refresh row address REF_ADDR may be refreshed.

[0036] The row address multiplexer 251 may receive the row address ROW_ADDR from the address register 230 and may receive the refresh row address REF_ADDR to be refreshed from the refresh address generator 290. The row address multiplexer 251 may selectively select one of the row address ROW_ADDR and the refresh row address REF_ADDR, and may output the selected row address as the row address RA to the row decoder 250. The row address RA output from the row address multiplexer 251 may be applied to the first to eighth row decoders 250a - 250h.

[0037] The row decoder 250 may select a row to be activated among multiple rows of the memory cell array 210 based on the row address ROW_ADDR or the refresh row address REF_ADDR. To this end, the row decoder 250 may apply a driving voltage to the word line corresponding to the row to be activated. In an embodiment, multiple row decoders 250a - 250h corresponding to multiple memory banks 210a - 210h may be provided.

[0038] The column decoder 260 may select a column to be activated among multiple columns of the memory cell array 210 based on the column address COL_ADDR. To this end, the column decoder 260 may activate the sense amplifier 211 corresponding to the column address COL_ADDR through the I / O gating circuit 270. In an embodiment, multiple column decoders 260a - 260h corresponding to multiple memory banks 210a - 210h may be provided.

[0039] The input / output gating circuit 270 can be a circuit that gates input / output data. In an embodiment, the I / O gating circuit 270 can include a data latch for storing data read from the memory cell array 210 and a write driver for writing data into the memory cell array 210. The data read from the memory cell array 210 can be read out by the sense amplifier 211 and stored in the I / O gating circuit 270.

[0040] The sense amplifier 211 can read out the data read from the memory cell array 210. In an embodiment, a plurality of sense amplifiers 211a - 211h corresponding to the plurality of memory banks 210a - 210h can be provided. For example, a codeword CW read from a memory cell array of the first to eighth memory banks 210a - 210h can be read out by the sense amplifiers 211a - 211h corresponding to the memory cell array and stored in the input / output gating circuit 270. The codeword CW can include a plurality of symbols. Each of the plurality of symbols can include a plurality of bits.

[0041] When the memory device 20 performs a write operation, the data input / output buffer 280 can send the data DQ to the ECC engine 300. When the memory device 20 performs a read operation, the data input / output buffer 280 can send the data DQ received from the ECC engine 300 to the memory controller 10. In addition, when the memory device 20 performs a read operation, the data input / output buffer 280 can send the decoded flag F_DEC received from the flag generator 500 to the memory controller 10.

[0042] The ECC engine 300 can perform ECC encoding on the write data to be written into the memory cell array 210 according to the ECC control signal CTRL_ECC. Specifically, the ECC engine 300 can generate parity bits for the write data. The ECC engine 300 can send the data DQ and the parity bits to the input / output gating circuit 270. The input / output gating circuit 270 can write the data DQ and the parity bits into the memory cell array 210.

[0043] The ECC engine 300 can perform ECC decoding on the read data read from the memory cell array 210 according to the ECC control signal CTRL_ECC. Specifically, the ECC engine 300 can perform ECC decoding on the codeword CW stored in the input / output gating circuit 270. For example, the ECC engine 300 can perform ECC decoding on the codeword CW read from each row of the memory cell array 210.

[0044] The ECC engine 300 can detect errors within a codeword CW. The ECC engine 300 can generate information about the positions of the detected errors and information about the error values. Specifically, the ECC engine 300 can generate an error location polynomial ELP and an error evaluation polynomial EEP when performing ECC decoding. In an embodiment, the error location polynomial ELP can be a polynomial generated based on the positions of the errors within the codeword CW. In an embodiment, the error evaluation polynomial EEP can be a polynomial generated based on the error data values.

[0045] If an error is detected in the codeword CW, the ECC engine 300 can correct the error in the codeword CW based on the error location polynomial ELP and the error evaluation polynomial EEP to generate corrected data CDQ. The ECC engine 300 can provide the corrected data CDQ as data DQ to the memory controller 10 through the data input / output buffer 280.

[0046] The ECC engine 300 can send the error location polynomial ELP and the error evaluation polynomial EEP to the flag generator 500. In addition, the ECC engine 300 can send the corrected data CDQ to the flag generator 500.

[0047] The erase detector 400 can store vulnerable row data P_ERS of vulnerable rows where errors may occur. The vulnerable rows within the memory cell array 210 can be preset in the process steps of the storage device 20. For example, the vulnerable row data P_ERS can include the data positions corresponding to the vulnerable rows. The vulnerable row data P_ERS can include the positions of the estimated errors within the codeword CW. For example, the position of the estimated error can be the second data of the first symbol, the third data of the second symbol, etc. The erase detector 400 can transfer the vulnerable row data P_ERS to the ECC engine 300. The ECC engine 300 can assume that an error occurs in the data corresponding to the positions included in the vulnerable row data P_ERS.

[0048] The ECC engine 300 can determine that an error has occurred in the data corresponding to the position within the codeword CW based on the vulnerable row data P_ERS, and can change the value of the data. The ECC engine 300 can generate an error location polynomial ELP and an error evaluation polynomial EEP based on the vulnerable row data P_ERS. For example, the error location polynomial ELP generated based on the vulnerable row data P_ERS can be a polynomial that is based not only on the position of the error existing within the codeword CW, but also on the position of the estimated error included in the vulnerable row data P_ERS. In addition, the error evaluation polynomial EEP generated based on the vulnerable row data P_ERS can be a polynomial that is based not only on the error value existing within the codeword CW, but also on the value of the estimated error included in the vulnerable row data P_ERS.

[0049] The ECC engine 300 can also send the vulnerable row data P_ERS to the flag generator 500. However, the present invention is not limited thereto, and the flag generator 500 can receive the vulnerable row data P_ERS from the erase detector 400. In an embodiment, the data of the vulnerable row within the erase detector 400 can be updated periodically.

[0050] The flag generator 500 can generate a decoding flag F_DEC indicating the decoding state of the ECC decoding result. As described above, the storage device 20 can read data from the storage cell array 210, and can correct the error in the read data to output the corrected data CDQ as the data DQ. The decoding state can indicate whether the data DQ is normal data or data including an uncorrectable error. Specifically, if the data DQ includes an uncorrectable error, the decoding state can be an uncorrectable error (UE). For example, if the data DQ includes an error beyond the correction capability of the ECC engine 300, the decoding state can be UE. If the data DQ includes a correctable error, the decoding state can be a correctable error (CE). If the data DQ does not include an error, the decoding state can be no error (NE). Specifically, the flag generator 500 can generate the decoding flag F_DEC based on the error location polynomial ELP, the error evaluation polynomial EEP, and the corrected data CDQ received from the ECC engine 300.

[0051] In an embodiment, the ECC engine 300 may use forward error correction (FEC) techniques to correct errors. Hereinafter, the ECC engine 300 is described as using Reed-Solomon (R-S) codes to correct errors, but the present invention is not limited thereto, and the ECC engine 300 may correct errors in various ways. The R-S code may be a non-binary cyclic code, and its symbols include m-bit sequences (m is an integer greater than 2). In the R-S code, selecting different parameters for the code gives different levels of protection and affects the complexity of the implementation. The R-S code may be described by an (n, k) code. Here, n is the length of the entire code, and k is the length of the data. That is, n - k may represent the length of the parity check. In addition, the error correction capability of the ECC engine 300 may be expressed as Equation 1.

[0052] (Equation 1)

[0053] In Equation 1, t is the error correction capability of the ECC engine, n is the length of the entire code, and k is the length of the data.

[0054] The error correction capability of the ECC engine 300 may indicate the number of correctable bits in the entire code. Since the length of the entire code and the length of the data are preset, the error correction capability of the ECC engine 300 may be preset.

[0055] On the other hand, if the position of the estimated error is preset based on the vulnerable row data P_ERS received from the erasure detector 400, the error correction capability of the ECC engine 300 may be expressed as Equation 2.

[0056] (Equation 2)

[0057] In Equation 2, t is the error correction capability of the ECC engine, n is the length of the entire code, k is the length of the data, and e is the number of preset errors.

[0058] As shown in Equation 2, the correction ability of the ECC engine 300 can be set by considering the number of errors at preset positions. For example, assume that the length of the entire code is 16 and the length of the data is 8. In this case, since the correction ability of the ECC engine 300 is (16 - 8) / 2, the correction ability of the ECC engine 300 can be 4. On the other hand, if it is assumed that two errors are preset based on the vulnerable row data P_ERS, the correction ability of the ECC engine 300 can be (16 - 8 - 2) / 2, so the correction ability of the ECC engine 300 can be 3. However, because there are two preset errors, the ECC engine 300 can basically correct five errors including the two preset errors. That is, compared with when the vulnerable row data P_ERS is not considered, the correction ability of the ECC engine 300 can be improved when the vulnerable row data P_ERS is considered.

[0059] Figure 3 is a view showing an Figure 2 ECC engine according to an embodiment. Figure 4 is a view showing an ECC decoding circuit according to an embodiment.

[0060] Referring to Figure 3 , the first memory bank 210a may include a normal cell array 2101 and an ECC cell array 2103.

[0061] The ECC engine 300 may include an ECC encoding circuit 310 and an ECC decoding circuit 320.

[0062] The ECC encoding circuit 310 may receive write data WDQ to be written. The ECC encoding circuit 310 may generate a parity bit PRT for the write data WDQ based on the ECC control signal CTRL_ECC. The ECC encoding circuit 310 may store the write data WDQ in the storage cells of the normal cell array 2101 and may store the parity bit PRT in the storage cells of the ECC cell array 2103.

[0063] Based on the ECC control signal CTRL_ECC, the ECC decoding circuit 320 may use the read data RDQ read from the normal cell array 2101 and the parity bit PRT read from the ECC cell array 2103 to correct errors in the read data RDQ. The ECC decoding circuit 320 may output corrected data CDQ with corrected errors. In an embodiment, the ECC decoding circuit 320 may also receive vulnerable row data P_ERS from the erase detector 400.

[0064] Referring together to Figure 4 and Figure 3, the ECC decoding circuit 320 may include a syndrome generator 3201, an error polynomial generator 3203, an error position detector 3205, an error value calculator 3207, and an error corrector 3209.

[0065] The syndrome generator 3201 may receive the read data RDQ and the parity bit PRT. The syndrome generator 3201 may also receive the vulnerable row data P_ERS. Since errors may be added during the process of storing and reading data in the memory cell array 210, the read data RDQ may include errors. The syndrome generator 3201 may generate a syndrome SDR for the read data RDQ to detect the presence or absence of errors in the read data RDQ. In an embodiment, if the syndrome generator 3201 generates a syndrome SDR with a value of 0, it may be determined that the read data RDQ does not include errors. In an embodiment, if the syndrome generator 3201 generates a syndrome SDR with any value other than 0, it may be determined that the read data RDQ includes errors. The syndrome generator 3201 may transmit the syndrome SDR to the error polynomial generator 3203.

[0066] The error polynomial generator 3203 may use the read data RDQ and the syndrome SDR to generate an error location polynomial ELP. Specifically, the error polynomial generator 3203 may use the Berlekamp-Massy (BM) algorithm for the syndrome SDR to calculate the coefficients of the error location polynomial ELP. On the other hand, the present invention is not limited thereto, and the error polynomial generator 3203 may use the Euclidean algorithm to calculate the coefficients of the error location polynomial ELP. In addition, the error polynomial generator 3203 may use the read data RDQ and the syndrome SDR to generate an error evaluation polynomial EEP.

[0067] In an embodiment, the error polynomial generator 3203 may generate an error location polynomial ELP based on the read data RDQ, the syndrome SDR, and the vulnerable row data P_ERS. In an embodiment, the error polynomial generator 3203 may generate an error evaluation polynomial EEP based on the read data RDQ, the syndrome SDR, and the vulnerable row data P_ERS.

[0068] The error polynomial generator 3203 may send the error location polynomial ELP and the error evaluation polynomial EEP to Figure 2 the flag generator 500. The error polynomial generator 3203 may also send the vulnerable row data P_ERS to the flag generator 500.

[0069] The error location detector 3205 can obtain the error location R_ELP based on the error location polynomial ELP. Specifically, the error location detector 3205 can use the Chien search to obtain the error location R_ELP. The error location polynomial ELP can indicate whether each of multiple symbols within the codeword CW includes an error. The error location R_ELP can indicate the error location within each symbol.

[0070] The error location detector 3205 can send the error location R_ELP to the flag generator 500.

[0071] The error value calculator 3207 can obtain the error value R_EEP based on the error evaluation polynomial EEP. Specifically, the error value calculator 3207 can use the Forney algorithm that utilizes the differentiation of the error evaluation polynomial EEP to obtain the error value R_EEP.

[0072] The error value calculator 3207 can send the error value R_EEP to the flag generator 500.

[0073] The error corrector 3209 can generate the corrected data CDQ based on the read data RDQ and the error value R_EEP. In an embodiment, the error corrector 3209 can generate the corrected data CDQ by adding the error value R_EEP to the symbol at the error location R_ELP of the read data RDQ.

[0074] The error corrector 3209 can send the corrected data CDQ to the flag generator 500.

[0075] On the other hand, although Figure 3 it is shown that the first memory bank 210a and the ECC engine 300 are connected, the present invention is not limited thereto, and the first memory bank 210a and the ECC engine 300 can be connected through the input / output gating circuit 270.

[0076] Figure 5 is a view showing the ECC decoding operation of the ECC decoding circuit according to an embodiment Figure 4 of.

[0077] First, the syndrome generator 3201 receives the read data RDQ and the parity bit PRT (S1001).

[0078] The syndrome generator 3201 generates a syndrome SDR for the read data RDQ (S1003).

[0079] Specifically, the syndrome generator 3201 can generate a syndrome SDR based on the read data RDQ and the parity bit PRT corresponding to the read data RDQ. For example, the syndrome generator 3201 can use an XOR array operation to generate the syndrome SDR.

[0080] The syndrome generator 3201 determines whether the value of the syndrome SDR is 0 (S1005).

[0081] If the value of the syndrome SDR is 0, the syndrome generator 3201 can determine that there is no error in the read data RDQ and can end the ECC decoding operation. The ECC decoding circuit 320 can output the read data RDQ as the data DQ.

[0082] If the value of the syndrome SDR is not 0, the syndrome generator 3201 can transmit the syndrome SDR to the error polynomial generator 3203.

[0083] If the value of the syndrome SDR is not 0, the error polynomial generator 3203 generates an error location polynomial ELP and an error evaluation polynomial EEP (S1007).

[0084] The error polynomial generator 3203 can use the syndrome SDR to calculate the coefficients of the error location polynomial ELP. In an embodiment, the error polynomial generator 3203 can further generate the error location polynomial ELP based on the position of the estimated error within the vulnerable row data P_ERS.

[0085] The error location detector 3205 obtains the error location R_ELP based on the error location polynomial ELP (S1009).

[0086] In an embodiment, if the error location detector 3205 successfully obtains the error location R_ELP, the error location R_ELP can include the position of the estimated error.

[0087] The error value calculator 3207 obtains the error value R_EEP based on the error evaluation polynomial EEP (S1011).

[0088] The error corrector 3209 obtains the correction data CDQ (S1013).

[0089] Specifically, the error corrector 3209 can correct the read data RDQ based on the error location R_ELP and the error value R_EEP to generate the correction data CDQ.

[0090] Figure 6 is a view showing a Figure 2 flag generator according to an embodiment.

[0091] Refer toFigure 6 The syndrome checker 500 may include a syndrome checker 501, a first comparison logic 503, a second comparison logic 505, a third comparison logic 507, and a fourth comparison logic 509. In addition, the signature generator 500 may include a signature determination circuit 511.

[0092] The signature generator 500 may receive an error location polynomial ELP, an error evaluation polynomial EEP, an error location R_ELP, an error value R_EEP, and correction data CDQ from the ECC engine 300. In addition, the signature generator 500 may receive vulnerable row data P_ERS from the ECC engine 300 or the erasure detector 400.

[0093] The syndrome checker 501 may calculate a corrected syndrome of the correction data CDQ and may generate a corrected syndrome signal C_SDR.

[0094] In an embodiment, if the value of the corrected syndrome calculated by the syndrome checker 501 is 0, the syndrome checker 501 may determine that the correction data CDQ does not include an error. In an embodiment, if the syndrome calculated by the syndrome checker 501 has any value other than 0, it may be determined that the correction data CDQ includes an error. If the corrected syndrome has any value other than 0, the syndrome checker 501 may generate a corrected syndrome signal C_SDR having an enable level. If the value of the corrected syndrome is 0, the corrected syndrome checker 501 may generate a corrected syndrome signal C_SDR having a disabled level.

[0095] The syndrome checker 501 may transmit the corrected syndrome signal C_SDR to the signature determination circuit 511.

[0096] The first comparison logic 503 may receive the error location polynomial ELP and the error evaluation polynomial EEP. The first comparison logic 503 may compare the order of the error location polynomial ELP with the order of the error evaluation polynomial EEP to generate a first result RES1. If the order of the error location polynomial ELP is less than or equal to the order of the error evaluation polynomial EEP, the first comparison logic 503 may generate a first result RES1 having an enable level. If the order of the error location polynomial ELP is greater than the order of the error evaluation polynomial EEP, the first comparison logic 503 may generate a first result RES1 having a disabled level.

[0097] The first comparison logic 503 may transmit the first result RES1 to the signature determination circuit 511.

[0098] The second comparison logic 505 can receive the error location R_ELP and the error locator polynomial ELP. The second comparison logic 505 can generate a second result RES2 by comparing the order of the error locator polynomial ELP with the number of error locations R_ELP. If the order of the error locator polynomial ELP is different from the number of error locations R_ELP, the second comparison logic 505 can generate a second result RES2 with an enable level. If the order of the error locator polynomial ELP is the same as the number of error locations R_ELP, the second comparison logic 505 can generate a second result RES2 with a disable level.

[0099] The second comparison logic 505 can transfer the second result RES2 to the flag determination circuit 511.

[0100] The third comparison logic 507 can receive the error locator polynomial ELP. The third comparison logic 507 can generate a third result RES3 by comparing the order of the error locator polynomial ELP with the correction capability of the ECC engine 300. If the order of the error locator polynomial ELP exceeds the correction capability of the ECC engine 300, the third comparison logic 507 can generate a third result RES3 with an enable level. If the order of the error locator polynomial ELP is less than or equal to the correction capability of the ECC engine 300, the third comparison logic 507 can generate a third result RES3 with a disable level. Here, the correction capability of the ECC engine 300 can be determined based on the length of the entire code, the length of the data, and the number of preset errors in the vulnerable row data P_ERS.

[0101] The third comparison logic 507 can transfer the third result RES3 to the flag determination circuit 511.

[0102] The fourth comparison logic 509 can receive the vulnerable row data P_ERS and the error location R_ELP. The fourth comparison logic 509 can generate a fourth result RES4 by comparing the estimated error locations within the vulnerable row data P_ERS with the error location R_ELP. If the error location R_ELP does not include the estimated error locations within the vulnerable row data P_ERS, the fourth comparison logic 509 can generate a fourth result RES4 with an enable level. If the error location R_ELP includes the estimated error locations within the vulnerable row data P_ERS, the fourth comparison logic 509 can generate a fourth result RES4 with a disable level.

[0103] The fourth comparison logic 509 can transfer the fourth result RES4 to the flag determination circuit 511.

[0104] The syndrome determination circuit 511 can be connected to the syndrome checker 501, the first comparison logic 503, the second comparison logic 505, the third comparison logic 507, and the fourth comparison logic 509. In an embodiment, the syndrome determination circuit 511 can be an OR circuit. The syndrome determination circuit 511 can receive the corrected syndrome C_SDR, the first result RES1, the second result RES2, the third result RES3, and the fourth result RES4, and can generate a decoded flag F_DEC with an enable level if at least one of the corrected syndrome C_SDR, the first result RES1, the second result RES2, the third result RES3, and the fourth result RES4 has an enable level.

[0105] Figure 7 is a view showing the operation of a Figure 6 flag generator according to an embodiment.

[0106] First, the syndrome checker 501 receives the corrected data CDQ and generates a syndrome (S2000).

[0107] Specifically, the syndrome checker 501 can receive the corrected data CDQ from the ECC engine 300 and generate a syndrome for the corrected data CDQ.

[0108] The syndrome checker 501 determines whether the value of the generated syndrome is 0 (S2001).

[0109] If the value of the syndrome is not 0, the syndrome checker 501 generates a corrected syndrome signal C_SDR with an enable level, and the syndrome determination circuit 511 generates a decoded flag F_DEC with an enable level (S2013).

[0110] If the value of the syndrome is 0, the syndrome checker 501 can determine that there is no error in the corrected data CDQ. Thereafter, the first comparison logic 503 can compare the order of the error location polynomial ELP with the order of the error evaluation polynomial EEP (S2003).

[0111] If the order of the error location polynomial ELP is less than or equal to the order of the error evaluation polynomial EEP, the syndrome determination circuit 511 generates a decoded flag F_DEC with an enable level (S2013).

[0112] If the order of the error location polynomial ELP is greater than the order of the error evaluation polynomial EEP, the second comparison logic 505 compares the order of the error location polynomial ELP with the number of error positions R_ELP (S2005).

[0113] If the order of the error location polynomial ELP and the number of error locations R_ELP are different, the flag determination circuit 511 generates a decoded flag F_DEC with an enable level (S2013).

[0114] If the order of the error location polynomial ELP and the number of error locations R_ELP are the same, the third comparison logic 507 compares the order of the error location polynomial ELP with the correction ability of the ECC engine 300 (S2007).

[0115] If the order of the error location polynomial ELP is greater than the correction ability of the ECC engine 300, the flag determination circuit 511 generates a decoded flag F_DEC with an enable level (S2013).

[0116] If the order of the error location polynomial ELP is less than or equal to the correction ability of the ECC engine 300, the fourth comparison logic 509 compares the position of the estimated error in the vulnerable row data P_ERS with the error locations R_ELP (S2009).

[0117] If the error locations R_ELP do not include the position of the estimated error in the vulnerable row data P_ERS, the flag determination circuit 511 generates a decoded flag F_DEC with an enable level (S2013).

[0118] If the error locations R_ELP include the position of the estimated error in the vulnerable row data P_ERS, the flag determination circuit 511 generates a decoded flag F_DEC with a disable level (S2011).

[0119] On the other hand, although Figure 7 it is shown that the flag generator 500 sequentially executes each step, the present invention is not limited thereto, and the flag generator 500 may execute each step in any order.

[0120] Figure 8 is a graph showing the possibility of detecting an uncorrectable error in a storage device according to an embodiment.

[0121] Specifically, Figure 8 is a graph showing the undetected error probability (UEP), where depending on the number of estimated errors stored in the vulnerable row data of the erasure detector, there will be undetected uncorrectable errors. Here, the uncorrectable error may be a data error exceeding the correction ability of the storage device.

[0122] The storage device can determine whether the data includes an uncorrectable error through multiple conditions, thereby easily detecting the case where the data includes an uncorrectable error.

[0123] As Figure 8As shown, compared with a storage device according to the prior art, a storage device according to an embodiment may have a lower probability of undetected uncorrectable errors. That is, compared with a storage device according to the prior art, a storage device according to the present invention may have a higher probability of detecting uncorrectable errors. Therefore, compared with a storage device according to the prior art, the probability of a silent data corruption (SDC) phenomenon occurring in a storage device according to the present embodiment may be lower.

[0124] Figure 9 is a view showing a computer system according to an embodiment.

[0125] Referring Figure 9 , the computer system 800 may include a host 810, a host memory 820, and a Compute Express Link (CXL) device 850. The computer system 800 may include two or more CXL devices 850. In an embodiment, the computer system 800 may be included in a user device such as a personal computer (PC), a laptop computer, a server, a media player, a digital camera, etc., or may be included in an automotive device such as a navigation device, a black box, vehicle electrical equipment, etc. Alternatively, the computer system 800 may be a mobile system such as a mobile phone, a smartphone, a tablet personal computer (PC), a wearable device, a health device, or an Internet of Things (IoT) device.

[0126] The host 810 may control the overall operation of the computer system 800. In an embodiment, the host 810 may be one of various processors such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a data processing unit (DPU), etc. In an embodiment, the host 810 may include a single-core processor or a multi-core processor.

[0127] The host 810 and the CXL device 850 may communicate with each other using CXL.mem as a memory access protocol. CXL.mem may be a memory access protocol that supports memory access. The host 810 may access the memory 852 within the CXL device 850 through CXL.mem.

[0128] Although Figure 9The CXL device 850 is shown to include one memory 852, but the present invention is not limited thereto, and the CXL device 850 may include two or more memories. The host 810 may send a request to the CXL device 850 indicating the memory 852 and including a memory identifier, a command, and an address. In an embodiment, the command may include an activate command, a read command, and a write command. The activate command may be a command to change a target row of the memory 852 within the CXL device 850 to an active state in order to write data to or read data from the CXL device 850. The CXL device 850 may activate (e.g., drive) the memory cells of the target row in response to the activate command. The read / write command may be a command to perform a read or write operation in the target memory cell of the row that has been changed to the active state.

[0129] The host 810 may send a request to the CXL device 850 through the CXL interface 840.

[0130] The host memory 820 may be used as the main memory or system memory of the computer system 800. In an embodiment, the host memory 820 may be a dynamic random access memory (DRAM) device and may have a dual in-line memory module (DIMM) form factor. However, the present invention is not limited thereto, and the host memory 820 may include non-volatile memory such as flash memory, phase change RAM (PRAM), resistive RAM (RRAM), magnetoresistive RAM (MRAM), etc.

[0131] In an embodiment, the host 810 may be directly connected to the host memory 820. In an embodiment, the host memory 820 may communicate directly with the host 810 through a DDR interface. In an embodiment, the host 810 may include a memory controller configured to control the host memory 820. However, the present invention is not limited thereto, and the host memory 820 may communicate with the host 810 through various interfaces.

[0132] The CXL device 850 may be implemented as a separate storage device or memory module. If there are multiple CXL devices 850, each of the multiple CXL devices 850 may be connected to the CXL interface 840 through a different physical port. That is, since multiple CXL devices 850 are connected to the CXL interface 840, the capacity of the storage area managed by the host 810 may be increased.

[0133] The CXL device 850 may include a CXL controller 851 and a memory 852.

[0134] The CXL controller 851 may include intellectual property (IP) circuits designed to implement an application-specific integrated circuit (ASIC) and / or a field-programmable gate array (FPGA). In various embodiments, the CXL controller 851 may be implemented to support the CXL protocol (e.g., the CXL 2.0 protocol or any other version thereof). The CXL controller 851 may convert CXL data packets and signals of the memory interface of the memory 852 with each other. For example, the CXL controller 851 may convert a CXL data packet transmitted from the host 810 into a memory identifier, command, address, and data indicating the memory 852.

[0135] The CXL controller 851 may convert the data received from the host 810 to store the converted data in the memory 852, or may convert the data stored in the memory 852 to send the converted data to the host 810.

[0136] The memory 852 may include one or a combination of a dynamic random access memory (DRAM), a high bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an Optane DIMM, a non-volatile DIMM (NVMDIMM), a double data rate synchronous dynamic random access memory (DDR SDRAM), and a low power double data rate synchronous dynamic random access memory (LPDDR SDRAM).

[0137] In an embodiment, the memory 852 may be the storage device described in Figures 1 to 7 If the data stored in the memory 852 is read, the memory 852 may perform ECC decoding. The memory 852 may use multiple values generated during the execution of ECC decoding to determine whether the data includes an uncorrectable error. In an embodiment, the data position where an error may occur in the data read from the memory 852 may be preset as an estimated error.

[0138] For example, the memory 852 may determine whether the data includes an uncorrectable error based on at least one of the following: the value of the syndrome correction calculated for the correction data generated by performing ECC decoding on the read data; the result of comparing the order of the error location polynomial ELP with the order of the error evaluation polynomial EEP; the result of comparing the order of the error location polynomial ELP with the number of solutions of the error location polynomial ELP; the result of comparing the order of the error location polynomial ELP with the correction capability of the memory 852; and the result of comparing the position of the estimated error with the position of the solution of the error location polynomial ELP.

[0139] Since the memory 852 determines whether data includes an uncorrectable error through multiple conditions, it can easily detect the case where the data includes an uncorrectable error. Therefore, the reliability of the data stored in the memory 852 can be improved.

[0140] In an embodiment, the host 810 and the CXL device 850 can be configured to share the same interface. For example, the host 810 and the CXL device 850 can communicate with each other through the CXL interface 840. In an embodiment, the CXL interface 840 can be a low-latency and high-bandwidth link that supports the consistency of input / output (IO) protocols, memory access, and dynamic protocol multiplexing to enable various connections between accelerators, storage devices, or various electronic devices.

[0141] In an embodiment, the host 810 can communicate with the CXL device 850 through the CXL interface 840.

[0142] The host 810 and the CXL device 850 can communicate with each other through the CXL interface 840. However, the present invention is not limited thereto, and the host 810 and the CXL device 850 can communicate with each other based on various computing interfaces such as the GEN-Z protocol, the NVLink protocol, the CCIX protocol, the OpenCAPI protocol, etc.

[0143] Figure 10 is an example block diagram showing a computing device according to an embodiment.

[0144] Reference Figure 10 , the computing device 900 includes a processor 910, a memory 920, a memory controller 930, a storage device 940, a communication interface 950, and a bus 960. The computing device 900 may also include another general component.

[0145] The processor 910 controls the overall operation of each configuration of the computing device 900. The processor 910 can be implemented as at least one of various processing units such as a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), etc.

[0146] The memory 920 stores various data and commands. The memory 920 can be implemented as the storage device described in reference Figures 1 to 7 .

[0147] If the data stored in the memory 920 is read, the memory 920 can perform ECC decoding. The memory 920 can use multiple values generated during the execution of ECC decoding to determine whether the data includes an uncorrectable error. In an embodiment, the data position where an error may occur in the data read from the memory 920 can be preset as an estimated error.

[0148] For example, the memory 920 may determine whether the data includes an uncorrectable error based on at least one of the following: the value of a syndrome correction calculated for correction data generated by performing ECC decoding on the read data; the result of comparing the order of the error location polynomial ELP with the order of the error evaluation polynomial EEP; the result of comparing the order of the error location polynomial ELP with the number of solutions of the error location polynomial ELP; the result of comparing the order of the error location polynomial ELP with the correction ability of the memory 920; and the result of comparing the estimated location of the error with the locations of the solutions of the error location polynomial ELP.

[0149] Since the memory 920 determines whether the data includes an uncorrectable error through multiple conditions, it can easily detect the case where the data includes an uncorrectable error. Therefore, the reliability of the data stored in the memory 920 can be improved.

[0150] In an embodiment, the memory controller 930 may be provided as a chip separate from the processor 910. In an embodiment, the memory controller 930 may be provided as an internal configuration of the processor 910.

[0151] The storage device 940 stores programs and data non-temporarily. In an embodiment, the storage device 940 may be implemented as a non-volatile memory.

[0152] The communication interface 950 supports wired / wireless Internet communication of the computing device 900. In addition, the communication interface 950 may support various communication methods other than Internet communication.

[0153] The bus 960 provides a communication function between components of the computing device 900. According to the communication protocol between components, the bus 960 may include at least one type of bus.

[0154] Figure 11 is a block diagram showing a computer system according to an embodiment.

[0155] For ease of description, the detailed description of the above components is omitted. Referring to Figure 11 , the computer system 1000 may include a first CPU 1110, a second CPU 1120, a GPU 1130, an NPU 1140, a CXL switch SW_CXL, a CXL storage 1210, a CXL memory 1220, a PCIe device 1310, and an accelerator 1320.

[0156] The first CPU 1110, the second CPU 1120, the GPU 1130, the NPU 1140, the CXL storage 1210, the CXL memory 1220, the PCIe device 1310, and the accelerator 1320 can be commonly connected to the CXL switch SW_CXL and can communicate with each other through the CXL switch SW_CXL.

[0157] In an embodiment, each of the first CPU 1110, the second CPU 1120, the GPU 1130, and the NPU 1140 can be directly connected to a separate storage device. The CXL storage 1210 and the CXL memory 1220 can be used as the storage space STR of the computer system 1000.

[0158] The CXL storage 1210 can store data received from one or more of the first CPU 1110, the second CPU 1120, the GPU 1130, and the NPU 1140 through the CXL switch SW_CXL, or can output the stored data. At least some regions of the CXL memory 1220 can be allocated as dedicated regions for the CXL storage 1210, and the CXL storage 1210 can use this dedicated region as a buffer memory.

[0159] In an embodiment, the CXL memory 1220 can be the storage device described in Figures 1 to 7 The CXL memory 1220 can store data received from one or more of the first CPU 1110, the second CPU 1120, the GPU 1130, and the NPU 1140 through the CXL switch SW_CXL.

[0160] If the data stored in the CXL memory 1220 is read, the CXL memory 1220 can perform ECC decoding. The CXL memory 1220 can use multiple values generated during the execution of ECC decoding to determine whether the data includes uncorrectable errors. In an embodiment, the data positions where errors may occur in the data read from the CXL memory 1220 can be preset as estimated errors.

[0161] For example, the CXL memory 1220 can determine whether the data includes uncorrectable errors based on at least one of the following: the value of the syndrome correction calculated for the correction data generated by performing ECC decoding on the read data; the result of comparing the order of the error location polynomial ELP with the order of the error evaluation polynomial EEP; the result of comparing the order of the error location polynomial ELP with the number of solutions of the error location polynomial ELP; the result of comparing the order of the error location polynomial ELP with the correction ability of the CXL memory 1220; and the result of comparing the position of the estimated error with the position of the solution of the error location polynomial ELP.

[0162] Since the CXL memory 1220 determines whether data includes an uncorrectable error through multiple conditions, it can easily detect the case where the data includes an uncorrectable error. Therefore, the reliability of the data stored in the CXL memory 1220 can be improved.

[0163] In an embodiment, the CXL switch SW_CXL may be connected to a PCIe device 1310 or an accelerator 1320 configured to support various functions, and the PCIe device 1310 or the accelerator 1320 may communicate with each of the first CPU 1110, the second CPU 1120, the GPU 1130, and the NPU 1140 through the CXL switch SW_CXL, or may access the storage space STR including the CXL storage 1210 and the CXL memory 1220.

[0164] In an embodiment, the CXL switch SW_CXL may be connected to an external network or fabric and may be configured to communicate with an external server through the external network or fabric.

[0165] Although the present disclosure has been described in connection with presently considered practical embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, the present invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A storage device, the storage device comprising: A memory cell array, the memory cell array including a plurality of memory cells arranged in multiple rows; An erase detector configured to store vulnerable row data, the vulnerable row data including positions of estimated errors corresponding to vulnerable rows among the multiple rows; An ECC engine, where ECC stands for error correction code, the ECC engine being configured to decode first data read from the memory cell array in response to a read command based on the vulnerable row data to generate information about a first error included in the first data, and correct the first error to generate second data; And A flag generator configured to generate a decoding flag indicating a decoding state of the ECC engine based on the vulnerable row data, the information about the first error, and the second data.

2. The storage device according to claim 1, wherein, The flag generator includes: A syndrome checker configured to generate a second syndrome for the second data; and A flag determination circuit configured to generate the decoding flag indicating that the first error is an uncorrectable error if a value of the second syndrome is not 0.

3. The storage device according to claim 1, wherein, The ECC engine includes: A syndrome generator configured to generate a first syndrome for the first data; and An error polynomial generator configured to generate an error location polynomial indicating a position of the first error based on the first data, the first syndrome, and the vulnerable row data, wherein the information about the first error includes the error location polynomial.

4. The memory device according to claim 3, wherein, The error polynomial generator is configured to calculate coefficients of the error location polynomial using the Berlekamp - Massey algorithm.

5. The memory device according to claim 3, wherein, A correction ability indicating a number of correctable bits in the first data is predetermined, and wherein the flag generator includes: A first comparison logic configured to compare an order of the error location polynomial with the correction ability, and generate a first result having an enabling level if the order of the error location polynomial exceeds the correction ability; and A flag determination circuit configured to generate the decoding flag indicating that the first error is an uncorrectable error based on the first result having the enabling level.

6. The storage device according to claim 3, wherein, The ECC engine includes an error position detector configured to obtain the position of the first error from the error location polynomial using Chien search.

7. The memory device according to claim 6, wherein, The flag generator includes: A second comparison logic configured to compare the position of the estimated error with the position of the first error, and generate a second result having an enabling level if the position of the first error does not include the position of the estimated error; and A flag determination circuit configured to generate the decoding flag indicating that the first error is an uncorrectable error based on the second result having the enabling level.

8. The memory device according to claim 6, wherein, The flag generator includes: A third comparison logic configured to compare the order of the error - location polynomial with the number of positions of the first error, and generate a third result with an enable level if the order of the error - location polynomial and the number of positions of the first error are different; and A flag determination circuit configured to generate the decoding flag indicating that the first error is an uncorrectable error based on the third result with the enable level.

9. The memory device according to claim 3, wherein, The ECC engine includes: An error polynomial generator configured to generate an error - evaluation polynomial indicating the data value of the first error based on the first data, the first syndrome, and the vulnerable - row data, and the information about the first error includes the error - evaluation polynomial.

10. The storage device according to claim 9, wherein, The flag generator includes: A fourth comparison logic configured to compare the order of the error - location polynomial with the order of the error - evaluation polynomial, and generate a fourth result with an enable level if the order of the error - location polynomial is less than or equal to the order of the error - evaluation polynomial; and A flag determination circuit configured to generate the decoding flag indicating that the first error is an uncorrectable error based on the fourth result with the enable level.

11. An operation method of a storage device including a storage cell array, the operation method includes: Receiving first data read from the storage cell array including a plurality of storage cells arranged in multiple rows in response to a read command; Generating a first syndrome for the first data; Generating information about a first error included in the first data based on the first syndrome and vulnerable - row data, the vulnerable - row data including positions of estimated errors corresponding to vulnerable rows in the multiple rows; Generating second data by correcting the first error; And Generating a decoding flag indicating a decoding state based on the vulnerable - row data, the information about the first error, and the second data.

12. The operation method according to claim 11, wherein, Generating the decoding flag includes generating a second syndrome for the second data, and if the value of the second syndrome is not 0, generating the decoding flag indicating that the first error is an uncorrectable error.

13. The operating method according to claim 11, wherein, Generating the information about the first error includes: Generating an error - location polynomial indicating the position of the first error based on the first data, the first syndrome, and the vulnerable - row data; Generating an error - evaluation polynomial indicating the data value of the first error based on the first data, the first syndrome, and the vulnerable - row data; and Obtaining the position of the first error based on the error - location polynomial.

14. The operating method according to claim 13, wherein, Generating the decoding flag includes: Comparing the order of the error - location polynomial with a correction ability indicating the number of correctable bits in the first data; and If the order of the error - location polynomial exceeds the correction ability, generating the decoding flag indicating that the first error is an uncorrectable error.

15. The operating method according to claim 14, wherein, Generating the decoding flag includes: Compare the position of the estimated error with the position of the first error; and If the position of the first error does not include the position of the estimated error, generate the decoding flag indicating that the first error is an uncorrectable error.

16. The operating method according to claim 14, wherein, Generating the decoding flag includes: Compare the order of the error locator polynomial with the number of positions of the first error; and If the order of the error locator polynomial and the number of positions of the first error are different, generate the decoding flag indicating that the first error is an uncorrectable error.

17. The operating method according to claim 14, wherein, Generating the decoding flag includes: Compare the order of the error locator polynomial with the order of the error evaluator polynomial; and If the order of the error locator polynomial is less than or equal to the order of the error evaluator polynomial, generate the decoding flag indicating that the first error is an uncorrectable error.

18. A memory system, the memory system comprising: A memory controller configured to send a read command and receive a decoding flag indicating a decoding state of a storage device in response to the read command; And A storage device including a memory cell array having a plurality of memory cells arranged in multiple rows, and the storage device is configured to: Read first data from the memory cell array in response to the read command; Decode the first data based on vulnerable row data including positions of estimated errors corresponding to vulnerable rows in the multiple rows to generate information about a first error included in the first data; Correct the first error to generate second data; And Generate the decoding flag indicating the decoding state based on the vulnerable row data, the information about the first error, and the second data.

19. The memory system according to claim 18, wherein, The storage device is configured to generate a second syndrome for the second data, and if the value of the second syndrome is not 0, generate the decoding flag indicating that the first error is an uncorrectable error.

20. The memory system according to claim 19, wherein, The storage device is configured to: Generate an error locator polynomial indicating the position of the first error based on the first data, a first syndrome generated according to the first data, and the vulnerable row data; And If the order of the error locator polynomial exceeds the correction capability indicating the number of correctable bits in the first data, or the position of the first error does not include the position of the estimated error, generate the decoding flag indicating that the first error is an uncorrectable error.

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