Semiconductor structure and preparation method thereof
By removing the first barrier layer and wiring layer in the preparation method of the semiconductor structure, annealing is performed, and grooves are formed in the trench, the problem of raised defects of the copper wiring layer in the thermal process is solved, and the electrical performance and stability of the device are improved.
Patent Information
- Application Number
- CN202510450248.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-10
- Publication Date
- 2025-07-18
AI Technical Summary
During the semiconductor manufacturing process, copper wiring layer is prone to copper mound-shaped convex defects during the subsequent thermal process, affecting the electrical performance and stability of the device.
A method for preparing a semiconductor structure is provided, including annealing the wiring layer after removing the first barrier layer and the wiring layer to release residual stress between the grains and to form grooves in the trench to enhance protection and support of the dielectric layer to the wiring layer.
It effectively reduces the occurrence of hay-shaped protrusion defects in the copper wiring layer during the subsequent thermal process, and improves the electrical performance and reliability of the device.
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Figure CN120341176A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method for manufacturing the same. Background Art
[0002] With the continuous development of semiconductor technology, the back-end manufacturing process of integrated circuits has gradually evolved towards high integration and high performance. In the back-end manufacturing process of integrated circuits, compared with the traditional aluminum interconnect process, the copper interconnect process has lower resistivity and better electromigration resistance performance, which can effectively reduce signal transmission delay and improve device performance. However, with the continuous reduction of the feature size of semiconductor devices, especially after entering the deep sub-micron stage, the influence of parasitic capacitance on signal delay and crosstalk has become increasingly significant. To meet the requirements of high-performance integrated circuit chips, adopting the copper interconnect process and filling a low dielectric constant material between metal layers can effectively reduce the influence of parasitic capacitance.
[0003] In the copper interconnect process, the Damascene process is the current mainstream method for manufacturing copper wires. However, after the CMP (Chemical Mechanical Polishing) process of the copper wires is completed in this process, copper hillock-like protrusion defects are likely to occur during subsequent thermal processes. The copper protrusion defects seriously affect the electrical performance and stability of the device. The main reason for the formation of hillock-like protrusion defects is that during the subsequent thermal process of copper grains, due to the residual stress generated by thermal expansion and contraction, local deformation occurs in the copper wire, resulting in hillock-like protrusion defects. Since the copper hillock-like protrusion defects seriously affect the performance and reliability of the device, therefore, there is an urgent need for a method to reduce copper hillock-like protrusion defects to meet the requirements of high-performance integrated circuit chip manufacturing. Summary of the Invention
[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present application is to provide a semiconductor structure and a method for manufacturing the same, so as to solve the problem that copper hillock-like protrusion defects are likely to occur in the copper wiring layer during subsequent thermal processes in the prior art.
[0005] To achieve the above object and other related objects, the present application provides a method for manufacturing a semiconductor structure, including the following steps:
[0006] Provide a semiconductor substrate, and one side of the semiconductor substrate has a dielectric layer;
[0007] Form a first barrier layer and a trench on the dielectric layer, the first barrier layer covers the dielectric layer, and the trench penetrates through the dielectric layer and the first barrier layer;
[0008] Form a wiring layer on the first barrier layer and fill the trench with the wiring layer;
[0009] Remove the wiring layer and the first barrier layer on the first barrier layer, and expose the dielectric layer;
[0010] Anneal the wiring layer.
[0011] Optionally, removing the wiring layer and the first barrier layer on the first barrier layer includes the following steps:
[0012] Use a first polishing liquid under a first polishing pressure to perform CMP processing on the wiring layer to remove a part of the wiring layer on the first barrier layer;
[0013] Use the first polishing liquid under a second polishing pressure to perform CMP processing on the wiring layer to remove the remaining wiring layer on the first barrier layer and expose the first barrier layer;
[0014] Use a second polishing liquid to perform CMP processing on the first barrier layer to remove the first barrier layer and expose the dielectric layer.
[0015] Optionally, in the step of annealing the wiring layer, the annealing temperature is 350 °C to 400 °C.
[0016] Optionally, in the step of annealing the wiring layer, the annealing time is 3 min to 5 min.
[0017] Optionally, after annealing the wiring layer, the following steps are further included:
[0018] Perform CMP processing on the wiring layer in the trench to form a groove on the side of the wiring layer away from the bottom of the trench.
[0019] Optionally, after annealing the wiring layer, the following steps are further included:
[0020] Form a second barrier layer on the dielectric layer and cover the wiring layer.
[0021] This application also provides a semiconductor structure prepared by using any one of the preparation methods in the foregoing embodiments, including:
[0022] A semiconductor substrate, one side of the semiconductor substrate has a dielectric layer, and the dielectric layer has a trench, and the trench penetrates the dielectric layer;
[0023] A wiring layer filled in the trench.
[0024] Optionally, a groove is provided on the side of the wiring layer away from the bottom of the trench, and the width of the groove is greater than or equal to the width of the end of the wiring layer away from the bottom of the trench.
[0025] Optionally, a step structure is formed between the bottom of the groove and the upper surface of the dielectric layer, and the height of the step structure is
[0026] Optionally, the semiconductor structure further includes a second barrier layer, wherein the second barrier layer is formed on the dielectric layer and covers the wiring layer.
[0027] As described above, compared with the prior art, the semiconductor structure and the preparation method thereof provided by the present application have at least the following beneficial effects:
[0028] The preparation method of the present application, after removing the wiring layer on the first barrier layer and the first barrier layer, and before performing other thermal processes, annealing the wiring layer can release the residual stress between different grains in the wiring layer in advance, reduce the hillocks caused by grain boundary merging, and effectively reduce the hillock defects caused by heating the wiring layer during the subsequent thermal process; and after completing the annealing treatment of the wiring layer, CMP treatment is performed on the wiring layer in the groove to form a groove, so that the dielectric layer wrapping the wiring layer can better provide protection and support for the wiring layer, further reducing the diffusion and expansion of the wiring layer in the subsequent thermal process, and further reducing the hillock defects caused by heating the wiring layer. The semiconductor structure provided by the present application is prepared by the aforementioned preparation method, and therefore also has the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0030] Figure 1 A schematic flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present application is shown.
[0031] Figure 2 Display as Figure 1 The schematic diagram of the structure of forming a first barrier layer and a trench on a dielectric layer in the preparation method shown.
[0032] Figure 3 Display as Figure 1 A schematic structural diagram of forming a wiring layer in the preparation method shown.
[0033] Figure 4 Display as Figure 1 A schematic structural diagram of a semiconductor structure after the first barrier layer and part of the wiring layer are removed in the preparation method shown.
[0034] Figure 5 It shows a top - view structural schematic diagram of the mound - like protrusion defect on the surface of a semiconductor structure in the prior art provided by an embodiment of the present application.
[0035] Figure 6 Shown as Figure 5 A cross - sectional structural schematic diagram of the shown mound - like protrusion defect cut along the white coil.
[0036] Figure 7 It shows a flowchart of a method for fabricating a semiconductor structure provided by an alternative embodiment in Embodiment 1 of the present application.
[0037] Figure 8 Shown as Figure 7 A structural schematic diagram of a groove formed after removing part of the wiring layer in the shown fabrication method.
[0038] Figure 9 Shown as Figure 7 A structural schematic diagram of a second barrier layer formed on the dielectric layer in the shown fabrication method.
[0039] Schematic illustration of reference numerals:
[0040] 11. Semiconductor substrate; 111. Dielectric layer; 1111. Groove; 121. First barrier layer; 122. Wiring layer; 1221. Groove; 123. Second barrier layer. Detailed implementation manners
[0041] To make the technical objectives, technical solutions, and technical effects of the present application clearer, the technical solutions in the present application will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Usually, the components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0042] Therefore, the following detailed description of the embodiments of the present application is not intended to limit the scope of the present application claimed, but merely represents the selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts fall within the scope of protection of the present application. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.
[0043] In the description of this application, it should be noted that the descriptions with reference terms such as "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples" mean that the specific features, structures, materials, or characteristics described in combination with the embodiments or examples are included in at least one embodiment or example of this application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.
[0044] This application provides a method for fabricating a semiconductor structure, which is used to reduce the hillock-like protrusion defects on the wiring layer of the semiconductor structure. Referring to Figures 1 to 4 , the fabrication method provided by this application includes steps S1 to S5, specifically including:
[0045] S1. Provide a semiconductor substrate 11, and one side of the semiconductor substrate 11 has a dielectric layer 111;
[0046] S2. Form a first barrier layer 121 and a trench 1111 on the dielectric layer 111. The first barrier layer 121 covers the dielectric layer 111, and the trench 1111 penetrates through the dielectric layer 111 and the first barrier layer 121;
[0047] S3. Form a wiring layer 122 on the first barrier layer 121, and fill the trench 1111 with the wiring layer 122;
[0048] S4. Remove the wiring layer 122 and the first barrier layer 121 located on the first barrier layer 121, and expose the dielectric layer 111;
[0049] S5. Anneal the wiring layer 122.
[0050] Referring to Figure 5 and Figure 6 , Figure 5 shows a top-view structural schematic diagram of the hillock-like protrusion defects on the surface of the semiconductor structure, Figure 6 shows along the semiconductor structure Figure 2The cross-sectional view cut by a line segment in [the figure] shows that there are numerous grain boundaries in the wiring layer 122. After removing the wiring layer 122 on the first barrier layer 121 and the first barrier layer 121, during the subsequent thermal process, the wiring layer 122 is prone to grain boundary merging when heated. Grain boundary merging will cause grain protrusions to form bulges, resulting in mound-like protrusion defects on the surface of the wiring layer 122. In the preparation method of the present application, by annealing the wiring layer 122 after removing the wiring layer 122 on the first barrier layer 121 and the first barrier layer 121 and before performing other processes, the stress between different grains of the wiring layer 122 can be released in advance, reducing the protrusions caused by grain boundary merging, and thus effectively reducing the mound-like protrusion defects caused by the heating of the wiring layer 122 during the subsequent thermal process.
[0051] The present application also provides a semiconductor structure prepared by using the above preparation method. Referring to Figure 4 , the semiconductor structure of the present application includes a semiconductor substrate 11 and a wiring layer 122. One side of the semiconductor substrate 11 has a dielectric layer 111, and a trench 1111 is formed in the dielectric layer 111. The trench 1111 penetrates the dielectric layer 111, and the wiring layer 122 is filled in the trench 1111; optionally, the depth of the trench 1111 in the semiconductor structure is greater than the thickness of the wiring layer 122, so that the trench 1111 extends into the semiconductor substrate 11 on one side of the dielectric layer 111 to achieve electrical interconnection between various devices in the semiconductor structure.
[0052] In order to elaborate on the semiconductor structure and its preparation method of the present application in more detail, the technical solutions of the present application will be described below in conjunction with specific embodiments. It should be noted that, without conflict, the technical features and technical solutions in each embodiment can be combined and used with each other.
[0053] Embodiment 1
[0054] This embodiment provides a preparation method of a semiconductor structure. Referring to Figures 1 to 4 , it includes steps S1 to S5, specifically including:
[0055] S1. Provide a semiconductor substrate 11, and one side of the semiconductor substrate 11 has a dielectric layer 111;
[0056] S2. Form a first barrier layer 121 and a trench 1111 on the dielectric layer 111. The first barrier layer 121 covers the dielectric layer 111, and the trench 1111 penetrates the dielectric layer 111 and the first barrier layer 121;
[0057] S3. Form a wiring layer 122 on the first barrier layer 121 and fill the trench 1111 with the wiring layer 122;
[0058] S4. Remove the wiring layer 122 and the first barrier layer 121 on the first barrier layer 121, and expose the dielectric layer 111;
[0059] S5. Anneal the wiring layer 122.
[0060] In step S1, referring to Figure 2 , the semiconductor substrate 11 is any semiconductor product for the subsequent copper interconnect process. The semiconductor substrate 11 may include, for example, a semiconductor substrate and an active device layer formed on the semiconductor substrate, or the semiconductor substrate 11 may also adopt other suitable structures. The dielectric layer 111 is preferably a low-k dielectric layer 111, which can effectively reduce the influence of parasitic capacitance and improve the signal delay problem between metal wires. The material of the dielectric layer 111 may be, for example, a silicate compound, a methyl silicate compound, and other suitable materials. For example, the dielectric layer 111 is a BD (Black Diamond) layer with a dielectric constant of 2.55. The dielectric layer 111 can be formed by chemical vapor deposition process or other suitable processes.
[0061] In step S2 of this embodiment, referring to Figure 2 and Figure 3 , the first barrier layer 121 is used to avoid damage to the dielectric layer 111 caused by mechanical stress during the subsequent removal of the redundant wiring layer 122. Since the dielectric layer 111 is relatively soft in texture, it is easy to damage the dielectric layer 111 during subsequent etching or polishing processes, resulting in poor consistency of parasitic resistance. By depositing and forming the first barrier layer 121 on the surface of the dielectric layer 111, the dielectric layer 111 can be protected, and damage to the dielectric layer 111 during subsequent manufacturing processes can be effectively reduced or prevented. The constituent material of the first barrier layer 121 may be, for example, TEOS (tetraethyl orthosilicate) or other suitable materials. The first barrier layer 121 can be deposited by chemical vapor deposition process or other suitable processes. Optionally, the first barrier layer 121 is, for example, a TEOS layer, and at least part of the structural layer in the first barrier layer 121 can be used as an intermetal dielectric layer to reduce the diffusion of copper in the wiring layer 122 into the dielectric layer 111.
[0062] In an alternative embodiment, the wiring layer 122 is a copper wiring layer 122. After performing step S2 to form the first barrier layer 121, it may further include the step of forming a metal mask layer on the first barrier layer 121 to reduce the diffusion of copper in the wiring layer 122 into the dielectric layer 111; the constituent material of the metal mask layer may be, for example, titanium, titanium nitride, or other suitable materials. The trench 1111 is used to fill and form the wiring layer 122 subsequently. The trench 1111 penetrates through the first barrier layer 121 and the dielectric layer 111 and extends into the semiconductor substrate 11 on the side of the dielectric layer 111 away from the first barrier layer 121. The trench 1111 can be formed by photolithography process or other suitable means.
[0063] In step S3, referring to Figure 3 , the wiring layer 122 is a metal layer. Optionally, the wiring layer 122 is, for example, a copper wiring layer 122. The wiring layer 122 can be formed by electroplating or other suitable processes. The wiring layer 122 is formed on the first barrier layer 121 and fills the trench 1111 to achieve electrical interconnection between various devices within the semiconductor structure. Optionally, the wiring layer 122 is a copper wiring layer 122. The step of forming the wiring layer 122 in step S3 may further include forming a seed layer on the first barrier layer 121 and on the surface of the trench 1111 for subsequent growth of the copper wiring layer 122. For the specific formation method of the copper wiring layer 122, please refer to the prior art, and it will not be elaborated in detail in this embodiment.
[0064] In step S4, referring to Figure 4 , the CMP process is used to polish the wiring layer 122 formed in step S3 and the first barrier layer 121 formed in step S2 respectively, so as to remove the wiring layer 122 on the first barrier layer 121 and the first barrier layer 121 to expose the dielectric layer 111. Optionally, in the step of removing the first barrier layer 121 in step S4, it further includes removing a part of the dielectric layer 111 and a part of the wiring layer 122 to planarize the surfaces of the dielectric layer 111 and the wiring layer 122.
[0065] In an alternative embodiment, performing step S4 to remove the wiring layer 122 on the first barrier layer 121 and the first barrier layer 121 includes the following steps: using a first polishing liquid under a first polishing pressure to perform CMP processing on the wiring layer 122 to remove a part of the wiring layer 122 on the first barrier layer 121; using the first polishing liquid under a second polishing pressure to perform CMP processing on the wiring layer 122 to remove the remaining wiring layer 122 on the first barrier layer 121 and expose the first barrier layer 121; using a second polishing liquid to perform CMP processing on the first barrier layer 121 to remove the first barrier layer 121 and expose the dielectric layer 111.
[0066] Further, the wiring layer 122 is a copper wiring layer 122, the first polishing pressure is greater than the second polishing pressure, the first polishing liquid is a copper polishing liquid, and the second polishing liquid is a barrier layer polishing liquid; the first polishing pressure is a high polishing pressure, and the copper polishing liquid is a polishing liquid for grinding a copper substrate. Under the first polishing pressure, using the first polishing liquid and a polishing pad for grinding a copper substrate, CMP treatment is performed on the wiring layer 122 to quickly remove a large amount of the wiring layer 122; the second polishing pressure is a low polishing pressure. Under the second polishing pressure, using the first polishing liquid and a polishing pad for grinding a copper substrate, CMP treatment is performed on the wiring layer 122 to remove the remaining wiring layer 122 on the first barrier layer 121; the barrier layer polishing liquid is a polishing liquid for grinding the first barrier layer 121. Using the second polishing liquid to perform CMP treatment on the first barrier layer 121 to remove the first barrier layer 121 and a part of the wiring layer 122, thereby exposing the dielectric layer 111 and achieving surface planarization of the dielectric layer 111 and the wiring layer 122.
[0067] In step S5, the wiring layer 122 after CMP is annealed to release the stress between the grains in the wiring layer 122 and reduce the protrusions caused by grain boundary coalescence. The wiring layer 122 can be annealed in a nitrogen atmosphere. Optionally, for example, the wiring layer 122 can also be annealed in an argon, helium, or other suitable inert gas atmosphere.
[0068] In an alternative embodiment, the wiring layer 122 is a copper wiring layer 122. In the step of annealing the wiring layer 122 in step S5, the annealing temperature is 350°C to 400°C. The annealing temperature can be, for example, 350°C, 360°C, 370°C, 380°C, 390°C, 400°C, or other suitable temperatures to achieve sufficient release of the stress between different copper grains in the copper wiring layer 122. By controlling the annealing temperature of the wiring layer 122 within a suitable range, it helps to fully release the residual stress between different copper grains in the copper wiring layer 122; when the annealing temperature is too high, it will cause a decrease in the performance of the wiring layer 122, and in severe cases, it will cause damage to the device, affecting the working performance and reliability of the wiring layer 122; when the annealing temperature is too low, the residual stress between different copper grains cannot be fully released, reducing the improvement effect on copper hillock defects.
[0069] In an alternative embodiment, the wiring layer 122 is a copper wiring layer 122. In the step of annealing the wiring layer 122 in step S5, the annealing time is 3 min to 5 min. The annealing time can be, for example, 3 min, 3.5 min, 4 min, 4.5 min, 5 min or other suitable durations to fully release the stress between different copper grains in the copper wiring layer 122. By controlling the annealing time of the wiring layer 122 within a suitable range, it helps to fully release the residual stress between different copper grains in the copper wiring layer 122. When the annealing time is too long, it will increase the time and production cost, and at the same time, it may increase the risk of having an adverse impact on the working performance of the wiring layer 122. When the annealing time is too short, the residual stress between different copper grains cannot be fully released, reducing the improvement effect on the copper hillock defects.
[0070] In an alternative embodiment, referring to Figure 7 and Figure 8 , after completing the step of annealing the wiring layer 122 in step S5, the following steps are further included: S6. Perform CMP processing on the wiring layer 122 in the trench 1111 to form a groove 1221 on the side of the wiring layer 122 away from the bottom of the trench 1111. The groove 1221 can form a step structure between the upper surface of the wiring layer 122 and the upper surface of the dielectric layer 111. Optionally, perform CMP processing on the wiring layer 122 in the trench 1111 to remove part of the wiring layer 122 and part of the dielectric layer 111, so as to form a groove 1221 between the dielectric layer 111 and the upper surface of the wiring layer 122. Further, the wiring layer 122 is a copper wiring layer 122. The CMP processing can be performed on the wiring layer 122 in the trench 1111 by using a first polishing liquid and a polishing pad for grinding a copper substrate to remove part of the wiring layer 122 and part of the dielectric layer 111 adjacent to the wiring layer 122, so that a groove 1221 is formed between the remaining wiring layer 122 and the dielectric layer 111. By providing the groove 1221 to form a step structure between the upper surface of the wiring layer 122 and the dielectric layer 111, the support and protection effects on the wiring layer 122 can be improved, reducing the photoelectric diffusion and expansion of the wiring layer 122 in subsequent thermal processes and reducing the generation of hillock defects, further improving the improvement effect on the hillock defects of the wiring layer 122.
[0071] In this embodiment, referring to Figure 7 and Figure 9, after performing step S5 of annealing the wiring layer 122, the following steps are further included: S7, forming a second barrier layer 123 on the dielectric layer 111 and covering the wiring layer 122. The second barrier layer 123 covering the wiring layer 122 and the dielectric layer 111 can serve as a copper spillover barrier layer to prevent copper from diffusing into the medium. The constituent material of the second barrier layer 123 can be, for example, a metal, a metal nitride, or other suitable materials and their combinations. For example, the second barrier layer 123 can be an NDC (nitride doped silicon carbide) layer, a Ta / TaN layer, or other suitable material layers, and a deposition process or other suitable means can be used to form the second barrier layer 123. Optionally, after forming the groove 1221 on the wiring layer 122, the second barrier layer 123 is formed on the dielectric layer 111, and the second barrier layer 123 fills the groove 1221 and covers the wiring layer 122.
[0072] Embodiment 2
[0073] This embodiment provides a semiconductor structure, which is prepared by using any one of the semiconductor structure preparation methods in Embodiment 1. Refer to Figure 4 , the semiconductor structure of this embodiment includes a semiconductor substrate 11 and a wiring layer 122.
[0074] One side of the semiconductor substrate 11 has a dielectric layer 111, and a trench 1111 is provided in the dielectric layer 111. The trench 1111 penetrates the dielectric layer 111, and the wiring layer 122 fills the trench 1111. Optionally, the trench 1111 penetrates the dielectric layer 111 and extends into the semiconductor substrate 11 on one side of the dielectric layer 111, and the wiring layer 122 fills the trench 1111 for realizing electrical interconnection between devices in the semiconductor structure.
[0075] In this embodiment, refer to Figure 8 , a groove 1221 is formed on one side of the wiring layer 122 away from the bottom of the trench 1111. The groove 1221 is surrounded by the upper surface of the dielectric layer 111 and the wiring layer 122. The distance between the upper surface of the dielectric layer 111 and the bottom of the trench 1111 is less than the distance between the upper surface of the dielectric layer 111 and the bottom of the trench 1111 to form the above groove 1221. Among them, the upper surface of the dielectric layer 111 is the surface of the dielectric layer 111 away from the side in contact with the semiconductor substrate 11, and the upper surface of the wiring layer 122 is the surface of the wiring layer 122 away from the bottom of the trench 1111. Optionally, the width of the groove 1221 is greater than or equal to the width of one end of the wiring layer 122 away from the bottom of the trench 1111. Looking down at the semiconductor structure along the thickness direction of the semiconductor substrate 11, the projection surface of the wiring layer 122 is located within the contour of the trench 1111, so as to facilitate polishing to form the above groove 1221 and ensure the flatness of the upper surface of the wiring layer 122.
[0076] In an alternative embodiment, a stepped structure is formed between the bottom of the groove 1221 and the upper surface of the dielectric layer 111, and the height of the stepped structure is wherein the height of the stepped structure is the height of the stepped structure along the thickness direction of the semiconductor substrate 11. Optionally, the height of the stepped structure can be, for example, or other suitable values. When the above-mentioned step height is too large, the contact resistance of the wiring layer 122 will increase, reducing the working performance of the wiring layer 122. When the step height is too small, the effect of the dielectric layer 111 on supporting the wiring layer 122 and passivating copper diffusion will be reduced, thereby reducing the improvement effect on the hillock bulge defect. It can be seen that by forming the groove 1221 between the upper part of the wiring layer 122 and the dielectric layer 111 and controlling the stepped structure formed by the bottom of the groove 1221 and the dielectric layer 111 to have a suitable height, the wiring layer 122 can be fully wrapped, so that the dielectric layer 111 can better provide protection and support for the wiring layer 122, reduce the diffusion and expansion of the wiring layer 122 during the subsequent thermal process, and further reduce the hillock bulge defect generated by the copper wiring layer 122.
[0077] In this embodiment, referring to Figure 9 , the semiconductor structure may further include a second barrier layer 123, and the second barrier layer 123 is formed on the dielectric layer 111 and covers the wiring layer 122. Optionally, the side of the wiring layer 122 away from the bottom of the trench 1111 has a groove 1221, and the second barrier layer 123 covers the dielectric layer 111 and fills the groove 1221 to cover the wiring layer 122.
[0078] The semiconductor structure in this embodiment is prepared by using any one of the preparation methods in Embodiment 1. Therefore, the semiconductor structure in this embodiment also has the beneficial effects of Embodiment 1.
[0079] The above embodiments merely illustrate the principles and effects of the present application and are not used to limit the present application. Any person familiar with this technology can modify, change or combine the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present application should still be covered by the claims of the present application.
Claims
1. A method for preparing a semiconductor structure, characterized in that, It includes the following steps: Provide a semiconductor substrate, one side of which has a dielectric layer; Form a first barrier layer and a trench on the dielectric layer, the first barrier layer covering the dielectric layer, and the trench penetrating through the dielectric layer and the first barrier layer; Form a wiring layer on the first barrier layer and fill the trench with the wiring layer; Remove the wiring layer on the first barrier layer and the first barrier layer, and expose the dielectric layer; Anneal the wiring layer.
2. The manufacturing method of the semiconductor structure according to claim 1, wherein, Removing the wiring layer on the first barrier layer and the first barrier layer includes the following steps: Use a first polishing liquid under a first polishing pressure to perform CMP processing on the wiring layer to remove a part of the wiring layer on the first barrier layer; Use the first polishing liquid under a second polishing pressure to perform CMP processing on the wiring layer to remove the remaining wiring layer on the first barrier layer and expose the first barrier layer; Use a second polishing liquid to perform CMP processing on the first barrier layer to remove the first barrier layer and expose the dielectric layer.
3. The manufacturing method of the semiconductor structure according to claim 1, wherein, In the step of annealing the wiring layer, the annealing temperature is 350°C to 400°C.
4. The method for manufacturing a semiconductor structure according to claim 1, wherein, In the step of annealing the wiring layer, the annealing time is 3 min to 5 min.
5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, After annealing the wiring layer, it further includes the following steps: Perform CMP processing on the wiring layer in the trench to form a groove on the side of the wiring layer away from the bottom of the trench.
6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, After annealing the wiring layer, it further includes the following steps: Form a second barrier layer on the dielectric layer and cover the wiring layer.
7. A semiconductor structure prepared by using the preparation method according to any one of claims 1 to 6, characterized in that, It includes: A semiconductor substrate, one side of which has a dielectric layer, and the dielectric layer has a trench that penetrates through the dielectric layer; A wiring layer filled in the trench.
8. The semiconductor structure according to claim 7, wherein, The side of the wiring layer away from the bottom of the trench has a groove, and the width of the groove is greater than or equal to the width of the end of the wiring layer away from the bottom of the trench.
9. The semiconductor structure according to claim 8, wherein A stepped structure is formed between the bottom of the groove and the upper surface of the dielectric layer, and the height of the stepped structure is 10. The semiconductor structure according to claim 7, wherein, It further includes a second barrier layer, which is formed on the dielectric layer and covers the wiring layer.