Semiconductor device and semiconductor package having redistribution lines

Abstract

The invention relates to a semiconductor device and a semiconductor package having redistribution lines. A semiconductor device includes: a semiconductor chip having a chip pad; a redistribution line disposed on the semiconductor chip; and a first dielectric layer disposed on the semiconductor chip and the redistribution line. The redistribution wire is connected to the chip pad and has a wire bond pad section. The first dielectric layer has a first opening exposing the wire bond pad section. The redistribution line includes a copper layer, a nickel layer on the copper layer, and a gold layer on the nickel layer. A side surface of the nickel layer protrudes beyond a side surface of the copper layer.

Description

Technical Field

[0001] Various embodiments of the disclosed technology generally relate to a semiconductor device and a semiconductor package having redistribution lines. Background Art

[0002] A semiconductor device includes an integrated circuit for storing or processing data and has chip pads for inputting data to the integrated circuit or outputting data of the integrated circuit to the outside.

[0003] The semiconductor device may include a redistribution line (RDL) pattern. The redistribution line may be electrically connected to the chip pad and may extend from the area where the chip pad is provided to another area. The redistribution line may extend the chip pad substantially to a connection point with an electrical connection member such as a lead and / or a bump. Through the redistribution line, the connection point where the connection member is connected to the semiconductor device may be changed to a position separated from the position of the chip pad. Summary of the Invention

[0004] In an embodiment, a semiconductor device may include: a semiconductor chip having chip pads; a redistribution line provided on the semiconductor chip; and a first dielectric layer provided on the semiconductor chip and the redistribution line. The redistribution line is connected to the chip pads and has a wire bond pad section. The first dielectric layer has a first opening exposing the wire bond pad section. The redistribution line includes a copper layer, a nickel layer on the copper layer, and a gold layer on the nickel layer. A side surface of the nickel layer protrudes beyond a side surface of the copper layer.

[0005] In an embodiment, a semiconductor device may include: a semiconductor chip; a redistribution line provided on the semiconductor chip; and a first dielectric layer provided on the semiconductor chip and the redistribution line. The redistribution line has a wire bond pad section. The first dielectric layer has a first opening exposing the wire bond pad section. The redistribution line includes a conductive layer, a barrier metal layer on the conductive layer, and a bonding metal layer on the barrier metal layer. The barrier metal layer has a flange section that protrudes beyond a side surface of the conductive layer.

[0006] In an embodiment, a semiconductor package may include: a first semiconductor device including a first semiconductor chip, redistribution lines disposed on the first semiconductor chip, and a first dielectric layer disposed on the first semiconductor chip and the redistribution lines; and a second semiconductor device stacked on the first semiconductor device. The redistribution lines have a wire bonding pad section and a bump bonding pad section. The first dielectric layer has a first opening exposing the wire bonding pad section and a second opening exposing the bump bonding pad section. The second semiconductor device includes a second semiconductor chip and conductive bumps connected to the second semiconductor chip. The conductive bumps are bonded to the bump bonding pad section of the redistribution lines. The redistribution lines include a conductive layer, a barrier metal layer disposed on the conductive layer, and a bonding metal layer disposed on the barrier metal layer. Side surfaces of the barrier metal layer protrude beyond side surfaces of the conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic plan view of a semiconductor device according to an embodiment of the disclosed technology.

[0008] Figure 2 is a cross-sectional view of an embodiment taken along line Figure 1 A-A' thereof.

[0009] Figure 3 is an enlarged plan view showing redistribution lines and a first dielectric layer of a semiconductor device according to an embodiment of the disclosed technology.

[0010] Figure 4 is a cross-sectional view of an embodiment taken along line Figure 3 B-B' thereof.

[0011] Figure 5 is a cross-sectional view of an embodiment taken along line Figure 3 C-C' thereof.

[0012] Figure 6 is a cross-sectional view of an embodiment taken along line Figure 3 D-D' thereof.

[0013] Figure 7 is a cross-sectional view of an embodiment taken along line Figure 3 E-E' thereof.

[0014] Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 and Figure 13 are views showing a method of forming a semiconductor device according to an embodiment of the disclosed technology.

[0015] Figure 14It is a cross-sectional view of a semiconductor package according to an embodiment of the disclosed technology. Detailed Embodiment

[0016] Hereinafter, embodiments of the disclosed technology will be described in detail with reference to the accompanying drawings. In the following description, although shown in different drawings, the same elements will be referred to by the same reference numerals. In addition, in the following description of the present disclosure, detailed descriptions of known functions and configurations included herein will be omitted when they may obscure the subject matter of the present disclosure. It should be noted that, unless otherwise specifically stated, the terms "comprising", "having", "including", etc. used in the specification and claims should not be construed as being limited to the means listed thereafter. When an indefinite article or a definite article (e.g., "a", "an", and "the") is used in reference to a singular noun, this may include the plural of the noun unless otherwise specifically stated.

[0017] In addition, when describing components of the present disclosure, terms similar to first, second, A, B, (a), and (b) may be used. These are only for distinguishing one component from another, and do not limit the substance, order, sequence, or quantity of the components.

[0018] In the description of the positional relationship of components, when describing that at least two components are "connected", "coupled", or "linked", it will be understood that at least two components may be directly "connected", "coupled", or "linked", but may be indirectly "connected", "coupled", or "linked" when another component is interposed between the two components. Here, the other component may be included in at least one of the at least two components that are "connected", "coupled", or "linked" to each other. It will be understood that when an element or layer, etc. is referred to as being "on", "connected to", or "coupled to" another element or layer, etc., it may be directly on the other element or layer, directly connected or coupled to the other element or layer, or there may be intermediate elements or layers, etc. Conversely, when an element or layer, etc. is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, etc., there are no intermediate elements or layers, etc. The same reference numerals always refer to the same elements. For ease of description, spatial relative terms such as "below", "above", "beneath", "under", "upper", etc. may be used herein to describe the relationship of one element or feature to another element or feature shown in the figures. It will be understood that, in addition to the orientation depicted in the figures, the spatial relative terms are intended to also cover different orientations of the device during use or operation. For example, if the device in the figure is flipped, an element described as being "below" or "beneath" other elements or features will be oriented "above" the other elements or features. Thus, examples of the term "below" may cover both the upper and lower orientations. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative descriptive terms used herein are to be interpreted accordingly.

[0019] In the description of the temporal flow relationship for a component, a method of operation, or a method of manufacture, in cases where the "before" and "after" relationships in terms of time or the "before" and "after" relationships in terms of process are described, for example, by "after", "subsequently", "next", or "before", non-consecutive cases may be included unless "immediately" or "directly" is used.

[0020] In cases where a numerical value of a component or its corresponding information (e.g., height, etc.) is mentioned, even without a separate explicit description, the numerical value or its corresponding information may be interpreted as including an error range that can be caused by various factors (e.g., process variables, internal or external shocks, noise, etc.).

[0021] Hereinafter, various embodiments of the disclosed technology will be described in detail with reference to the accompanying drawings.

[0022] Various embodiments of the disclosed technology are directed to providing a semiconductor device and a semiconductor package having redistribution lines.

[0023] According to various embodiments of the disclosed technology, a semiconductor device and a semiconductor package having redistribution lines with lead bonding pads can be provided.

[0024] Figure 1 is a schematic plan view of a semiconductor device based on an embodiment of the disclosed technology, Figure 2 is along Figure 1 a cross-sectional view of the embodiment taken along line A-A'.

[0025] Referring to Figure 1 and Figure 2 Based on an embodiment of the disclosed technology, the semiconductor device 100 may include a semiconductor chip 10, a plurality of redistribution lines 20, and a first dielectric layer 30.

[0026] An integrated circuit (not shown) including unit transistors may be integrated into the semiconductor chip 10. The semiconductor chip 10 has a plurality of chip pads 10A. The chip pads 10A may be electrically connected to the integrated circuit through an interconnect pattern (not shown) within the semiconductor chip 10. The chip pads 10A are provided as connection terminals for electrically connecting the semiconductor chip 10 to an external device.

[0027] The chip pad 10A can be disposed in the first region R1 of the semiconductor chip 10. The first region R1 can be the central region of the semiconductor chip 10 in the X-axis direction of the X-Y plane. The semiconductor chip 10 can be a central pad type semiconductor chip. The chip pad 10A can be arranged in two columns in the Y-axis direction of the X-Y plane in the first region R1 of the semiconductor chip 10. However, the disclosed technology is not limited to this, and the arrangement of the chip pad 10A can be changed in various ways. Figure 1 The second region R2 and the third region R3, which are two edge regions of the semiconductor chip 10 in the X-axis direction, can be spaced apart from the first region R1 in the X-axis direction.

[0028] The semiconductor chip 10 can include non-volatile memories such as NAND flash memory, NOR flash memory, PRAM (phase change random access memory), and MRAM (magnetoresistive random access memory), volatile memories such as DRAM (dynamic random access memory) and SRAM (static random access memory), or processors such as CPU (central processing unit), GPU (graphics processing unit), AP (application processor), and NPU (neural processing unit).

[0029] The redistribution lines 20 can be disposed on the semiconductor chip 10. The redistribution lines 20 can extend from the first region R1 of the semiconductor chip 10 to the second region R2 or the third region R3. As Figure 1 shown, among the six redistribution lines 20, three redistribution lines 20 can extend from the first region R1 to the second region R2, and the remaining three redistribution lines 20 can extend from the first region R1 to the third region R3.

[0030] Each redistribution line 20 can include a wire bonding pad section 21, a bump bonding pad section 22, an overlapping pad section 23, and trace sections 24, 24A, and 24B that connect them to each other.

[0031] The wire bonding pad section 21 of the redistribution line 20 can be disposed on the second region R2 and the third region R3 of the semiconductor chip 10. For example, as Figure 1 shown, the wire bonding pad sections 21 of three of the six redistribution lines 20 can be disposed on the second region R2, and the wire bonding pad sections 21 of the remaining three redistribution lines 20 can be disposed on the third region R3. The overlapping pad section 23 of the redistribution line 20 can be disposed on the first region R1 of the semiconductor chip 10. The bump bonding pad section 22 of the redistribution line 20 can be disposed on the first region R1 of the semiconductor chip 10 to be spaced apart from the overlapping pad section 23.

[0032] The overlapping pad section 23 of the redistribution line 20 can overlap with the chip pad 10A of the semiconductor chip 10. The overlapping pad section 23 is electrically connected to the chip pad 10A, and the trace sections 24:24A and 24B, the wire bond pad section 21, and the bump bond pad section 22 are connected to the overlapping pad section 23. The redistribution line 20 can extend from the chip pad 10A provided in the first region R1 of the semiconductor chip 10 to the second region R2 or the third region R3 where the wire bond pad section 21 is provided.

[0033] The overlapping pad sections 23 of the redistribution line 20 can be arranged in two columns in the Y-axis direction on the first region R1 of the semiconductor chip 10. However, the disclosed technology is not limited to this, and the arrangement of the overlapping pad sections 23 can vary according to the arrangement of the chip pads 10A.

[0034] The wire bond pad sections 21 of the redistribution line 20 can be arranged in the Y-axis direction on the second region R2 and the third region R3 of the semiconductor chip 10. As Figure 1 shown, the wire bond pad sections 21 of three of the six redistribution lines 20 can be arranged in one column in the Y-axis direction on the second region R2, and the wire bond pad sections 21 of the remaining three redistribution lines 20 can be arranged in one column in the Y-axis direction on the third region R3. As Figure 1 shown, the bump bond pad sections 22 of the redistribution line 20 can be arranged in two columns in the Y-axis direction on the first region R1 of the semiconductor chip 10. The bump bond pad sections 22 of the redistribution line 20 can be arranged by being offset in the X-axis direction with respect to the chip pads 10A of the semiconductor chip 10.

[0035] The trace sections 24:24A and 24B of the redistribution line 20 can include a first trace section 24A and a second trace section 24B. The first trace section 24A can connect the wire bond pad section 21 and the bump bond pad section 22, and the second trace section 24B can connect the bump bond pad section 22 and the overlapping pad section 23.

[0036] The wire bond pad section 21 is connected to one end of the first trace section 24A, and the width can be greater than the width of the first trace section 24A.

[0037] The bump bond pad section 22 can be connected between the other end of the first trace section 24A opposite to one end of the first trace section 24A and one end of the second trace section 24B. In Figure 1In this case, the first trace section 24A and the second trace section 24B have a constant width, and the bump bonding pad section 22 has a smaller width compared to the first trace section 24A and the second trace section 24B. However, the embodiments of the disclosed technology are not limited thereto. The widths of the first trace section 24A and the second trace section 24B may not be constant, and the width of the bump bonding pad section 22 may have a size that is smaller than the maximum width of the first trace section 24A and the second trace section 24B and larger than their minimum width.

[0038] The overlapping pad section 23 may be connected to the other end of the second trace section 24B opposite to one end of the second trace section 24B, and may have a larger width compared to the second trace section 24B.

[0039] The second dielectric layer 40 having an opening exposing the chip pad 10A may be disposed on the semiconductor chip 10. The second dielectric layer 40 may cover the top surface of the semiconductor chip 10 and may expose the chip pad 10A. The second dielectric layer 40 may electrically isolate the redistribution lines 20 from the semiconductor chip 10. The second dielectric layer 40 may include a photosensitive polymer material such as polyimide.

[0040] The redistribution lines 20 may be disposed on the second dielectric layer 40 and the chip pad 10A exposed through the opening of the second dielectric layer 40. The redistribution lines 20 may be configured to include a conductive layer 2, a barrier metal layer 3 located on the conductive layer 2, and a bonding metal layer 4 located on the barrier metal layer 3. In addition, the redistribution lines 20 may further include a base metal layer 1 located below the conductive layer 2.

[0041] The base metal layer 1 may be disposed on the surface of the second dielectric layer 40 and the surface of the chip pad 10A. The base metal layer 1 may be disposed between the conductive layer 2 and the second dielectric layer 40. The base metal layer 1 may extend to be disposed between the conductive layer 2 and the chip pad 10A. The base metal layer 1 may contact the chip pad 10A of the semiconductor chip 10 and may electrically connect the chip pad 10A and the conductive layer 2.

[0042] The base metal layer 1 may be attached to the second dielectric layer 40, the chip pad 10A, and the conductive layer 2. The base metal layer 1 may inhibit the diffusion of the metal included in the conductive layer 2 into the semiconductor chip 10. The base metal layer 1 may provide a base for the redistribution lines 20. The base metal layer 1 may include titanium (Ti) or titanium tungsten (TiW). The base metal layer 1 may be a titanium layer.

[0043] The conductive layer 2 may be disposed on the top surface 1T of the base metal layer 1. The conductive layer 2 includes a bottom surface 2B facing the top surface 1T of the base metal layer 1, a top surface 2T opposite to the bottom surface 2B, and side surfaces 2S connecting the edges of the bottom surface 2B and the edges of the top surface 2T. The outer peripheral section of the conductive layer 2 has an overhanging structure not supported by the underlying base metal layer 1. The outer peripheral section of the conductive layer 2 has an overhanging structure continuous along the side surface 1S of the base metal layer 1. The side surface 2S of the conductive layer 2 may protrude beyond the side surface 1S of the base metal layer 1. The conductive layer 2 may include copper (Cu). The conductive layer 2 may be a copper layer.

[0044] The barrier metal layer 3 is disposed on the top surface 2T of the conductive layer 2. The barrier metal layer 3 includes a bottom surface 3B facing the top surface 2T of the conductive layer 2, a top surface 3T opposite to the bottom surface 3B, and side surfaces 3S connecting the edges of the bottom surface 3B and the edges of the top surface 3T.

[0045] As will be described later, the bonding metal layer 4 may include gold. When solder is bonded to the bump bonding pad section 22, the gold in the bonding metal layer 4 may disappear by diffusing into the solder. In an embodiment, the copper of the conductive layer 2 may diffuse to the interface with the solder, and thus, an intermetallic compound may be generated. The barrier metal layer 3 may inhibit the copper of the conductive layer 2 from diffusing to the interface with the solder to reduce the consumption of the copper of the conductive layer 2 and prevent or mitigate the formation of a thick intermetallic compound. The barrier metal layer 3 may be made of a metal material that adheres to the copper of the conductive layer 2 and the gold (Au) of the bonding metal layer 4. The barrier metal layer 3 may include nickel (Ni). The barrier metal layer 3 may be a nickel layer.

[0046] The barrier metal layer 3 has a flange section OH that protrudes beyond the side surface 2S of the conductive layer 2. The flange section OH of the barrier metal layer 3 has an overhanging structure not supported by the underlying conductive layer 2. The flange section OH of the barrier metal layer 3 has an overhanging structure continuous along the side surface 2S of the conductive layer 2. The side surface 3S of the barrier metal layer 3 may protrude beyond the side surface 2S of the conductive layer 2.

[0047] The bonding metal layer 4 is disposed on the top surface 3T of the barrier metal layer 3. The bonding metal layer 4 includes a bottom surface 4B facing the top surface 3T of the barrier metal layer 3, a top surface 4T opposite to the bottom surface 4B, and side surfaces 4S connecting the edges of the bottom surface 4B and the edges of the top surface 4T. As Figure 2 shown, the side surface 4S of the bonding metal layer 4 may be aligned with the side surface 3S of the barrier metal layer 3, but the embodiments of the disclosed technology are not limited thereto.

[0048] The bonding metal layer 4 may include a metal capable of wire bonding. The bonding metal layer 4 may include gold (Au). The bonding metal layer 4 may be a gold layer.

[0049] The first dielectric layer 30 may be disposed on the second dielectric layer 40 and the redistribution lines 20. The first dielectric layer 30 may extend on the top surface of the bonding metal layer 4 to expose the lead bonding pad section 21. The first dielectric layer 30 may protect the redistribution lines 20. The first dielectric layer 30 may include a photosensitive polymer material such as polyimide.

[0050] The first dielectric layer 30 covers the overlapping pad section 23 and the trace section 24 of the redistribution lines 20, and has openings OP1 and OP2 that expose the lead bonding pad section 21 and the bump bonding pad section 22 of the redistribution lines 20. The openings OP1 and OP2 include a first opening OP1 that exposes the lead bonding pad section 21 and a second opening OP2 that exposes the bump bonding pad section 22.

[0051] The first opening OP1 is arranged to individually expose the lead bonding pad section 21 of the redistribution lines 20. The first openings OP1 correspond one-to-one with the lead bonding pad sections 21, and each first opening OP1 may expose the corresponding lead bonding pad section 21. Although not shown, metal leads may be bonded to the surface of the lead bonding pad section 21 exposed through the first opening OP1 of the first dielectric layer 30. The metal leads may be connected to the lead bonding pad sections 21, and may be electrically connected to the chip pads 10A via the first trace section 24A, the second trace section 24B, and the bump bonding pad section 22.

[0052] As Figure 1 shown, the second opening OP2 may be configured in the form of a line extending in the Y-axis direction to simultaneously expose the bump bonding pad sections 22 arranged in a line in the Y-axis direction. Corresponding to the arrangement structure of the bump bonding pad sections 22 arranged in two columns in the Y-axis direction, two columns of second openings OP2 in the form of lines extending in the Y-axis direction may be configured in the first dielectric layer 30. Conductive bumps may be bonded to the surface of the bump bonding pad section 22 exposed through the second opening OP2 of the first dielectric layer 30. The conductive bumps may be connected to the bump bonding pad sections 22, and may be electrically connected to the chip pads 10A via the second trace section 24B.

[0053] Figure 3 is an enlarged plan view of the redistribution lines and the first dielectric layer of a semiconductor device showing an embodiment based on the disclosed technology, Figure 4 is a cross-sectional view taken along line B-B’ of Figure 3 , Figure 5 is a cross-sectional view taken along line C-C’ of Figure 3 , Figure 6 is a cross-sectional view taken along line D-D’ of Figure 3 , Figure 7 is a cross-sectional view taken along line E-E’ of Figure 3 .

[0054] Reference Figures 3 to 5 , in the wire bonding pad section 21, the flange section OH of the barrier metal layer 3 protrudes beyond the side surface 2S of the conductive layer 2. In the wire bonding pad section 21, the flange section OH of the barrier metal layer 3 has a hanging structure not supported by the underlying conductive layer 2. The width of the flange section OH of the barrier metal layer 3 in the wire bonding pad section 21 may be d1. In the wire bonding pad section 21, the flange section OH of the barrier metal layer 3 has a hanging structure continuous along the side surface 2S of the conductive layer 2.

[0055] In the wire bonding pad section 21, the side surface 3S of the barrier metal layer 3 may protrude beyond the side surface 2S of the underlying conductive layer 2. In the wire bonding pad section 21, the side surface 3S of the barrier metal layer 3 may be spaced apart from the side surface 2S of the underlying conductive layer 2 by a distance d1. In the wire bonding pad section 21, the edge section of the bottom surface 3B of the barrier metal layer 3 connecting the side surface 3S and the side surface 2S of the conductive layer 2 does not overlap with the conductive layer 2.

[0056] In the wire bonding pad section 21, the outer peripheral section of the conductive layer 2 has a hanging structure not supported by the underlying base metal layer 1. In the wire bonding pad section 21, the outer peripheral section of the conductive layer 2 has a hanging structure continuous along the side surface 1S of the base metal layer 1. In the wire bonding pad section 21, the side surface 2S of the conductive layer 2 may protrude beyond the side surface 1S of the base metal layer 1.

[0057] The first dielectric layer 30 is provided to cover the side surface of the wire bonding pad section 21. Specifically, the first dielectric layer 30 is provided to cover the side surface 4S of the bonding metal layer 4, the side surface 3S of the barrier metal layer 3, the side surface 2S of the conductive layer 2, and the side surface 1S of the base metal layer 1 in the wire bonding pad section 21. Additionally, the first dielectric layer 30 is provided to cover the edge section of the bottom surface 3B of the barrier metal layer 3 between the side surface 2S of the conductive layer 2 and the side surface 3S of the barrier metal layer 3 in the wire bonding pad section 21.

[0058] In the wire bonding pad section 21, in an embodiment, the first dielectric layer 30 may cover the side surface 3S of the barrier metal layer 3 to prevent or mitigate the formation of a layer that serves as a metal diffusion path. If the side surface 3S of the barrier metal layer 3 is exposed, as process by-products combine with the exposed side surface 3S in subsequent processes, a metal inorganic compound may be formed. When the barrier metal layer 3 includes nickel, the metal inorganic compound may be nickel sulfide in which nickel combines with sulfur. The layer of the metal inorganic compound may provide a path through which the metal of the conductive layer 2 moves. When the conductive layer 2 includes copper, as copper is ionized, the copper may diffuse into the bonding metal layer 4. In an embodiment, the diffused copper may be oxidized again, resulting in discoloration of the surface of the bonding metal layer 4 and hindering the bonding of the metal wire to the bonding metal layer 4. In an embodiment, since the first dielectric layer 30 inhibits the formation of a metal diffusion path, the occurrence of discoloration of the surface of the bonding metal layer 4 or the defect that the metal wire falls off without bonding to the bonding metal layer 4 may be inhibited or prevented.

[0059] The first dielectric layer 30 may extend to cover an edge section of the top surface 4T of the bonding metal layer 4 in the wire bonding pad section 21. Accordingly, the edge EG of the first opening OP1 may be spaced apart from the side surface 4S of the bonding metal layer 4. As Figure 4 shown, the edge EG of the first opening OP1 may be spaced apart from the side surface 4S of the bonding metal layer 4 by a distance d2. The edge EG of the first opening OP1 may be disposed on the top surface 4T of the bonding metal layer 4, and the first dielectric layer 30 may continuously cover the edge section of the top surface 4T of the bonding metal layer 4 along the edge EG of the first opening OP1.

[0060] The metal wire may be bonded to an exposed section of the top surface 4T of the bonding metal layer 4 of the wire bonding pad section 21 exposed through the first opening OP1 of the first dielectric layer 30. The exposed section of the top surface 4T of the bonding metal layer 4 of the wire bonding pad section 21 exposed through the first opening OP1 may be defined as a wire bonding region. The wire bonding region may be spaced apart from the flange section OH of the barrier metal layer 3 having an overhang structure by a distance d3. The magnitude of the distance d3 corresponds to the difference between the distance d2 and the distance d1. The wire bonding region may not overlap with the flange section OH of the barrier metal layer 3.

[0061] The metal element forming the conductive layer 2 may be ionized when exposed to moisture. When the conductive layer 2 includes copper, the copper of the conductive layer 2 may be ionized and then may diffuse along the surface of the conductive layer disposed between the conductive layer 2 and the wire bonding region into the wire bonding region.

[0062] According to an embodiment of the disclosed technology, by extending the first dielectric layer 30 to cover the edge section of the top surface 4T of the bonding metal layer 4 of the wire bonding pad section 21, external moisture penetration into the conductive layer 2 can be prevented or mitigated, thereby suppressing the ionization of the copper in the conductive layer 2. According to an embodiment of the disclosed technology, by configuring the side surface 3S of the barrier metal layer 3 in the wire bonding pad section 21 to protrude beyond the side surface 2S of the underlying conductive layer 2, the length of the path of the copper in the conductive layer 2 reaching the wire bonding region (i.e., the length of the diffusion path) can be increased. Based on this fact, in the embodiment, the diffusion of the copper in the conductive layer 2 into the wire bonding region can be suppressed or prevented, and defects such as discoloration of the wire bonding region and detachment of the metal wire can be suppressed or prevented.

[0063] Referring to Figure 3 , Figure 6 and Figure 7 , in the bump bonding pad section 22, the flange section OH of the barrier metal layer 3 protrudes beyond the side surface 2S of the conductive layer 2. In the bump bonding pad section 22, the flange section OH of the barrier metal layer 3 has a hanging structure not supported by the underlying conductive layer 2. The flange section OH of the barrier metal layer 3 in the bump bonding pad section 22 has a hanging structure continuous along the side surface 2S of the conductive layer 2. The width of the flange section OH of the barrier metal layer 3 in the bump bonding pad section 22 can be d1.

[0064] In the bump bonding pad section 22, the side surface 3S of the barrier metal layer 3 protrudes beyond the side surface 2S of the underlying conductive layer 2. The side surface 3S of the barrier metal layer 3 in the bump bonding pad section 22 can be spaced apart from the side surface 2S of the underlying conductive layer 2 by a distance d1. In the bump bonding pad section 22, the edge section of the bottom surface 3B of the barrier metal layer 3 connecting the side surface 3S and the side surface 2S of the conductive layer 2 does not overlap with the conductive layer 2.

[0065] In the bump bonding pad section 22, the outer peripheral section of the conductive layer 2 has a hanging structure not supported by the base metal layer 1. In the bump bonding pad section 22, the outer peripheral section of the conductive layer 2 has a hanging structure continuous along the side surface 1S of the base metal layer 1. In the bump bonding pad section 22, the side surface 2S of the conductive layer 2 protrudes beyond the side surface 1S of the underlying base metal layer 1.

[0066] The second opening OP2 of the first dielectric layer 30 is provided to expose the bump bonding pad section 22. The second opening OP2 is provided to expose the top surface 4T and the side surface 4S of the bonding metal layer 4, the side surface 3S of the barrier metal layer 3, the side surface 2S of the conductive layer 2, the edge section of the bottom surface 3B of the barrier metal layer 3 between the side surface 3S of the barrier metal layer 3 and the side surface 2S of the conductive layer 2, and the side surface 1S of the base metal layer 1 in the bump bonding pad section 22.

[0067] The bump bonding pad section 22 can be a structure to be coupled with a bump including a solder layer. In an embodiment, the solder coupling is performed at a higher temperature than the bonding lead coupling, and a thick intermetallic compound layer is formed. Therefore, in an embodiment, the copper oxide formed on the surface of the bump bonding pad section 22 may not have a significant impact on the bondability.

[0068] Figures 8 to 13 is a view showing a method of forming a semiconductor device according to an embodiment of the disclosed technology.

[0069] Referring to Figure 8 , a pre-base metal layer 1' can be formed on the semiconductor chip 10, and a seed layer 2-1 can be formed on the pre-base metal layer 1'.

[0070] A second dielectric layer 40 having an opening exposing the chip pad 10A can be further provided on the semiconductor chip 10. A pre-base metal layer 1' can be formed on the surface of the second dielectric layer 40 and the surface of the chip pad 10A exposed through the opening of the second dielectric layer 40. A seed layer 2-1 can be formed on the surface of the pre-base metal layer 1'.

[0071] The pre-base metal layer 1' and the seed layer 2-1 can be formed by a deposition method such as sputtering. The pre-base metal layer 1' can include titanium or titanium tungsten, and the seed layer 2-1 can include copper.

[0072] Referring to Figure 9 , an anti-plating pattern PR can be formed on the seed layer 2-1. The anti-plating pattern PR can be patterned to have an opening region OR that provides a template for the redistribution line 20 of Figure 2 . The anti-plating pattern PR can be patterned by forming a resist layer and selectively exposing and developing the resist layer.

[0073] In the opening region OR of the anti-plating pattern PR, the conductive layer 2-2, the barrier metal layer 3, and the bonding metal layer 4 can be sequentially grown.

[0074] The conductive layer 2-2 can be grown on the seed layer 2-1 through a plating process. The barrier metal layer 3 can be grown on the conductive layer 2-2 through a plating process. The bonding metal layer 4 can be grown on the barrier metal layer 3 through a plating process. The conductive layer 2-2 can include copper, the barrier metal layer 3 can include nickel, and the bonding metal layer 4 can include gold.

[0075] Referring to Figure 10 , the anti-plating pattern PR can be removed through a stripping process (see Figure 9 ). In the stripping process, a stripper including a sulfur (S) component can be used.

[0076] The section of the seed layer 2-1 that does not overlap with the conductive layer 2-2 can be removed. In other words, the section of the seed layer 2-1 (see Figure 9 ) that is exposed due to the removal of the anti-plating pattern PR (see Figure 9 ) can be selectively etched and removed.

[0077] Referring to Figure 11 , the side surfaces of the seed layer 2-1 and the conductive layer 2-2 can be recessed through an etching process. The seed layer 2-1 and the conductive layer 2-2 remaining after the etching process can configure the conductive layer 2.

[0078] An isotropic etching process can be used as the etching process. As a result of the etching process, a first horizontal groove HH1 can be formed below the flange section OH of the barrier metal layer 3. The first horizontal groove HH1 continuously extends along the side surface 2S of the conductive layer 2.

[0079] As the first horizontal groove HH1 is formed, the flange section OH of the barrier metal layer 3 can have an overhanging structure not supported by the conductive layer 2. The side surface 3S of the barrier metal layer 3 can be spaced apart from the side surface 2S of the conductive layer 2, and the edge section of the bottom surface 3B of the barrier metal layer 3 can be exposed between the side surface 3S of the barrier metal layer 3 and the side surface 2S of the conductive layer 2.

[0080] Referring to Figure 12 , through the etching process, the section of the pre-base metal layer 1' (see Figure 11 ) that does not overlap with the conductive layer 2 can be removed.

[0081] In the process of etching the pre-base metal layer 1' (see Figure 11 ) so that the pre-base metal layer 1' (see Figure 11 ) does not remain in the area that does not overlap with the conductive layer 2, over-etching can be performed. As a result of the over-etching, a second horizontal groove HH2 can be formed below the outer peripheral section of the conductive layer 2. Although not shown, the second horizontal groove HH2 can continuously extend along the side surface 1S of the base metal layer 1.

[0082] As the second horizontal groove HH2 is formed, the outer peripheral section of the conductive layer 2 has a hanging structure not supported by the base metal layer 1. The side surface 2S of the conductive layer 2 may be spaced apart from the side surface 1S of the base metal layer 1, and the edge section of the bottom surface 2B of the conductive layer 2 may be exposed between the side surface 2S of the conductive layer 2 and the side surface 1S of the base metal layer 1.

[0083] The base metal layer 1, the conductive layer 2, the barrier metal layer 3, and the bonding metal layer 4 may configure the redistribution line 20. The redistribution line 20 may include a wire bonding pad section 21, a bump bonding pad section 22, an overlapping pad section 23, and trace sections 24: 24A and 24B.

[0084] Referring Figure 13 , a first dielectric layer 30 may be formed to cover the redistribution line 20 and the second dielectric layer 40, and a first opening OP1 exposing the wire bonding pad section 21 of the redistribution line 20 and a second opening OP2 exposing the bump bonding pad section 22 of the redistribution line 20 may be formed in the first dielectric layer 30.

[0085] The first dielectric layer 30 may be formed to cover the overlapping pad section 23 and the trace sections 24: 24A and 24B of the redistribution line 20. The first dielectric layer 30 may extend to cover the side surface of the wire bonding pad section 21 and the edge section of the top surface of the wire bonding pad section 21. Specifically, the first dielectric layer 30 may be formed to cover the side surface 4S of the bonding metal layer 4, the side surface 3S of the barrier metal layer 3, the side surface 2S of the conductive layer 2, and the side surface 1S of the base metal layer 1 in the wire bonding pad section 21. The first dielectric layer 30 may extend to cover the edge section of the top surface 4T of the bonding metal layer 4 in the wire bonding pad section 21. Therefore, the edge EG of the first opening OP1 may be spaced apart from the side surface 4S of the bonding metal layer 4 of the wire bonding pad section 21. The first opening OP1 may not overlap with the flange section OH of the barrier metal layer 3 having a hanging structure.

[0086] The first dielectric layer 30 may be formed to fill the first horizontal groove HH1 (see Figure 12 ) and cover the bottom surface 3B of the flange section OH of the barrier metal layer 3 of the wire bonding pad section 21 that protrudes beyond the side surface 2S of the conductive layer 2 of the wire bonding pad section 21. The first dielectric layer 30 may fill the second horizontal groove HH2 (see Figure 12 ). In the wire bonding pad section 21, the outer peripheral section of the bottom surface 2B of the conductive layer 2 may protrude beyond the side surface 1S of the base metal layer 1. In the wire bonding pad section 21, the first dielectric layer 30 may be formed to cover the outer peripheral section of the bottom surface 2B of the conductive layer 2.

[0087] The second opening OP2 in the first dielectric layer 30 may be formed to expose the top surface and the side surface of the bump bonding pad section 22 (see Figure 7 ).

[0088] Specifically, in the bump bonding pad section 22 (see Figure 7 ), the second opening OP2 may be formed to expose the top surface 4T (see Figure 7 ) and the side surface 4S (see Figure 7 ) of the bonding metal layer 4 (see Figure 7 ), the side surface 3S (see Figure 7 ) of the barrier metal layer 3 (see Figure 7 ), the side surface 2S (see Figure 7 ) of the conductive layer 2 (see Figure 7 ), the bottom surface 3B (see Figure 7 ) of the barrier metal layer 3 (see Figure 7 ) of the edge section, and the side surface 1S (see Figure 7 ) of the base metal layer 1 (see Figure 7 ).

[0089] The first dielectric layer 30 may be made of a photosensitive polymer material such as polyimide, and after the first opening OP1 and the second opening OP2 are formed in the first dielectric layer 30, a baking process for baking the photosensitive polymer material may be performed.

[0090] In a state where the first dielectric layer 30 covers the side surface 3S of the barrier metal layer 3 of the wire bonding pad section 21 so that the side surface 3S of the barrier metal layer 3 of the wire bonding pad section 21 is not exposed to the outside, a baking process for baking the first dielectric layer 30 may be performed.

[0091] Therefore, in an embodiment, a layer serving as a metal diffusion path may be prevented or reduced from being generated on the side surface 3S of the barrier metal layer 3 of the wire bonding pad section 21 during the baking process. In an embodiment, when the side surface 3S of the barrier metal layer 3 is exposed, process by-products may combine with the exposed side surface 3S to form a metal inorganic compound. In an embodiment, when the barrier metal layer 3 includes nickel, the metal inorganic compound may be nickel sulfide in which nickel combines with sulfur. In an embodiment, since the baking process is performed in a state where the first dielectric layer 30 covers the side surface 3S of the barrier metal layer 3 of the wire bonding pad section 21, even when the baking process is performed in a temperature range where the remaining sulfur component may react with nickel after being used in the semiconductor device manufacturing process, nickel sulfide may be inhibited or prevented from being generated on the side surface 3S of the barrier metal layer 3 of the wire bonding pad section 21. Therefore, in an embodiment, the metal of the conductive layer 2 may be inhibited from diffusing to the bonding metal layer 4 of the wire bonding pad section 21 through nickel sulfide.

[0092] An embodiment of a semiconductor device 100 based on the disclosed technology can be used in manufacturing a semiconductor package.

[0093] Figure 14 FIG. is a cross-sectional view for explaining a semiconductor package according to an embodiment of the disclosed technology.

[0094] Referring to Figure 14 , a semiconductor package according to an embodiment of the disclosed technology may include a first semiconductor device 100A, a second semiconductor device 200A, a package substrate 300, and metal leads 400. A semiconductor package according to an embodiment of the disclosed technology may further include an adhesive layer 500, a connection structure 600, and a molding member 700.

[0095] The package substrate 300 may include circuits and / or interconnect structures for electrically connecting the first semiconductor device 100A and the second semiconductor device 200A to an external device. For example, the package substrate 300 may include a printed circuit board (PCB), an insert, a redistribution layer, etc. Top surface substrate pads 310 may be provided on the top surface of the package substrate 300. The top surface substrate pads 310 may include bonding fingers. Bottom surface substrate pads 320 for connecting to the connection structure 600 may be provided on the bottom surface of the package substrate 300. The connection structure 600 may be electrically connected to another semiconductor package or a printed circuit board. The connection structure 600 may include solder balls. When the connection structure 600 is a solder ball, the bottom surface substrate pads 320 may include ball pads. Although not shown, the top surface substrate pads 310 may be electrically connected to the corresponding bottom surface substrate pads 320 through circuits and / or interconnect structures in the package substrate 300.

[0096] The first semiconductor device 100A may be the semiconductor device 100 described above with reference to Figures 1 to 13 . The first semiconductor device 100A may include a first semiconductor chip 10, redistribution lines 20, and a first dielectric layer 30. The first semiconductor device 100A may further include a second dielectric layer 40 that covers the first semiconductor chip 10 under the redistribution lines 20 and has an opening exposing the chip pad 10A of the first semiconductor chip 10.

[0097] The first semiconductor chip 10 may be arranged in a face-up type on the package substrate 300 such that the active surface provided with the chip pad 10A faces up, and the non-active surface of the first semiconductor chip 10 may be attached to the package substrate 300 through the adhesive layer 500.

[0098] The redistribution lines 20 are provided on the second dielectric layer 40 and the chip pad 10A of the first semiconductor chip 10, and extend to the edge of the first semiconductor chip 10 while being connected to the chip pad 10A of the first semiconductor chip 10. Although in Figure 14In the cross-section shown, only one chip pad 10A and only one redistribution line 20 are shown. However, a plurality of chip pads 10A are arranged in at least one column in the Y-axis direction of the X-Y plane, and a plurality of redistribution lines 20 are respectively connected to the plurality of chip pads 10A.

[0099] The redistribution line 20 may include a wire bonding pad section 21 disposed adjacent to the edge of the first semiconductor chip 10, a bump bonding pad section 22 connected to the bumps of the second semiconductor chip 210, an overlapping pad section 23 connected to the chip pad 10A of the first semiconductor chip 10, and trace sections 24:24A and 24B connecting them to each other.

[0100] The bump bonding pad section 22 of the redistribution line 20 may be set by being offset in the X-axis direction with respect to the chip pad 10A of the first semiconductor chip 10.

[0101] The redistribution line 20 may include a conductive layer 2, a barrier metal layer 3 located on the conductive layer 2, and a bonding metal layer 4 located on the barrier metal layer 3. In addition, the redistribution line 20 may further include a base metal layer 1 located below the conductive layer 2.

[0102] The base metal layer 1 may be disposed on the surface of the second dielectric layer 40 and the surface of the chip pad 10A. The base metal layer 1 may contact the chip pad 10A of the first semiconductor chip 10 and may electrically connect the chip pad 10A and the conductive layer 2.

[0103] The conductive layer 2 may be disposed on the base metal layer 1. The outer peripheral section of the conductive layer 2 has an overhanging structure not supported by the underlying base metal layer 1. The outer peripheral section of the conductive layer 2 has an overhanging structure continuous along the side surface 1S of the base metal layer 1.

[0104] The barrier metal layer 3 is disposed on the top surface 2T of the conductive layer 2. The barrier metal layer 3 has a flange section OH protruding beyond the side surface 2S of the conductive layer 2. The flange section OH of the barrier metal layer 3 has an overhanging structure not supported by the underlying conductive layer 2. The flange section OH of the barrier metal layer 3 has an overhanging structure continuous along the side surface 2S of the conductive layer 2. The side surface 3S of the barrier metal layer 3 may protrude beyond the side surface 2S of the conductive layer 2.

[0105] The bonding metal layer 4 is disposed on the top surface 3T of the barrier metal layer 3.

[0106] The first dielectric layer 30 is disposed on the first semiconductor chip 10 and the redistribution lines 20, and has a first opening OP1 exposing the lead bonding pad section 21 of the redistribution line 20 and a second opening OP2 exposing the bump bonding pad section 22 of the redistribution line 20. The first dielectric layer 30 may extend to cover the side surface of the lead bonding pad section 21 and the edge section of the top surface of the lead bonding pad section 21.

[0107] The first dielectric layer 30 is disposed to cover the side surface of the lead bonding pad section 21. Specifically, the first dielectric layer 30 is disposed to cover the side surface 4S of the bonding metal layer 4, the side surface 3S of the barrier metal layer 3, the side surface 2S of the conductive layer 2, and the side surface 1S of the base metal layer 1 in the lead bonding pad section 21. Additionally, the first dielectric layer 30 is disposed to cover the edge section of the bottom surface 3B of the barrier metal layer 3 between the side surface 2S of the conductive layer 2 and the side surface 3S of the barrier metal layer 3 in the lead bonding pad section 21.

[0108] In an embodiment, in the lead bonding pad section 21, the first dielectric layer 30 may cover the side surface 3S of the barrier metal layer 3 to prevent or mitigate the formation of a layer serving as a metal diffusion path. In an embodiment, since the first dielectric layer 30 suppresses the formation of a metal diffusion path, defects such as surface discoloration of the bonding metal layer 4 or detachment of the metal lead 400 without being bonded to the bonding metal layer 4 can be suppressed or prevented.

[0109] The first dielectric layer 30 may extend to cover the edge section of the top surface 4T of the bonding metal layer 4 in the lead bonding pad section 21. Accordingly, the edge EG of the first opening OP1 may be spaced apart from the side surface 4S of the bonding metal layer 4. The edge EG of the first opening OP1 may be disposed on the top surface 4T of the bonding metal layer 4, and the first dielectric layer 30 may continuously cover the edge section of the top surface 4T of the bonding metal layer 4 along the edge EG of the first opening OP1.

[0110] The metal lead 400 may be bonded to the exposed section of the top surface 4T of the bonding metal layer 4 of the lead bonding pad section 21 exposed through the first opening OP1 of the first dielectric layer 30. The exposed section of the top surface 4T of the bonding metal layer 4 of the lead bonding pad section 21 exposed through the first opening OP1 may be defined as the lead bonding region. The lead bonding region may not overlap with the flange section OH of the barrier metal layer 3 having an overhang structure.

[0111] The second semiconductor device 200A includes a second semiconductor chip 210 and conductive bumps 220 connected to the chip pads 210A of the second semiconductor chip 210. The second semiconductor chip 210 is connected to the bump bonding pad section 22 of the redistribution line 20 of the first semiconductor device 100A through the conductive bumps 220. AlthoughFigure 14 In the cross-section shown, only one chip pad 210A and only one conductive bump 220 are shown. However, a plurality of chip pads 210A may be arranged in at least one column in the Y-axis direction of the X-Y plane, and a plurality of conductive bumps 220 may be respectively connected to the plurality of chip pads 210A.

[0112] The second semiconductor chip 210 may be a semiconductor chip substantially the same as the first semiconductor chip 10. In this case, the chip pads 210A of the second semiconductor chip 210 may have the same layout structure as the chip pads 10A of the first semiconductor chip 10.

[0113] In addition to the first semiconductor chip 10 having the active surface on which the chip pads 10A are provided facing upward, the second semiconductor chip 210 may be disposed face-down type above the first semiconductor device 100A such that the active surface on which the chip pads 210A are provided faces downward.

[0114] The conductive bump 220 may be positioned to overlap with the chip pad 210A. The conductive bump 220 may include a conductive pillar 221 and a solder layer 222. The conductive pillar 221 may be provided under the second semiconductor chip 210. The solder layer 222 may be provided at the lower end of the conductive pillar 221 and may be bonded to the bump bonding pad section 22 of the redistribution line 20.

[0115] The second semiconductor chip 210 may be connected to the first semiconductor device 100A while being offset in the X-axis direction with respect to the first semiconductor chip 10. In an embodiment, since the bump bonding pad section 22 of the redistribution line 20 of the first semiconductor device 100A is provided by being offset in the X-axis direction with respect to the chip pads 10A of the first semiconductor chip 10, the layout of the chip pads 210A of the second semiconductor chip 210 is the same as the layout of the chip pads 10A of the first semiconductor chip 10, and the conductive bump 220 overlaps with the chip pads 210A of the second semiconductor chip 210, the second semiconductor chip 210 may be connected to the first semiconductor device 100A in a state of being offset in the X-axis direction with respect to the first semiconductor chip 10. Therefore, the first semiconductor chip 10 and the second semiconductor chip 210 may partially overlap each other.

[0116] The molded member 700 is formed to surround the first semiconductor device 100A, the second semiconductor device 200A, and the metal lead 400. The molded member 700 can seal the first semiconductor device 100A, the second semiconductor device 200A, and the metal lead 400 to protect the first semiconductor device 100A, the second semiconductor device 200A, and the metal lead 400 from the external environment. The first semiconductor device 100A and the second semiconductor device 200B can be spaced apart from each other, and the molded member 700 can extend between the first semiconductor device 100A and the second semiconductor device 200B. In Figure 14 , the molded member 700 is formed to substantially completely cover the second semiconductor device 200A. However, embodiments of the disclosed technology are not limited thereto, and the molded member 700 can be formed to expose a section of the surface of the second semiconductor device 200A.

[0117] In an embodiment, the molded member 700 can include a sealant material such as an epoxy molding compound (EMC) material. In an embodiment, for example, the sealant material can include an epoxy resin component and fillers dispersed therein.

[0118] Although examples of embodiments of the present disclosure have been described for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed above and in the drawings should be considered only in a descriptive sense and not for limiting the technical scope. The technical scope of the present disclosure is not limited by the embodiments and the drawings.

[0119] Cross - reference to related applications

[0120] This application claims the priority of Korean Patent Application No. 10 - 2024 - 0008174, filed with the Korean Intellectual Property Office on January 18, 2024, which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, the semiconductor device comprising: A semiconductor chip, the semiconductor chip comprising a chip pad; A redistribution line, the redistribution line disposed on the semiconductor chip, wherein the redistribution line is connected to the chip pad, and the redistribution line comprises a wire bonding pad section; and A first dielectric layer, the first dielectric layer disposed on the semiconductor chip and the redistribution line, the first dielectric layer comprising a first opening exposing the wire bonding pad section, Wherein, the redistribution line comprises a copper layer, a nickel layer on the copper layer, and a gold layer on the nickel layer, and the nickel layer comprises side surfaces protruding beyond the side surfaces of the copper layer.

2. The semiconductor device according to claim 1, Among them, The first dielectric layer covers the side surfaces of the gold layer, the side surfaces of the nickel layer, and the side surfaces of the copper layer.

3. The semiconductor device according to claim 2, Among them, The first dielectric layer further extends to cover the bottom surface of the nickel layer.

4. The semiconductor device according to claim 1, Among them, The first dielectric layer extends on the top surface of the gold layer to expose the wire bonding pad section.

5. The semiconductor device according to claim 4, wherein, The first opening is spaced apart from the side surface of the gold layer.

6. The semiconductor device according to claim 1, the semiconductor device further comprising: A second dielectric layer, the second dielectric layer disposed on the semiconductor chip, the second dielectric layer comprising an opening exposing the chip pad.

7. The semiconductor device according to claim 6, Among them, The redistribution line further comprises a titanium layer disposed between the copper layer and the second dielectric layer, and Wherein, the titanium layer extends to be disposed between the copper layer and the chip pad.

8. The semiconductor device according to claim 7, wherein, The side surface of the copper layer protrudes beyond the side surface of the titanium layer.

9. The semiconductor device according to claim 1, Among them, The redistribution line further has a bump bonding pad section, and Wherein, the first dielectric layer further has a second opening exposing the top surface and the side surfaces of the bump bonding pad section.

10. The semiconductor device according to claim 1, wherein, The flange section of the nickel layer in the wire bonding pad section comprises an overhanging structure protruding beyond the side surface of the copper layer, and The flange section of the nickel layer overlaps with the first dielectric layer.

11. A semiconductor device, the semiconductor device comprising: A semiconductor chip; A redistribution line, the redistribution line disposed on the semiconductor chip, the redistribution line comprising a wire bonding pad section; And A first dielectric layer, the first dielectric layer disposed on the semiconductor chip and the redistribution line, the first dielectric layer comprising a first opening exposing the wire bonding pad section, Wherein, the redistribution line comprises a conductive layer, a barrier metal layer disposed on the conductive layer, and a bonding metal layer on the barrier metal layer, and the barrier metal layer comprises a flange section protruding beyond the side surface of the conductive layer.

12. The semiconductor device according to claim 11, Among them, The first dielectric layer covers the side surfaces of the bonding metal layer, the side surfaces of the barrier metal layer, and the side surfaces of the conductive layer.

13. The semiconductor device according to claim 12, Among them, wherein the first dielectric layer further extends to cover the bottom surface of the barrier metal layer.

14. The semiconductor device according to claim 11, Among them, wherein the first dielectric layer extends on the top surface of the bonding metal layer to expose the wire bonding pad section.

15. The semiconductor device according to claim 14, wherein, The first opening is spaced apart from the side surface of the bonding metal layer.

16. The semiconductor device according to claim 11, Among them, wherein the redistribution line further has a bump bonding pad section, and wherein the first dielectric layer further has a second opening exposing the bump bonding pad section.

17. The semiconductor device according to claim 11, wherein, The redistribution line further includes a base metal layer disposed under the conductive layer.

18. The semiconductor device according to claim 17, wherein, The side surface of the conductive layer protrudes beyond the side surface of the base metal layer.

19. The semiconductor device according to claim 11, wherein, The flange section of the barrier metal layer overlaps with the first dielectric layer.

20. A semiconductor package, the semiconductor package comprising: a first semiconductor device including a first semiconductor chip, redistribution lines disposed on the first semiconductor chip, and a first dielectric layer disposed on the first semiconductor chip and the redistribution lines, the redistribution lines including a wire bonding pad section and a bump bonding pad section, and the first dielectric layer including a first opening exposing the wire bonding pad section and a second opening exposing the bump bonding pad section; and a second semiconductor device including a second semiconductor chip and conductive bumps connected to the second semiconductor chip, the second semiconductor device being stacked on the first semiconductor device such that the conductive bumps are bonded to the bump bonding pad section of the redistribution lines, wherein the redistribution lines include a conductive layer, a barrier metal layer disposed on the conductive layer, and a bonding metal layer located on the barrier metal layer, the barrier metal layer including a side surface protruding beyond the side surface of the conductive layer.

21. The semiconductor package according to claim 20, wherein, The first dielectric layer is disposed to cover the side surface of the bonding metal layer, the side surface of the barrier metal layer, and the side surface of the conductive layer.

22. The semiconductor package according to claim 21, Among them, wherein the first dielectric layer further extends to cover the bottom surface of the barrier metal layer.

23. The semiconductor package according to claim 20, wherein, The first opening is spaced apart from the side surface of the bonding metal layer.

24. The semiconductor package according to claim 20, Among them, wherein the redistribution lines further include a base metal layer disposed between the conductive layer and the semiconductor chip, and wherein the side surface of the conductive layer protrudes beyond the side surface of the base metal layer.

25. The semiconductor package according to claim 20, wherein, The barrier metal layer includes nickel.

26. The semiconductor package according to claim 20, wherein, The conductive layer includes copper, and the bonding metal layer includes gold.

27. The semiconductor package according to claim 20, Among them, wherein the first semiconductor chip includes chip pads connected to the redistribution lines, and wherein the bump bonding pad section is offset in a first direction relative to the chip pads.

28. The semiconductor package according to claim 27, wherein The second semiconductor device is offset in the first direction relative to the first semiconductor device.

29. The semiconductor package according to claim 20, the semiconductor package further comprising: An encapsulation substrate, the encapsulation substrate including a top surface substrate pad and supporting the first semiconductor device and the second semiconductor device; A metal lead, one end of the metal lead being connected to the top surface substrate pad and the other end of the metal lead being connected to the lead bonding pad section; And A molding member, the molding member sealing the first semiconductor device and the second semiconductor device and the metal lead.

30. The semiconductor package according to claim 20, Among them, In the lead bonding pad section, a flange section of the barrier metal layer includes an overhang structure that protrudes beyond a side surface of the conductive layer, and Wherein, the overhang structure overlaps with the first dielectric layer.

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