Package-on-package structure

Abstract

The embodiment of the invention provides a package-on-package structure. The package-on-package structure includes a first package, a plurality of conductive bumps, a second package and an underfill. A conductive bump is disposed on the second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps, and includes a semiconductor device and an encapsulation material encapsulating the semiconductor device. A shortest distance from an upper surface of the encapsulation material to an upper surface of the semiconductor device is greater than or substantially equal to twice a thickness of the semiconductor device. The underfill is filled between the first package and the second package.

Description

[0001] Relevant information of divisional application

[0002] This application is a divisional application of the invention patent application with the application date of June 19, 2018, the application number of "201810628042.8", and the invention title of "Stacked package structure". Technical field

[0003] Embodiments of the present invention relate to a stacked package structure. Background art

[0004] With the increasing demand for smaller electronic products, manufacturers in the electronics industry and the like are constantly seeking ways to reduce the size of integrated circuits used in electronic products. For this purpose, three-dimensional type integrated circuit packaging technologies have been developed and used.

[0005] Manufacturing 3D integrated chips requires stacking multiple semiconductor packages, coupling circuits between corresponding packages, and bonding the packages with an electrically insulating adhesive to form a stacked package structure. For example, subsequent high-temperature treatment steps for curing the electrically insulating adhesive subject the stacked package structure to mechanical stress, which can cause undesirable side effects such as warping, cracking, delamination, and defect formation. Summary of the invention

[0006] Embodiments of the present invention are directed to a stacked package structure having a high production yield.

[0007] According to an embodiment of the present invention, the stacked package structure includes a first package, a plurality of conductive bumps, a second package, and underfill. The conductive bumps are disposed on a second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps and includes a semiconductor device and a encapsulation material encapsulating the semiconductor device. The shortest distance from an upper surface of the encapsulation material to an upper surface of the semiconductor device is greater than or equal to twice the thickness of the semiconductor device. The underfill is filled between the first package and the second package.

[0008] According to an embodiment of the present invention, a stacked package structure includes a first package, a plurality of conductive bumps, a second package, and an underfill. The first package includes an encapsulated semiconductor device and a redistribution structure. The encapsulated semiconductor device includes a first semiconductor device, a first encapsulation material encapsulating the first semiconductor device, and a plurality of vias extending through the first encapsulation material. The redistribution structure is disposed on a first surface of the encapsulated semiconductor device and is electrically connected to the encapsulated semiconductor device. The conductive bumps are disposed on a second surface of the encapsulated semiconductor device and are electrically connected to the encapsulated semiconductor device. The second surface is opposite to the first surface. The second package is disposed on the second surface of the encapsulated semiconductor device and includes a second semiconductor device and a second encapsulation material encapsulating the second semiconductor device. The shortest distance from an upper surface of the second encapsulation material to an upper surface of the second semiconductor device is greater than or equal to twice the thickness of the second semiconductor device. The underfill is filled between the first package and the second package.

[0009] According to an embodiment of the present invention, a stacked package structure includes a first package, a plurality of conductive bumps, a second package, and an underfill. The first package includes an encapsulated semiconductor device and a redistribution structure, and the redistribution structure is disposed on a first surface of the encapsulated semiconductor device and is electrically connected to the encapsulated semiconductor device. The conductive bumps are disposed on a second surface of the encapsulated semiconductor device and are electrically connected to the encapsulated semiconductor device. The second package is disposed on the second surface through the conductive bumps and includes a plurality of semiconductor devices and an encapsulation material encapsulating the semiconductor devices. The shortest distance from an upper surface of the encapsulation material to a topmost surface of the semiconductor device is greater than or equal to twice the maximum thickness of the semiconductor device. The underfill is filled between the first package and the second package. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Aspects of embodiments of the present invention are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0011] Figures 1 to 8 A cross-sectional view illustrating an intermediate stage in manufacturing a stacked package structure according to some exemplary embodiments of the present invention.

[0012] Figure 9 A graph depicting the relationship between the warpage of the second package and the underfill failure rate at a specified temperature.

[0013] Figure 10 A graph depicting the relationship between the warpage of the second package and the underfill failure rate at another specified temperature.

[0014] Figure 11Cross-sectional view of a stacked package structure according to some exemplary embodiments of the present invention.

[0015] Figure 12 Cross-sectional view of a stacked package structure according to some exemplary embodiments of the present invention.

[0016] Explanation of reference numerals

[0017] 10, 10', 10'': Stacked package structure;

[0018] 100: First package;

[0019] 101: Encapsulated semiconductor device;

[0020] 110, 110a: First semiconductor device;

[0021] 112: Substrate;

[0022] 113: Pad;

[0023] 114: Via hole;

[0024] 116, 116a, 143: Dielectric layer;

[0025] 120, 120a: First encapsulation material;

[0026] 130: Through hole;

[0027] 140, 230: Redistribution structure;

[0028] 142: Redistribution line;

[0029] 144: Under bump metal layer;

[0030] 160: Carrier;

[0031] 165: Adhesive layer;

[0032] 170, 170a: Insulating layer;

[0033] 172: Opening;

[0034] 182: Electrical connector;

[0035] 184: Integrated passive device;

[0036] 200, 200', 200'': Second package;

[0037] 201: Lower surface;

[0038] 210, 210a, 210b, 210c: Second semiconductor device;

[0039] 212, 222: Upper surface;

[0040] 212a, 212b: Top surface;

[0041] 220, 220': Second encapsulation material;

[0042] 300: Conductive bump;

[0043] 400: Underfill;

[0044] A1: Central region;

[0045] A2: Peripheral region;

[0046] D1, D2, T1, T1': Shortest distance;

[0047] S1: First surface;

[0048] S2: Second surface;

[0049] T2, T3, T4: Thickness. Detailed implementation

[0050] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the embodiments of the present invention. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, embodiments of the present invention may repeat reference numerals and / or letters in various instances. This repetition is for the purpose of simplicity and clarity, and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0051] In addition, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", and their like may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. Except for the orientation depicted in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0052] In addition, for ease of description, terms such as "first", "second", "third", "fourth", and their like may be used herein to describe similar or different elements or features as shown in the figures, and may be used interchangeably depending on the order of occurrence or the context of the description.

[0053] Other features and processes may also be included. For example, test structures may be included to assist in validating test 3D packages or 3DIC devices. The test structures may include, for example, test pads formed in the redistribution layer or on the substrate, which allows testing of the 3D package or 3DIC, using probes and / or probe cards, etc. The verification tests may be performed on the intermediate structure and the final structure. Additionally, the structures and methods disclosed herein may be combined with and have a test method of intermediate verification of known good dies to increase yield and reduce costs.

[0054] Figures 1 to 8 A cross-sectional view of an intermediate stage in manufacturing a stacked package structure according to some exemplary embodiments of the present invention is shown. It should be noted that embodiments of the present invention will be described with reference to some embodiments in a specific scenario, i.e., a Package on Package (PoP) structure. However, the concepts in the embodiments of the present invention can also be applied to other semiconductor structures or circuits. A PoP structure and a method of forming the PoP structure are provided according to various embodiments. An intermediate stage of forming the PoP structure is illustrated according to some embodiments. Variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numerals are used to denote like elements.

[0055] In some embodiments, a description of an intermediate stage of forming the PoP structure 10 as shown in Figure 8 is as follows. Referring to Figure 1 , a carrier 160 is provided, and an adhesive layer 165 may be disposed on the carrier 160. In some embodiments, the carrier 160 may be a glass carrier, a ceramic carrier, or the like. The adhesive layer 165 may be a light to heat conversion release coating (LTHC) or the like. In some embodiments, an insulating layer 170a may be selectively disposed on the carrier 160 or on the adhesive layer 165 (if present). Subsequently, a plurality of vias 130 are formed on the carrier 160, and the vias 130 surround a central region A1 where the first semiconductor device 110 is to be disposed. In some embodiments, the vias 130 are disposed in a peripheral region A2 of the carrier 160 surrounding the central region A1. It should be noted that the terms "central" and "peripheral" herein may not be interpreted literally, but rather as relative spatial terms that are intended to cover different orientations of the device during use or operation, in addition to the orientation depicted in the drawings. In the present embodiment, the vias 130 are formed on the insulating layer 170a located on the carrier 160, however, embodiments of the present invention are not limited thereto. In an alternative embodiment, the insulating layer 170a and the adhesive layer 165 may be omitted, and the vias 130 are formed directly on the carrier 160.

[0056] In some embodiments, at least one first semiconductor device 110a as shown in Figure 2 is formed on the carrier 160 and within the central region A1. In this embodiment, the first semiconductor device 110a is formed on the insulating layer 170a located on the carrier 160, however, the embodiments of the present invention are not limited thereto. In some embodiments, the first semiconductor device 110a may be a logic chip containing logic circuits therein. In some exemplary embodiments, the number of the first semiconductor devices 110a may be multiple, and may be multiple device dies designed for mobile phone applications, and may include, for example, a Power Management Integrated Circuit (PMIC) die and a Transceiver (TRX) die. Although only one first semiconductor device 110a is shown, more semiconductor devices may be placed above the carrier 160 and flush with each other.

[0057] In some embodiments, the carrier 160 may include a plurality of central regions A1 configured in an array manner, for example. Accordingly, the vias 130 may be formed to surround each central region A1, and a plurality of first semiconductor devices 110a may be respectively disposed on the plurality of central regions A1, such that the vias 130 may surround each first semiconductor device 110a. With these arrangements, a plurality of PoP structures may be formed simultaneously. For the sake of simplicity and clarity, Figures 1 to 8 only the manufacturing process of one of the plurality of PoP structures is shown in Figure 1 For example, one of the plurality of central regions A1 surrounded by some of the plurality of vias 130 is shown in

[0058] In some embodiments, the vias 130 may be pre-formed and then placed on the carrier 160. In alternative embodiments, the vias 130 may be formed by, for example, an electroplating process. The electroplating of the vias 130 may be performed before placing the first semiconductor device 110a, and may include the following steps. For example, first, a seed layer (not shown) is formed above the carrier 160, a photoresist layer (not shown) is formed and patterned, and the vias 130 are formed by electroplating on the exposed part of the seed layer by the photoresist layer. The photoresist layer and the part of the seed layer covered by the photoresist layer may then be removed. The first semiconductor device 110a may then be placed above the carrier 160. The material of the vias 130 may include copper, aluminum, or the like. Accordingly, the bottom end of the vias 130 is substantially flush with the back surface of the first semiconductor device 110a.

[0059] In some exemplary embodiments, a plurality of vias 114 (e.g., copper vias) may be formed on an active surface (e.g., a top surface) of a first semiconductor device 110a and electrically coupled to pads 113 on a substrate 112 of the first semiconductor device 110a. In some embodiments, a dielectric layer 116a may be formed on the active surface (e.g., the top surface) of the first semiconductor device 110a and may cover a top surface of the vias 114. In other embodiments, a top surface of the dielectric layer 116a may be substantially flush with the top surface of the vias 114. Alternatively, the dielectric layer 116a may be omitted, and the vias 114 may protrude from the active surface of the first semiconductor device 110. In some embodiments, a top end of the via 130 may be substantially flush with the top surface of the vias 114. In other embodiments, the top end of the via 130 may be substantially higher than the top surface of the vias 114. Alternatively, the top end of the via 130 may be substantially lower than the top surface of the vias 114 but substantially higher than a bottom surface of the vias 114.

[0060] Subsequently, the first semiconductor device 110a and the via 130 on the carrier 160 are encapsulated by a first encapsulation material 120a. In other words, the first encapsulation material 120a is formed on the carrier 160 to encapsulate the via 130 at the peripheral region A2 and the first semiconductor device 110a at the central region A1. In some embodiments, the first encapsulation material 120a fills a gap between the first semiconductor device 110a and the via 130 and may contact an insulating layer 170a. The first encapsulation material 120a may include a molding compound, an epoxy resin, or a resin, etc. In some embodiments, a top surface of the first encapsulation material 120a may be higher than a top end of the via 130 and a top surface of the dielectric layer 116a. That is, the first encapsulation material 120a covers the top end of the via 130 and the top surface of the dielectric layer 116a.

[0061] Subsequently, a thinning process (which may be a grinding process) is performed to thin the first encapsulation material 120a (and the dielectric layer 116a) until a top end of the via 130 and a top surface of the vias 114 are exposed. The resulting structure is illustrated in Figure 3 As a result of the thinning process, the top end of the via 130 is substantially flush with the top surface of the vias 114 and is substantially flush with a top surface of the first encapsulation material 120 and a top surface of the dielectric layer 116, as shown in Figure 3 In the entire description, as shown in Figure 3The resulting structure including the first semiconductor device 110, the via 130, and the first encapsulation material 120 shown in

[0062] Next, referring to Figure 4 , a redistribution structure 140 is formed on the first surface S1 of the encapsulated semiconductor device 101. The redistribution structure 140 is electrically connected to the first semiconductor device 110 and the via 130 of the encapsulated semiconductor device 101. In some embodiments, the redistribution structure 140 is formed above the encapsulated semiconductor device 101 to connect to the via 114 of the first semiconductor device 110 and the via 130. In some embodiments, the redistribution structure 140 may also interconnect the via 114 and the via 130. The redistribution structure 140 may be formed, for example, by the following steps: depositing a conductive layer, patterning the conductive layer to form redistribution lines 142, partially covering the redistribution lines 142 with a dielectric layer 143 and filling the gaps between the redistribution lines 142, etc. The material of the redistribution lines 142 may include a metal or a metal alloy including aluminum, copper, tungsten, and / or an alloy thereof. The dielectric layer 143 may be formed of a dielectric material such as an oxide, a nitride, a carbide, a carbonitride, a combination thereof, and / or a multi-layer thereof. The redistribution lines 142 are formed in the dielectric layer 143 and are electrically connected to the first semiconductor device 110 and the via 130. Additionally, an under bump metallurgy (UBM) layer 144 may be formed on the redistribution structure 140 by sputtering, evaporation, electroless plating, or the like.

[0063] Referring to Figure 5, according to some exemplary embodiments, at least one of the electrical connectors 182 and at least one integrated passive device (IPD) 184 are disposed on the redistribution line structure 140. The formation of the electrical connectors 182 may include placing solder balls on the UBM layer 144 (or on the redistribution line structure 140), and then reflowing the solder balls. In an alternative embodiment, the formation of the electrical connectors 182 may include performing an electroplating process to form solder bumps on the UBM layer 144 (or on the redistribution line structure 140), and then reflowing the solder bumps. The electrical connectors 182 may also include conductive pillars, or conductive pillars with solder caps, which may also be formed by electroplating. The integrated passive device 184 may be fabricated using standard wafer manufacturing techniques such as thin film and lithography processes, and may be mounted on the redistribution line structure 140 by, for example, flip chip bonding or wire bonding, etc.

[0064] Subsequently referring to Figure 6 , the carrier 160 can be removed. In some embodiments, the carrier 160 is detached from the encapsulated semiconductor device 101 and the insulating layer 170a (if present) by making the adhesive layer 165 lose adhesion or reducing the adhesion. The adhesive layer 165 may be removed together with the carrier 160. For example, the adhesive layer 165 may be exposed to UV light so that the adhesive layer 165 loses adhesion or reduces the adhesion, and thus the carrier 160 and the adhesive layer 165 can be removed from the encapsulated semiconductor device 101.

[0065] After removing the carrier 160, the bottom end of the via 130 is exposed. In the illustrated structure, the bottom end of the via 130 is flush with the bottom surface of the first semiconductor device 110 and the bottom surface of the first encapsulation material 120. In embodiments where the insulating layer 170a is omitted, a grinding process may be performed to slightly grind the bottom surface of the first semiconductor device 110 and the bottom end of the via 130. Alternatively, the grinding process may be omitted.

[0066] Referring to Figure 7 , in embodiments having the insulating layer 170a, a patterning process may subsequently be performed on the insulating layer 170a to form a plurality of openings 172. Thus, an insulating layer 170 with a plurality of openings 172 can be formed. The openings 172 are respectively located on the vias 130 to expose the bottom ends of the vias 130. In some embodiments, the openings 172 may be formed by a lithography process, a laser drilling process, etc. Accordingly, the resulting structure is the first package 100 as shown in Figure 7 the figure.

[0067] Referring to Figure 8, a plurality of conductive bumps 300 may be formed on a second surface S2 of an encapsulated semiconductor device 101 of the first package 100 to be electrically connected to a via hole 130 of the first package 100. The second surface S2 is opposite to the first surface S1. That is, the redistribution structure 140 and the conductive bumps 300 are respectively disposed on two opposite surfaces S1 and S2 of the encapsulated semiconductor device 101. In some embodiments, the conductive bumps 300 are disposed in openings 172 of an insulating layer 170 to be connected to the via hole 130. In some embodiments, the conductive bumps 300 are disposed on a peripheral region A2 of the second surface S2 and surround a central region A1, and the first semiconductor device 110 is located within the central region A1.

[0068] Subsequently, a second package 200 is disposed on the first package 100 and is electrically connected to the via hole 130 through the conductive bumps 300. In some embodiments, the second package 200 is disposed on the second surface S2 of the encapsulated semiconductor device 101 through the conductive bumps 300. The second package 200 is mounted on the first package 100 in such a manner that its lower surface 201 faces the second surface S2 of the encapsulated semiconductor device 101. In some embodiments, the second package 200 may be a package, a device die, a passive device, and / or the like. In some embodiments, the stacked package structure 10 may vertically combine a discrete memory package and a logic package, and the second package 200 may be employed in memories such as dynamic random access memory (DRAM) and other memories, however, embodiments of the present invention are not limited thereto.

[0069] Subsequently, an underfill 400 is filled into a gap between the first package 100 and the second package 200 to enhance the strength of the conductive bumps 300 and thus enhance the strength of the entire stacked package structure 10. In some embodiments, the underfill 400 covers the central region A1 and the peripheral region A2 and encapsulates the conductive bumps 300. The underfill 400 may subsequently be cured by a thermal curing process, and the range of the curing temperature may be about 100 °C to 150 °C. Accordingly, the resulting structure is the stacked package structure 10 as Figure 8 shown.

[0070] In some embodiments, the second package 200 may be mounted on the first package 100 by means of flip-chip bonding, and the second package 200 may include at least one second semiconductor device 210 disposed on a redistribution structure 230 and a second encapsulation material 220 encapsulating the second semiconductor device 210. In some embodiments, the redistribution structure 230 may be a package substrate. In other embodiments, the redistribution structure 230 may be a redistribution layer (RDL) similar to the redistribution structure 140, which is formed by, for example, the following steps: depositing a conductive layer, patterning the conductive layer to form redistribution lines, partially covering the redistribution lines with a dielectric layer, and filling the gaps between the redistribution lines, etc.

[0071] Generally speaking, during the bonding process, if the second semiconductor device 210, the second encapsulation material 220, and the redistribution structure 230 have different coefficients of thermal expansion (CTE), different degrees of expansion will occur when the package 200 is heated and cooled. The different degrees of expansion exert great stress on the solder ball connectors, which may cause warpage of the second package 200. Additional difficulties arise when flip-chip packages are included in a stacked package configuration. In the stacked package structure 10, for example, two packages 100 and 200, such as an application specific integrated circuit (ASIC) and a memory package (e.g., a dynamic random access memory (DRAM)), may be mounted in a stacked manner. For example, the second package 200 may be larger than the first package 100 and may have an array of conductive bumps 300 around its perimeter to form a connection to the first package 100. Configurations such as the stacked package structure 10 increase the likelihood of package warpage.

[0072] Accordingly, when the underfill 400 is dispensed between the first package 100 and the second package 200 with a warped profile, the underfill 400 may not be able to completely fill the gap, which may result in the formation of voids in the underfill 400. In addition, with high-temperature curing, the voids in the underfill 400 will become larger and rapidly nucleate, causing delamination. Therefore, it is very important to control the warped profile of the stacked package structure 10 so that the underfill 400 fills the gap between the first package 100 and the second package 200 without the formation of voids.

[0073] A series of experiments are conducted to obtain the relationship between the warpage of the package during the curing process and the failure rate (such as cracking or delamination, etc.) of the underfill 400, and the failure rate of the underfill 400 of the stacked package structure 10 caused by different degrees of warpage of the second package 200 can be calculated accordingly. To monitor the warpage of the stacked package structure 10, a co-planarity measurement tool can be used, which can use the Shadow Moire' technique to measure the co-planarity of the stacked package structure 10. Of course, the following experimental data and conditions are provided only for illustrative purposes, and the embodiments of the present invention are not limited thereto, but actually cover all relevant variations as a result of the teachings provided herein.

[0074] Figure 9 A graph depicting the relationship between the warpage of the second package and the underfill failure rate at a specified temperature. Figure 10 A graph depicting the relationship between the warpage of the second package and the underfill failure rate at another specified temperature. In Figure 9 the experiment shown, the stacked package structure 10 was exposed to a specified temperature of about 100 °C to simulate the curing process of the underfill 400. It has been found that when the warpage of the second package 200 is generally equal to or less than about -20 microns, the failure rate of the underfill 400 reaches 0%. Additionally, when the second package 200 has a concave warpage profile (i.e., the warpage of the second package 200 is negative), the failure rate of the underfill 400 is less than 10%.

[0075] In Figure 10 the experiment shown, the stacked package structure 10 was exposed to a specified temperature of about 150 °C to simulate the curing process of the underfill 400. Similarly, it has been found that when the warpage of the second package 200 is generally equal to or less than about -20 microns, the failure rate of the underfill 400 reaches 0%. Additionally, when the second package 200 has a concave warpage profile (i.e., the warpage of the second package 200 is negative), the failure rate of the underfill 400 is also less than 10%.

[0076] In view of this, the warpage profile of the second package 200 can be controlled to be a concave warpage profile to reduce the failure rate of the underfill 400. In one of the embodiments, the lower surface 201 of the second package 200 is curved towards the second surface S2 of the encapsulated semiconductor device 101, and the lower surface 201 is the surface facing the second surface S2. In some embodiments, the shortest distance D1 from the central region A1 of the second surface S2 to the second package 200 is generally less than the shortest distance D2 from any position on the peripheral region A2 of the second surface S2 to the second package 200. That is, as Figure 8As shown, the distance (e.g., gap width) between the first package 100 and the second package 200 gradually decreases from the peripheral region A2 to the central region A1. For example, the shortest distance D1 at the central region A1 can generally range from about 30 microns to 60 microns, while the shortest distance D2 at the peripheral region A2 can generally range from about 100 microns to 140 microns. Of course, the numerical ranges in the examples are provided for illustrative purposes only, and the embodiments of the present invention are not limited to the examples, but actually cover all variations relevant as a result of the teachings provided herein.

[0077] To achieve the concave warped profile of the second package 200, the shortest distance T1 from the upper surface 222 of the second encapsulation material 220 to the upper surface 212 of the second semiconductor device 210 is greater than or substantially equal to twice the thickness T2 of the second semiconductor device 210 (i.e., ). With this configuration, due to the thermal expansion mismatch between the components of the second package 200, the second package 200 will have a concave warped profile after the thermal process. Thus, the gap width between the first package 100 and the second package 200 gradually decreases from the peripheral region A2 to the central region A1. Thereby, when the underfill 400 is dispensed from the peripheral region A2 and flows towards the central region A1, the underfill 400 can easily fill the gap at the central region A1 due to capillary action without void formation.

[0078] Figure 11 A cross-sectional view illustrating a stacked package structure according to some exemplary embodiments of the present invention. It should be noted that Figure 11 the stacked package structure 10' shown contains many features that are the same as or similar to the previously Figure 8 disclosed stacked package structure 10. For the purposes of clarity and simplicity, the detailed description of the same or similar features may be omitted, and the same or similar reference numerals refer to the same or similar components. The following describes Figure 11 the main differences between the stacked package structure 10' shown and Figure 8 the stacked package structure 10 shown.

[0079] In some embodiments, the second package 200' includes a plurality of second semiconductor devices 210a, 210b disposed on a redistribution structure 230 and a second encapsulation material 220 encapsulating the plurality of second semiconductor devices 210a, 210b. In some embodiments, the redistribution structure 230 may be an encapsulation substrate. In other embodiments, the redistribution structure 230 may be a redistribution layer (RDL) similar to the redistribution structure 140. In some embodiments, the shortest distance T1 from the upper surface 222 of the second encapsulation material 220 to the topmost surface of the plurality of second semiconductor devices 210a, 210b is greater than or substantially equal to twice the maximum thickness of the plurality of second semiconductor devices 210a, 210b.

[0080] In this embodiment, the second semiconductor devices 210a and 210b are disposed side by side on the redistribution structure 230. The thicknesses T2 and T3 of the second semiconductor device 210a and the second semiconductor device 210b may be the same. In this case, the shortest distance T1 from the upper surface 222 to the top surface 212a or 212b of either the second semiconductor device 210a or the second semiconductor device 210b is greater than or substantially equal to twice the thickness T2 or T3 of either the second semiconductor device 210a or the second semiconductor device 210b. In other embodiments, the thickness T2 of the second semiconductor device 210a and the thickness T3 of the second semiconductor device 210b may be different. For example, the thickness T2 of the second semiconductor device 210a is greater than the thickness T3 of the second semiconductor device 210b. In this case, the shortest distance T1 from the upper surface 222 to the top surface 212a of the second semiconductor device 210a is greater than or substantially equal to twice the thickness T2 of the second semiconductor device 210a. It should be noted that Figure 11 two second semiconductor devices 210a, 210b are shown, however, the embodiments of the present invention do not limit the configuration and number of the second semiconductor devices 210a, 210b in the second package 200.

[0081] With this configuration, the second package 200' will have a concave warpage profile after the thermal process, so that the gap width between the first package 100 and the second package 200' gradually decreases from the peripheral region A2 to the central region A1. Thus, when the underfill 400 is dispensed from the peripheral region A2 and flows toward the central region A1, the underfill 400 can easily flow above the central region A1 due to capillary action and fill the gap between the first package 100 and the second package 200' without void formation.

[0082] Figure 12A cross-sectional view of a stacked package structure according to some exemplary embodiments of the present invention is shown. It should be noted that Figure 12 the stacked package structure 10” shown therein includes many features that are the same as or similar to those of the previously Figure 8 disclosed stacked package structure 10. For the purposes of clarity and simplicity, the detailed descriptions of the same or similar features may be omitted, and the same or similar reference numerals refer to the same or similar components. The main differences between the stacked package structure 10” shown below Figure 12 and the stacked package structure 10 shown Figure 8 are described.

[0083] In some embodiments, the second package 200” includes a plurality of second semiconductor devices 210a, 210b, 210c disposed on a redistribution structure 230 and a second encapsulation material 220' encapsulating the plurality of second semiconductor devices 210a, 210b, 210c. In some embodiments, the redistribution structure 230 may be a package substrate. In other embodiments, the redistribution structure 230 may be a redistribution layer (RDL) similar to the redistribution structure 140. In some embodiments, the shortest distance T1 from the upper surface 222 of the second encapsulation material 220' to the topmost surface among the plurality of second semiconductor devices 210a, 210b, 210c is greater than or substantially equal to twice the maximum thickness of the plurality of second semiconductor devices 210a, 210b, 210c.

[0084] In this embodiment, the second semiconductor devices 210b and 210c are stacked on top of each other on the redistribution structure 230, and the second semiconductor device 210a is disposed beside the second semiconductor devices 210b and 210c. The thicknesses T2, T3, and T4 of the second semiconductor device 210a, the second semiconductor device 210b, and the second semiconductor device 210c may be the same. In this case, the shortest distance T1' from the upper surface 222 to the topmost surface 212b among the second semiconductor device 210a, the second semiconductor device 210b, and the second semiconductor device 210c is greater than or substantially equal to twice the thickness T2, T3, or T4 of any one of the second semiconductor device 210a, the second semiconductor device 210b, and the second semiconductor device 210c. In other embodiments, the thicknesses T2, T3, and T4 of the second semiconductor device 210a, the second semiconductor device 210b, and the second semiconductor device 210c may be different. For example, the thickness T3 of the second semiconductor device 210b is greater than the thickness T4 of the second semiconductor device 210c. In this case, the shortest distance T1' from the upper surface 222 to the topmost surface 212b of the second semiconductor device 210b is greater than or substantially equal to twice the thickness T3 of the second semiconductor device 210b (i.e., if T3≥T4, then T1'□2×T3). In this case, the distance T1 from the upper surface 222 to the top surface 212a of the second semiconductor device 210a will also be greater than or substantially equal to twice the thickness T2, because the sum of the thickness T3 and the thickness T4 is greater than the thickness T2. Of course, if the thickness T2 is greater than the sum of the thickness T3 and the thickness T4, the distance T1 from the upper surface 222 to the top surface 212a becomes the shortest distance among the distance T1 and the distance T1', then the shortest distance T1 is critical in determining the warpage of the second package 200”. It should be noted that the configuration and number of the second semiconductor devices 210a, 210b, and 210c in the second package 200” are for illustration only, and the embodiments of the present invention are not limited thereto.

[0085] With this configuration, the second package 200” will have a concave warpage profile after the thermal process, which means that the gap width between the first package 100 and the second package 200” gradually decreases from the peripheral region A2 to the central region A1. Thus, when the underfill 400 is dispensed from the peripheral region A2 and flows towards the central region A1, the underfill 400 can easily flow over the central region A1 due to capillary action and fill the gap between the first package 100 and the second package 200” without void formation. Therefore, the yield rates of the stacked package structure in the embodiments of the present invention are significantly improved.

[0086] Based on the above discussion, it can be seen that the embodiments of the present invention provide various advantages. However, it should be understood that not all advantages must be discussed herein, and other embodiments may provide different advantages, and specific advantages are not required for all embodiments.

[0087] According to some embodiments of the present invention, a stacked package structure includes a first package, a plurality of conductive bumps, a second package, and an underfill. The conductive bumps are disposed on a second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps and includes a semiconductor device and an encapsulation material encapsulating the semiconductor device. The shortest distance from an upper surface of the encapsulation material to an upper surface of the semiconductor device is greater than or equal to twice the thickness of the semiconductor device. The underfill is filled between the first package and the second package.

[0088] According to some embodiments of the present invention, the plurality of conductive bumps are disposed on a peripheral region of the second surface.

[0089] According to some embodiments of the present invention, a lower surface of the second package is curved toward the second surface of the first package, wherein the lower surface faces the second surface.

[0090] According to some embodiments of the present invention, the shortest distance from a central region of the second surface to the second package is less than the shortest distance from any position on the peripheral region of the second surface to the second package.

[0091] According to some embodiments of the present invention, the shortest distance from an upper surface of the encapsulation material to an upper surface of the semiconductor device is greater than or equal to twice the thickness of the semiconductor device.

[0092] According to some embodiments of the present invention, the second package includes a plurality of semiconductor devices and the encapsulation material encapsulating the plurality of semiconductor devices.

[0093] According to some embodiments of the present invention, the shortest distance from an upper surface of the encapsulation material to a topmost surface of the plurality of semiconductor devices is greater than or equal to twice the maximum thickness of the plurality of semiconductor devices.

[0094] According to some embodiments of the present invention, the underfill covers a central region and a peripheral region of the second surface, and encapsulates the plurality of conductive bumps.

[0095] According to some embodiments of the present invention, a stacked package structure includes a first package, a plurality of conductive bumps, a second package, and an underfill. The first package includes an encapsulated semiconductor device and a redistribution structure. The encapsulated semiconductor device includes a first semiconductor device, a first encapsulation material encapsulating the first semiconductor device, and a plurality of vias extending through the first encapsulation material. The redistribution structure is disposed on a first surface of the encapsulated semiconductor device and is electrically connected to the encapsulated semiconductor device. The conductive bumps are disposed on a second surface of the encapsulated semiconductor device and are electrically connected to the encapsulated semiconductor device. The second surface is opposite to the first surface. The second package is disposed on the second surface of the encapsulated semiconductor device and includes a second semiconductor device and a second encapsulation material encapsulating the second semiconductor device. The shortest distance from an upper surface of the second encapsulation material to an upper surface of the second semiconductor device is greater than or equal to twice the thickness of the second semiconductor device. The underfill is filled between the first package and the second package.

[0096] According to some embodiments of the present invention, the shortest distance from a central region of the second surface to the second package is less than the shortest distance from any position on a peripheral region of the second surface to the second package.

[0097] According to some embodiments of the present invention, the plurality of conductive bumps are disposed on the peripheral region.

[0098] According to some embodiments of the present invention, the underfill covers the central region and the peripheral region, and encapsulates the plurality of conductive bumps.

[0099] According to some embodiments of the present invention, the number of the second semiconductor devices is plural, and the second encapsulation material encapsulates the plurality of second semiconductor devices.

[0100] According to some embodiments of the present invention, the shortest distance from an upper surface of the second encapsulation material to a topmost surface of the plurality of second semiconductor devices is greater than or equal to twice the maximum thickness of the plurality of second semiconductor devices.

[0101] According to some embodiments of the present invention, a lower surface of the second package is curved toward the second surface.

[0102] According to some embodiments of the present invention, a stacked package structure includes a first package, a plurality of conductive bumps, a second package, and an underfill. The first package includes an encapsulated semiconductor device and a redistribution structure disposed on a first surface of the encapsulated semiconductor device and electrically connected to the encapsulated semiconductor device. The conductive bumps are disposed on a second surface of the encapsulated semiconductor device and electrically connected to the encapsulated semiconductor device. The second package is disposed on the second surface through the conductive bumps and includes a plurality of semiconductor devices and an encapsulation material encapsulating the semiconductor devices. The shortest distance from an upper surface of the encapsulation material to a topmost surface of the semiconductor devices is greater than or equal to twice the maximum thickness of the semiconductor devices. The underfill is filled between the first package and the second package.

[0103] According to some embodiments of the present invention, the shortest distance from a central region of the second surface to the second package is less than the shortest distance from any position on a peripheral region of the second surface to the second package.

[0104] According to some embodiments of the present invention, a lower surface of the second package is curved toward the second surface.

[0105] According to some embodiments of the present invention, the plurality of semiconductor devices are arranged side by side.

[0106] According to some embodiments of the present invention, the plurality of semiconductor devices are stacked on one another.

[0107] The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of the embodiments of the present invention. Those skilled in the art should appreciate that they may readily use the embodiments of the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent constructs do not depart from the spirit and scope of the embodiments of the present invention, and that various changes, substitutions, and alterations may be made therein without departing from the spirit and scope of the embodiments of the present invention.

Claims

1. A stacked package structure, comprising: A first package having a central region and a peripheral region surrounding the central region; And A second package stacked on the first package and electrically connected to the first package, the second package including one or more semiconductor devices and a encapsulation material encapsulating the one or more semiconductor devices; Wherein the shortest distance from the top surface of the encapsulation material to the topmost surface of the one or more semiconductor devices is greater than or equal to twice the maximum thickness of the one or more semiconductor devices; An underfill disposed between the first package and the second package; Wherein the bottom surface of the second package is curved toward the upper surface of the first package such that the shortest distance from the first package to the second package at the central region is less than the shortest distance from the first package to the second package at the peripheral region.

2. The stacked package structure according to claim 1, wherein the difference between the shortest distance from the first package to the second package at the peripheral region and the shortest distance from the first package to the second package at the central region is equal to or greater than 20 μm.

3. The stacked package structure according to claim 1, further comprising conductive bumps disposed between the first package and the second package, wherein the first package is electrically connected to the second package through the conductive bumps.

4. The stacked package structure according to claim 3, wherein the conductive bumps are disposed on the peripheral region of the first package.

5. The stacked package structure according to claim 1, wherein the gap width between the first package and the second package gradually decreases from the peripheral region of the first package to the central region of the first package.

6. The stacked package structure according to claim 1, wherein the second package includes a redistribution structure, and the one or more semiconductor devices are disposed on the redistribution structure.

7. The stacked package structure according to claim 1, wherein the first package includes encapsulated semiconductor devices and a redistribution structure, the redistribution structure is disposed on a first surface of the encapsulated semiconductor devices and electrically connected to the encapsulated semiconductor devices.

8. The stacked package structure according to claim 1, wherein the underfill is void-free.

9. The stacked package structure according to claim 1, wherein the second package includes two or more semiconductor devices, and at least two of the semiconductor devices are arranged side by side within the encapsulation material.

10. The stacked package structure according to claim 1, wherein the second package includes two or more semiconductor devices, and at least two of the semiconductor devices are stacked on top of each other and embedded within the encapsulation material.

11. A stacked package structure, comprising: A first package having a central region and a peripheral region surrounding the central region; And A second package that is stacked on the first package and electrically connected to the first package, the second package including a semiconductor device and an encapsulation material encapsulating the semiconductor device; wherein a shortest distance from a top surface of the encapsulation material to a topmost surface of the semiconductor device is greater than or substantially equal to twice a maximum thickness of the semiconductor device, a shortest distance from the first package to the second package at the central region is less than a shortest distance from the first package to the second package at the peripheral region, and a difference between the shortest distance from the first package to the second package at the peripheral region and the shortest distance from the first package to the second package at the central region is substantially equal to or greater than about 20 μm.

12. A stacked package structure, comprising: a first package having a central region and a peripheral region surrounding the central region; and a second package that is stacked on the first package and electrically connected to the first package, the second package including a semiconductor device and an encapsulation material encapsulating the semiconductor device; wherein a shortest distance from a top surface of the encapsulation material to a topmost surface of the semiconductor device is greater than or substantially equal to twice a maximum thickness of the semiconductor device, a shortest distance from the first package to the second package at the central region is less than a shortest distance from the first package to the second package at the peripheral region, and a difference between the shortest distance from the first package to the second package at the peripheral region and the shortest distance from the first package to the second package at the central region is substantially equal to or less than about 20 μm.

Images