Multi-level UPQC topological structure evaluation method and system

Abstract

The invention relates to the technical field of level data evaluation, in particular to a multi-level UPQC topological structure evaluation method and system. The method comprises the following steps: acquiring a multi-level UPQC design drawing; carrying out design parameter extraction on the multi-level UPQC design drawing to obtain UPQC design parameters; deconstructing an electrical cooperation mode according to the UPQC design parameters; performing electric energy connection topology mapping based on an electric cooperation mode to obtain connection topology structure data; constructing a UPQC topological structure model based on the connection topological data and the power distribution path data; through a data processing technology and an analogue simulation technology, accurate identification of a power flow direction path is realized, and the steady-state performance of the UPQC topological structure is detected, so that the performance index of the multi-level UPQC topological structure is accurately evaluated, the evaluation accuracy is improved, and the evaluation time is shortened.

Description

Technical Field

[0001] The present invention relates to the technical field of level data evaluation, and particularly to a multi-level UPQC topology evaluation method and system. Background Art

[0002] The Unified Power Quality Conditioner (UPQC) is a power device integrating various power quality regulation functions, which can simultaneously solve power grid voltage quality problems (such as voltage dips, voltage rises, voltage transients) and current quality problems (such as current harmonics, reactive power compensation). The UPQC usually consists of a series module (DVR part) and a parallel module (APF part). Existing multi-level UPQC topology evaluation technologies mainly focus on the analysis of single characteristics or single structures, lacking a comprehensive evaluation of multi-level UPQC topologies, lacking accurate identification and analysis of power flow paths, and existing evaluation methods often focus on steady-state performance while ignoring the evaluation of dynamic performance, lacking detection of topology component losses and effective quantification of the sensitivity of power redundancy regulation. Summary of the Invention

[0003] Based on this, it is necessary to provide a multi-level UPQC topology evaluation method and system to solve at least one of the above technical problems.

[0004] To achieve the above object, a multi-level UPQC topology evaluation method, the method includes the following steps:

[0005] Step S1: Obtain the multi-level UPQC design drawings; extract the design parameters from the multi-level UPQC design drawings to obtain the UPQC design parameters;

[0006] Step S2: Deconstruct the electrical cooperation mode according to the UPQC design parameters; perform power connection topology mapping based on the electrical cooperation mode to obtain connection topology structure data; identify the level power flow path for the connection topology structure data to obtain power distribution path data; construct a UPQC topology structure model based on the connection topology data and the power distribution path data;

[0007] Step S3: Obtain multi-level operation data; input the multi-level operation data into the UPQC topology structure model and monitor the multi-level working performance parameters; perform UPQC structure steady-state identification on the multi-level working performance parameters to generate structure steady-state data; perform topology component loss detection on the structure steady-state data to generate topology component loss data;

[0008] Step S4: Evaluate the sensitivity of power redundancy regulation based on the topological component loss data; perform a performance evaluation of the topological structure module of the UPQC topological structure model based on the sensitivity of power redundancy regulation to obtain a multi-level UPQC topological structure evaluation report.

[0009] By obtaining the design drawings of the multi-level UPQC and extracting the design parameters, the present invention can fully reflect the electrical characteristics and topological structure of the UPQC system. Based on the design parameters, the electrical cooperation mode is deconstructed, and further, the connection topological structure data is obtained through the power connection topology mapping, and the level power flow path is identified. Finally, an accurate UPQC topological structure model is constructed. This process ensures a comprehensive understanding and modeling of the multi-level UPQC system from design to operation. After obtaining the multi-level operation data and inputting it into the UPQC topological structure model, the multi-level working performance parameters can be monitored in real time. By performing a structural steady-state identification on these parameters, structural steady-state data is generated, providing a quantitative basis for the stability under different operating conditions. At the same time, by detecting the topological component losses in the structural steady-state data, the loss conditions of each component in actual operation can be accurately evaluated, providing key information for the optimization and maintenance of the system; based on the topological component loss data, evaluating the sensitivity of power redundancy regulation can accurately reflect the power regulation ability of the system under different working conditions. This sensitivity evaluation not only considers the impact of loss data on power redundancy but also combines the performance characteristics of the topological structure module, making the performance evaluation of the UPQC topological structure more comprehensive and in-depth. In this way, the regulation efficiency of the system under different operating conditions can be effectively identified; based on the sensitivity of power redundancy regulation, performing a module performance evaluation on the UPQC topological structure model can generate a detailed multi-level UPQC topological structure evaluation report, covering the performance of the system under different working conditions, including key indicators such as power distribution, loss conditions, and power regulation ability, providing comprehensive technical support for the optimal design, operation management, and fault diagnosis of the UPQC system, and improving the overall performance and reliability of the system. Therefore, through data processing technology and simulation technology, the present invention realizes the accurate identification of the power flow path and detects the steady-state performance of the UPQC topological structure, thereby accurately evaluating the performance indicators of the multi-level UPQC topological structure, improving the accuracy of the evaluation and shortening the evaluation time.

[0010] Preferably, step S1 includes the following steps:

[0011] Step S11: Obtain the design drawings of the multi-level UPQC;

[0012] Step S12: Mark the hardware modules of the multi-level UPQC design drawings, where the hardware modules include a series converter module, a shunt converter module, and a DC bus energy storage element module;

[0013] Step S13: Extract the number of switching connection nodes of the series converter module in the frequency range of 10 kHz to 50 kHz, extract the rated voltage range of 110 V to 400 V, and the rated current capacity, and record them as the design parameters of the series converter;

[0014] Step S14: Extract the number of grid interfaces, the current output, and the voltage control parameters of the parallel converter module, and record them as the design parameters of the parallel converter;

[0015] Step S15: Extract the voltage energy storage capacity of the DC bus energy storage component module, and extract the charge and discharge current in the charge and discharge rate range of 0.5C to 2C, and record them as the design parameters of the DC bus energy storage;

[0016] Step S16: Combine the design parameters of the series converter, the design parameters of the parallel converter, and the design parameters of the DC bus energy storage into the UPQC design parameters.

[0017] The acquisition of the multi-level UPQC design drawings in the present invention provides an accurate structural basis for the subsequent evaluation process. The hardware layout and electrical connection relationships of the multi-level UPQC system are detailedly recorded in the design drawings, ensuring the accuracy and pertinence of the subsequent parameter extraction and analysis processes. Through the design drawings, the topological structures and mutual relationships of each hardware module can be clarified; by marking the hardware modules in the multi-level UPQC design drawings, the series converter module, the shunt converter module, and the DC bus energy storage element module can be clearly distinguished. This process provides a clear scope and object for the subsequent parameter extraction, avoiding omission or confusion during the parameter extraction process. Through marking, the independence and pertinence of the parameter extraction of each module and the subsequent evaluation process can be ensured. Extract the number of switch connection nodes, the rated voltage range (110V - 400V), and the rated current capacity of the series converter module, and record them as the series converter design parameters, which can accurately obtain the key electrical characteristics of the series converter module in the multi-level UPQC topological structure. The number of switch connection nodes reflects the topological complexity and current distribution ability of the series converter module; extract the number of grid interfaces, the current output, and the voltage control parameters of the shunt converter module, and record them as the shunt converter design parameters, which can clarify the electrical function and control ability of the shunt converter module in the multi-level UPQC topological structure. The number of grid interfaces reflects the connection ability of the shunt converter module to the grid, and the current output and voltage control parameters determine its power regulation accuracy and stability in the system; extract the voltage energy storage capacity and the charge and discharge current (the charge and discharge rate is 0.5C - 2C) of the DC bus energy storage element module, and record them as the DC bus energy storage design parameters, which can accurately obtain the energy storage and release ability of the energy storage element module in the multi-level UPQC topological structure; the voltage energy storage capacity reflects the capacity size of the energy storage element, and the charge and discharge current determines its energy conversion efficiency and dynamic response ability in the system; combine the series converter design parameters, the shunt converter design parameters, and the DC bus energy storage design parameters into the UPQC design parameters, avoiding the evaluation error caused by parameter dispersion.

[0018] Preferably, the deconstructing of the electrical cooperation mode according to the UPQC design parameters in step S2 includes:

[0019] Perform node current capacity mapping on the rated current capacity according to the number of switch connection nodes to obtain the node current mapping value; based on the node current mapping value, perform voltage level adaptability detection on the rated voltage range, parameterize the adaptation relationship of the voltage level adaptability to the series converter module, and generate the series converter electrical adaptation data;

[0020] Determine the interface current flux of the current output according to the number of grid interfaces, detect the voltage control degree of the parallel converter module based on the interface current flux and voltage control parameters, map the voltage control degree to a constraint relationship, and generate the constraint data of the parallel converter;

[0021] Detect the rated energy storage capacity based on the voltage energy storage capacity and the charge and discharge current; determine the energy storage limit according to the rated energy storage capacity, and determine the energy storage element limit for the DC bus energy storage element module based on the energy storage limit to obtain the DC bus energy storage limit data;

[0022] Perform electrical collaborative matching based on the electrical adaptation data of the series converter, the constraint data of the parallel converter, and the DC bus energy storage limit data to obtain the electrical collaborative method.

[0023] In the present invention, by mapping the rated current capacity to the node current capacity according to the number of switch connection nodes, detecting the voltage level adaptation degree of the rated voltage range based on the mapped value, and then parameterizing the adaptation relationship of the voltage level adaptation degree for the series converter module, it can ensure that the series converter module accurately matches the voltage level and current capacity requirements of the grid in the multi-level UPQC topology structure, thereby improving the power quality regulation ability and operation stability of the system; determine the interface current flux of the current output according to the number of grid interfaces, detect the voltage control degree of the parallel converter module based on the interface current flux and voltage control parameters, and map the voltage control degree to a constraint relationship, which can effectively constrain the voltage control degree of the parallel converter module and ensure its stable operation in the multi-level UPQC topology structure, avoiding the degradation of system performance caused by voltage fluctuations; detect the rated energy storage capacity based on the voltage energy storage capacity and the charge and discharge current, determine the energy storage limit according to the rated energy storage capacity, and then determine the energy storage element limit for the DC bus energy storage element module based on the energy storage limit, which can ensure that the DC bus energy storage element module matches the energy storage capacity and the charge and discharge current in the multi-level UPQC topology structure, avoid overcharging or over-discharging of the energy storage element, extend the service life of the energy storage element, and improve the energy utilization efficiency of the system; perform electrical collaborative matching based on the electrical adaptation data of the series converter, the constraint data of the parallel converter, and the DC bus energy storage limit data. This collaborative matching process can achieve the efficient collaborative work of each module in the multi-level UPQC topology structure, optimize the overall performance of the system, improve the power quality regulation efficiency, and reduce the system operation cost.

[0024] Preferably, the electrical connection topology mapping based on the electrical collaborative method in step S2 includes:

[0025] Classify the electrical collaborative method into types, including the electrical adaptation type of the series converter, the constraint type of the parallel converter, and the DC bus energy storage limit type;

[0026] Detect the total series electrical energy of the series converter electrical adaptation type; perform electrical series parameterization on the total series electrical energy to obtain electrical series parameters; determine the series topology structure according to the electrical series parameters to obtain series topology structure data;

[0027] Detect the parallel electrical energy distribution of the parallel converter constraint type; perform parallel path marking according to the parallel electrical energy distribution, and determine the parallel topology structure based on the parallel path to obtain parallel topology structure data;

[0028] Detect the electrical energy buffer of the DC bus energy storage limit type; determine the DC bus buffer structure according to the electrical energy buffer to obtain DC bus buffer structure data;

[0029] Merge the series topology structure data, parallel topology structure data, and DC bus buffer structure to generate connection topology structure data.

[0030] The present invention divides the electrical cooperation method into a series converter electrical adaptation type, a parallel converter constraint type, and a DC bus energy storage limit type, realizing the accurate classification of the functions of each key module in the multilevel UPQC topology structure, ensuring that the functional positioning of each module in the system is accurate.

[0031] Detect the total series electrical energy of the series converter electrical adaptation type, perform electrical series parameterization on it, and determine the series topology structure based on the electrical series parameters. It can accurately optimize its topology structure according to the actual electrical energy transmission capacity of the series converter, ensuring efficient electrical energy transmission and voltage adaptation within a high frequency range (10 kHz to 50 kHz) and a wide voltage range (110 V to 400 V); detect the parallel electrical energy distribution of the parallel converter constraint type, perform parallel path marking according to this distribution, and then determine the parallel topology structure; by accurately distributing the parallel electrical energy, it can optimize the power transmission path of the parallel converter module, ensuring efficient electrical energy distribution and voltage control in the multilevel UPQC topology structure; detect the electrical energy buffer of the DC bus energy storage limit type, determine the DC bus buffer structure according to this buffer, and generate DC bus buffer structure data, which can accurately optimize the buffer capacity of the DC bus according to the charge and discharge rate (0.5C to 2C) and voltage energy storage capacity of the energy storage element, ensuring efficient energy buffering and voltage stability under dynamic conditions; merge the series topology structure data, parallel topology structure data, and DC bus buffer structure data, realizing the collaborative optimization of each module in the multilevel UPQC topology structure, ensuring that the system as a whole has efficient electrical energy transmission, distribution, and buffering capabilities.

[0032] Preferably, the identification of the level power flow path for the connection topology structure data in step S2 includes:

[0033] Perform structural segment marking and segmentation on the connection topology structure data to generate the structural segment positions;

[0034] Perform series voltage division quantity detection on the structural segment positions to obtain the series voltage division quantity;

[0035] Perform parallel current division quantity detection on the structural segment positions to obtain the parallel current division quantity;

[0036] Calculate the level power difference based on the series voltage division quantity and the parallel current division quantity; perform difference site marking on the structural segment positions according to the level power difference, and record the power quantity of the difference sites to obtain the structural segment power difference quantity;

[0037] Sort the structural segment power difference quantity in ascending order to obtain the power ascending data;

[0038] Determine the power flow direction based on the power ascending data, and record the power ascending quantity to obtain the power distribution path data.

[0039] The present invention performs structural segment marking and segmentation on the connection topology structure data, realizes the refined division of the multi-level UPQC topology structure, can clarify the specific positions and functional boundaries of each structural segment in the system, and provides a clear analysis object for subsequent voltage division, current division quantity detection and power difference calculation; performing series voltage division quantity detection on the structural segment positions can accurately obtain the voltage distribution of each structural segment in the series path, ensuring that the voltage distribution of the series converter module at different levels meets the design requirements; performing parallel current division quantity detection on the structural segment positions can accurately measure the current distribution of each structural segment in the parallel path, provides a quantitative basis for the power distribution of the parallel converter module, and ensures that the parallel topology structure can efficiently realize power distribution; by calculating the level power difference between the series voltage division quantity and the parallel current division quantity, the power difference between each structural segment can be quantified, and the calculation process is based on the logarithmic relationship of the power level, which can effectively reflect the dynamic change of power between different structural segments; performing difference site marking on the structural segment positions and recording the power quantity can clarify the specific position and magnitude of the power difference, provides accurate positioning information for subsequent power distribution optimization, and ensures that the system can achieve dynamic adjustment under the condition of power imbalance; sorting the structural segment power difference quantity in ascending order can clearly present the priority of the power difference of each structural segment, provides an ordered data basis for the optimization of the power distribution path, and ensures that the system can be reasonably distributed according to the priority of power demand; determining the power flow direction based on the power ascending data and recording the power ascending quantity realizes the visualization and optimization of the power flow in the multi-level UPQC topology structure, and ensures that the system can achieve efficient and stable power distribution under dynamic operating conditions.

[0040] Preferably, the input of the multilevel operation data into the UPQC topology model and the monitoring of the multilevel working performance parameters in step S3 include:

[0041] Determine the input voltage range of the multilevel operation data, and measure the level switching frequency according to the input voltage range;

[0042] Identify the single-level operation characteristics based on the input voltage range and the level switching frequency, and perform a multilevel operation coupling mode analysis on the single-level operation characteristics to obtain multilevel operation mode data;

[0043] Input the multilevel operation mode data into the UPQC topology model and start the UPQC simulation;

[0044] Continuously monitor the output voltage harmonics of the UPQC topology model and record the output voltage harmonic content;

[0045] Continuously monitor the total harmonic distortion of the current of the UPQC topology model and record the total harmonic distortion rate of the current;

[0046] Continuously monitor the level change response characteristics of the UPQC topology model and record the level response time;

[0047] Integrate the output voltage harmonic content, the total harmonic distortion rate of the current, and the level response time to obtain the multilevel working performance parameters.

[0048] The present invention determines the input voltage range and measures the level switching frequency, which can provide an accurate description of the input conditions for the operation of a multilevel UPQC system. The determination of the input voltage range provides basic data for the operation of the system at different voltage levels, while the measurement of the level switching frequency provides key parameters for the subsequent analysis of the level operation mode. By identifying the single-level operation characteristics and analyzing the multilevel operation coupling mode, the single-level operation characteristics can be organically combined with the multilevel operation mode, effectively reflecting the dynamic characteristics of the multilevel UPQC system under different operation modes. Inputting the multilevel operation mode data into the UPQC topology model and starting the simulation can achieve the performance evaluation of the system under actual operation conditions. The simulation process can simulate the voltage, current, and level switching characteristics of the system under different operation modes. Continuously monitoring the output voltage harmonics and recording their contents can accurately evaluate the voltage quality of the system. Calculating the harmonic content by methods such as Fourier transform can represent the total harmonic distortion rate of the harmonic voltage (THDu) in percentage form. Continuously monitoring the total harmonic distortion of the current and recording its distortion rate can accurately evaluate the current quality of the system. The total harmonic distortion rate of the current (THDi) is obtained by calculating the ratio of the effective value of the harmonic current to the effective value of the fundamental current, which can effectively reflect the interference degree of the current harmonics in the system. Continuously monitoring the level change response characteristics and recording the level response time can evaluate the dynamic performance of the system during the level switching process. The level response time reflects the response speed of the system to the change of the input voltage and is an important indicator to measure the stability and rapidity of the system. Integrating the above monitoring data to generate multilevel working performance parameters can comprehensively evaluate the comprehensive performance of the UPQC topology in actual operation, ensuring that the multilevel UPQC system achieves the best performance in terms of power quality improvement and dynamic response ability.

[0049] Preferably, the steady-state identification of the UPQC structure for the multilevel working performance parameters in step S3 includes:

[0050] Detect the harmonic order of the output voltage harmonic content, set the number of harmonic order detection rounds to 5 - 8 rounds, and obtain the output voltage harmonic order;

[0051] Mark the output voltage harmonic content with voltage harmonic time according to the output voltage harmonic order; identify the harmonic cycle characteristics based on the voltage harmonic time and the output voltage harmonic order to generate output voltage harmonic cycle data;

[0052] Determine the distortion amplitude of the total harmonic distortion rate of the current with the output voltage harmonic cycle data to obtain the level harmonic distortion amplitude value;

[0053] Evaluate the impedance fluctuation of the level harmonic distortion amplitude value based on the level response time to generate the level impedance fluctuation degree;

[0054] Map the stable state of the UPQC structure according to the degree of level impedance fluctuation to obtain the structure steady-state data.

[0055] In the present invention, by setting the harmonic order detection round to 5 - 8 rounds, the harmonic components and their frequency characteristics in the output voltage can be comprehensively identified, ensuring an accurate assessment of the harmonic characteristics in the multilevel UPQC topology structure; marking the time of the harmonic content in the output voltage can clarify the distribution characteristics of the harmonic components in the time domain, ensuring a precise analysis of the dynamic characteristics of the harmonics; by identifying the harmonic period characteristics, the periodic change law of the harmonics can be quantified, ensuring a comprehensive assessment of the harmonic impact on the system; using the harmonic period data of the output voltage to measure the distortion amplitude of the total harmonic distortion rate of the current can quantify the degree of influence of the harmonics on the current waveform, ensuring an accurate assessment of the dynamic performance of the system; combining the level response time to evaluate the impedance fluctuation of the level harmonic distortion amplitude value can accurately reflect the impedance change characteristics of the system under dynamic operating conditions, ensuring a precise analysis of the system stability; mapping the stable state of the structure based on the level impedance fluctuation degree can generate data reflecting the stability of the UPQC topology structure, ensuring the stable operation of the system under complex working conditions.

[0056] Preferably, the detection of topological component losses for the structure steady-state data in step S3 includes:

[0057] Extract the electrical steady-state operating frequency, electrical steady-state regulation accuracy, and electrical steady-state modulation method of the structure steady-state data;

[0058] Conduct a detection of the regulation conduction loss according to the electrical steady-state operating frequency and the electrical steady-state regulation accuracy to obtain the regulation conduction loss data;

[0059] Conduct a detection of the modulation measure loss based on the electrical steady-state regulation accuracy and the electrical steady-state modulation method to obtain the modulation measure loss data;

[0060] Conduct a detection of the operation loss based on the electrical steady-state operating frequency and the electrical steady-state modulation method to obtain the modulation operation loss data;

[0061] Merge the regulation conduction loss data, the modulation measure loss data, and the modulation operation loss data to obtain the topological component loss data.

[0062] The present invention extracts the electrical steady-state operating frequency, electrical steady-state regulation accuracy, and electrical steady-state modulation method from the structural steady-state data, which can provide accurate operating parameters for subsequent loss detection; based on the electrical steady-state operating frequency and electrical steady-state regulation accuracy, the on-state loss detection of the level adjustment is carried out, which can quantify the on-state loss of the power device under steady-state operation and ensure the accurate evaluation of the system efficiency; through the electrical steady-state regulation accuracy and electrical steady-state modulation method, the modulation measure loss detection is carried out, which can quantify the energy loss in the modulation process; combining the electrical steady-state operating frequency and electrical steady-state modulation method to carry out the operating loss detection can comprehensively evaluate the loss situation of the system under steady-state operation; combining the on-state loss data, modulation measure loss data, and modulation operating loss data can comprehensively reflect the loss characteristics of the multi-level UPQC topology under steady-state operation, providing complete data support for system performance evaluation and optimization.

[0063] Preferably, step S4 includes the following steps:

[0064] Step S41: Determine the electrical energy impact on the topology component loss data to obtain the electrical energy output impact data;

[0065] Step S42: Record the redundant electrical energy according to the electrical energy output impact data, and perform redundant adjustment interval numerical detection on the redundant electrical energy. When the redundant electrical energy is 0% - 30%, it is marked as the low-level redundant adjustment interval; when the redundant electrical energy is 30% - 70%, it is marked as the medium-level redundant adjustment interval; when the redundant electrical energy is 70% - 100%, it is marked as the high-level redundant adjustment interval;

[0066] Step S43: Integrate the low-level redundant adjustment interval, medium-level redundant adjustment interval, and high-level redundant adjustment interval to obtain the level redundant adjustment interval data;

[0067] Step S44: Evaluate the adjustment sensitivity of the topology component loss data according to the level redundant adjustment interval data to generate the electrical energy redundant adjustment sensitivity;

[0068] Step S45: Based on the electrical energy redundant adjustment sensitivity, evaluate the change in operating condition loss of the UPQC topology structure model to obtain the operating condition loss evaluation data;

[0069] Step S46: Evaluate the module performance adjustment efficiency of the UPQC topology structure model according to the operating condition loss evaluation data to obtain the module performance adjustment evaluation data;

[0070] Step S47: Summarize the operating condition loss evaluation data and the module performance adjustment evaluation data into an evaluation report to obtain the multi-level UPQC topology structure evaluation report.

[0071] By measuring the power influence amount of the topological component loss data, the present invention can quantify the actual influence of the loss on the system power output, providing basic data for the subsequent recording of redundant electric energy and the detection of the adjustment range, and ensuring the accurate evaluation of the system energy utilization efficiency; recording redundant electric energy based on the power output influence amount data, and dividing low, medium, and high redundancy adjustment ranges according to the size of the redundant electric energy can clarify the operating state of the system at different redundancy levels, providing a classification basis for the subsequent evaluation of the adjustment sensitivity; integrating the data of different redundancy adjustment ranges to ensure a systematic analysis of the system redundancy adjustment ability; evaluating the adjustment sensitivity of the topological component loss data based on the level redundancy adjustment range data can quantify the adjustment ability of the system in different redundancy ranges, and the generated power redundancy adjustment sensitivity provides key parameters for the subsequent evaluation of the loss change under different operating conditions; using the power redundancy adjustment sensitivity to evaluate the loss change under different operating conditions of the UPQC topological structure model can comprehensively analyze the loss change characteristics of the system under different operating conditions, and the generated loss evaluation data under different operating conditions provides data support for the subsequent evaluation of the module performance adjustment efficiency; evaluating the module performance adjustment efficiency of the UPQC topological structure model based on the loss evaluation data under different operating conditions can quantify the performance adjustment efficiency of each module under different conditions, generating module performance adjustment evaluation data; summarizing the loss evaluation data under different operating conditions and the module performance adjustment evaluation data can systematically reflect the performance of the UPQC topological structure under different operating conditions, providing a comprehensive evaluation basis for the optimal design and operation of the system.

[0072] The present invention also provides a level UPQC topological structure evaluation system for the above-mentioned level UPQC topological structure evaluation method. The level UPQC topological structure evaluation system includes:

[0073] A UPQC design parameter acquisition module for obtaining a multi-level UPQC design drawing; extracting design parameters from the multi-level UPQC design drawing to obtain UPQC design parameters;

[0074] A UPQC topological structure model construction module for deconstructing the electrical cooperation mode according to the UPQC design parameters; performing power connection topology mapping based on the electrical cooperation mode to obtain connection topology structure data; identifying the level power flow path of the connection topology structure data to obtain power distribution path data; constructing a UPQC topological structure model based on the connection topology data and the power distribution path data;

[0075] The topology component loss detection module is used to obtain multi-level operation data; input the multi-level operation data into the UPQC topology structure model and monitor the multi-level working performance parameters; perform UPQC structure steady-state identification on the multi-level working performance parameters to generate structure steady-state data; perform topology component loss detection on the structure steady-state data to generate topology component loss data;

[0076] The topology structure module performance evaluation module is used to evaluate the sensitivity of power redundancy regulation according to the topology component loss data; perform topology structure module performance evaluation on the UPQC topology structure model based on the sensitivity of power redundancy regulation to obtain a multi-level UPQC topology structure evaluation report.

[0077] The present invention realizes the full-process automatic processing from multi-level UPQC design parameter acquisition to topology structure performance evaluation, can accurately extract design parameters, construct an accurate topology structure model, and perform real-time monitoring and analysis on multi-level operation data. The system can quantitatively evaluate the loss characteristics of topology components, identify the sensitivity of power redundancy regulation, and generate a detailed topology structure evaluation report, thereby improving the efficiency and accuracy of UPQC topology structure evaluation. Brief Description of the Drawings

[0078] Figure 1 It is a schematic diagram of the step flow of a multi-level UPQC topology structure evaluation method;

[0079] Figure 2 It is Figure 1 a detailed implementation step flow schematic diagram of step S1 in;

[0080] Figure 3 It is Figure 1 a detailed implementation step flow schematic diagram of step S4 in;

[0081] The realization, functional features and advantages of the object of the present invention will be further described with reference to the embodiments and the accompanying drawings. Detailed Embodiments

[0082] The technical method of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0083] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor methods and / or microcontroller methods.

[0084] It should be understood that although terms such as "first" and "second" may be used herein to describe various units, these units should not be limited by these terms. These terms are only used to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, the first unit may be referred to as the second unit, and similarly the second unit may be referred to as the first unit. The term "and / or" used herein includes any and all combinations of one or more of the listed associated items.

[0085] To achieve the above object, please refer to Figures 1 to 3 , a method for evaluating a multilevel UPQC topology structure, the method comprising the following steps:

[0086] Step S1: Obtain the design drawings of the multilevel UPQC; extract the design parameters from the design drawings of the multilevel UPQC to obtain the UPQC design parameters;

[0087] Step S2: Decompose the electrical cooperation mode according to the UPQC design parameters; perform power connection topology mapping based on the electrical cooperation mode to obtain connection topology structure data; identify the level power flow path for the connection topology structure data to obtain power distribution path data; construct a UPQC topology structure model based on the connection topology data and the power distribution path data;

[0088] Step S3: Obtain the multilevel operation data; input the multilevel operation data into the UPQC topology structure model and monitor the multilevel working performance parameters; perform UPQC structure steady-state identification on the multilevel working performance parameters to generate structure steady-state data; perform topology component loss detection on the structure steady-state data to generate topology component loss data;

[0089] Step S4: Evaluate the power redundancy regulation sensitivity according to the topology component loss data; perform topology structure module performance evaluation on the UPQC topology structure model based on the power redundancy regulation sensitivity to obtain a multilevel UPQC topology structure evaluation report.

[0090] The present invention can completely reflect the electrical characteristics and topological structure of the UPQC system by obtaining the design drawings of the multilevel UPQC and extracting the design parameters. Based on the design parameters, the electrical cooperation mode is deconstructed. Further, the connection topology structure data is obtained through the mapping of the power connection topology, and the power flow path of the levels is identified. Finally, an accurate UPQC topology structure model is constructed. This process ensures a comprehensive understanding and modeling of the multilevel UPQC system from design to operation. After obtaining the multilevel operation data, it is input into the UPQC topology structure model to monitor the multilevel working performance parameters in real time. By performing structural steady-state identification on these parameters, structural steady-state data is generated, providing a quantitative basis for the stability of the system under different operating states. At the same time, by detecting the losses of the topological components in the structural steady-state data, the loss conditions of each component in actual operation can be accurately evaluated, providing key information for the optimization and maintenance of the system; based on the topological component loss data, the sensitivity of the power redundancy regulation is evaluated, which can accurately reflect the power regulation ability of the system under different working conditions. This sensitivity evaluation not only considers the impact of the loss data on the power redundancy, but also combines the performance characteristics of the topological structure modules, making the performance evaluation of the UPQC topology structure more comprehensive and in-depth. In this way, the regulation efficiency of the system under different operating states can be effectively identified; based on the sensitivity of the power redundancy regulation, the performance of the modules of the UPQC topology structure model is evaluated, and a detailed evaluation report of the multilevel UPQC topology structure can be generated, covering the performance of the system under different working conditions, including key indicators such as power distribution, loss conditions, and power regulation ability, providing comprehensive technical support for the optimal design, operation management, and fault diagnosis of the UPQC system, and improving the overall performance and reliability of the system. Therefore, the present invention realizes the accurate identification of the power flow path and detects the steady-state performance of the UPQC topology structure through data processing technology and simulation technology, thereby accurately evaluating the performance indicators of the multilevel UPQC topology structure, improving the accuracy of the evaluation and shortening the evaluation time.

[0091] In the embodiment of the present invention, with reference to Figure 1 as shown, it is a schematic diagram of the step flow of a method for evaluating a multilevel UPQC topology structure of the present invention. In this example, the method for evaluating the multilevel UPQC topology structure includes the following steps:

[0092] Step S1: Obtain the design drawings of the multilevel UPQC; extract the design parameters from the design drawings of the multilevel UPQC to obtain the UPQC design parameters;

[0093] In the embodiment of the present invention, a multi-level UPQC design drawing is obtained through an electrical design software or a drawing management system. The drawing should include the detailed circuit connection mode of the multi-level UPQC, the layout of each component, and the annotation information of key parameters. The specific operation is as follows: Read the pre-designed multi-level UPQC topology drawing file from a storage device, and the file format is usually in CAD format or other common electrical design drawing formats. Subsequently, use image recognition technology or circuit analysis software to extract the design parameters of the multi-level UPQC design drawing. The image recognition technology identifies and analyzes the circuit components, connection lines, and annotated parameters in the drawing through steps such as grayscale image processing, edge detection, and shape description. Specifically, convert the color drawing into a grayscale image to simplify the image recognition process; extract the outlines of circuit components and connection lines through an edge detection algorithm; calculate the geometric features of circuit components, such as area, perimeter, etc., and extract the annotated parameter information. The key design parameters extracted include the number of levels of the multi-level topology structure, the capacitor voltage values of each sub-module, inductance values, the types and quantities of switching devices, etc. For example, for a modular multilevel converter (MMC)-type UPQC, parameters such as the capacitor voltage value (such as ±Vdc) of each sub-module and the arm inductor value (L) need to be extracted.

[0094] Step S2: Decompose the electrical cooperation mode according to the UPQC design parameters; perform power connection topology mapping based on the electrical cooperation mode to obtain connection topology structure data; identify the level power flow path of the connection topology structure data to obtain power distribution path data; construct a UPQC topology structure model based on the connection topology data and the power distribution path data;

[0095] In the embodiments of the present invention, the electrical cooperation mode of the multilevel UPQC is deconstructed according to the design parameters. By analyzing the capacitor voltage values (such as ±Vdc), inductance values (L), types and quantities of switching devices, etc. in the design parameters, and combining the basic principles of the electrical system, the series-parallel port cooperation relationship of the UPQC is determined. For the non-isolated single-phase three-arm UPQC, its parallel port consists of arm a (VT1, VT2), arm b (VT3, VT4) and the port filter (La1, La2, Ca), which is used to compensate the power factor and harmonic current on the grid side; the series port consists of arm b (VT3, VT4), arm c (VT5, VT6) and the series filter (Cbc, Lc), which is used to compensate the load voltage. Based on the electrical cooperation mode, the power connection topology mapping is carried out. Using the electrical system modeling tool, the deconstructed series-parallel port relationship is mapped into the power connection topology structure. By setting the connection relationship of each arm, filter parameters and the connection mode of the DC bus capacitor; the parallel port is equivalent to a current source and is connected in parallel to the grid; the series port is equivalent to a voltage source and is connected in series between the grid and the load; the level power flow path in the connection topology structure data is identified to obtain the power distribution path data. By analyzing the power flow direction in the topology structure and combining the active power exchange relationship of the DC bus capacitor, the power distribution path between each arm is identified. For example, the instantaneous power flowing from the parallel port to the DC bus capacitor (ppc) and the instantaneous power flowing from the DC bus capacitor to the series port (psc) are identified, and the power distribution coefficients of each path are calculated according to these power flow relationships. Use an electrical system modeling tool (such as MATLAB / Simulink or PSIM) to build a model. The specific steps are as follows: Input the inductance value (1mH), capacitance value (10μF) of each arm and the switching characteristics of the IGBT (such as turn-on and turn-off times) into the modeling tool; according to the connection topology data, the parallel port is equivalent to a current source and the series port is equivalent to a voltage source; the parallel port is connected to the grid side, and the series port is connected between the grid and the load. According to the power distribution path data, set the power exchange relationship between the DC bus capacitor and each port; add external conditions: add the grid-side voltage and load-side voltage to the model to simulate the actual operating environment; verify the accuracy of the model through simulation. During the simulation process, monitor the stability of the DC bus voltage and the accuracy of power distribution. If it is found that the DC bus voltage fluctuates greatly, the fluctuation can be reduced by adjusting the power distribution coefficient or optimizing the control strategy.

[0096] Step S3: Obtain multilevel operation data; input the multilevel operation data into the UPQC topology structure model and monitor the multilevel working performance parameters; perform UPQC structure steady-state identification on the multilevel working performance parameters to generate structure steady-state data; perform topology component loss detection on the structure steady-state data to generate topology component loss data;

[0097] In the embodiments of the present invention, multilevel operation data is acquired, and key electrical parameters in the UPQC system are monitored in real time through high-precision sensors and a data acquisition system, including the DC bus voltage (Vdc), the arm currents (Ia, Ib, Ic), the sub-module capacitor voltage (Uc), the grid-side voltage (Ug), and the load-side voltage (UL). The sampling frequency is set to 10 kHz to ensure the accuracy and real-time nature of the data. The multilevel operation data is input into the UPQC topology model, and the multilevel working performance parameters are monitored. The UPQC topology model constructed by using simulation software (such as MATLAB / Simulink) takes the acquired operation data as the input signal; through model simulation, the steady-state performance parameters of the system are monitored in real time, including the fluctuation range of the DC bus voltage (ΔVdc), the balance degree of the sub-module capacitor voltage (ΔUc), the grid-side power factor and the total harmonic distortion rate of the load-side voltage (THD_L); a steady-state identification of the UPQC structure is performed on the multilevel working performance parameters. By analyzing the spectral characteristics of the grid-side current (Ig) and the load-side current (IL) through Fourier transform, it is identified whether the system reaches steady-state operation. When the ratio of the fundamental component to the total harmonic component of the grid-side current is greater than 0.95 and the fluctuation range of the DC bus voltage is less than ±1% of the rated voltage, it is determined that the system is in steady-state operation; at this time, the key parameters in the steady state are recorded, including the average value of the DC bus voltage (Vdc_avg), the average value of the sub-module capacitor voltage (Uc_avg), and the fundamental component of the grid-side current (Ig_fundamental). A topological component loss detection is performed on the steady-state structure data. According to the steady-state data and in combination with the characteristic parameters of the IGBT module and the capacitor, the losses of each component are calculated; for the IGBT module, an average power loss calculation model based on the switching period is adopted to calculate the conduction loss, turn-on loss, and turn-off loss respectively. The specific calculation methods are as follows: the conduction loss is related to the product of the IGBT terminal voltage and the collector current and the duty cycle of the switching period; the turn-on loss is related to the switching frequency, turn-on energy, gate resistance coefficient, and junction temperature coefficient; the turn-off loss is related to the switching frequency, turn-off energy, gate resistance coefficient, and junction temperature coefficient. For the sub-module capacitor, by monitoring its voltage and current waveforms, the losses of its equivalent series resistance (ESR) and capacitance value are calculated. A multi-point sampling method is adopted to sample the sub-module capacitor voltage within the power frequency cycle. In combination with information such as the IGBT switching signal, modulation ratio, AC-side current, and voltage, voltage and current state equations are constructed, and the capacitance value and ESR value are obtained by solving.

[0098] Step S4: Evaluate the sensitivity of power redundancy regulation according to the topological component loss data; perform a performance evaluation of the topological structure module on the UPQC topology model based on the sensitivity of power redundancy regulation to obtain a multilevel UPQC topology evaluation report.

[0099] In the embodiments of the present invention, according to the loss data of topological components, the sensitivity of power redundancy regulation is evaluated. Specifically, for the IGBT module, the losses are mainly divided into conduction loss, turn-on loss and turn-off loss. Taking the IGBT of model FF450R12ME4 as an example,

[0100] Conduction loss: By measuring the conduction voltage drop (Vce_on) and operating current (Ic) of the IGBT, and combining with the duty cycle (D), the conduction loss P_cond = Vce_on × Ic × D is calculated. Turn-on loss: The turn-on loss P_on is related to the switching frequency (f_sw) and turn-on energy (E_on), and the calculation formula is P_on = f_sw × E_on. Turn-off loss: The turn-off loss P_off is related to the switching frequency (f_sw) and turn-off energy (E_off), and the calculation formula is P_off = f_sw × E_off. The capacitor loss is mainly caused by the equivalent series resistance (ESR). For a capacitor with a rated capacitance value of 100 μF, the ESR value of the capacitor is measured using a capacitance tester. Assume the ESR is 5 Ω. According to the capacitance value (C) and operating frequency (f), the capacitive reactance Xc = 1 / (2πfC) is calculated. For example, for a frequency of 50 Hz and a capacitor of 100 μF, Xc ≈ 318.3 Ω; the capacitor loss P_loss = I^2 × ESR, where I is the ripple current flowing through the capacitor. For example, when the ripple current is 5.28 A, the power loss is about 1.115 W. Combining the loss data of the IGBT and the capacitor with parameters such as the DC bus voltage fluctuation range (ΔVdc) and the sub-module capacitor voltage balance degree (ΔUc), the influence of the loss on power redundancy regulation is analyzed. If the increase in loss leads to an increase in ΔVdc, it indicates that the sensitivity of power redundancy regulation is relatively high. The analytic hierarchy process (AHP) is used to evaluate the performance of the UPQC topological structure model. According to the sensitivity of power redundancy regulation, combining factors such as loss, reliability, transient and steady-state characteristics, system stability, and cost, an evaluation index system is constructed: Relationship between loss and topology: Taking the total loss of the IGBT and the capacitor as the index; Reliability: Taking the range of the IGBT junction temperature change and the ESR stability of the capacitor as the index; Transient and steady-state characteristics: Taking the DC bus voltage fluctuation range (ΔVdc) and the sub-module capacitor voltage balance degree (ΔUc) as the index; System stability: Taking the power factor on the grid side Taking the total harmonic distortion rate of the load - side voltage (THD_L) as an index; Cost: Taking the unit loss cost of IGBT modules and capacitors as an index; Through the analytic hierarchy process and combined with data analysis, determine the weight coefficients of each index. For example, the weight of the loss index is 0.3, the weight of the reliability index is 0.25, the weight of the transient - steady - state characteristic index is 0.2, the weight of the system stability index is 0.15, and the weight of the cost index is 0.1. According to the weight coefficients and the actual values of each index, calculate the comprehensive scores of different topological structures (such as cascaded H - bridge, modular multilevel converter MMC, etc.); According to the performance ranking results, generate a multi - level UPQC topological structure evaluation report.

[0101] As an example of the present invention, refer to Figure 2 As shown, in this example, the step S1 includes:

[0102] Step S11: Obtain the multi - level UPQC design drawings;

[0103] Step S12: Mark the hardware modules of the multi - level UPQC design drawings, where the hardware modules include a series converter module, a shunt converter module, and a DC - bus energy - storage element module;

[0104] Step S13: Extract the number of switch connection nodes in the frequency range of 10 kHz to 50 kHz of the series converter module, extract the rated voltage range of 110 V to 400 V, and the rated current capacity, and record them as the series converter design parameters;

[0105] Step S14: Extract the number of grid interfaces, the current output, and the voltage control parameters of the shunt converter module, and record them as the shunt converter design parameters;

[0106] Step S15: Extract the voltage energy - storage capacity of the DC - bus energy - storage element module, extract the charge - discharge current in the charge - discharge rate range of 0.5C to 2C, and record them as the DC - bus energy - storage design parameters;

[0107] Step S16: Combine the series converter design parameters, the shunt converter design parameters, and the DC - bus energy - storage design parameters into UPQC design parameters.

[0108] In the embodiments of the present invention, a professional electrical design software (such as AutoCAD or SolidWorks) is used to open and read the design drawing file of the multilevel UPQC. The design drawing should include detailed circuit connections, hardware module layouts, and key parameter markings; in the design drawing, a marking tool is used to distinguish and mark the hardware modules. The hardware modules include a series converter module, a shunt converter module, and a DC bus energy storage element module. The series converter module usually includes switching devices (such as IGBTs) and inductors; the shunt converter module includes a grid interface and a filter; the DC bus energy storage element module includes capacitors or batteries; image recognition technology or manual measurement tools are used to extract the number of switching connection nodes in the series converter module with a frequency range of 10 kHz to 50 kHz. For example, by analyzing the layout of the switching devices in the circuit diagram, the number of nodes is counted as 10; the rated voltage range of the series converter module is extracted, and by reading the drawing markings or design specifications, its range is confirmed to be 110V to 400V; the rated current capacity is extracted, and by analyzing the current path and the rated current of the switching devices, its value is determined to be 100A. These parameters are recorded as the design parameters of the series converter; the number of grid interfaces of the shunt converter module is extracted, and by counting the number of interfaces marked in the drawing, it is determined to be 3; the current output is extracted, and by analyzing the design current path of the shunt converter, its value is determined to be 150A; the voltage control parameter is extracted, and by reading the control range marked in the drawing, it is confirmed to be ±10% of the rated voltage. These parameters are recorded as the design parameters of the shunt converter; the voltage energy storage capacity of the DC bus energy storage element module is extracted, and by reading the capacitor or battery parameters marked in the drawing, its value is confirmed to be 1000V; the charge and discharge current with a charge and discharge rate of 0.5C to 2C is extracted, and by analyzing the charge and discharge characteristic curve of the energy storage element, its value is determined to be 50A to 200A. These parameters are recorded as the design parameters of the DC bus energy storage; the above-extracted design parameters of the series converter, the design parameters of the shunt converter, and the design parameters of the DC bus energy storage are integrated to form the complete UPQC design parameters.

[0109] Preferably, the deconstructing of the electrical cooperation mode according to the UPQC design parameters in step S2 includes:

[0110] Perform a node current capacity mapping on the rated current capacity according to the number of switching connection nodes to obtain a node current mapping value; based on the node current mapping value, perform a voltage level adaptability detection on the rated voltage range, parameterize the adaptability relationship of the voltage level to the series converter module, and generate the electrical adaptation data of the series converter;

[0111] Determine the interface current flux of the current output according to the number of grid interfaces, detect the voltage control degree of the parallel converter module based on the interface current flux and voltage control parameters, map the voltage control degree to a constraint relationship, and generate parallel converter constraint data;

[0112] Detect the rated energy storage capacity based on the voltage energy storage capacity and the charge and discharge current; determine the energy storage limit according to the rated energy storage capacity, and determine the energy storage element limit for the DC bus energy storage element module based on the energy storage limit to obtain the DC bus energy storage limit data;

[0113] Perform electrical collaborative matching based on the series converter electrical adaptation data, parallel converter constraint data, and DC bus energy storage limit data to obtain an electrical collaborative method.

[0114] In an embodiment of the present invention, an electrical design software (such as AutoCAD or SolidWorks) is used to read the design parameters of the series converter module, and the number of switch connection nodes (such as 10) and the rated current capacity (such as 100 A) are extracted. Through the node current capacity mapping algorithm, a corresponding current capacity is assigned to each node; if the number of nodes is 10 and the rated current capacity is 100 A, the current capacity mapping value of each node is 10 A; according to the node current mapping value (10 A), combined with the rated voltage range (110 V to 400 V) of the series converter module, a voltage level adaptability detection tool is used for analysis. By calculating the adaptation relationship between the node current mapping value and the rated voltage range, series converter electrical adaptation data is generated. For example, if the adaptation degree of the node current mapping value within the rated voltage range is high, it indicates that the module has good electrical adaptability at this voltage level; the number of grid interfaces (such as 3) and the current output (such as 150 A) of the parallel converter module are extracted. Through the interface current flux calculation tool, the current flux of each interface is determined. If the number of grid interfaces is 3 and the current output is 150 A, the current flux of each interface is 50 A. Combining the voltage control parameters (such as ±10% of the rated voltage), the voltage control degree of the parallel converter module is detected, and constraint data is generated. The voltage energy storage capacity (such as 1000 V) and the charge and discharge current (such as 50 A to 200 A) of the DC bus energy storage element module are extracted. Through the energy storage capacity detection tool, the rated energy storage capacity is calculated; if the voltage energy storage capacity is 1000 V and the charge and discharge current range is 50 A to 200 A, the rated energy storage capacity is 100 kW. According to the rated energy storage capacity, the energy storage limit is determined, and DC bus energy storage limit data is generated; the series converter electrical adaptation data, the parallel converter constraint data, and the DC bus energy storage limit data are input into the electrical collaborative matching system. Through the collaborative matching algorithm, the electrical collaborative relationship between each module is analyzed. If the electrical adaptability of the series converter is good, and the constraint data of the parallel converter matches the DC bus energy storage limit data, it is determined that the UPQC topology has a good electrical collaborative mode.

[0115] Preferably, the power connection topology mapping based on the electrical collaborative mode in step S2 includes:

[0116] The electrical collaborative mode is classified, which is classified into the series converter electrical adaptation type, the parallel converter constraint type, and the DC bus energy storage limit type;

[0117] Detect the total series electrical energy of the series converter electrical adaptation type; parameterize the series electrical energy to obtain series electrical parameters; determine the series topology structure according to the series electrical parameters to obtain series topology structure data;

[0118] Detect the parallel power distribution amount of the parallel converter constraints; perform parallel path marking according to the parallel power distribution amount, determine the parallel topology based on the parallel path, and obtain the parallel topology data;

[0119] Detect the power buffer amount of the DC bus energy storage limit type; determine the DC bus buffer structure according to the power buffer amount, and obtain the DC bus buffer structure data;

[0120] Merge the series topology data, the parallel topology data, and the DC bus buffer structure to generate the connection topology data.

[0121] In the embodiments of the present invention, the electrical cooperation method is divided into a series converter electrical adaptation type, a parallel converter constraint type, and a DC bus energy storage limit type. Through an electrical cooperation matching tool, the series converter electrical adaptation data, the parallel converter constraint data, and the DC bus energy storage limit data are analyzed to determine the cooperation type of each module; an electric energy detection device is used to detect the total electric energy of the series converter module. According to the rated current capacity of the series converter (such as 100 A) and the node current mapping value (such as 10 A / node), the total series electric energy is calculated. For example, if the number of nodes is 10, the total series electric energy is 100 A × 10 nodes = 1000 A; according to the total series electric energy, the electric energy is distributed to each node through a parameterization tool to obtain the series electric energy parameters. For example, when the total electric energy of 1000 A is distributed to 10 nodes, the series electric energy parameter of each node is 100 A; according to the series electric energy parameters, combined with the rated voltage range of the series converter module (such as 110 V to 400 V), the series topology structure is determined through a topology structure analysis tool. If the series electric energy parameter is 100 A and the rated voltage range is 110 V to 400 V, the corresponding series topology structure data is generated, and the voltage and current parameters of each node are recorded; an electric energy distribution detection tool is used to calculate the parallel electric energy distribution according to the current output of the parallel converter module (such as 150 A) and the number of grid interfaces (such as 3). For example, the electric energy distribution of each interface is 150 A / 3 = 50 A; according to the parallel electric energy distribution, each interface is marked through a parallel path marking tool, and the parallel topology structure is determined based on the interface current flux and voltage control parameters (such as ±10% of the rated voltage). If the electric energy distribution of each interface is 50 A and the voltage control range is ±10%, the corresponding parallel topology structure data is generated; an energy storage detection device is used to detect the electric energy buffer of the DC bus energy storage element module. According to the voltage energy storage capacity (such as 1000 V) and the charge and discharge current (such as 50 A to 200 A), the electric energy buffer is calculated. For example, the electric energy buffer is 1000 V × 200 A = 200 kW. According to the electric energy buffer, the DC bus buffer structure is determined through a buffer structure analysis tool. For example, if the electric energy buffer is 200 kW, the corresponding DC bus buffer structure data is generated, and the charge and discharge limit of the energy storage element is recorded. The series topology structure data, the parallel topology structure data, and the DC bus buffer structure data are integrated, and the complete connection topology structure data is generated through a topology structure merging tool.

[0122] Preferably, the identification of the level power flow path for the connection topology structure data in step S2 includes:

[0123] Mark and segment the connection topology structure data to generate the structure segment positions;

[0124] Detect the series voltage division quantity at the structural segment position to obtain the series voltage division quantity;

[0125] Detect the parallel current division quantity at the structural segment position to obtain the parallel current division quantity;

[0126] Calculate the level power difference based on the series voltage division quantity and the parallel current division quantity; Mark the difference position points at the structural segment position according to the level power difference, and record the power quantity of the difference position points to obtain the structural segment power difference quantity;

[0127] Sort the structural segment power difference quantities in ascending order to obtain the power ascending data;

[0128] Determine the power flow direction according to the power ascending data, and record the power ascending quantity to obtain the power distribution path data.

[0129] In the embodiment of the present invention, an electrical topology analysis tool is used to process the connection topology structure data. First, the entire topology structure is segmented and labeled according to the electrical connection relationship of the topology structure. For example, the series converter module is divided into multiple structural segments, and each structural segment includes several switch connection nodes. Suppose the entire series converter module includes 10 nodes, and it is divided into 3 structural segments according to electrical functions, which are respectively labeled as segment 1 (nodes 1-3), segment 2 (nodes 4-7), and segment 3 (nodes 8-10); a high-precision voltage detection device is used to measure the voltage of each structural segment. Suppose the voltage of segment 1 is 110V, the voltage of segment 2 is 220V, and the voltage of segment 3 is 330V. These voltage values are the series voltage division amounts of each structural segment; a current detection device is used to measure the parallel current distribution of each structural segment. For example, suppose the total current of the parallel converter module is 150A, and the current distribution amount of each structural segment is determined through parallel shunt flow detection. Suppose the parallel shunt flow of segment 1 is 50A, segment 2 is 60A, and segment 3 is 40A; according to the series voltage division amount and the parallel shunt flow, the level power difference of each structural segment is calculated. For example, the power of segment 1 is 110V×50A = 5.5kW, the power of segment 2 is 220V×60A = 13.2kW, and the power of segment 3 is 330V×40A = 13.2kW. Calculate the power difference. For example, the power difference between segment 1 and segment 2 is 13.2kW - 5.5kW = 7.7kW; for the calculated power difference, mark the corresponding structural segment position. The power difference of 7.7kW between segment 1 and segment 2 is marked as difference site 1, and the power difference between segment 2 and segment 3 is 0kW (because their powers are the same), which is marked as difference site 2. These marked difference sites and their power amounts are recorded as the structural segment power difference amounts; all the structural segment power difference amounts are sorted in ascending order. For example, suppose the obtained power difference amounts are: difference site 1 is 7.7kW, and difference site 2 is 0kW; after sorting, the power ascending data is: 0kW (difference site 2), 7.7kW (difference site 1); according to the power ascending data, determine the power flow direction, from difference site 2 (0kW) to difference site 1 (7.7kW), and the power flow is from segment 2 to segment 1. Record the power value of each difference site to clarify the flow direction and magnitude of the power in the topology structure.

[0130] Preferably, the inputting the multilevel operation data into the UPQC topology structure model and monitoring the multilevel working performance parameters in step S3 includes:

[0131] Determine the input voltage range amount of the multilevel operation data, and measure the level switching frequency according to the input voltage range amount;

[0132] Identify the single-level operation characteristics based on the input voltage range and the level switching frequency, and perform a multi-level operation coupling mode analysis on the single-level operation characteristics to obtain multi-level operation mode data;

[0133] Input the multi-level operation mode data into the UPQC topology model and start the UPQC simulation;

[0134] Continuously monitor the output voltage harmonics of the UPQC topology model and record the output voltage harmonic content;

[0135] Continuously monitor the total harmonic distortion of the current of the UPQC topology model and record the total harmonic distortion rate of the current;

[0136] Continuously monitor the level change response characteristics of the UPQC topology model and record the level response time;

[0137] Integrate the output voltage harmonic content, the total harmonic distortion rate of the current, and the level response time to obtain the multi-level working performance parameters.

[0138] In the embodiments of the present invention, a high-precision voltage sensor is used to collect the input voltage signal in the multi-level operation data to determine the input voltage range. For example, the input voltage range is 110V to 400V; through frequency measurement techniques (such as direct measurement method or equal-precision measurement method), the frequency of the input voltage signal is measured to obtain the level switching frequency. Assuming that the frequency of the input voltage signal is 50Hz, the frequency can be accurately measured by the equal-precision measurement method; according to the input voltage range (110V to 400V) and the level switching frequency (50Hz), a signal analysis tool is used to identify the single-level operation characteristics. For example, the voltage amplitude during single-level operation is 220V, and the corresponding level switching frequency is 50Hz. Through a multi-level operation coupling mode analysis tool, the single-level operation characteristics are coupled and analyzed with the multi-level operation mode to generate multi-level operation mode data, and the voltage, frequency, and their switching characteristics of each level are recorded. The multi-level operation mode data is imported into the UPQC topology model, and the UPQC simulation is started using simulation software (such as MATLAB / Simulink). During the simulation process, according to the input multi-level operation mode data, the actual operation state of the UPQC system is simulated; during the simulation process, a harmonic analysis tool (such as FFT analysis) is used to monitor the output voltage of the UPQC topology model in real time. The output voltage signal is collected through a high-precision data acquisition card (such as NI-9215), and the harmonic content of the output voltage is calculated using the FFT optimization algorithm (such as Hanning window + interpolation correction). For example, the total harmonic distortion rate (THD) of the output voltage is 5%, and this data is recorded as the harmonic content of the output voltage; similarly, the harmonic analysis tool is used to monitor the current signal of the UPQC topology model. The current signal is collected through a current sensor (such as HIOKI CT6840), and the total harmonic distortion rate (THD) of the current is calculated. For example, the total harmonic distortion rate of the current is 3%, and this data is recorded; a high-speed data acquisition card (such as NI-9215) is used to monitor the level change of the UPQC topology model in real time. By analyzing the time delay during the level switching process, the level response time is recorded. For example, the level response time is 100μs; the recorded output voltage harmonic content (5%), the total harmonic distortion rate of the current (3%), and the level response time (100μs) are integrated to generate the multi-level working performance parameters.

[0139] Preferably, the UPQC structure steady-state identification of the multi-level working performance parameters in step S3 includes:

[0140] Perform harmonic order detection on the harmonic content of the output voltage, set the number of harmonic order detection rounds to 5 to 8 rounds, and obtain the harmonic order of the output voltage;

[0141] Perform voltage harmonic time marking on the output voltage harmonic content according to the harmonic order of the output voltage; identify the harmonic cycle characteristics based on the voltage harmonic time and the harmonic order of the output voltage, and generate the output voltage harmonic cycle data;

[0142] Measure the distortion amplitude of the total current harmonic distortion rate with the output voltage harmonic cycle data to obtain the level harmonic distortion amplitude value;

[0143] Evaluate the impedance fluctuation of the level harmonic distortion amplitude value based on the level response time, and generate the level impedance fluctuation degree;

[0144] Map the stable state of the UPQC structure according to the level impedance fluctuation degree to obtain the structure steady state data.

[0145] In the embodiments of the present invention, a harmonic analyzer or a power quality analyzer is used to detect the harmonic order of the output voltage of the UPQC topology model. The number of rounds of harmonic order detection is set to 5 to 8 rounds, and the voltage signal is decomposed into a fundamental wave and each harmonic component through the fast Fourier transform (FFT) technique. For example, the detected harmonic orders include the 3rd, 5th, 7th, and 9th orders, and these harmonic orders are recorded as the harmonic orders of the output voltage. Based on the detected harmonic orders of the output voltage, time series analysis technology is used to time-mark the harmonic signals. The time points when each harmonic component appears are recorded through a high-precision data acquisition system. For example, the 3rd harmonic appears at 0.01 seconds, the 5th harmonic appears at 0.02 seconds, and so on. These time marks are used for subsequent analysis of the periodic characteristics of the harmonics. The variance curve period identification method is used to analyze the periodic characteristics of the voltage harmonic signal. Combining the voltage harmonic time and the harmonic order, the periodic characteristics of each harmonic component are calculated. For example, the period of the 3rd harmonic is 0.02 seconds, and the period of the 5th harmonic is 0.01 seconds. Output voltage harmonic period data is generated, and the periodic characteristics of each harmonic component are recorded. According to the output voltage harmonic period data, its influence on the total harmonic distortion (THD) of the current is analyzed. By comparing the current distortion conditions under different harmonic periods, the level harmonic distortion amplitude value is calculated. For example, when the period of the 3rd harmonic is 0.02 seconds, the total harmonic distortion rate of the current is 3.5%; when the period of the 5th harmonic is 0.01 seconds, the total harmonic distortion rate of the current is 4.2%. These distortion amplitude values are recorded as the level harmonic distortion amplitude values. The level harmonic distortion amplitude value is evaluated for impedance fluctuation using level response time data (such as 100 μs). By analyzing the relationship between the time delay and the harmonic distortion amplitude during the level switching process, the impedance fluctuation degree is evaluated. For example, if the level response time is 100 μs and the distortion amplitude of the 3rd harmonic is 3.5%, the corresponding impedance fluctuation degree is 5%. These impedance fluctuation degrees are recorded as the evaluation results. The level impedance fluctuation degree data is input into the UPQC structure steady state mapping system. By analyzing the relationship between the impedance fluctuation degree and the system stability, the structure steady state data is generated. For example, if the impedance fluctuation degree is 5%, the mapping result shows that the UPQC structure is in a stable state; if the impedance fluctuation degree exceeds 10%, the mapping result shows that the system may enter an unstable state. The finally obtained structure steady state data is used for subsequent topology evaluation.

[0146] Preferably, the topology component loss detection of the structure steady state data in step S3 includes:

[0147] Extracting the electrical steady state operating frequency, electrical steady state regulation accuracy, and electrical steady state modulation method of the structure steady state data;

[0148] Performing level adjustment conduction loss detection according to the electrical steady state operating frequency and the electrical steady state regulation accuracy to obtain regulation conduction loss data;

[0149] Based on the electrical steady-state regulation accuracy and the electrical steady-state modulation method, perform modulation measure loss detection to obtain modulation measure loss data;

[0150] Based on the electrical steady-state operating frequency and the electrical steady-state modulation method, perform operating loss detection to obtain modulation operating loss data;

[0151] Merge the regulation conduction loss data, the modulation measure loss data, and the modulation operating loss data for topological component loss to obtain topological component loss data.

[0152] In the embodiment of the present invention, through the simulation results of the UPQC topological structure model, key parameters in the structure steady-state data are extracted. For example, the electrical steady-state operating frequency is 50 Hz, the electrical steady-state regulation accuracy is ±1%, and the electrical steady-state modulation method is pulse width modulation (PWM); a power analyzer is used to detect the conduction loss of power devices (such as IGBTs) in the UPQC. Under the conditions of the electrical steady-state operating frequency (50 Hz) and the regulation accuracy (±1%), the voltage drop and current of the power device in the conduction state are measured, and the regulation conduction loss data is calculated. For example, the voltage drop of a certain IGBT in the conduction state is 2 V, the current is 100 A, and the conduction loss is 200 W. Through a simulation analysis tool, combined with the electrical steady-state regulation accuracy (±1%) and the modulation method (PWM), the switching loss during the modulation process is analyzed. For example, in PWM modulation, the switching loss is mainly determined by the switching frequency and device characteristics. Assuming the switching frequency is 10 kHz and the loss per switching process is 10 mJ, the modulation measure loss data is calculated. The overall operating loss of the UPQC under the conditions of the electrical steady-state operating frequency (50 Hz) and the modulation method (PWM) is evaluated using a simulation model. By monitoring the DC bus voltage, current, and the operating states of each power device, the total loss during operation is calculated. For example, the operating loss includes conduction loss, switching loss, and capacitor charge and discharge loss, and the total loss is 500 W. The above detected loss data is integrated to form complete topological component loss data. For example, the regulation conduction loss is 200 W, the modulation measure loss is 100 W, the modulation operating loss is 500 W, and the combined topological component loss data is 800 W.

[0153] As an example of the present invention, refer to Figure 3 As shown, in this example, step S4 includes:

[0154] Step S41: Determine the electrical energy impact amount of the topological component loss data to obtain electrical energy output impact amount data;

[0155] Step S42: Perform redundant electrical energy recording based on the electrical energy output impact data, and perform redundant adjustment interval numerical detection on the redundant electrical energy. When the redundant electrical energy is 0% - 30%, it is marked as a low-level redundant adjustment interval; when the redundant electrical energy is 30% - 70%, it is marked as a medium-level redundant adjustment interval; when the redundant electrical energy is 70% - 100%, it is marked as a high-level redundant adjustment interval;

[0156] Step S43: Integrate the low-level redundant adjustment interval, medium-level redundant adjustment interval, and high-level redundant adjustment interval to obtain the level redundant adjustment interval data;

[0157] Step S44: Evaluate the adjustment sensitivity of the topology component loss data according to the level redundant adjustment interval data to generate the electrical energy redundant adjustment sensitivity;

[0158] Step S45: Based on the electrical energy redundant adjustment sensitivity, evaluate the change in operating condition loss of the UPQC topology structure model to obtain the operating condition loss evaluation data;

[0159] Step S46: Evaluate the module performance adjustment efficiency of the UPQC topology structure model according to the operating condition loss evaluation data to obtain the module performance adjustment evaluation data;

[0160] Step S47: Summarize the operating condition loss evaluation data and the module performance adjustment evaluation data into an evaluation report to obtain a multi-level UPQC topology structure evaluation report.

[0161] In the embodiments of the present invention, a high-precision power analyzer is used to monitor the key components (such as IGBTs, capacitors, etc.) in the UPQC topology in real time and record their loss data. Through dynamic power measurement technology, combined with the fast Fourier transform (FFT) or wavelet transform, the power output signal is decomposed in the frequency domain to calculate the power values of each frequency component. For example, for a certain IGBT module, at the 50 Hz fundamental frequency, its loss is 200 W; at the 10 kHz switching frequency, the loss is 50 W. By comparing and analyzing these loss data with the power values of the power output signal, the power output influence quantity data is obtained. Based on the power output influence quantity data, the redundant electric energy is calculated. For example, if the total power output of the system is 1000 W and the actual demand is 800 W, then the redundant electric energy is 200 W. According to the percentage of the redundant electric energy, it is divided into different intervals: when the redundant electric energy is 0% - 30%, it is marked as the low-level redundant adjustment interval; when the redundant electric energy is 30% - 70%, it is marked as the medium-level redundant adjustment interval; when the redundant electric energy is 70% - 100%, it is marked as the high-level redundant adjustment interval. The above marked redundant adjustment interval data is integrated to form the complete level redundant adjustment interval data. For example, record the percentage of the redundant electric energy and its corresponding adjustment interval under different operating conditions of the system for subsequent analysis. Combining the level redundant adjustment interval data, analyze the change trend of the loss data of the topology components. For example, when the system is in the low-level redundant adjustment interval, the change of the loss data is small, indicating that the adjustment sensitivity is low; when in the high-level redundant adjustment interval, the change of the loss data is significant, indicating that the adjustment sensitivity is high. Through quantitative analysis, use simulation tools (such as MATLAB / Simulink) to simulate the UPQC topology model, and combine the power redundancy adjustment sensitivity to simulate the loss changes under different operating conditions. For example, in the low redundant adjustment interval, the simulation results show that the loss is 300 W; in the medium redundant adjustment interval, the loss is 400 W; in the high redundant adjustment interval, the loss is 500 W. Record these data as the loss evaluation data for operating conditions. Analyze the loss evaluation data for operating conditions and calculate the module performance adjustment efficiency. For example, if in a certain operating condition, the loss is reduced from 300 W to 250 W, then the adjustment efficiency is 16.7%. By comparing the adjustment efficiencies under different operating conditions, generate the module performance adjustment evaluation data. Summarize all the above evaluation data to form a multi-level UPQC topology evaluation report. The report details the loss evaluation data for operating conditions and the module performance adjustment evaluation data, providing a basis for the subsequent optimization of the topology structure.

[0162] The present invention also provides a level UPQC topology evaluation system for the above-mentioned level UPQC topology evaluation method. The level UPQC topology evaluation system includes:

[0163] The UPQC design parameter acquisition module is used to obtain the multi-level UPQC design drawings; extract the design parameters from the multi-level UPQC design drawings to obtain the UPQC design parameters;

[0164] The UPQC topology structure model construction module is used to deconstruct the electrical cooperation mode according to the UPQC design parameters; perform power connection topology mapping based on the electrical cooperation mode to obtain connection topology structure data; identify the level power flow path of the connection topology structure data to obtain power distribution path data; construct the UPQC topology structure model based on the connection topology data and the power distribution path data;

[0165] The topology component loss detection module is used to obtain the multi-level operation data; input the multi-level operation data into the UPQC topology structure model and monitor the multi-level working performance parameters; perform UPQC structure steady-state identification on the multi-level working performance parameters to generate structure steady-state data; perform topology component loss detection on the structure steady-state data to generate topology component loss data;

[0166] The topology structure module performance evaluation module is used to evaluate the sensitivity of power redundancy regulation according to the topology component loss data; perform topology structure module performance evaluation on the UPQC topology structure model based on the sensitivity of power redundancy regulation to obtain the multi-level UPQC topology structure evaluation report.

[0167] The present invention realizes the full-process automatic processing from the acquisition of multi-level UPQC design parameters to the evaluation of topology structure performance, can accurately extract design parameters, construct an accurate topology structure model, and perform real-time monitoring and analysis on multi-level operation data. The system can quantitatively evaluate the loss characteristics of topology components, identify the sensitivity of power redundancy regulation, and generate a detailed topology structure evaluation report, thereby improving the efficiency and accuracy of UPQC topology structure evaluation.

[0168] Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, it is intended to cover all changes falling within the meaning and scope of the equivalent elements of the application documents within the present invention.

[0169] The above are only the specific embodiments of the present invention, which enable those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for evaluating a multilevel UPQC topology, characterized in that, Including the following steps: Step S1: Obtain the multi-level UPQC design drawing; extract the design parameters from the multi-level UPQC design drawing to obtain the UPQC design parameters; Step S2: Decompose the electrical cooperation mode according to the UPQC design parameters; perform power connection topology mapping based on the electrical cooperation mode to obtain the connection topology structure data; identify the level power flow path for the connection topology structure data to obtain the power distribution path data; Construct a UPQC topology structure model based on the connection topology data and the power distribution path data; Step S3: Obtain the multi-level operation data; input the multi-level operation data into the UPQC topology structure model and monitor the multi-level working performance parameters; perform UPQC structure steady-state identification on the multi-level working performance parameters to generate the structure steady-state data; perform topology component loss detection on the structure steady-state data to generate the topology component loss data; Step S4: Evaluate the sensitivity of power redundancy regulation according to the topology component loss data; perform topology structure module performance evaluation on the UPQC topology structure model based on the sensitivity of power redundancy regulation to obtain a multi-level UPQC topology structure evaluation report.

2. The multi-level UPQC topology evaluation method according to claim 1, wherein Step S1 includes the following steps: Step S11: Obtain the multi-level UPQC design drawing; Step S12: Mark the hardware modules of the multi-level UPQC design drawing, where the hardware modules include a series converter module, a shunt converter module, and a DC bus energy storage element module; Step S13: Extract the number of switch connection nodes in the frequency range of 10 kHz to 50 kHz for the series converter module, extract the rated voltage range of 110 V to 400 V, and the rated current capacity, and record them as the series converter design parameters; Step S14: Extract the number of grid interfaces, current output, and voltage control parameters for the shunt converter module, and record them as the shunt converter design parameters; Step S15: Extract the voltage energy storage capacity of the DC bus energy storage element module, and extract the charge and discharge current amounts with a charge and discharge rate of 0.5C to 2C, and record them as the DC bus energy storage design parameters; Step S16: Combine the series converter design parameters, the shunt converter design parameters, and the DC bus energy storage design parameters into the UPQC design parameters.

3. The multi-level UPQC topology evaluation method according to claim 2, characterized in that, The decomposition of the electrical cooperation mode according to the UPQC design parameters in Step S2 includes: Perform node current capacity mapping on the rated current capacity according to the number of switch connection nodes to obtain the node current mapping value; perform voltage level adaptability detection on the rated voltage range based on the node current mapping value, and parameterize the adaptation relationship of the voltage level adaptability to the series converter module to generate the series converter electrical adaptation data; Determine the interface current flux for the current output according to the number of grid interfaces, perform voltage control degree detection on the shunt converter module based on the interface current flux and the voltage control parameters, and map the voltage control degree to generate the shunt converter constraint data; Based on the voltage energy storage capacity and the charge and discharge current flow, the rated energy storage capacity is detected; according to the rated energy storage capacity, the energy storage limit is determined, and the energy storage limit is used to determine the energy storage element limit for the DC bus energy storage element module, obtaining the DC bus energy storage limit data; Based on the electrical adaptation data of the series converter, the constraint data of the parallel converter, and the DC bus energy storage limit data, electrical collaborative matching is performed to obtain an electrical collaborative method.

4. The multi-level UPQC topology evaluation method according to claim 1, characterized in that The electrical connection topology mapping based on the electrical collaborative method in step S2 includes: Classify the electrical collaborative method into types, including the electrical adaptation type of the series converter, the constraint type of the parallel converter, and the DC bus energy storage limit type; Detect the total series electrical energy of the electrical adaptation type of the series converter; parameterize the series electrical energy to obtain series electrical parameters; determine the series topology structure according to the series electrical parameters, obtaining series topology structure data; Detect the parallel electrical energy distribution of the constraint type of the parallel converter; mark the parallel circuit based on the parallel electrical energy distribution, and determine the parallel topology structure based on the parallel circuit, obtaining parallel topology structure data; Detect the electrical energy buffer of the DC bus energy storage limit type; determine the DC bus buffer structure according to the electrical energy buffer, obtaining DC bus buffer structure data; Merge the series topology structure data, the parallel topology structure data, and the DC bus buffer structure to generate connection topology structure data.

5. The multi-level UPQC topology evaluation method according to claim 1, characterized in that The identification of the level power flow path for the connection topology structure data in step S2 includes: Mark and segment the connection topology structure data to generate the position of the structure segment; Detect the series voltage division amount of the position of the structure segment to obtain the series voltage division amount; Detect the parallel current division amount of the position of the structure segment to obtain the parallel current division amount; Calculate the level power difference based on the series voltage division amount and the parallel current division amount; mark the difference site for the position of the structure segment according to the level power difference, and record the power amount at the difference site, obtaining the structure segment power difference amount; Sort the structure segment power difference amounts in ascending order to obtain power ascending order data; Determine the power flow direction according to the power ascending order data and record the power ascending amount to obtain the power distribution path data.

6. The multi-level UPQC topology evaluation method according to claim 1, wherein The input of the multilevel operation data into the UPQC topology structure model and the monitoring of the multilevel working performance parameters in step S3 include: Determine the input voltage range of the multilevel operation data, and measure the level switching frequency according to the input voltage range; Identify the single-level operation characteristics based on the input voltage range and the level switching frequency, and perform multilevel operation coupling mode analysis on the single-level operation characteristics to obtain multilevel operation mode data; Input the multilevel operation mode data into the UPQC topology structure model and start the UPQC simulation; Continuously monitor the output voltage harmonics of the UPQC topology structure model and record the output voltage harmonic content; Continuously monitor the total harmonic distortion of the current of the UPQC topology structure model and record the current total harmonic distortion rate; Continuously monitor the level change response characteristics of the UPQC topology structure model and record the level response time; Integrate the harmonic content of the output voltage, the total harmonic distortion rate of the current, and the level response time to obtain the multi-level working performance parameters.

7. The multi-level UPQC topology evaluation method according to claim 6, characterized in that, The steady-state identification of the UPQC structure for the multi-level working performance parameters described in step S3 includes: Detect the harmonic order of the harmonic content of the output voltage, set the number of harmonic order detection rounds to 5 - 8 rounds, and obtain the harmonic order of the output voltage; Perform voltage harmonic time marking on the harmonic content of the output voltage according to the harmonic order of the output voltage; identify the harmonic cycle characteristics based on the voltage harmonic time and the harmonic order of the output voltage, and generate the output voltage harmonic cycle data; Measure the distortion amplitude of the total harmonic distortion rate of the current with the output voltage harmonic cycle data to obtain the level harmonic distortion amplitude value; Evaluate the impedance fluctuation of the level harmonic distortion amplitude value based on the level response time to generate the level impedance fluctuation degree; Map the stable state of the UPQC structure according to the level impedance fluctuation degree to obtain the structure steady-state data.

8. The multi-level UPQC topology evaluation method according to claim 1, wherein The detection of the topological component loss for the structure steady-state data described in step S3 includes: Extract the electrical steady-state operating frequency, electrical steady-state regulation accuracy, and electrical steady-state modulation method of the structure steady-state data; Detect the regulation conduction loss according to the electrical steady-state operating frequency and electrical steady-state regulation accuracy to obtain the regulation conduction loss data; Detect the modulation measure loss based on the electrical steady-state regulation accuracy and electrical steady-state modulation method to obtain the modulation measure loss data; Detect the operating loss based on the electrical steady-state operating frequency and electrical steady-state modulation method to obtain the modulation operating loss data; Merge the regulation conduction loss data, modulation measure loss data, and modulation operating loss data to obtain the topological component loss data.

9. The multi-level UPQC topology evaluation method according to claim 1, characterized in that Step S4 includes the following steps: Step S41: Measure the power influence amount of the topological component loss data to obtain the power output influence amount data; Step S42: Record the redundant electric energy according to the power output influence amount data, and perform numerical detection on the redundant adjustment interval of the redundant electric energy. When the redundant electric energy is 0% - 30%, it is marked as the low-level redundant adjustment interval; when the redundant electric energy is 30% - 70%, it is marked as the medium-level redundant adjustment interval; when the redundant electric energy is 70% - 100%, it is marked as the high-level redundant adjustment interval; Step S43: Integrate the low-level redundant adjustment interval, medium-level redundant adjustment interval, and high-level redundant adjustment interval to obtain the level redundant adjustment interval data; Step S44: Evaluate the adjustment sensitivity of the topological component loss data according to the level redundant adjustment interval data to generate the power redundant adjustment sensitivity; Step S45: Evaluate the change in operating condition loss of the UPQC topological structure model based on the power redundant adjustment sensitivity to obtain the operating condition loss evaluation data; Step S46: Evaluate the module performance adjustment efficiency of the UPQC topological structure model according to the operating condition loss evaluation data to obtain the module performance adjustment evaluation data; Step S47: Summarize the operating condition loss evaluation data and the module performance adjustment evaluation data to obtain the multi-level UPQC topological structure evaluation report.

10. A level UPQC topology evaluation system, characterized in that For implementing the method for evaluating the level UPQC topology structure as described in claim 1, the level UPQC topology structure evaluation system includes: A UPQC design parameter acquisition module, configured to obtain a multi-level UPQC design drawing; extract design parameters from the multi-level UPQC design drawing to obtain UPQC design parameters; A UPQC topology structure model construction module, configured to deconstruct the electrical cooperation mode according to the UPQC design parameters; perform power connection topology mapping based on the electrical cooperation mode to obtain connection topology structure data; identify the level power flow path in the connection topology structure data to obtain power distribution path data; construct a UPQC topology structure model based on the connection topology data and the power distribution path data; A topology component loss detection module, configured to obtain multi-level operation data; input the multi-level operation data into the UPQC topology structure model and monitor multi-level working performance parameters; perform UPQC structure steady-state identification on the multi-level working performance parameters to generate structure steady-state data; perform topology component loss detection on the structure steady-state data to generate topology component loss data; A topology structure module performance evaluation module, configured to evaluate the sensitivity of power redundancy regulation according to the topology component loss data; perform topology structure module performance evaluation on the UPQC topology structure model based on the sensitivity of power redundancy regulation to obtain a multi-level UPQC topology structure evaluation report.

Images