A multi-channel acquisition module, system and method based on trigger synchronous automatic calibration

Abstract

The present invention relates to a multi-channel acquisition module, system and method based on triggered synchronous automatic calibration, belonging to the field of electronic measurement. The acquisition module comprises a channel conditioning and acquisition circuit, a trigger and input / output feedback circuit, a clock synchronization and calibration signal generation circuit and an FPGA receiving and synchronization calibration circuit. The advantages of the present invention are: high multi-channel synchronization accuracy, support for convenient channel expansion, parallel interconnection delay calibration between modules, system calibration time does not increase linearly with the increase in the number of channels, and the interconnection relationship can be connected in a ring, without the need for large fan-out cables.

Description

Technical Field

[0001] The present invention relates to the field of electronic measurement technology, and in particular to a multi-channel acquisition module, system and method based on triggered synchronous automatic calibration. Background Art

[0002] In existing multi-channel acquisition systems, especially those comprised of multiple devices, the transmission of trigger signals between modules inevitably results in delay differences, leading to synchronization errors. Traditional calibration methods rely on external high-precision signal sources, which utilize fan-out devices such as power splitters to form a star network for trigger calibration. This is costly and has poor scalability, with the following drawbacks: 1. Limited synchronization accuracy: Sampling triggers are typically digital, which is limited by the data rate of standard FPGA I / O, typically resulting in accuracy at the nanosecond level. 2. Insufficient scalability: Adding acquisition channels requires adding calibration signal input connections, making it difficult to dynamically adjust delay parameters. This is difficult to achieve in very multi-channel systems. For example, for 128-channel synchronous acquisition, a tree-like structure of calibration signal connections is required when setting up the calibration network. After calibration, the measured signal must be reconnected via cables, making switching operations complex. 3. Poor real-time performance: Multi-channel synchronization relies on software-generated synchronization processing algorithms after acquiring acquired data, which cannot meet real-time acquisition requirements. Summary of the Invention

[0003] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a multi-channel acquisition module, system and method based on triggered synchronous automatic calibration, which solves the shortcomings of the prior art.

[0004] The object of the present invention is achieved by the following technical solutions: a multi-channel acquisition module based on trigger synchronization and automatic calibration, the acquisition module includes a channel conditioning and acquisition circuit, a trigger and input and output feedback circuit, a clock synchronization and calibration signal generation circuit and an FPGA receiving and synchronization calibration circuit;

[0005] The channel conditioning and acquisition circuit is configured to condition the measured signal through gain adjustment, AC / DC coupling control, and bandwidth limitation so that the signal meets the ADC sampling requirements;

[0006] The trigger and input / output feedback circuit is configured to realize the input and triggering of external trigger signals, as well as the transmission and feedback of trigger signals, so as to realize the trigger delay measurement among multiple channels;

[0007] The clock synchronization and calibration signal generation circuit is configured to generate a sampling clock, input and output a reference clock when multiple acquisition modules are cascaded, and generate a synchronization calibration signal for a single acquisition module;

[0008] The FPGA receiving and synchronization calibration circuit is configured to receive digital quantized signals sampled by each ADC, generate corresponding sampled data streams after protocol analysis, and perform edge-synchronized reading and writing after phase adjustment and edge-aligned FIFO processing in calibration mode, so that the sampled data of each channel is aligned end-to-end within the FPGA from the input interface to the data processing end.

[0009] The channel conditioning and acquisition circuit includes multiple acquisition channels, each of which includes two input sources: an external measured signal input and an internal integrated calibration signal, which are selected by a first analog switch. When triggering synchronous calibration, the first analog switch selects the calibration signal as input, and selects the measured signal as input after the calibration trigger synchronization is completed;

[0010] The selected signal is output to the ADC for collection after impedance adjustment, coupling, dynamic range adjustment, and offset adjustment. The data collected by the ADC is input to the FPGA receiving and synchronization calibration circuit;

[0011] When the ADC of each acquisition channel is working, the corresponding analog signal to digital signal conversion delay is fixed, and the sampling clock reference of all ADCs is consistent.

[0012] The trigger and input / output feedback circuit includes five signal input / output interfaces: trigger signal EXT input, master trigger input, master feedback output, slave trigger output, and slave feedback input;

[0013] After the trigger signal EXT of the previous acquisition module is selected through the second analog switch, this acquisition module is controlled to perform synchronous triggering. When performing synchronous triggering of multiple acquisition modules, the third analog switch of this acquisition module is controlled to select the main trigger input as the trigger signal of this acquisition module for synchronous acquisition of multiple acquisition modules. During trigger calibration, this acquisition module uses the main trigger input signal sent by the previous acquisition module for triggering, and after fanning out the signal, it is returned to the previous acquisition module through the main feedback output interface to perform trigger link delay measurement.

[0014] This acquisition module outputs the trigger signal to the next-level acquisition module through the trigger output interface as the main trigger input of the next-level acquisition module. During trigger calibration, this acquisition module receives the trigger signal fed back from the next-level acquisition module through the feedback input interface to measure the trigger delay from this acquisition module to the next-level acquisition module.

[0015] The clock synchronization and calibration signal generation circuit generates a clock reference signal required by the integrated phase-locked loop through a local crystal oscillator, and inputs the clock reference signal together with the externally provided clock reference signal into the integrated phase-locked loop, which selects the reference clock.

[0016] When multiple acquisition modules are interconnected for multi-channel parallel sampling, the multiple acquisition modules use phase-coherent, same-frequency reference clocks, and reference clock cascade is performed through the reference clock input and reference clock output interfaces. The clock reference output of the previous acquisition module is connected to the current acquisition module as the reference clock input of the current acquisition module. After completing the common reference, the sampling clocks of the multiple acquisition modules are in the same frequency-coherent state, which enables high-precision multi-channel synchronous acquisition. The integrated phase-locked loop generates the required acquisition master clock, and generates a divided calibration signal 10MHz and a reference clock signal 10MHz output to the next acquisition module through the integrated phase-locked loop.

[0017] The generated calibration signal is fanned out to multiple acquisition channels through a clock fanout device, while reducing the interference of jitter on the calibration signal phase. The generated calibration signal is connected to each analog channel and external trigger channel in the acquisition module respectively, and the consistency of the signal delay received by each channel is controlled by routing equal lengths.

[0018] The FPGA receiving and synchronization calibration circuit performs digital non-coding sampling of the trigger channel input signal through the SerDes interface at a rate of Gsps or higher, thereby increasing the sampling rate of the trigger signal and thereby improving the time accuracy of the trigger signal to the ps level. The obtained trigger signal sampling data is also read and written in an edge-synchronous manner, so that the trigger signal and the data of each acquisition channel are aligned in delay from the input interface end to the data processing end.

[0019] After completing the precise delay calibration, the data of all acquisition channels and trigger channels are delayed aligned from the input interface to the data processing interface. Using any signal as a trigger can achieve high-precision trigger synchronization of all parallel channels in a single acquisition module.

[0020] A multi-channel acquisition system based on triggered synchronous automatic calibration includes multiple acquisition modules. When the multiple acquisition modules are interconnected, the upper-level acquisition module outputs a clk_out signal to the lower-level acquisition module. After the clock phase reference is locked in the lower-level acquisition module, the clock reference signal is output to the lower-level acquisition module for reference, thereby achieving sampling time synchronization of the multiple acquisition modules.

[0021] A multi-channel acquisition method based on triggered synchronous automatic calibration, the acquisition method comprising:

[0022] S1. Input the calibration signal to each analog channel and trigger channel, perform conditioning and digital quantization respectively, receive it through the FPGA and synchronous calibration circuit, and obtain the digital quantization signal of each path inside the FPGA;

[0023] S2. Pass the same calibration signal through different acquisition links to obtain different delay quantization results. After clock domain conversion through asynchronous FIFO, perform edge delay calibration, control the cache read and write of each channel, correct the delay deviation of each channel, and obtain data collected synchronously by all channels;

[0024] S3. By fanning out the trigger signal from the previous acquisition module to the next acquisition module, and then returning it from the next acquisition module to the previous acquisition module to perform line delay measurement, the round-trip delay of the trigger signal transmission between the two acquisition modules is obtained. This allows the absolute delay between the trigger signal obtained by the next acquisition module and the actual trigger moment to be calculated, and the trigger moment calculation method of the next acquisition module to be corrected, thereby achieving precise trigger synchronization between the two acquisition modules.

[0025] S4. When any analog channel or trigger channel in any acquisition module in the entire system network is selected as the system trigger channel, the trigger delays of subsequent acquisition modules are accumulated and transmitted in sequence according to the trigger path transmission relationship. This controls the precise synchronization of triggering of all channels in all acquisition modules, achieving precise alignment of parallel acquisition across all channels.

[0026] The S2 specifically includes the following contents:

[0027] S21. Each acquisition channel performs quantized data analysis according to the corresponding ADC quantization protocol, and writes the corresponding data and the accompanying clock into the write port of the asynchronous FIFO inside the FPGA. At the read port of the FIFO, the master clock inside the FPGA is used to generate a read signal, synchronizing the acquired data in different clock domains to the same data processing clock domain.

[0028] S22. Process the generated quantized data in parallel to obtain parallel multi-channel data, segment the parallel multi-channel data to obtain multiple groups of data, search for the corresponding edge position in each group, set a 16-bit register, each bit characterizes whether the corresponding order satisfies the structure of the digital Schmidt comparator, set upper and lower thresholds of the comparison level when searching for the rising edge, output the corresponding result according to the relationship between the data and the upper and lower thresholds according to the set conditions, obtain multiple groups of parallel comparison result registers for each channel, and then search for whether there is an edge change from 0 to 1 in each group according to the priority of the data point. If there is a rising edge, output pos_edge_vld as 1, otherwise output as 0, and output the corresponding bit index number pos_edge_idx;

[0029] S23. Since the delays of different links are different, the beats of the edges and the corresponding pos_edge_idx are different. Therefore, pos_edge_idx is adjusted to be the same. Pos_edge_idx is used as the search condition. Data shift adjustment is performed according to different values. After adjustment, the data edge of each link is adjusted to the first sampling point under the master clock.

[0030] S24. After reset, the write enable of each FIFO is turned on according to the input pos_edge_vld signal. After judging that each FIFO reaches a certain threshold, the read enable of each FIFO is turned on synchronously to obtain the signal with the same edge after synchronization.

[0031] The S3 specifically includes the following contents:

[0032] S31. In each acquisition module, use the built-in calibration signal and the SerDes interface of the FPGA to quantize the calibration trigger signal. The quantized signal undergoes protocol deserialization, cross-clock domain synchronization conversion, edge judgment, edge sequence shifting, and edge beat alignment to obtain quantized data for trigger delay alignment in each acquisition module.

[0033] S32. The upper-level acquisition module sends the calibration signal to the lower-level acquisition module as the input signal. The lower-level acquisition module replicates the calibration signal through fan-out and feeds it back to the upper-level acquisition module. The two SerDes of the upper-level acquisition module quantize the calibration signal and the feedback signal respectively. After quantization by the two SerDes, the delay of the quantization edge is the round-trip delay of the trigger line of the two acquisition modules. The transmission delay is composed of the circuit delay of the two acquisition modules and the round-trip delay of the cable. The circuit delay is controlled by routing the trigger output and the feedback input with equal length during circuit design. Since the round-trip cable is a pair of equal-length wires, the round-trip delay of the cable is considered to be symmetrical. Therefore, the total delay value Cal_dly of the calibration signal is divided by 2 to obtain the trigger signal transmission delay Trig_pdly of the two acquisition modules.

[0034] S33. The obtained trigger signal is transmitted with a delay of Trig_pdly, recorded through a register, and then read by the control software and sent to the next-level acquisition module. The trigger position is corrected in the next-level acquisition module. Since the trigger signal of the previous-level acquisition module received by the next-level acquisition module has a delay of Trig_pdly, after the next-level acquisition module completes the trigger and waveform capture, the trigger point is advanced and the time value of Trig_pdly is corrected to obtain the real starting point. The corresponding pre-trigger depth and post-trigger depth of the next-level acquisition module are adjusted by Trig_pdly to adapt to the sampling delay caused by the trigger transmission.

[0035] The acquisition method further includes: when channel expansion is required, selecting an acquisition module to be added between any two acquisition modules in the entire system, and calibrating the delay between the new acquisition module and the upper and lower acquisition modules; after the trigger delay calibration is completed between the new acquisition module and the upper and lower acquisition modules, the system delay setting is updated, and the expanded acquisition system can be used;

[0036] The acquisition method also includes a system accuracy test, which includes: using two signals with a synchronous phase relationship as input signals for the entire multi-channel, selecting one of the two channels as a trigger channel from any two channels of the multi-channel acquisition system after calibration of the two signal input ends, observing the acquired waveform display results, and determining whether synchronous trigger acquisition is performed between the two channels through a cursor measurement function.

[0037] The present invention has the following advantages: a multi-channel acquisition module, system and method based on triggered synchronous automatic calibration, high multi-channel synchronization accuracy, support for convenient channel expansion, parallel pairwise interconnection delay calibration between modules, system calibration time does not increase linearly with the increase in the number of channels, and the interconnection relationship can be achieved using a ring connection without the need for large fan-out cables. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a schematic structural diagram of a single multi-channel acquisition module of the present invention;

[0039] Figure 2 Schematic diagram of the clock synchronization and calibration signal generation circuit;

[0040] Figure 3 This is a schematic diagram of the channel conditioning and acquisition circuit;

[0041] Figure 4 Schematic diagram of trigger and input and output feedback circuit;

[0042] Figure 5 This is a schematic diagram of the FPGA receiving and synchronization calibration circuit;

[0043] Figure 6 This is a schematic diagram of the connection structure of multiple multi-channel acquisition modules of the present invention;

[0044] Figure 7 Schematic diagram of edge sequence shift;

[0045] Figure 8 Schematic diagram of trigger delay correction for master and slave acquisition modules. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present application provided below in conjunction with the drawings is not intended to limit the scope of protection of the present application for which protection is claimed, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. The present invention is further described below in conjunction with the drawings.

[0047] like Figure 1 As shown, one embodiment of the present invention relates to a multi-channel acquisition module based on trigger synchronization and automatic calibration, which includes a channel conditioning and acquisition circuit, a trigger and input and output feedback circuit, a clock synchronization and calibration signal generation circuit, and an FPGA receiving and synchronization calibration circuit.

[0048] Furthermore, if Figure 2 As shown, the clock synchronization and calibration signal generation circuit realizes the generation of sampling clock and the reference clock input and output functions when multiple modules are cascaded, and by adding a signal fan-out circuit, the synchronization calibration signal generation of a single module is realized.

[0049] The local crystal oscillator generates the clock reference signal required by the integrated phase-locked loop (PLL). This signal, along with the externally supplied clock reference signal, is input into the integrated phase-locked loop (PLL), which then selects the reference clock. The local crystal oscillator uses an oven-controlled crystal oscillator with an initial accuracy of ≤±0.3ppm at the reference temperature.

[0050] When interconnecting multiple acquisition modules for multi-channel parallel sampling, they need to use phase-coherent, co-frequency reference clocks. Reference clock cascade can be achieved through the reference clock input and output interfaces. Connecting the clock reference output of the upper-level module to this module serves as its reference clock input. Once this common reference is established, the sampling clocks of multiple acquisition modules are frequency-coherent, enabling high-precision, multi-channel synchronous acquisition. An integrated phase-locked loop (PLL) is used to generate the required system acquisition master clock. This PLL also generates a divided 10MHz calibration signal and a 10MHz reference clock signal for output to subsequent stages.

[0051] The generated calibration signal is fanned out to multiple acquisition channels through a clock fanout. A low-jitter fanout is used to minimize jitter interference on the calibration signal phase. The generated calibration signal is connected to the analog channels (CH1-CH4) and external trigger channel (EXT) of a single acquisition module. By routing equal trace lengths, the signal delay consistency received by each channel is controlled. Using a low-jitter fanout to generate synchronized calibration signals across multiple channels effectively ensures excellent synchronization performance of the calibration source and improves system synchronization accuracy.

[0052] Furthermore, if Figure 3 As shown in the figure, the function of the channel conditioning and acquisition circuit is to condition the measured signal (external input or internal calibration signal) through circuits such as gain adjustment, AC / DC coupling control, and bandwidth limitation so that the external signal meets the ADC sampling requirements.

[0053] Each acquisition channel has two input sources: an external measured signal (e.g., CH1) and an internal calibration signal (calibration signal fan-out 1). These are selected via a 2:1 analog switch. The analog switch uses high-bandwidth signal relays to ensure the circuit's signal bandwidth is not affected by the inserted switch. During trigger-synchronized calibration, the internal calibration signal is selected as the input. After calibration trigger synchronization is complete, the measured signal is selected as the input.

[0054] The selected signal is output to the ADC for acquisition according to the corresponding conditioning circuits such as impedance adjustment, coupling, dynamic range adjustment, and offset adjustment of the acquisition system.

[0055] The ADC used to acquire signals supports a variety of interfaces and synchronization methods, including common LVDS parallel output, JESD protocol output, and serial output with synchronization frames. In this invention, the corresponding analog-to-digital conversion delay is fixed when each acquisition channel ADC is operating, and the sampling clock reference of all ADCs is consistent. Data collected by the ADCs is fed into the FPGA for subsequent alignment and processing. The calibration signal period used is greater than the maximum transmission conversion period of all acquisition links, ensuring that all acquisition links are aligned and deferred after the FPGA alignment process.

[0056] Furthermore, if Figure 4As shown in the figure, the trigger and input / output feedback circuit implements the input and triggering functions of external trigger signals, as well as the transmission and feedback of trigger signals, enabling trigger delay measurement across multiple channels. This circuit includes five signal input and output interfaces. The external trigger interface (EXT) uses a conventional interface (such as a BNC). The remaining master trigger input, slave feedback output, slave trigger output, and slave feedback input are dedicated multi-channel synchronization lines, interconnected using high-density integrated cables to reduce connector space. Because all signals in this circuit are transmitted using analog signals, they exhibit ultra-low jitter, enabling the trigger synchronization signal to achieve picosecond-level precision.

[0057] The trigger signal EXT from the upstream master acquisition module is selected via an analog switch to control the synchronous triggering of this acquisition module. When synchronizing multiple acquisition modules, the switches in the slave acquisition modules select the master trigger input signal as the trigger signal for this acquisition module. During trigger calibration, this acquisition module triggers using the master trigger input signal from the upstream module. This signal is then fanned out and transmitted back to the upstream module via the master feedback output interface for trigger link delay measurement.

[0058] This acquisition module outputs the used trigger signal to the next-level slave acquisition module as the main trigger input of the next-level slave acquisition module; during trigger calibration, this acquisition module receives the trigger signal fed back from the next-level slave acquisition module and performs trigger delay measurement from this acquisition module to the next-level slave acquisition module.

[0059] Furthermore, if Figure 5 As shown in the figure, the FPGA in the FPGA receiving and synchronization calibration circuit simulates the digital quantization signal sampled by each ADC, and after protocol analysis, generates the corresponding sampled data stream. Depending on the transmission protocol, there will be a corresponding accompanying clock.

[0060] In calibration mode, the asynchronous cache phase modulation module writes the received acquisition signal into an asynchronous FIFO (first-in, first-out queue). After phase adjustment and edge alignment FIFO processing, the output data is precisely phase-aligned within the FPGA through edge-synchronous reading and writing methods. This allows the sampling data of each channel to be end-to-end aligned in delay from the input interface end to the data processing end within the FPGA.

[0061] For the signal input by the trigger channel, digital non-coding sampling of more than Gsps (giga sampling) is performed through the SerDes interface to increase the sampling rate of the trigger signal, thereby improving the time accuracy of the trigger signal to the ps level (the conventional solution is ordinary IO port sampling with an accuracy of ns level). The obtained trigger signal sampling data is also read and written by the edge synchronization method, so that the trigger signal and the data of each acquisition channel are end-to-end aligned in delay from the input interface end to the data processing end.

[0062] After completing the above-mentioned precise delay calibration, the data of all acquisition channels and trigger channels are delayed aligned from the input interface to the data processing interface. Using any signal as a trigger, high-precision trigger synchronization can be achieved for all parallel channels within a single module.

[0063] The delay adjustment of trigger synchronization is automatically completed by the FPGA logic, and the software is not aware of the delay calibration data. It can be automatically completed by the FPGA logic control hardware during the power-on initialization process of a single module.

[0064] like Figure 6 As shown, another embodiment of the present invention relates to a multi-channel acquisition system based on trigger synchronous automatic calibration, which is composed of multiple multi-channel acquisition modules in the previous embodiment. When multiple acquisition modules are interconnected, Figure 6 The middle dashed line represents the reference clock connection method between multiple modules. The ACQ1 module outputs the clk_out signal to the ACQ2 module. After the clock phase reference is locked in the ACQ2 module, the ACQ2 module outputs the clock reference signal to the ACQ3 module for reference. And so on, the sampling time synchronization of multiple modules can be achieved.

[0065] Figure 6 The solid lines in the middle represent trigger-related input and output connections. As shown in the introduction to the signal interface of a single module, the master acquisition module, serving as the trigger channel, needs to output the trigger signal to the slave acquisition module. Each cascaded module needs to have two signals connected to the upper-level module: receiving the trigger synchronization signal sent by the upper-level module and returning the delayed trigger synchronization signal to the upper-level module, while maintaining the same signal transmission with the next-level module.

[0066] The last slave acquisition module ACQN, then the master acquisition module is used as ACQ1 as the slave acquisition module for signal connection. In this way, all modules are connected to form a first connected ring system.

[0067] Another embodiment of the present invention relates to a multi-channel acquisition method based on triggered synchronous automatic calibration, which specifically includes the following contents:

[0068] S1, calibration data acquisition in each channel;

[0069] The calibration signal is input to each analog channel and trigger channel for conditioning and digital quantization. The signal is then received by the FPGA, generating the digital quantized signal for each path. Due to differences in conditioning methods, analog-to-digital quantization methods, and digital signal transmission and analysis methods, each link will experience varying end-to-end delays from the moment the calibration signal is input to the moment the quantized signal is received by the FPGA. T_dly1 and T_dly2 are fixed after initialization.

[0070] S2, multi-channel trigger delay calibration and alignment in a single acquisition module;

[0071] By passing the same calibration signal through different acquisition links, different delay quantization results are obtained. After clock domain conversion through the asynchronous FIFO, edge delay calibration is performed. Controlling the cache read and write control of each channel corrects the delay deviation of each channel, and data is acquired synchronously from all channels on the FPGA. In this case, using any channel of a single module as a trigger signal, all other triggers can achieve precise synchronous acquisition.

[0072] Furthermore, S2 specifically includes the following contents:

[0073] S21, cross-clock domain synchronous conversion;

[0074] The data output by the ADC after sampling and quantization typically has a corresponding associated clock. Therefore, after receiving the data, the FPGA needs to perform clock synchronization processing and convert the data to the same clock domain. In this method, each acquisition channel parses the quantized data according to the quantization protocol of the corresponding ADC and writes the corresponding data and associated clock to the write port of the FPGA's internal asynchronous FIFO.

[0075] At the read port of the FIFO, the master clock inside the FPGA is used to generate a read signal to synchronize the collected data in different clock domains to the same data processing clock domain.

[0076] In this process, due to the reset logic of each asynchronous FIFO and the cross-clock domain processing of data, the delay of each data initialization may be different. This difference is processed by the subsequent delay synchronization processing algorithm.

[0077] S22, low congestion parallel edge judgment;

[0078] Due to the frequency limitations of the internal master clock, the quantized data generated by the received quantized sampled signals in the FPGA is typically processed in parallel. For a 10 GHz signal, 312.5 MHz is used for processing, resulting in 32 samples per master clock. For analog signals with fixed input delays, after passing through different analog-to-digital conversion links, the arrangement of the quantized data contains the delay information for the corresponding links. By setting up digital comparisons, the input phase synchronization point can be found in different quantization delay links.

[0079] To acquire data delay information at sampling rates of 10Gsps, 20Gsps, and higher, multi-channel parallel data processing is required. Due to timing requirements and logic level limitations in FPGAs, this invention splits the parallel multi-channel data to reduce the number of parallel channels. The 32 data points N0, N1…N31 at one clock are divided into two groups: the first group consists of N-1, N0…N15, and the second group consists of N15, N16…N31.

[0080] When processing ADC-quantized data, the low bits often appear as random noise due to quantization noise and errors. Therefore, a Schmitt threshold comparison is required for comparison. Within each group, the corresponding edge position is searched and a 16-bit register is set. Each bit indicates whether the corresponding sequence satisfies the structure of a digital Schmitt comparator. When searching for rising edges, the upper and lower comparison thresholds (com_h and com_l) are set. Based on the relationship between the data and the thresholds, the corresponding results are output according to the following conditions.

[0081] Condition 1: Nn>com_h, Condition 2: Nn>com_l, Condition 3: com_l≤Nn≤com_h;

[0082] If condition 1 is met, the bit outputs 1; if condition 2 is met, the bit outputs 0; if condition 3 is met, the bit uses the result of the previous comparison.

[0083] When processing triggers, which usually use high-speed SerDes for quantization, the converted register can be directly obtained because the quantization result is only 1 bit.

[0084] After obtaining multiple sets of parallel comparison result registers for each channel, first check within each set whether there is an edge change from 0 to 1 according to the priority of the data points. If so, the rising edge pos_edge_vld is output as 1; otherwise, it is output as 0 and the corresponding bit index pos_edge_idx is output.

[0085] When the sampling rate is extended, parallel multi-channel data can be split and combined to achieve parallel trigger position search at the 32-bit level or above within the FPGA.

[0086] S23, edge sequence shift;

[0087] After edge detection of the data, pos_edge_vld and pos_edge_idx are obtained. Due to the different delays of different links, the beats of the edges and the corresponding pos_edge_idx are different.

[0088] First, adjust pos_edge_idx to be the same, use pos_edge_idx as the search condition, and adjust the data shift according to different values. Figure 7 As shown in the figure, taking 32 channels of data per clock as an example, the data from two consecutive clocks (N0, N1, N2…N31, N32, N33…N62, N63) is shifted and updated at each clock. The corresponding data is selected for output based on pos_edge_idx. When pos_edge_idx is 1, the data obtained at each clock are N1 to N32, N33 to N64, and N65 to N96, respectively. The same applies to other cases. This adjustment aligns the data edge of each link to the first sampling point of the master clock.

[0089] S24, edge beat alignment operation;

[0090] Due to different link delays, the edges of the synchronized data paths appear at different clocks, requiring different delay adjustments for synchronization. In this method, the read and write control of the synchronous FIFO is used to synchronize the signal delay.

[0091] After reset, the write enable of each FIFO is turned on according to the input pos_edge_vld signal. After judging that each FIFO has reached a certain threshold, the read enable of each FIFO is turned on synchronously, and the signal with the same edge after synchronization can be obtained.

[0092] After the above algorithm process is processed, the data of each acquisition link can be synchronously triggered and aligned in the FPGA, and the propagation delay and conversion quantization delay in the link are compensated by adjusting the algorithm.

[0093] S3, precise calibration of trigger delay of adjacent master and slave acquisition modules;

[0094] Under the premise of achieving the aforementioned single-module multi-channel trigger synchronization, line delay measurement is performed by fanning out the trigger signal from the master acquisition module to the slave acquisition module, and then returning it from the slave acquisition module to the master acquisition module. This high-sampling-rate signal delay measurement, achieved solely using an FPGA without the need for a high-speed ADC, allows the round-trip delay of the trigger signal between the two modules to be determined. This allows the absolute delay between the trigger signal received from the slave acquisition module and the actual trigger moment to be calculated, and the trigger moment calculation method of the slave acquisition module to be corrected, achieving precise trigger synchronization between the master and slave acquisition modules. Because of the round-trip measurement method, there are no stringent requirements for the delay value of the interconnecting cables between the modules. Delay correction is performed by the system, reducing the hardware requirements during use.

[0095] Furthermore, the delay calibration between adjacent acquisition modules is implemented as follows:

[0096] S31, each acquisition module triggers acquisition synchronization calibration;

[0097] In each module, the built-in calibration signal is used to quantize the calibration trigger signal using the FPGA's high-speed SerDes interface. The quantized signal uses a method similar to the above section, undergoing protocol deserialization, cross-clock domain synchronization conversion, edge judgment, edge sequence shifting, and edge beat alignment to obtain quantized data for trigger delay alignment in each module.

[0098] S32, the master-slave acquisition module triggers delay measurement;

[0099] The master acquisition module ACQ1 sends the calibration pulse signal to the slave acquisition module ACQ2 through the ACQ1 trigger output interface. The slave acquisition module ACQ2 selects the signal as the input signal, replicates the signal through fan-out, and sends it back to the ACQ1 slave feedback input through the ACQ2 master feedback output interface of ACQ2.

[0100] In ACQ1, two high-speed SerDes (SerDes) quantize the calibration signal from ACQ1 and the feedback signal from ACQ2, respectively. The calibration signal is output from the fanout, passes through a cable, the internal fanout of ACQ2, and the feedback cable, and then returns to ACQ1. After being quantized by the two SerDes, the delay between the quantization edges is the round-trip delay between the two module trigger lines.

[0101] The transmission delay is composed of the circuit delay of the master and slave acquisition modules and the round-trip cable delay. The circuit delay is achieved by aligning the trigger output and feedback input with equal lengths during circuit design, enabling high-precision delay control. The round-trip cable delay can be assumed to be symmetrical because the round-trip cables are a pair of equal-length conductors. Therefore, the total calibration signal delay, Cal_dly, can be divided by 2 to obtain the trigger signal transmission delay, Trig_pdly, for the master and slave acquisition modules.

[0102] S33, master-slave acquisition module trigger delay correction;

[0103] like Figure 8 As shown in the figure, the received trigger signal is delayed by Trig_pdly and recorded in a register. After being read by the control software, it is sent to the slave acquisition module, where the trigger position is corrected. Because the trigger signal from the master acquisition module received by the slave acquisition module is delayed by Trig_pdly, after the slave acquisition module completes triggering and waveform capture, the trigger point is advanced and the Trig_pdly time value is corrected to obtain the actual trigger point.

[0104] Since the trigger point is moved forward by the acquisition module, the corresponding pre-trigger depth and post-trigger depth of the acquisition module need to be adjusted accordingly Trig_pdly to adapt to the sampling delay caused by the trigger transmission.

[0105] S4, trigger delay correction in multi-acquisition module multi-channel system;

[0106] After completing the trigger synchronization of the master-slave relationship described above, a one-dimensional array corresponding to the trigger delay correction value Trig_pdly of each adjacent acquisition module in all interconnected modules can be obtained. When any analog or external trigger channel in any module in the entire system network is selected as the system trigger channel, the trigger delays of subsequent modules are accumulated and issued in sequence according to the trigger path transmission relationship. This can control the precise synchronization of triggering of all channels in all modules, resulting in precise alignment of parallel acquisition of all channels.

[0107] S5, delay correction during system expansion;

[0108] When channel expansion is required, a module can be added between any two modules in the ring system. Only the delay between the new module and the upstream and downstream modules needs to be calibrated, eliminating the need to recalibrate the entire system. Once the trigger delay between the new module and the upstream and downstream modules is calibrated, the system delay settings can be updated and the expanded acquisition system can be used.

[0109] At the same time, in the interface for triggering correction Trig_pdly, a software delay adjustment interface that can be adjusted by the user is reserved, which can be further followed up with the user's actual measurement results for correction.

[0110] S6, system accuracy test;

[0111] Use two signals with a strictly synchronized phase relationship as the entire multi-channel input signal. For example, you can use a pulse signal through a power splitter to generate two input signals with fixed phases. Input these two signals into any two channels of a calibrated multi-channel acquisition system. Select one of the two channels as the trigger channel, observe the acquired waveform display, and use the cursor measurement function to determine whether the two channels are synchronously triggered and acquired.

[0112] When testing system accuracy, software automatically calculates the signal delay in the data collected by the two channels. Edge detection is implemented using software, comparing the horizontal coordinate differences of the edges of the two channels and recording the results in a statistical histogram. Histogram statistics can be used to measure the overall synchronization accuracy of the system after multiple tests.

[0113] The foregoing description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein and should not be construed as excluding other embodiments. Rather, the present invention is capable of various other combinations, modifications, and improvements, and is capable of modifications within the scope of the concepts described herein, through the above teachings, or through techniques or knowledge in the relevant fields. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention are intended to be within the scope of the appended claims.

Claims

1. A multi-channel acquisition module based on triggered synchronous automatic calibration, characterized by: The acquisition module includes a channel conditioning and acquisition circuit, a trigger and input and output feedback circuit, a clock synchronization and calibration signal generation circuit, and an FPGA receiving and synchronization calibration circuit; The channel conditioning and acquisition circuit is configured to condition the measured signal through gain adjustment, AC / DC coupling control, and bandwidth limitation so that the signal meets the ADC sampling requirements; The trigger and input / output feedback circuit is configured to realize the input and triggering of external trigger signals, as well as the transmission and feedback of trigger signals, so as to realize the trigger delay measurement among multiple channels; The clock synchronization and calibration signal generation circuit is configured to generate a sampling clock, input and output a reference clock when multiple acquisition modules are cascaded, and generate a synchronization calibration signal for a single acquisition module; The FPGA receiving and synchronization calibration circuit is configured to receive the digital quantized signals sampled by each ADC, generate corresponding sampled data streams after protocol analysis, and read and write data using edge synchronization after phase adjustment and edge alignment FIFO processing in calibration mode, so that the sampled data of each channel is aligned end-to-end in the FPGA from the input interface to the data processing end; The trigger and input / output feedback circuit includes five signal input / output interfaces: trigger signal EXT input, master trigger input, master feedback output, slave trigger output, and slave feedback input; After the trigger signal EXT of the previous acquisition module is selected through the second analog switch, this acquisition module is controlled to perform synchronous triggering. When performing synchronous triggering of multiple acquisition modules, the third analog switch of this acquisition module is controlled to select the main trigger input as the trigger signal of this acquisition module for synchronous acquisition of multiple acquisition modules. During trigger calibration, this acquisition module uses the main trigger input signal sent by the previous acquisition module for triggering, and after fanning out the signal, it is returned to the previous acquisition module through the main feedback output interface to perform trigger link delay measurement. This acquisition module outputs the trigger signal to the next-level acquisition module through the trigger output interface as the main trigger input of the next-level acquisition module. During trigger calibration, this acquisition module receives the trigger signal fed back from the next-level acquisition module through the feedback input interface to measure the trigger delay from this acquisition module to the next-level acquisition module.

2. The multi-channel acquisition module based on triggered synchronous automatic calibration according to claim 1, characterized in that: The channel conditioning and acquisition circuit includes multiple acquisition channels, each of which includes two input sources: an external measured signal input and an internal integrated calibration signal, which are selected by a first analog switch. When triggering synchronous calibration, the first analog switch selects the calibration signal as input, and selects the measured signal as input after the calibration trigger synchronization is completed; The selected signal is output to the ADC for collection after impedance adjustment, coupling, dynamic range adjustment, and offset adjustment. The data collected by the ADC is input to the FPGA receiving and synchronization calibration circuit; When the ADC of each acquisition channel is working, the corresponding analog signal to digital signal conversion delay is fixed, and the sampling clock reference of all ADCs is consistent.

3. The multi-channel acquisition module based on triggered synchronous automatic calibration according to claim 1, characterized in that: The clock synchronization and calibration signal generation circuit generates a clock reference signal required by the integrated phase-locked loop through a local crystal oscillator, and inputs the clock reference signal together with the externally provided clock reference signal into the integrated phase-locked loop, which selects the reference clock. When multiple acquisition modules are interconnected for multi-channel parallel sampling, the multiple acquisition modules use phase-coherent, same-frequency reference clocks, and reference clock cascade is performed through the reference clock input and reference clock output interfaces. The clock reference output of the previous acquisition module is connected to the current acquisition module as the reference clock input of the current acquisition module. After completing the common reference, the sampling clocks of the multiple acquisition modules are in the same frequency-coherent state, which enables high-precision multi-channel synchronous acquisition. The integrated phase-locked loop generates the required acquisition master clock, and generates a divided calibration signal 10MHz and a reference clock signal 10MHz output to the next acquisition module through the integrated phase-locked loop. The generated calibration signal is fanned out to multiple acquisition channels through a clock fanout device, while reducing the interference of jitter on the calibration signal phase. The generated calibration signal is connected to each analog channel and external trigger channel in the acquisition module respectively, and the consistency of the signal delay received by each channel is controlled by routing equal lengths.

4. The multi-channel acquisition module based on triggered synchronous automatic calibration according to claim 1, characterized in that: The FPGA receiving and synchronization calibration circuit performs digital non-coding sampling of the trigger channel input signal through the SerDes interface at a rate of Gsps or higher, thereby increasing the sampling rate of the trigger signal and thereby improving the time accuracy of the trigger signal to the ps level. The obtained trigger signal sampling data is also read and written in an edge-synchronous manner, so that the trigger signal and the data of each acquisition channel are aligned in delay from the input interface end to the data processing end. After completing the precise delay calibration, the data of all acquisition channels and trigger channels are delayed aligned from the input interface to the data processing interface. Using any signal as a trigger can achieve high-precision trigger synchronization of all parallel channels in a single acquisition module.

5. A multi-channel acquisition system based on triggered synchronous automatic calibration, characterized by: The system includes multiple acquisition modules according to any one of claims 1 to 4; when the multiple acquisition modules are interconnected, the upper-level acquisition module outputs a clk_out signal to the lower-level acquisition module, and after the clock phase reference is locked in the lower-level acquisition module, the clock reference signal is output to the lower-level acquisition module for reference, thereby achieving sampling time synchronization of the multiple acquisition modules.

6. A multi-channel acquisition method based on triggered synchronous automatic calibration, characterized in that: The collection method includes: S1. Input the calibration signal to each analog channel and trigger channel, perform conditioning and digital quantization respectively, receive it through the FPGA and synchronous calibration circuit, and obtain the digital quantization signal of each path inside the FPGA; S2. Pass the same calibration signal through different acquisition channels to obtain different delay quantization results. After clock domain conversion through the asynchronous FIFO inside the FPGA, edge delay calibration is performed to control the cache read and write of each channel, correct the delay deviation of each channel, and obtain data collected synchronously by all channels; S3. By fanning out the trigger signal from the previous acquisition module to the next acquisition module, and then returning it from the next acquisition module to the previous acquisition module to perform line delay measurement, the round-trip delay of the trigger signal transmission between the two acquisition modules is obtained. This allows the absolute delay between the trigger signal obtained by the next acquisition module and the actual trigger moment to be calculated, and the trigger moment calculation method of the next acquisition module to be corrected, thereby achieving precise trigger synchronization between the two acquisition modules. S4. When any analog channel or trigger channel in any acquisition module in the entire system network is selected as the system trigger channel, the trigger delays of subsequent acquisition modules are accumulated and issued in sequence according to the trigger path transmission relationship, thereby controlling all channels of all acquisition modules to trigger accurately synchronously, and obtaining the result of precise alignment of parallel acquisition of all channels.

7. The multi-channel acquisition method based on triggered synchronous automatic calibration according to claim 6, characterized in that: The S2 specifically includes the following contents: S21. Each acquisition channel performs quantized data analysis according to the corresponding ADC quantization protocol, and writes the corresponding data and the accompanying clock into the write port of the asynchronous FIFO inside the FPGA. At the read port of the FIFO, the master clock inside the FPGA is used to generate a read signal, synchronizing the acquired data in different clock domains to the same data processing clock domain. S22. Process the generated quantized data in parallel to obtain parallel multi-channel data, segment the parallel multi-channel data to obtain multiple groups of data, search for the corresponding edge position in each group, set a 16-bit register, each bit characterizes whether the corresponding order satisfies the structure of the digital Schmidt comparator, set upper and lower thresholds of the comparison level when searching for the rising edge, output the corresponding result according to the relationship between the data and the upper and lower thresholds according to the set conditions, obtain multiple groups of parallel comparison result registers for each channel, and then search for whether there is an edge change from 0 to 1 in each group according to the priority of the data point. If there is a rising edge, output pos_edge_vld as 1, otherwise output as 0, and output the corresponding bit index number pos_edge_idx; S23. Since the delays of different links are different, the beats of the edges and the corresponding pos_edge_idx are different. Therefore, pos_edge_idx is adjusted to be the same. Pos_edge_idx is used as the search condition. Data shift adjustment is performed according to different values. After adjustment, the data edge of each link is adjusted to the first sampling point under the master clock. S24. After reset, the write enable of each FIFO is turned on according to the input pos_edge_vld signal. After judging that each FIFO has reached the threshold, the read enable of each FIFO is turned on synchronously to obtain the signal with the same edge after synchronization.

8. The multi-channel acquisition method based on triggered synchronous automatic calibration according to claim 6, characterized in that: The S3 specifically includes the following contents: S31. In each acquisition module, use the built-in calibration signal and the SerDes interface of the FPGA to quantize the calibration trigger signal. The quantized signal undergoes protocol deserialization, cross-clock domain synchronization conversion, edge judgment, edge sequence shifting, and edge beat alignment to obtain quantized data for trigger delay alignment in each acquisition module. S32. The upper-level acquisition module sends the calibration signal to the lower-level acquisition module as the input signal. The lower-level acquisition module replicates the calibration signal through fan-out and feeds it back to the upper-level acquisition module. The two SerDes of the upper-level acquisition module quantize the calibration signal and the feedback signal respectively. After quantization by the two SerDes, the delay of the quantization edge is the round-trip delay of the trigger line of the two acquisition modules. The transmission delay is composed of the circuit delay of the two acquisition modules and the round-trip delay of the cable. The circuit delay is controlled by routing the trigger output and the feedback input with equal length during circuit design. Since the round-trip cable is a pair of equal-length wires, the round-trip delay of the cable is considered to be symmetrical. Therefore, the total delay value Cal_dly of the calibration signal is divided by 2 to obtain the trigger signal transmission delay Trig_pdly of the two acquisition modules. S33. The obtained trigger signal is transmitted with a delay of Trig_pdly, recorded through a register, and then read by the control software and sent to the next-level acquisition module. The trigger position is corrected in the next-level acquisition module. Since the trigger signal of the previous-level acquisition module received by the next-level acquisition module has a delay of Trig_pdly, after the next-level acquisition module completes the trigger and waveform capture, the trigger point is advanced and the time value of Trig_pdly is corrected to obtain the real starting point. The corresponding pre-trigger depth and post-trigger depth of the next-level acquisition module are adjusted by Trig_pdly to adapt to the sampling delay caused by the trigger transmission.

9. A multi-channel acquisition method based on triggered synchronous automatic calibration according to any one of claims 6 to 8, characterized in that: The acquisition method further includes: when channel expansion is required, selecting an acquisition module to be added between any two acquisition modules in the entire system, and calibrating the delay between the new acquisition module and the upper and lower acquisition modules; after the trigger delay calibration is completed between the new acquisition module and the upper and lower acquisition modules, the system delay setting is updated, and the expanded acquisition system can be used; The acquisition method also includes a system accuracy test, which includes: using two signals with a synchronous phase relationship as input signals for the entire multi-channel, selecting one of the two channels as a trigger channel from any two channels of the multi-channel acquisition system after calibration of the two signal input ends, observing the acquired waveform display results, and determining whether synchronous trigger acquisition is performed between the two channels through a cursor measurement function.

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