Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and electronic equipment. The semiconductor device comprises a plurality of vertically stacked transistors; a first word line and a second word line penetrate through different layers and extend in the direction perpendicular to the substrate; the transistor comprises a semiconductor layer; the semiconductor layers of the transistors in different layers are disconnected; the first word line comprises a first vertical part and a plurality of first extension parts extending from the first vertical part to one side of the second word line, and the plurality of first extension parts are distributed at intervals and are in one-to-one correspondence with the plurality of transistors; the second word line comprises a plurality of first grooves which are distributed at intervals and have openings facing the first word line, a second groove which extends along the inner wall of the first groove and has an opening facing the first word line is formed in the semiconductor layer, and the second groove is filled with a first extension part corresponding to the transistor to which the semiconductor layer belongs. According to the scheme provided by the embodiment of the invention, a double-word-line stacked transistor structure is provided, a memory array without a gating transistor is conveniently realized, the process is simplified, and the cost is reduced.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are increasingly reduced, and the types and quantities of devices included in a single chip increase accordingly, making any minor difference in the process production likely to affect the device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since Moore's Law came out, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the requirements of current products. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this document. This overview is not intended to limit the scope of protection of the claims.

[0005] This application provides a semiconductor device, a manufacturing method thereof, and an electronic device, which simplify the process.

[0006] Embodiments of this application provide a semiconductor device, including:

[0007] A plurality of transistors, stacked along a direction perpendicular to the substrate in different layers;

[0008] A first word line, extending along a direction perpendicular to the substrate through the different layers;

[0009] A second word line, extending along a direction perpendicular to the substrate through the different layers;

[0010] The transistor includes: a semiconductor layer; the semiconductor layers of the transistors in different layers are disconnected from each other;

[0011] The first word line includes a first vertical portion and a plurality of first extending portions extending from the first vertical portion toward the second word line side, the plurality of first extending portions are spaced apart along a direction perpendicular to the substrate and correspond to the plurality of transistors one by one; the second word line includes a plurality of first grooves spaced apart along a direction perpendicular to the substrate with openings facing the first word line, the semiconductor layer is formed with second grooves extending along the inner walls of the first grooves with openings facing the first word line, and the first extending portion corresponding to the transistor to which the semiconductor layer belongs fills the second groove.

[0012] In some embodiments, the transistor also includes a first electrode and a second electrode connected to the semiconductor layer, the first electrode and the second electrode are arranged on both sides of the first word line and distributed along a first direction, the first word line and the second word line are distributed along a second direction, and the first direction and the second direction intersect and are parallel to the substrate.

[0013] In some embodiments, the first word line also includes a plurality of second extension portions extending from the first vertical portion toward one side of the first electrode, the plurality of second extension portions are spaced apart in a direction perpendicular to the substrate and correspond one-to-one to the plurality of transistors, the semiconductor layer also forms a third groove formed by the second groove extending in a direction parallel to the substrate and opening toward the first word line, and the second extension portion corresponding to the transistor to which the semiconductor layer belongs fills the third groove.

[0014] In some embodiments, the first electrode is connected to a side of the third groove facing away from the second electrode.

[0015] In some embodiments, the second groove includes a bottom wall and a first side wall and a second side wall parallel to the substrate and respectively connected to the bottom wall; the semiconductor layer also includes a first extension portion formed by the first side wall extending in a direction parallel to the substrate and away from the third groove, and a second extension portion formed by the second side wall extending in a direction parallel to the substrate and away from the third groove; the second electrode is connected to the first extension portion on one side facing the second extension portion, and is connected to the second extension portion on one side facing the first extension portion.

[0016] In some embodiments, the first word line also includes a plurality of third extension portions extending from the first vertical portion toward one side of the second electrode, the plurality of third extension portions are spaced apart in a direction perpendicular to the substrate and correspond one-to-one to the plurality of transistors, the first extension portion, the second extension portion and the second electrode form a fourth groove opening toward the first word line, and the third extension portions corresponding to the transistors to which the first extension portion and the second extension portion belong fill the fourth groove.

[0017] In some embodiments, the second word line is further formed with a fifth groove opening toward the second electrode, the first extension portion extends to the fifth groove along a direction parallel to the substrate, the second extension portion extends to the fifth groove along a direction parallel to the substrate, and the second electrode fills the fifth groove.

[0018] In some embodiments, the second word line is further formed with a sixth groove opening toward the first electrode, and the first electrode extends along an inner wall of the sixth groove.

[0019] In some embodiments, the second word line also fills a groove formed by an adjacent first protruding portion and the first vertical portion on the first word line.

[0020] In some embodiments, the semiconductor device further includes:

[0021] Insulating layers and conductive layers alternately distributed along a direction perpendicular to the substrate; holes penetrating through the insulating layers and the conductive layers; the holes include first sub-holes located in the insulating layers and second sub-holes located in the conductive layers, and the second sub-holes have seventh grooves extending in a horizontal direction with respect to the first sub-holes.

[0022] In some embodiments, the semiconductor device further includes: a plurality of capacitors, the capacitors including a first capacitor electrode and a second capacitor electrode, and the first electrode is multiplexed with the first capacitor electrode.

[0023] In some embodiments, the second capacitor electrode includes a first sub-electrode;

[0024] In the hole, the first capacitor electrode surrounding the first sub-electrode, the first dielectric layer surrounding the first sub-electrode, and the first sub-electrode are sequentially distributed from the outside to the inside.

[0025] In some embodiments, the first capacitor electrode is distributed on the inner wall of the seventh groove, the first sub-electrode extends in a direction perpendicular to the substrate and has a protruding portion extending into the seventh groove, and the first sub-electrode fills the hole.

[0026] In some embodiments, the second capacitor electrode further includes a second sub-electrode;

[0027] The second sub-electrode is distributed on the side of the first capacitor electrode facing away from the substrate, the side facing the substrate, and the side facing away from the semiconductor layer, and a second dielectric layer is provided between the second sub-electrode and the first capacitor electrode.

[0028] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including:

[0029] Providing a substrate, and forming a stacked structure including alternately arranged insulating layers and sacrificial layers on the substrate;

[0030] Performing patterning on the stacked structure to form a first trench penetrating through the stacked structure, the first trench extending in a first direction; a transistor region is included between adjacent first trenches spaced apart in a second direction; the first direction and the second direction intersect and are parallel to the substrate;

[0031] Form a first hole in the transistor region that penetrates the stacked structure in a direction perpendicular to the substrate, the first hole being close to one of two first trenches adjacent along the second direction;

[0032] Form a second trench outside the transistor region that penetrates the stacked structure, the second trench extending along the second direction; etch the sacrificial layer along a direction parallel to the substrate based on the second trench to form a sub-trench extending along the second direction provided in the sacrificial layer, and, etch the sacrificial layer along a direction parallel to the substrate based on the first hole to form a first groove surrounding the first hole provided in the sacrificial layer, and the sub-trench and the first groove communicate; form a semiconductor layer covering the inner wall of the first groove and covering the side wall of the sub-trench parallel to the substrate; form a first word line in the first hole that fills the first hole including the first groove;

[0033] Form a second hole in the transistor region that penetrates the stacked structure in a direction perpendicular to the substrate, the second hole being close to the other first trench among two first trenches adjacent along the second direction;

[0034] Etch the sacrificial layer along a direction parallel to the substrate based on the second hole to expose at least a part of the side wall of the semiconductor layer facing the second hole; etch the insulating layer along a direction parallel to the substrate based on the second hole to expose the side wall of the first hole facing the second hole; form a second word line in the second hole that fills the second hole.

[0035] In some embodiments, the forming a semiconductor layer covering the inner wall of the first groove and covering the side wall of the sub-trench parallel to the substrate includes:

[0036] Deposit a semiconductor thin film and a first dummy layer thin film in sequence in the first hole, the first groove, the second trench, and the sub-trench; etch and remove the semiconductor thin film in the second trench and the first hole to form a semiconductor layer covering the inner wall of the first groove and covering the side wall of the sub-trench parallel to the substrate.

[0037] In some embodiments, the etching the sacrificial layer along a direction parallel to the substrate based on the second hole to expose at least a part of the side wall of the semiconductor layer facing the second hole includes:

[0038] Etch the sacrificial layer along a direction parallel to the substrate based on the second hole to form a second groove surrounding the second hole provided in the sacrificial layer, the second groove exposing the side wall of the semiconductor layer provided between the first hole and the second hole and facing the second hole;

[0039] Etching the insulating layer in a direction parallel to the substrate of the second hole to expose the sidewall of the first hole facing the second hole includes: etching the insulating layer in a direction parallel to the substrate of the second hole, such that in the first direction, the aperture of the sub-hole of the second hole in the sacrificial layer is smaller than the aperture of the sub-hole in the insulating layer, and in the second direction, the sidewall of the first hole is exposed.

[0040] An embodiment of the present disclosure provides an electronic device, including the above semiconductor device.

[0041] An embodiment of the present application includes a semiconductor device, a manufacturing method thereof, and an electronic device. The semiconductor device includes: a plurality of transistors distributed in different layers and stacked along a direction perpendicular to the substrate; a first word line extending through the different layers along a direction perpendicular to the substrate; a second word line extending through the different layers along a direction perpendicular to the substrate; the transistor includes: a semiconductor layer; the semiconductor layers of the transistors in different layers are disconnected; the first word line includes a first vertical portion and a plurality of first extending portions extending from the first vertical portion to one side of the second word line, the plurality of first extending portions are spaced apart along a direction perpendicular to the substrate and correspond to the plurality of transistors one by one; the second word line includes a plurality of first grooves spaced apart along a direction perpendicular to the substrate and having an opening facing the first word line, and the semiconductor layer is formed with a second groove extending along the inner wall of the first groove and having an opening facing the first word line, and the first extending portion corresponding to the transistor to which the semiconductor layer belongs fills the second groove. An embodiment of the present application provides a 3D stacked transistor controlled by a dual word line. For a memory array composed of such 3D stacked transistors, by activating a first word line and a second word line, it is possible to select a vertical column of memory cells (i.e., a group of memory cells at the same position in different layers). Compared with a memory array composed of single-gate transistors, this solution does not require a select transistor to be provided for the word line, and there is no need to add a manufacturing process step for the select transistor, which can simplify the structure and reduce the cost.

[0042] Other features and advantages of the present application will be described in the following description, and in part, will be obvious from the description, or will be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings.

[0043] Other aspects can be understood after reading and understanding the drawings and the detailed description. Description of the Drawings

[0044] The drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the description. Together with the embodiments of the present application, they are used to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0045] Figure 1ATop view of a semiconductor device provided for some embodiments Figure 1B is a cross-sectional view perpendicular to the substrate along the Figure 1A AA' direction in Figure 1C is a cross-sectional view perpendicular to the substrate along the Figure 1A BB' direction in Figure 1D is a cross-sectional view perpendicular to the substrate along the Figure 1A CC' direction in Figure 1E is a cross-sectional view perpendicular to the substrate along the Figure 1A DD' direction in Figure 1F is a cross-sectional view perpendicular to the substrate along the Figure 1A EE' direction in Figure 1G is a cross-sectional view parallel to the substrate along the Figure 1F FF' direction provided for some embodiments Figure 1H is a cross-sectional view parallel to the substrate along the Figure 1F FF' direction provided for other embodiments;

[0046] Figure 2A is a top view of the formed stacked structure provided for some embodiments Figure 2B is a cross-sectional view perpendicular to the substrate along the Figure 2A AA' direction in

[0047] Figure 3A is a top view of the formed first trench and second insulating layer provided for some embodiments Figure 3B is a cross-sectional view perpendicular to the substrate along the Figure 3A GG' direction in

[0048] Figure 4A is a top view of the formed first hole provided for some embodiments Figure 4B is a cross-sectional view perpendicular to the substrate along the Figure 4A AA' direction in

[0049] Figure 5A is a top view of the formed second trench provided for some embodiments Figure 5B is a cross-sectional view perpendicular to the substrate along the Figure 5A AA' direction in

[0050] Fig. 6A is a top view of the formed first lateral groove and sub-trench provided for some embodiments Figure 6B is a cross-sectional view perpendicular to the substrate along the Fig. 6A AA' direction in

[0051] Fig. 7A is a top view of the formed semiconductor structure layer and first dummy layer provided for some embodiments Figure 7B is a cross-sectional view perpendicular to the substrate along the Fig. 7A AA' direction in

[0052] Fig. 8A Top views after disconnecting semiconductor layers of different layers provided for some embodiments, Figure 8B Along the Fig. 8A Cross-sectional view perpendicular to the substrate in the AA' direction of;

[0053] Fig. 9A Top views after forming a second dummy layer provided for some embodiments, Fig. 9B Along the Fig. 9A Cross-sectional view perpendicular to the substrate in the AA' direction of;

[0054] Fig. 10A Top views after exposing a first hole and a first lateral groove provided for some embodiments, Fig. 10B Along the Fig. 10A Cross-sectional view perpendicular to the substrate in the AA' direction of;

[0055] Fig.11A Top views after forming a first gate insulating layer and a first word line provided for some embodiments, Fig. 11B Along the Fig.11A Cross-sectional view perpendicular to the substrate in the AA' direction of;

[0056] Fig. 12A Top views after forming a second hole provided for some embodiments, Fig. 12B Along the Fig. 12A Cross-sectional view perpendicular to the substrate in the BB' direction of;

[0057] Fig.13A Top views after laterally etching a sacrificial layer provided for some embodiments, Fig. 13B Along the Fig.13A Cross-sectional view perpendicular to the substrate in the BB' direction of, Fig. 13C Along the Fig.13A Cross-sectional view perpendicular to the substrate in the CC' direction of;

[0058] Fig.14A Top views after laterally etching a first insulating layer provided for some embodiments, Fig. 14B Along the Fig.14A Cross-sectional view perpendicular to the substrate in the BB' direction of, Fig. 14C Along the Fig.14A Cross-sectional view perpendicular to the substrate in the CC' direction of;

[0059] Fig.15A Top views after forming a second gate insulating layer and a second word line provided for some embodiments, Fig. 15B Along the Fig.15A Cross-sectional view perpendicular to the substrate in the BB' direction of, Fig. 15C Along the Fig.15ACross-sectional view perpendicular to the substrate in the CC' direction;

[0060] Fig.16A Top view after forming the bit line layer for some embodiments, Fig. 16B Along Fig.16A Cross-sectional view perpendicular to the substrate in the AA' direction in Fig. 16C Along Fig.16A Cross-sectional view perpendicular to the substrate in the BB' direction in

[0061] Fig.17A Top view after forming the bit line and the third insulating layer for some embodiments, Fig. 17B Along Fig.17A Cross-sectional view perpendicular to the substrate in the AA' direction in Fig. 17C Along Fig.17A Cross-sectional view perpendicular to the substrate in the BB' direction in

[0062] Fig.18A Top view after forming the third hole for some embodiments, Fig.18B Along Fig.18A Cross-sectional view perpendicular to the substrate in the DD' direction in Fig.18C Along Fig.18A Cross-sectional view perpendicular to the substrate in the EE' direction in

[0063] Fig.19A Top view after forming the fourth lateral groove for some embodiments, Fig.19B Along Fig.19A Cross-sectional view perpendicular to the substrate in the AA' direction in Fig.19C Along Fig.19A Cross-sectional view perpendicular to the substrate in the BB' direction in Fig.19D Along Fig.19A Cross-sectional view perpendicular to the substrate in the DD' direction in Fig.19E Along Fig.19A Cross-sectional view perpendicular to the substrate in the EE' direction in

[0064] Fig. 20A Top view after forming the first electrode layer and the fourth insulating layer for some embodiments, Fig. 20B Along Fig. 20A Cross-sectional view perpendicular to the substrate in the AA' direction in Fig. 20C Along Fig. 20A Cross-sectional view perpendicular to the substrate in the BB' direction in Fig.20D Along Fig. 20A Cross-sectional view perpendicular to the substrate in the DD' direction in Fig.20E Along Fig. 20A Cross-sectional view perpendicular to the substrate in the EE' direction in

[0065] Fig.21ATop view after forming the first electrode provided for some embodiments, Fig. 21B Cross-sectional view perpendicular to the substrate along the Fig.21A AA' direction in Fig. 21C Cross-sectional view perpendicular to the substrate along the Fig.21A BB' direction in Fig.21D Cross-sectional view perpendicular to the substrate along the Fig.21A DD' direction in Fig.21E Cross-sectional view perpendicular to the substrate along the Fig.21A EE' direction in;

[0066] Fig.22A Top view after forming the first sub-electrode and the first dielectric layer provided for some embodiments, Fig. 22B Cross-sectional view perpendicular to the substrate along the Fig.22A AA' direction in Fig. 22C Cross-sectional view perpendicular to the substrate along the Fig.22A BB' direction in Fig.22D Cross-sectional view perpendicular to the substrate along the Fig.22A DD' direction in Fig.22E Cross-sectional view perpendicular to the substrate along the Fig.22A EE' direction in;

[0067] Fig.23A Top view after forming the third trench provided for some embodiments, Fig. 23B Cross-sectional view perpendicular to the substrate along the Fig.23A AA' direction in Fig.23C Cross-sectional view perpendicular to the substrate along the Fig.23A BB' direction in Fig.23D Cross-sectional view perpendicular to the substrate along the Fig.23A DD' direction in Fig.23E Cross-sectional view perpendicular to the substrate along the Fig.23A EE' direction in. Detailed implementation manners

[0068] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined arbitrarily with each other.

[0069] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should have the ordinary meanings understood by those of ordinary skill in the field to which the present disclosure belongs.

[0070] The embodiments of the present disclosure do not necessarily limit the sizes shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.

[0071] The ordinal numbers such as "first", "second", "third", etc. in the present disclosure are set to avoid confusion of constituent elements and do not represent any order, quantity or importance.

[0072] In the present disclosure, for convenience, terms indicating orientation or positional relationship such as "middle part", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of constituent elements with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the directions describing the constituent elements. Therefore, it is not limited to the terms described in the disclosure and can be appropriately replaced according to the situation.

[0073] In the present disclosure, unless otherwise clearly specified and limited, the terms "mounted", "connected", "coupled" should be understood in a broad sense. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be directly connected, or indirectly connected through an intermediate member, or the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific situations.

[0074] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region or drain electrode) and the source electrode (source electrode terminal, source region or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to the region where current mainly flows.

[0075] In the present disclosure, it can be that the first electrode is the drain electrode and the second electrode is the source electrode, or it can be that the first electrode is the source electrode and the second electrode is the drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, etc., the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" can be interchanged with each other.

[0076] In the present disclosure, "connection" includes the case where constituent elements are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transfer electrical signals between the constituent elements that can be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0077] In the present disclosure, "parallel" means approximately parallel or nearly parallel. For example, the state where the angle formed by two straight lines is more than -10° and less than 10°, and thus, it also includes the state where the angle is more than -5° and less than 5°. Additionally, "perpendicular" means approximately perpendicular. For example, the state where the angle formed by two straight lines is more than 80° and less than 100°, and thus, it also includes the state where the angle is more than 85° and less than 95°.

[0078] "A and B are of an integral structure" in the embodiments of the present disclosure may mean that there is no obvious fault or gap, etc., as an obvious boundary interface in the micro-structure. Generally, a connected film layer patterned on one film layer is of an integral structure. For example, A and B use the same material to form one film layer and are simultaneously formed into a structure with a connection relationship through the same patterning process.

[0079] In the embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0080] Figure 1A A top view of a semiconductor device provided for some embodiments, Figure 1B For along Figure 1A a cross-sectional view perpendicular to the substrate 1 in the AA' direction; Figure 1C For along Figure 1A a cross-sectional view perpendicular to the substrate 1 in the BB' direction, Figure 1D For along Figure 1A a cross-sectional view perpendicular to the substrate 1 in the CC' direction, Figure 1E For along Figure 1A a cross-sectional view perpendicular to the substrate 1 in the DD' direction, Figure 1F For along Figure 1A a cross-sectional view perpendicular to the substrate 1 in the EE' direction, Figure 1G For along Figure 1F a cross-sectional view parallel to the substrate 1 in the FF' direction. As Figures 1A to 1G shown, the embodiments of the present disclosure provide a semiconductor device, including a multi-layer memory cell array vertically stacked on the substrate 1, and the multi-layer memory cell array may be distributed along the third direction Z. The third direction Z may be perpendicular to the substrate 1.

[0081] The memory cell array may include a plurality of bit lines 30, a plurality of first word lines 40a, a plurality of second word lines 40b, and a plurality of memory cells. Each of the memory cell arrays may include a plurality of memory cells arrayed along a first direction X parallel to the substrate 1 and a second direction Y parallel to the substrate 1. The first direction X and the second direction Y may intersect. As Figure 1GAs shown, the bit line 30 can be a conductive wire extending along the second direction Y. Multiple bit lines 30 of the same memory cell array can be spaced apart from each other, and the multiple bit lines 30 of the same memory cell array can be spaced apart along the first direction X. The bit lines 30 of different memory cell arrays can be stacked on the substrate 1, and the bit lines 30 at the same position of different layers are spaced apart from each other.

[0082] The first word line 40a can extend along the third direction Z. Multiple memory cells stacked vertically at the same position of different layers share one first word line 40a, and multiple memory cells stacked vertically at the same position of different layers share one second word line 40b; different memory cells in the same layer correspond to different first word lines 40a, and different memory cells in the same layer correspond to different second word lines 40b.

[0083] The memory cell can be a 1T or 2T memory cell or other multi-transistor memory cells.

[0084] Taking the 1T1C memory cell as an example, the memory cell can include a transistor and a capacitor connected to the transistor. The transistor and the capacitor of the same memory cell can be distributed along the first direction X. The transistor can include a first gate electrode 26a, a second gate electrode 26b, a first electrode 51, and a second electrode 52. The first gate electrode 26a can be a part of the first word line 40a, and the first gate electrodes 26a of the transistors at the same position of different layers can be a part of the same first word line 40a. The second gate electrode 26b can be a part of the second word line 40b, and the second gate electrodes 26b of the transistors at the same position of different layers can be a part of the same second word line 40b.

[0085] The second electrode 52 can be connected to the bit line 30, or the second electrode 52 can be a part of the bit line 30. The second electrodes 52 of the transistors of the memory cells in the same column of the same memory cell array can be connected to the same bit line 30. That is, the second electrodes 52 of the transistors in the same column distributed along the second direction Y are connected to form a bit line 30 extending along the second direction Y. The second electrodes 52 of the transistors of the memory cells in adjacent columns of the same memory cell array can be connected to different bit lines 30.

[0086] The capacitor can include a first capacitor electrode 41 and a second capacitor electrode 42. The first electrode 51 can be connected to the first capacitor electrode 41 of the capacitor, or the first electrode 51 and the first capacitor electrode 41 are multiplexed.

[0087] Hereinafter, a semiconductor device including multiple vertically stacked transistors at the same position will be taken as an example for description, and the memory cell is taken as an example of 1T1C for description.

[0088] As Figures 1A to 1GAs shown, an embodiment of the present disclosure provides a semiconductor device, which includes:

[0089] A plurality of transistors, stacked along a direction perpendicular to the substrate 1 in different layers;

[0090] A first word line 40a, extending through the different layers along a direction perpendicular to the substrate 1;

[0091] A second word line 40b, extending through the different layers along a direction perpendicular to the substrate 1;

[0092] The transistor may include: a semiconductor layer 23, as Figure 1D shown, the first word line 40a includes a first vertical portion L1 and a plurality of first protruding portions P1 extending from the first vertical portion L1 toward the second word line 40b. The plurality of first protruding portions P1 correspond to the plurality of transistors one by one and are spaced apart along a direction perpendicular to the substrate 1. The second word line 40b is formed with a plurality of first grooves A1 spaced apart along a direction perpendicular to the substrate 1 and having an opening facing the first word line 40a. The semiconductor layer 23 is formed with a second groove A2 extending along the inner wall of the first groove A1 and having an opening facing the first word line. The first protruding portion P1 corresponding to the transistor to which the semiconductor layer 23 belongs fills the second groove A2; the semiconductor layers 23 of the transistors in different layers are disconnected.

[0093] The above solution provides a 3D stacked transistor controlled by a double word line. A memory array composed of the 3D stacked transistors can activate a first word line and a second word line to select a vertical column of memory cells (i.e., a group of memory cells at the same position in different layers). Compared with a memory array composed of single-gate transistors, this solution does not require a selection transistor for the word line, does not need to add a manufacturing process step for the selection transistor, and requires a small number of word line drivers. Moreover, when the number of stacked layers changes, the number of word line drivers remains unchanged, which can reduce costs.

[0094] In some embodiments, a first gate insulating layer 24a is disposed between the first word line 40a and the semiconductor layer 23, and the first gate insulating layer 24a surrounds the first word line 40a.

[0095] In some embodiments, the first gate insulating layers 24a of the transistors at the same position in different layers are connected to form an integral structure. The solution provided in this embodiment can form the first gate insulating layers 24a of a plurality of transistors through a single manufacturing process, simplifying the process.

[0096] In some embodiments, a second gate insulating layer 24b is disposed between the second word line 40b and the semiconductor layer 23, and the second gate insulating layer 24b surrounds the second word line 40b.

[0097] In some embodiments, the second gate insulating layers 24b of transistors at the same position in different layers are connected to form an integrated structure. The solution provided in this embodiment can form the second gate insulating layers 24b of multiple transistors through a single manufacturing process, thereby simplifying the process.

[0098] In some embodiments, Figure 1D As shown, the second word line 40b also fills the groove formed by the adjacent first extension part P1 and the first vertical part L1 on the first word line 40a. That is, the first word line 40a and the second word line 40b both form a concave-convex structure, and the concave-convex structures of the two are staggered with each other, the extension part of the first word line 40a (that is, the protruding part of the concave-convex structure) is embedded in the groove of the second word line 40b, and the extension part of the second word line 40b is embedded in the groove of the first word line 40a. The first word line 40a and the second word line 40b are insulated by the first gate insulating layer 24a and the second gate insulating layer 24b.

[0099] In some embodiments, the transistor further includes a first electrode 51 and a second electrode 52 connected to the semiconductor layer 23, the first electrode 51 and the second electrode 52 are arranged on both sides of the first word line 40a and distributed along a first direction X, the first word line 40a and the second word line 40b are distributed along a second direction Y, and the first direction X and the second direction Y intersect.

[0100] In some embodiments, the first word line 40a further includes a plurality of second extensions P2 extending from the first vertical portion L1 toward one side of the first electrode 51, the plurality of second extensions P2 are spaced apart in a direction perpendicular to the substrate 1 and correspond to the plurality of transistors one by one, the semiconductor layer 23 is further formed with a third groove A3 formed by the second groove A2 extending in a direction parallel to the substrate 1 and opening toward the first word line 40a, and the second extension P2 corresponding to the transistor to which the semiconductor layer 23 belongs fills the third groove A3. The second groove A2 may include a bottom wall and a first side wall and a second side wall respectively connected to the bottom wall and parallel to the substrate 1, and the bottom wall may be perpendicular to the substrate 1. The bottom wall, the first side wall and the second side wall may extend in a direction parallel to the substrate 1, respectively, to form the third groove A3. The third groove A3 and the second groove A2 may be arranged on two adjacent sides of the first word line 40a. In some embodiments, the semiconductor layer 23 is also distributed on the side of the second extension P2 away from the second word line 40b.

[0101] In some embodiments, Figure 1BAs shown, the semiconductor layer 23 may further include a first extension portion 231 formed by the first sidewall extending in a direction parallel to the substrate 1 and away from the third groove A3, and a second extension portion 232 formed by the second sidewall extending in a direction parallel to the substrate 1 and away from the third groove A3; the second electrode 52 is connected to one side of the first extension portion 231 facing the second extension portion 232, and is also connected to one side of the second extension portion 232 facing the first extension portion 231.

[0102] In some embodiments, as Figure 1B shown, the first word line 40a further includes a plurality of third protruding portions P3 extending from the first vertical portion L1 toward the second electrode 52. The plurality of third protruding portions P3 are spaced apart in a direction perpendicular to the substrate 1 and correspond to the plurality of transistors one by one. An opening of the fourth groove A4 formed by the first extension portion 231, the second extension portion 232, and the second electrode 52 faces the first word line 40a, and the third protruding portions P3 corresponding to the transistors to which the first extension portion 231 and the second extension portion 232 belong fill the fourth groove A4.

[0103] In some embodiments, the first protruding portion P1, the second protruding portion P2, and the third protruding portion P3 may be continuously extended to form an annular protruding portion surrounding the first vertical portion L1, and the annular protruding portion is an open-loop annular protruding portion.

[0104] In some embodiments, as Figure 1B shown, the first electrode 51 may be connected to the sidewall of the third groove A3 on the side away from the second electrode 52.

[0105] In some embodiments, as Figure 1C shown, the second word line 40b further forms a fifth groove A5 with an opening facing the second electrode 52. The first extension portion 231 extends in a direction parallel to the substrate 1 to the fifth groove A5, and the second extension portion 232 extends in a direction parallel to the substrate 1 to the fifth groove A5, and the second electrode 52 fills the fifth groove A5.

[0106] In some embodiments, the first extension portions 231 of the transistors in the same layer and the same column are connected to each other to form an integral structure extending in the second direction Y and connected to the surface of the bit line 30 on the side away from the substrate 1; the second extension portions 232 of the transistors in the same layer and the same column are connected to each other to form an integral structure extending in the second direction Y and connected to the surface of the bit line 30 on the side facing the substrate 1. That is, both the surface of the bit line 30 on the side away from the substrate 1 and the surface on the side facing the substrate 1 are covered with the semiconductor layer 23.

[0107] In some embodiments, as Figure 1C As shown, the second word line 40 b is further formed with a sixth groove A6 opening toward the first electrode 51 , and the first electrode 51 may extend along the inner wall of the sixth groove A6 .

[0108] In some embodiments, the semiconductor device may further include:

[0109] An insulating layer and a conductive layer are alternately distributed along a direction perpendicular to the substrate 1; a first hole K1 penetrates the insulating layer and the conductive layer, the conductive layer includes a first electrode 51 and a second electrode 52 of the transistor, and the first hole K1 is distributed with a first gate insulating layer 24a and the first word line 40a surrounding the first word line 40a from the outside to the inside. The first hole K1 may include a first sub-hole located in the insulating layer and a second sub-hole located in the conductive layer, and the orthographic projection of the first sub-hole on the substrate 1 may fall within the orthographic projection of the second sub-hole on the substrate 1. In the solution provided in this embodiment, by setting the first hole and the second hole of different aperture sizes, etching can be performed in the hole to disconnect the semiconductor layer 23 of transistors of different layers. The boundary where the orthographic projection of the first sub-hole on the substrate 1 deviates from the second word line 40b may fall on the boundary where the orthographic projection of the second sub-hole on the substrate 1 deviates from the second word line 40b.

[0110] In some embodiments, the semiconductor device may further include:

[0111] The second hole K2 penetrates the insulating layer and the conductive layer, and the second hole K2 is provided with the second gate insulating layer 24b and the second word line 40b surrounding the second word line 40b from the outside to the inside. The second hole K2 may include a third sub-hole located in the conductive layer and a fourth sub-hole located in the insulating layer, and the orthographic projection of the third sub-hole on the substrate 1 may fall within the orthographic projection of the fourth sub-hole on the substrate 1. The orthographic projection of the third sub-hole on the substrate 1 is away from the boundary of the first word line 40a, and may fall on the boundary of the orthographic projection of the fourth sub-hole on the substrate 1 away from the first word line 40a.

[0112] In some embodiments, Figure 1G or Figure 1H As shown, the bit line 30 may be a strip electrode parallel to the substrate 1, a portion of the strip electrode may be the second electrode 52 of the transistor, and the surface of the strip electrode facing away from the substrate 1 and the surface facing the substrate 1 may be connected to the semiconductor layer 23. The side of the bit line 30 facing the transistor may have a groove with an opening facing the transistor corresponding to the connected transistor, such as Figure 1GAs shown, at this time, the first gate insulating layer 24a, the first word line 40a, the second gate insulating layer 24b, and the second word line 40b extend into the groove of the bit line 30. Alternatively, the bit line 30 may have no groove, as Figure 1H shown, that is, the bit line 30 forms a linear electrode.

[0113] In some embodiments, the semiconductor device may further include:

[0114] Insulating layers and conductive layers alternately distributed along the direction perpendicular to the substrate 1; a third hole K3 penetrating through the insulating layer and the conductive layer; the third hole K3 includes a fifth sub-hole located in the insulating layer and a sixth sub-hole located in the conductive layer, and the sixth sub-hole has a seventh groove extending in the horizontal direction relative to the fifth sub-hole. That is, the orthographic projection of the fifth sub-hole on the substrate 1 falls within the orthographic projection of the sixth sub-hole on the substrate 1.

[0115] In some embodiments, the semiconductor device may further include:

[0116] Multiple capacitors, the capacitors include a first capacitor electrode 41 and a second capacitor electrode 42, and the first electrode 51 and the first capacitor electrode 41 may be multiplexed;

[0117] In some embodiments, the second capacitor electrode 42 may include a first sub-electrode 421;

[0118] In the third hole K3, the first capacitor electrode 41 surrounding the first sub-electrode 421, the first dielectric layer 431 surrounding the first sub-electrode 421, and the first sub-electrode 421 are sequentially distributed from the outside to the inside.

[0119] In some embodiments, the first capacitor electrode 41 may be distributed on the inner wall of the seventh groove and does not completely fill the seventh groove. The first sub-electrode 421 extends along the direction perpendicular to the substrate 1 and has an extending portion extending into the seventh groove, and the first sub-electrode 421 fills the third hole K3.

[0120] Among them, the first electrodes 51 of the transistors at the same position in different layers are spaced apart, that is, physically disconnected.

[0121] In some embodiments, the second capacitive electrode 42 may further include a second sub-electrode 422. The second sub-electrode 422 may be distributed on the side of the first capacitive electrode 41 away from the substrate 1, on the side facing the substrate 1, and on the side away from the second semiconductor sub-layer 232. A second dielectric layer 432 is provided between the second sub-electrode 422 and the first capacitive electrode 41. The first dielectric layer 431 and the second dielectric layer 432 together constitute the dielectric layer 43 of the capacitor. The solution provided in this embodiment sets electrodes both inside and outside the first capacitive electrode 41 as the second capacitive electrode 42, which can increase the plate area of the capacitor as much as possible, increase the capacitance value, and the planar size occupied by the capacitor remains basically unchanged. The first sub-electrode 421 and the second sub-electrode 422 may be connected on the side of the plurality of memory arrays away from the substrate 1. The above capacitor structure is only an example, and the embodiments of the present disclosure are not limited thereto. It may be other structures. For example, the second capacitive electrode 42 may only include the first capacitive electrode 421. For another example, the third hole K3 may not be provided, and a groove exposing the semiconductor layer 23 and the second gate insulating layer 24b may be formed between adjacent first insulating layers 9, an electrode covering the inner wall of the groove is formed as the first capacitive electrode 41 of the capacitor, and an electrode filling the groove is formed as the second capacitive electrode 42 of the capacitor, and so on.

[0122] In some embodiments, the first sub-electrodes 421 of the capacitors connected to the transistors in different layers may be connected to form an integrated structure.

[0123] In some embodiments, the second sub-electrodes 422 of the capacitors connected to the transistors in different layers may be connected to form an integrated structure.

[0124] In some embodiments, every two columns of memory cells may be taken as a group, and the second sub-electrodes 422 of the capacitors connected to the transistors in the same group may be connected to form an integrated structure. That is, the second sub-electrodes 422 of the capacitors connected to the transistors in adjacent columns (two columns in the same group) of the same layer are connected to form an integrated structure.

[0125] The technical solution of this embodiment will be further described below through the manufacturing process of the semiconductor device in this embodiment. The "lithography process" mentioned in this embodiment includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and stripping the photoresist, which are mature manufacturing processes in related technologies. The "lithography process" mentioned in this embodiment includes coating a film layer, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can use known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can use known coating processes, and etching can use known methods, which will not be specifically limited here. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film of a certain material manufactured on a substrate using a deposition or coating process. If the "thin film" does not require a lithography process or a lithography process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" still requires a lithography process or a lithography process during the entire manufacturing process, it is called a "thin film" before the lithography process and a "layer" after the lithography process. The "layer" after the lithography process or the lithography process contains at least one "pattern".

[0126] In some embodiments, the manufacturing process of the semiconductor device may include:

[0127] 1) Forming a stacked structure;

[0128] The forming of the stacked structure may include: providing a substrate 1, alternately depositing a first insulating thin film and a sacrificial layer thin film on the substrate 1 to form a stacked structure including a plurality of alternately arranged first insulating layers 9 and sacrificial layers 10; depositing a hard mask thin film to form a hard mask layer 8.

[0129] At this time, the stacked structure includes a plurality of alternately arranged first insulating layers 9 and sacrificial layers 10, and a hard mask layer 8 disposed on the side of the topmost sacrificial layer 10 away from the substrate 1, and the hard mask layer 8 covers the sacrificial layer 10, as Figure 2A and Figure 2B shown. Figure 2A FIG. is a top view after forming the stacked structure provided for some embodiments, Figure 2B is along Figure 2A in the AA' direction is a cross-sectional view perpendicular to the substrate 1. The AA' direction may be parallel to the first direction X.

[0130] In some embodiments, the substrate 1 may be a conventional silicon substrate or other bulk substrates including a semiconductor material layer.

[0131] In some embodiments, the first insulating thin film may be a low-K dielectric layer, including but not limited to silicon oxides such as silicon dioxide (SiO2), etc.

[0132] In some embodiments, the sacrificial layer thin film may be a low-K material having an etching selectivity ratio with the first insulating thin film, such as silicon nitride (SiN), etc.

[0133] In some embodiments, the hard mask layer 8 may include, but is not limited to, at least one of the following: carbon, polysilicon, silicon oxide, etc.

[0134] Figure 2B The stacked structure shown in includes four first insulating layers 9 and three sacrificial layers 10, which is only an example. In other embodiments, the stacked structure may include more or fewer alternately arranged first insulating layers 9 and sacrificial layers 10.

[0135] 2) Form a first trench T1 and a second insulating layer 11;

[0136] Etch the plurality of stacked structures to form a plurality of first trenches T1 penetrating through the plurality of stacked structures; the first trenches T1 extend along a first direction X, and the plurality of first trenches T1 are spaced apart along the first direction X and a second direction Y. A storage unit region is defined between adjacent first trenches T1 along the second direction Y, and the storage unit region may include a transistor region and a capacitor region;

[0137] Deposit a second insulating thin film in each first trench T1 and planarize it to form a second insulating layer 11 filling the first trench T1; the second insulating layer 11 may be flush with the hard mask layer 8. As Figure 3A and Figure 3B shown, wherein, Figure 3A is a top view after forming the first trench T1 and the second insulating layer 11 provided for some embodiments, Figure 3B is a cross-sectional view perpendicular to the substrate 1 along the Figure 3A GG' direction in. The GG' direction may be parallel to the first direction X. The second insulating layer 11 may isolate a plurality of subsequent formed storage units.

[0138] In some embodiments, the second insulating thin film may be a low-K dielectric layer having an etching selectivity ratio with the first insulating layer and the sacrificial layer, including but not limited to silicon oxide, etc.

[0139] 3) Form a first hole K1;

[0140] Use dry etching to etch the stacked structure from the top layer to the bottom layer in the transistor region defined by adjacent first trenches T1 (the etching stops on the substrate 1) to form a first hole K1. At this time, the aperture of the second sub-hole of the first hole K1 in the first insulating layer 9 is the same as that of the first sub-hole in the sacrificial layer 10. As Figure 4A and Figure 4B shown, wherein, Figure 4ATop view after forming the first hole K1 provided for some embodiments Figure 4B Along Figure 4A A cross-sectional view perpendicular to the substrate 1 in the AA' direction in []. The first hole K1 is close to one of the two adjacent second insulating layers 11, and one side wall of the first hole K1 exposes the second insulating layer 11 it is close to, that is, one side wall of the first hole K1 is the second insulating layer 11.

[0141] 4) Form the second trench T2;

[0142] Etch the stacked structure from the top layer to the bottom layer to form a second trench T2 penetrating the stacked structure. The second trench T2 extends along the second direction Y, and a group of memory cells is defined between adjacent second trenches T2. Each group of memory cells includes two columns of memory cells, as shown in Figure 5A And Figure 5B Shown, where Figure 5A Top view after forming the second trench T2 provided for some embodiments Figure 5B Along Figure 5A A cross-sectional view perpendicular to the substrate 1 in the AA' direction in [].

[0143] 5) Form the first lateral groove V1 and the sub-trench V2;

[0144] Laterally etch the sacrificial layer 10 through the first hole K1 to form a first lateral groove V1, and laterally etch the sacrificial layer 10 through the second trench T2 to form a sub-trench V2. The sub-trench V2 extends along the second direction Y. The first lateral groove V1 partially surrounds the first hole K1, that is, surrounds three sides of the first hole K1, as shown in Fig. 6A And Figure 6B Shown, where Fig. 6A Top view after forming the first lateral groove V1 and the sub-trench V2 provided for some embodiments Figure 6B Along Fig. 6A A cross-sectional view perpendicular to the substrate 1 in the AA' direction in [].

[0145] 6) Form the semiconductor structure layer 23a and the first dummy layer 7;

[0146] Deposit a semiconductor thin film and a first dummy layer thin film in the first hole K1, the second trench T2, the first lateral groove V1, and the sub-trench V2 in sequence to form a semiconductor structure layer 23a and a first dummy layer 7, as shown in Fig. 7A And Figure 7B Shown, where Fig. 7A Top view after forming the semiconductor structure layer 23a and the first dummy layer 7 provided for some embodiments Figure 7B Along Fig. 7ACross-sectional view perpendicular to the substrate 1 in the AA' direction. The semiconductor structure layer 23a covers the inner walls of the first hole K1, the second trench T2, the first lateral groove V1, and the sub-trench V2. The first dummy layer 7 fills the first hole K1, the second trench T2, the first lateral groove V1, and the sub-trench V2. The semiconductor structure layer 23a includes semiconductor layers 23 of transistors at the same positions in multiple layers, and at this time, the semiconductor layers 23 of the transistors at the same positions in multiple layers are connected together.

[0147] In an exemplary embodiment of the present disclosure, the material of the semiconductor thin film may be silicon, polysilicon, or the like with a bandgap less than 1.65 eV, or it may be a wide-bandgap material, such as a metal oxide material with a bandgap greater than 1.65 eV.

[0148] For example, the material of the metal oxide semiconductor layer or the channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, and other materials. Of course, the metal oxide may not exclude compounds containing other elements, such as elements N, Si, etc.; nor does it exclude containing other trace doping elements.

[0149] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxide nitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), etc. As long as the leakage current of the transistor can meet the requirements, it can be specifically adjusted according to the actual situation.

[0150] These materials have a wide bandgap and low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the operating performance of the dynamic memory.

[0151] The materials of the above metal oxide semiconductor layer or channel only emphasize the element types of the materials, rather than the atomic ratios in the materials and the film qualities of the materials.

[0152] In some embodiments, the first dummy layer thin film may be an insulating material having an etching selectivity with respect to the first insulating thin film, such as SiN or the like.

[0153] 7) Disconnect the semiconductor layers 23 of different layers;

[0154] Etch and remove the semiconductor structure layer 23a and the first dummy layer 7 in the second trench T2 and the first hole K1, so as to disconnect the semiconductor layers 23 of different layers and avoid leakage. At this time, the semiconductor structure layer 23a forms a plurality of mutually disconnected semiconductor layers 23, as Fig. 8A and Figure 8B shown, wherein, Fig. 8A is a top view of the semiconductor layers 23 of different layers disconnected provided by some embodiments, Figure 8B is Fig. 8A a cross-sectional view perpendicular to the substrate 1 along the AA' direction in

[0155] 8) Form a second dummy layer 6;

[0156] Deposit a second dummy layer thin film on the substrate 1 having the foregoing structure to form a second dummy layer 6 filling the second trench T2 and the first hole K1, as Fig. 9A and Fig. 9B shown, wherein, Fig. 9A is a top view of the second dummy layer 6 formed provided by some embodiments, Fig. 9B is Fig. 9A a cross-sectional view perpendicular to the substrate 1 along the AA' direction in

[0157] In some embodiments, the second dummy layer thin film may be an insulating material having an etching selectivity with respect to the first insulating thin film, such as SiN or the like.

[0158] 9) Expose the first hole K1 and the first lateral groove V1;

[0159] Etch and remove the second dummy layer 6 in the first hole K1 and remove the first dummy layer 7 in the first lateral groove V1 to expose the first hole K1 and expose the semiconductor layer 23 in the first lateral groove V1, as Fig. 10A and Fig. 10B shown, wherein, Fig. 10A is a top view of the first hole K1 and the first lateral groove V1 exposed provided by some embodiments, Fig. 10B is Fig. 10AA cross-sectional view perpendicular to the substrate 1 in the AA' direction. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, a part of the first dummy layer 7 in the sub-groove V2 can be removed, that is, the first dummy layer 7 in the region V1' is removed. The region V1 expands a preset width in the direction of the sub-groove V2, which is the region V1'.

[0160] 10) Form a first gate insulating layer 24a and a first word line 40a;

[0161] Deposit a first gate insulating thin film and a first conductive thin film in sequence on the substrate 1 on which the foregoing structure is formed to form a first gate insulating layer 24a and a first word line 40a. The first word line 40a fills the first hole K1 and the first lateral groove V1, or fills the first hole K1 and the region V1', as Fig.11A and Fig. 11B shown, wherein, Fig.11A is a top view after forming the first gate insulating layer 24a and the first word line 40a provided for some embodiments, Fig. 11B is along Fig.11A a cross-sectional view perpendicular to the substrate 1 in the AA' direction.

[0162] In some embodiments, the material of the first gate insulating thin film may include one or more layers of High-K dielectric materials. In some embodiments, it may include oxides of one or more of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials. The subsequent second gate insulating thin film is similar to the first gate insulating thin film and will not be elaborated.

[0163] In some embodiments, the first conductive thin film may be one or more of the following different types of materials:

[0164] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing these metals mentioned above;

[0165] Or, it may be a conductive metal oxide, metal nitride, metal silicide, metal carbide, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO) and other conductive metal oxide materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other conductive metal nitride materials;

[0166] Or, it may be doped polysilicon, silicon, germanium, silicon germanium, etc. that are conductive.

[0167] Subsequent second, third, fourth, fifth, and sixth conductive films are similar to the first conductive film and will not be elaborated here.

[0168] 11) Form a second hole K2;

[0169] In the transistor region defined by adjacent first trenches T1, the stacked structure is etched from the top layer to the bottom layer using dry etching (the etching stops on the substrate 1) to form a second hole K2. At this time, the aperture diameters of the fourth sub-hole K22 of the first insulating layer 9 and the third sub-hole K21 of the sacrificial layer 10 in the second hole K2 are the same, as Fig. 12A and Fig. 12B shown, where Fig. 12A is a top view of the formed second hole K2 provided for some embodiments, Fig. 12B is along Fig. 12A in the BB' direction, a cross-sectional view perpendicular to the substrate 1. The second hole K1 is close to the second insulating layer 11 in the two adjacent second insulating layers 11 that is far from the first hole K1, and one side wall of the second hole K2 exposes the second insulating layer 11 it is close to, and one side wall of the second hole K2 is the second insulating layer 11. The second hole K2 and the first hole K1 in the same transistor region are distributed along the second direction Y.

[0170] 12) Horizontally etch the sacrificial layer 10;

[0171] The sacrificial layer 10 is horizontally etched through the second hole K2 to form a third horizontal groove V3, as Fig.13A , Fig. 13B and Fig. 13C shown; where Fig.13A is a top view of the horizontally etched sacrificial layer 10 provided for some embodiments, Fig. 13B is along Fig.13A in the BB' direction, a cross-sectional view perpendicular to the substrate 1, Fig. 13C is along Fig.13A in the CC' direction, a cross-sectional view perpendicular to the substrate 1. It can be seen that at this time, the aperture diameter of the third sub-hole K21 of the sacrificial layer 10 in the second hole K2 in the BB' direction is larger than the aperture diameter of the fourth sub-hole K22 of the first insulating layer 9, and in the CC' direction, the semiconductor layer 23 is exposed in the third horizontal groove V3. Fig.13A The region shown by the dashed line in is the outer boundary of the third horizontal groove V3. When horizontally etching the sacrificial layer 10, the semiconductor layer 23 on the side facing the sacrificial layer 10 can be etched away to expose the first dummy layer 7. However, the embodiments of the present disclosure are not limited thereto, and the semiconductor layer 23 on the side facing the sacrificial layer 10 may not be etched away. Fig. 13BShown is that the semiconductor layer 23 facing the side of the sacrificial layer 10 is etched away. In some other embodiments, the sacrificial layer 10 and a part of the first dummy layer 7 may be etched transversely based on the second hole K2 to form a groove V3'.

[0172] 13) Etch the first insulating layer 9 transversely;

[0173] Etch the first insulating layer 9 transversely through the second hole K2, such that the aperture of the third sub-hole K21 of the second hole K2 in the BB' direction in the sacrificial layer 10 is smaller than the aperture of the fourth sub-hole K22 in the first insulating layer 9, and in the BB' direction, a part of the first insulating layer 9 is retained without exposing the second dummy layer 6, and in the CC' direction, the first gate insulating layer 24a is exposed, as Fig.14A 、 Fig. 14B and Fig. 14C shown; wherein, Fig.14A is a top view of the first insulating layer 9 after being etched transversely provided for some embodiments, Fig. 14B is a cross-sectional view perpendicular to the substrate 1 along the Fig.14A BB' direction in Fig. 14C is a cross-sectional view perpendicular to the substrate 1 along the Fig.14A CC' direction in Fig.14A The region S1 in

[0174] is the boundary of the region where the first insulating layer 9 is etched, that is, the first insulating layer 9 in the region S1 is all etched away.

[0175] Deposit a second gate insulating film and a second conductive film in sequence on the substrate 1 on which the foregoing structure is formed to form a second gate insulating layer 24b and a second word line 40b. The second gate insulating layer 24b covers the inner wall of the second hole K2, and the second word line 40b fills the second hole K2 in which the second gate insulating layer 24b is formed, as Fig.15A 、 Fig. 15B and Fig. 15C shown; wherein, Fig.15A is a top view of the second gate insulating layer 24b and the second word line 40b after being formed provided for some embodiments, Fig. 15B is a cross-sectional view perpendicular to the substrate 1 along the Fig.15A BB' direction in Fig. 15C is a cross-sectional view perpendicular to the substrate 1 along the Fig.15A CC' direction in

[0176] 15) Form a bit line layer 30a;

[0177] Etch away the second dummy layer 6 in the second trench T2 and remove the first dummy layer 7 in the sub-trench V2;

[0178] Deposit a third conductive film to form a bit line layer 30a, and the bit line layer 30a fills the second trench T2 and the sub-trench V2; as Fig.16A , Fig. 16B and Fig. 16C shown, wherein, Fig.16A is a top view after forming the bit line layer 30a provided for some embodiments, Fig. 16B is a cross-sectional view perpendicular to the substrate 1 along the Fig.16A AA' direction in Fig. 16C is a cross-sectional view perpendicular to the substrate 1 along the Fig.16A BB' direction in

[0179] 16) Form a bit line 30 and a third insulating layer 12;

[0180] Etch and remove the bit line layer 30a in the second trench T2, and retain the bit line layer 30a in the sub-trench V2. At this time, the bit line layer 30a is divided into multiple bit lines 30 located in different layers, and the multiple bit lines 30 are disconnected from each other;

[0181] Deposit a third insulating film to form a third insulating layer 12 that fills the second trench T2. The third insulating layer 12 separates different groups of memory cells, as Fig.17A , Fig. 17B and Fig. 17C shown, wherein, Fig.17A is a top view after forming the bit line 30 and the third insulating layer 12 provided for some embodiments, Fig. 17B is a cross-sectional view perpendicular to the substrate 1 along the Fig.17A AA' direction in Fig. 17C is a cross-sectional view perpendicular to the substrate 1 along the Fig.17A BB' direction in

[0182] The third insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2), etc.

[0183] 17) Form a third hole K3;

[0184] In the capacitor region defined by the first trenches T1 adjacent to each other along the second direction Y, use dry etching to etch the stacked structure from the top layer to the bottom layer (the etching stops on the substrate 1) to form a plurality of third holes K3. At this time, the aperture of the third hole K3 in the sixth sub-hole K32 of the sacrificial layer 10 and the fifth sub-hole K31 in the first insulating layer 9 is the same, as Fig.18A , Fig.18B and Fig.18C shown, wherein, Fig.18A is a top view after forming the third hole K3 provided for some embodiments, Fig.18B is along Fig.18ACross-sectional view perpendicular to the substrate 1 in the DD' direction, Fig.18C along Fig.18A is a cross-sectional view perpendicular to the substrate 1 in the EE' direction of

[0185] 18) Form a fourth lateral groove V4;

[0186] Based on the third hole K3, laterally etch the sacrificial layer 10 to expand the aperture of the sixth sub-hole K32 of the third hole K3 located in the sacrificial layer 10, so that the fifth sub-hole K31 of the third hole K3 located in the first insulating layer 9 projects orthogonally onto the substrate 1 and falls within the orthogonal projection of the sixth sub-hole K32 onto the substrate 1. At this time, the sixth sub-hole K32 has a lateral fourth lateral groove V4 relative to the fifth sub-hole K31, as shown in Fig.19A , Fig.19B , Fig.19C , Fig.19D and Fig.19E shown, where Fig.19A is a top view of some embodiments after forming the fourth lateral groove V4, Fig.19B along Fig.19A is a cross-sectional view perpendicular to the substrate 1 in the AA' direction of Fig.19C along Fig.19A is a cross-sectional view perpendicular to the substrate 1 in the BB' direction of Fig.19D along Fig.19A is a cross-sectional view perpendicular to the substrate 1 in the DD' direction of Fig.19E along Fig.19A is a cross-sectional view perpendicular to the substrate 1 in the EE' direction of

[0187] When laterally etching the sacrificial layer 10 along the second direction Y, all of the sacrificial layer 10 in this direction is etched away, exposing the second insulating layer 11. When laterally etching the sacrificial layer 10 along the first direction X, all of the sacrificial layer 10 is etched away on the side facing the first word line 40a, exposing the semiconductor layer 23, and part of the sacrificial layer 10 is etched away on the side away from the first word line 40a, leaving part of the sacrificial layer 10.

[0188] 19) Form a first electrode layer 51a and a fourth insulating layer 13;

[0189] Deposit a fourth conductive thin film and a fourth insulating thin film in sequence in the third hole K3 to form a first electrode layer 51a and a fourth insulating layer 13; the fourth insulating layer 13 fills the third hole K3, as shown in Fig. 20A , Fig. 20B , Fig. 20C , Figure 20D , Figure 20E shown, where Figure 20A is a top view of some embodiments after forming the first electrode layer 51a and the fourth insulating layer 13, Figure 20B alongFigure 20A Cross-sectional view perpendicular to the substrate 1 in the AA' direction, Figure 20C is along Figure 20A Cross-sectional view perpendicular to the substrate 1 in the BB' direction, Figure 20D is along Figure 20A Cross-sectional view perpendicular to the substrate 1 in the DD' direction, Figure 20E is along Figure 20A Cross-sectional view perpendicular to the substrate 1 in the EE' direction.

[0190] In some embodiments, the fourth insulating film may be a low-K dielectric layer, including but not limited to silicon oxides such as silicon dioxide (SiO2).

[0191] 20) Form the first electrode 51;

[0192] Etch away the first electrode layer 51a and the fourth insulating layer 13 in the third hole K3 except for the region where the fourth lateral groove V4 is located, that is, only retain the first electrode layer 51a and the fourth insulating layer 13 located in the fourth lateral groove V4. The retained first electrode layer 51a is the plurality of mutually disconnected first electrodes 51, and the first electrode 51 is only located in the fourth lateral groove V4; the first electrode 51 covers the inner wall of the fourth lateral groove V4, including the top wall (the inner wall of the fourth lateral groove V4 away from the substrate 1) and the bottom wall (the inner wall of the fourth lateral groove V4 close to the substrate 1) of the fourth lateral groove V4 parallel to the substrate 1, and the four side walls of the fourth lateral groove V4 perpendicular to the substrate 1, as Figure 21A , Figure 21B , Figure 21C , Figure 21D and Figure 21E shown, where Figure 21A is a top view after forming the first electrode 51 provided in some embodiments, Figure 21B is along Figure 21A Cross-sectional view perpendicular to the substrate 1 in the AA' direction, Figure 21C is along Figure 21A Cross-sectional view perpendicular to the substrate 1 in the BB' direction, Figure 21D is along Figure 21A Cross-sectional view perpendicular to the substrate 1 in the DD' direction, Figure 21E is along Figure 21A Cross-sectional view perpendicular to the substrate 1 in the EE' direction. This first electrode 51 also serves as the first capacitive electrode 41 of the capacitor.

[0193] 21) Form the first sub-electrode 421 and the first dielectric layer 431;

[0194] Etch away the fourth insulating layer 13 located in the fourth lateral groove V4; at this time, all of the fourth insulating layer 13 is removed, and the surface of the first electrode 51 facing the third hole K3 is exposed;

[0195] Deposit a first dielectric thin film and a fifth conductive thin film in the third hole K3 in sequence to form a first dielectric layer 431 and a first sub-electrode 421; the first sub-electrode 421 fills the third hole K3, and the first sub-electrode 421 extends into the fourth lateral groove V4, as Figure 22A , Figure 22B , Figure 22C , Figure 22D and Figure 22E shown, wherein, Figure 22A is a top view after forming the first sub-electrode 421 and the first dielectric layer 431 provided by some embodiments, Figure 22B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 22A , Figure 22C is a cross-sectional view perpendicular to the substrate 1 along the BB' direction in Figure 22A , Figure 22D is a cross-sectional view perpendicular to the substrate 1 along the DD' direction in Figure 22A , Figure 22E is a cross-sectional view perpendicular to the substrate 1 along the EE' direction in Figure 22A .

[0196] In some embodiments, the first dielectric thin film may be a High-K dielectric material. In some embodiments, it may include one or more oxides such as hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials. The subsequent second dielectric thin film is similar to the first dielectric thin film and will not be elaborated.

[0197] 22) Form a third trench T3;

[0198] Etch the stacked structure from the top layer to the bottom layer to form a third trench T3 that penetrates the stacked structure. The third trench T3 extends along the second direction Y, and the third trench T3 is located between two adjacent columns of memory cells in the same group;

[0199] The first insulating layer 9 is laterally etched through the third trench T3, and the first insulating layer 9 is etched along the first direction X to expose the top wall (the surface facing the substrate 1 side) and the bottom wall (the surface facing away from the substrate 1 side) of the first capacitor electrode 41, and the sacrificial layer 10 is laterally etched to expose the side wall of the first capacitor electrode 41 facing the third trench T3, so that the second sub-electrode 422 formed subsequently can surround the top wall, bottom wall and side wall of the first capacitor electrode 41, thereby increasing the electrode area of the capacitor as much as possible. When the first insulating layer 9 is laterally etched, the side wall of the first gate insulating layer 24a facing the third trench T3 and the side wall of the second gate insulating layer 24b facing the third trench T3 are exposed; Figure 23A , Figure 23B , Figure 23C , Figure 23D and Figure 23E As shown, Figure 23A A top view after forming the third trench T3 is provided for some embodiments. Figure 23B For along Figure 23A A cross-sectional view perpendicular to the substrate 1 in the AA' direction, Figure 23C For along Figure 23A A cross-sectional view perpendicular to the substrate 1 in the BB' direction, Figure 23D For along Figure 23A A cross-sectional view perpendicular to the substrate 1 in the DD' direction, Figure 23E For along Figure 23A A cross-sectional view perpendicular to the substrate 1 in the EE' direction.

[0200] 23) forming a second sub-electrode 422 and a second dielectric layer 432;

[0201] A second dielectric film and a sixth conductive film are sequentially deposited in the third trench T3 to form a second dielectric layer 432 and a second sub-electrode 422; the second sub-electrode 422 fills the third trench T3. Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F and Figure 1G It can be seen that the second sub-electrodes 422 of two columns of memory cells in the same group are connected to form an integrated structure.

[0202] The present disclosure also provides an electronic device, including the semiconductor device described in any of the above embodiments. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include a memory in a computer, etc., which is not limited here.

[0203] Although the embodiments disclosed in the present invention are as above, the content described is only the embodiments adopted for the convenience of understanding the present invention and is not intended to limit the present invention. Any person skilled in the art within the scope of the present invention may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present invention. However, the scope of patent protection of the present invention shall still be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Multiple transistors are distributed in different layers and stacked along a direction perpendicular to the substrate; A first word line, extending through the different layers in a direction perpendicular to the substrate; A second word line, extending through the different layers in a direction perpendicular to the substrate; The transistor comprises: a semiconductor layer; semiconductor layers of transistors of different layers are disconnected; The first word line includes a first vertical portion and a plurality of first protruding portions extending from the first vertical portion toward one side of the second word line, the plurality of first protruding portions are spaced apart in a direction perpendicular to the substrate and correspond one to one with the plurality of transistors; the second word line includes a plurality of first grooves opening toward the first word line and spaced apart in a direction perpendicular to the substrate, the semiconductor layer is formed with a second groove extending along an inner wall of the first groove and opening toward the first word line, and the first protruding portion corresponding to the transistor to which the semiconductor layer belongs fills the second groove.

2. The semiconductor device according to claim 1, wherein The transistor also includes a first electrode and a second electrode connected to the semiconductor layer, the first electrode and the second electrode are arranged on both sides of the first word line and distributed along a first direction, the first word line and the second word line are distributed along a second direction, and the first direction and the second direction intersect and are parallel to the substrate.

3. The semiconductor device according to claim 2, wherein, The first word line also includes a plurality of second extension portions extending from the first vertical portion toward one side of the first electrode, the plurality of second extension portions are spaced apart in a direction perpendicular to the substrate and correspond one-to-one to the plurality of transistors, the semiconductor layer also forms a third groove formed by the second groove extending in a direction parallel to the substrate and opening toward the first word line, the second extension portion corresponding to the transistor to which the semiconductor layer belongs fills the third groove.

4. The semiconductor device according to claim 3, wherein, The first electrode is connected to a side of the third groove facing away from the second electrode.

5. The semiconductor device according to claim 3, wherein, The second groove includes a bottom wall and a first side wall and a second side wall parallel to the substrate and connected to the bottom wall respectively; the semiconductor layer also includes a first extension portion formed by the first side wall extending in a direction parallel to the substrate and away from the third groove, and a second extension portion formed by the second side wall extending in a direction parallel to the substrate and away from the third groove; the second electrode is connected to the first extension portion on one side facing the second extension portion, and is connected to the second extension portion on one side facing the first extension portion.

6. The semiconductor device according to claim 5, wherein, The first word line also includes a plurality of third extension portions extending from the first vertical portion toward one side of the second electrode, the plurality of third extension portions are spaced apart in a direction perpendicular to the substrate and correspond one-to-one to the plurality of transistors, the first extension portion, the second extension portion and the second electrode form a fourth groove opening toward the first word line, and the third extension portions corresponding to the transistors to which the first extension portion and the second extension portion belong fill the fourth groove.

7. The semiconductor device according to claim 5, wherein The second word line is further formed with a fifth groove opening toward the second electrode, the first extension portion extends to the fifth groove in a direction parallel to the substrate, the second extension portion extends to the fifth groove in a direction parallel to the substrate, and the second electrode fills the fifth groove.

8. The semiconductor device according to claim 2, wherein The second word line is further formed with a sixth groove having an opening facing the first electrode, and the first electrode extends along the inner wall of the sixth groove.

9. The semiconductor device according to claim 1, wherein The second word line further fills a groove formed by an adjacent first protruding portion and the first vertical portion on the first word line.

10. The semiconductor device according to claim 2, wherein, The semiconductor device further includes: Insulating layers and conductive layers alternately distributed along a direction perpendicular to the substrate; holes penetrating through the insulating layers and the conductive layers; the holes include a first sub-hole located in the insulating layer and a second sub-hole located in the conductive layer, and the second sub-hole has a seventh groove extending in a horizontal direction with respect to the first sub-hole.

11. The semiconductor device according to claim 10, wherein, The semiconductor device further includes: a plurality of capacitors, the capacitors including a first capacitive electrode and a second capacitive electrode, and the first electrode is multiplexed with the first capacitive electrode.

12. The semiconductor device according to claim 11, wherein, The second capacitive electrode includes a first sub-electrode; In the hole, there are sequentially distributed from outside to inside the first capacitive electrode surrounding the first sub-electrode, a first dielectric layer surrounding the first sub-electrode, and the first sub-electrode.

13. The semiconductor device according to claim 12, wherein, The first capacitive electrode is distributed on the inner wall of the seventh groove, the first sub-electrode extends in a direction perpendicular to the substrate and has a protruding portion extending into the seventh groove, and the first sub-electrode fills the hole.

14. The semiconductor device according to claim 12, wherein, The second capacitive electrode further includes a second sub-electrode; The second sub-electrode is distributed on the side of the first capacitive electrode facing away from the substrate, the side facing the substrate, and the side facing away from the semiconductor layer, and a second dielectric layer is provided between the second sub-electrode and the first capacitive electrode.

15. A method for manufacturing a semiconductor device, characterized in that, Including: Providing a substrate, and forming a stacked structure including alternately arranged insulating layers and sacrificial layers on the substrate; Pattern the stacked structure to form a first trench penetrating through the stacked structure, and the first trench extends in a first direction; A transistor region is included between adjacent first trenches spaced apart in a second direction; the first direction and the second direction intersect and are parallel to the substrate; Form a first hole penetrating through the stacked structure in a direction perpendicular to the substrate in the transistor region, and the first hole is close to one of two adjacent first trenches along the second direction; Form a second trench penetrating through the stacked structure outside the transistor region, and the second trench extends in the second direction; Etch the sacrificial layer along a direction parallel to the substrate based on the second trench to form a sub-trench extending in the second direction provided in the sacrificial layer, and etch the sacrificial layer along a direction parallel to the substrate based on the first hole to form a first groove surrounding the first hole provided in the sacrificial layer, and the sub-trench and the first groove communicate; form a semiconductor layer covering the inner wall of the first groove and covering the sidewall of the sub-trench parallel to the substrate; form a first word line filling the first hole including the first groove in the first hole; Form a second hole penetrating through the stacked structure in a direction perpendicular to the substrate in the transistor region, and the second hole is close to the other of two adjacent first trenches along the second direction; Etch the sacrificial layer along a direction parallel to the substrate based on the second hole, exposing at least a part of the sidewall of the semiconductor layer on the side facing the second hole; etch the insulating layer along a direction parallel to the substrate based on the second hole, exposing the sidewall of the first hole facing the second hole; form a second word line filling the second hole in the second hole.

16. The manufacturing method of the semiconductor device according to claim 15, characterized in that, The forming of the semiconductor layer covering the inner wall of the first groove and the sidewall parallel to the substrate of the sub-groove includes: Deposit a semiconductor thin film and a first dummy layer thin film in the first hole, the first groove, the second trench, and the sub-groove in sequence; etch and remove the semiconductor thin film in the second trench and the first hole to form a semiconductor layer covering the inner wall of the first groove and the sidewall parallel to the substrate of the sub-groove.

17. The manufacturing method of the semiconductor device according to claim 15, characterized in that, The etching of the sacrificial layer along a direction parallel to the substrate based on the second hole, exposing at least a part of the sidewall of the semiconductor layer on the side facing the second hole includes: Etch the sacrificial layer along a direction parallel to the substrate based on the second hole, forming a second groove provided in the sacrificial layer and surrounding the second hole, and the second groove exposes the sidewall of the semiconductor layer provided between the first hole and the second hole and on the side facing the second hole; The etching of the insulating layer along a direction parallel to the substrate based on the second hole, exposing the sidewall of the first hole facing the second hole includes: etching the insulating layer along a direction parallel to the substrate based on the second hole, such that the aperture of the sub-hole of the second hole in the sacrificial layer is smaller than the aperture of the sub-hole in the insulating layer in the first direction, and the sidewall of the first hole is exposed in the second direction.

18. An electronic device, characterized in that, Comprising a semiconductor device according to any one of claims 1 to 14.

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