Semiconductor device

Abstract

The present disclosure relates to a semiconductor device comprising: a substrate; a bit line extending in a vertical direction, the vertical direction being perpendicular to an upper surface of the substrate; a semiconductor pattern having first ends connected to the bit line and spaced apart in a vertical direction; a pair of word lines over and under the respective semiconductor patterns; and data storage patterns connected to the second ends of the respective semiconductor patterns. Each of the semiconductor patterns includes a first portion connected to the bit line and including polysilicon, a second portion connected to each of the data storage patterns and including an oxide semiconductor material, and a third portion between the first portion and the second portion and including a metal silicide material.

Description

[0001] This application claims the priority and benefit of Korean Patent Application No. 10-2024-0006981, filed with the Korean Intellectual Property Office on January 16, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Various example embodiments of the present disclosure relate to a semiconductor device. Background Art

[0003] There is a need for a technology to increase the integration degree of semiconductor devices. In the case of two-dimensional (2D) semiconductor devices, the integration degree is mainly determined by the area occupied by a unit memory cell, and the integration degree in this regard can depend on the level of fine pattern formation technology.

[0004] However, fine pattern formation technology requires expensive equipment, and thus, although the integration degree of 2D semiconductor devices is increasing, it is still limited. Accordingly, a three-dimensional (3D) semiconductor memory device having memory cells arranged in a 3D manner has been proposed. Summary of the Invention

[0005] Various example embodiments provide a semiconductor device for increasing the electrical reliability of a channel and reducing leakage current to improve operating characteristics.

[0006] Various example embodiments of the present disclosure provide a semiconductor device including: a substrate; bit lines extending in a vertical direction perpendicular to an upper surface of the substrate; semiconductor patterns having first ends connected to the bit lines and spaced apart in the vertical direction; a pair of word lines above and below the respective semiconductor patterns; and data storage patterns connected to second ends of the respective semiconductor patterns. Each of the semiconductor patterns includes a first portion connected to the bit line and including polysilicon, a second portion connected to each of the data storage patterns and including an oxide semiconductor material, and a third portion between the first portion and the second portion and including a metal silicide material.

[0007] Various example embodiments of the present disclosure provide a semiconductor device, the semiconductor device including: a substrate; bit lines extending in a vertical direction perpendicular to an upper surface of the substrate; semiconductor patterns having first ends connected to the bit lines and spaced apart in the vertical direction; a pair of word lines above and below the respective semiconductor patterns and extending in a first direction parallel to the upper surface of the substrate; and data storage patterns connected to second ends of the respective semiconductor patterns. Each of the semiconductor patterns includes a first portion connected to the bit line and including polysilicon, a second portion connected to the data storage pattern and including an oxide semiconductor material, and a third portion between the first portion and the second portion and including a metal silicide material, and an interface between the second portion and the third portion is between facing surfaces of the pair of word lines.

[0008] Various other example embodiments of the present disclosure provide a semiconductor device, the semiconductor device including: a substrate; bit lines extending in a vertical direction perpendicular to an upper surface of the substrate; semiconductor patterns having first ends connected to the bit lines and spaced apart in the vertical direction; a pair of word lines above and below the respective semiconductor patterns and extending in a first direction parallel to the upper surface of the substrate; and data storage patterns connected to second ends of the respective semiconductor patterns. Each of the semiconductor patterns includes a first portion connected to the bit line and including polysilicon, a second portion connected to the data storage pattern and including an oxide semiconductor material, and a third portion between the first portion and the second portion and including a metal silicide material, and the first portion, the third portion, and the second portion are sequentially arranged between the bit line and the data storage pattern in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction.

[0009] According to various example embodiments, the electrical reliability of the channel can be increased, and the leakage current can be reduced, thereby improving the operating characteristics of the semiconductor device.

[0010] According to various example embodiments, the contact resistance between portions of the channel including different materials can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A perspective view of a semiconductor device according to various example embodiments is shown.

[0012] Figure 2 A cross-sectional view of a semiconductor device according to various example embodiments is shown.

[0013] Figure 3 A cross-sectional view of a semiconductor device according to various example embodiments is shown.

[0014] Figure 4 A cross-sectional view of a semiconductor device according to various example embodiments is shown.

[0015] Figures 5 to 15 A cross-sectional view of a method for manufacturing a semiconductor device according to various example embodiments is shown. Detailed Description

[0016] In the following detailed description, specific example embodiments of the present disclosure are shown and described only by way of illustration. As those skilled in the art will recognize, the described example embodiments can be modified in various different ways, all of which do not depart from the spirit or scope of the present disclosure.

[0017] Portions unrelated to the description will be omitted to clearly describe the various example embodiments, and the same elements will be denoted by the same reference numerals throughout the specification.

[0018] For better understanding and ease of description, the dimensions and thicknesses of each structure shown in the drawings are arbitrarily shown, but the various example embodiments are not limited thereto. For clarity, the thicknesses of layers, films, panels, regions, etc. are exaggerated. For ease of description, the thicknesses of some layers and regions are exaggerated.

[0019] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element can be directly on the other element or there can also be intervening elements. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element can be directly on the other element or there can also be intervening elements.

[0020] Unless explicitly stated to the contrary, the word "comprising" and its variations will be understood to imply the inclusion of the stated elements but not the exclusion of any other elements.

[0021] The phrase "in a plan view" means observing a part of an object from the top, and the phrase "in a cross-sectional view" means observing a cross-section of a part of an object that is vertically cut from the side.

[0022] Now, reference will be made to Figure 1 and Figure 2 to describe a semiconductor device according to various example embodiments.

[0023] Figure 1 A perspective view of a semiconductor device according to various example embodiments is shown. Figure 2 A cross-sectional view of a semiconductor device according to various example embodiments is shown.

[0024] The semiconductor device 100 may include memory cells arranged in a three-dimensional manner. The memory cells may be arranged in a first direction DR1, a second direction DR2, and a third direction DR3. The first direction DR1 and the second direction DR2 may be parallel to the upper surface of the substrate 110 and may be referred to as horizontal directions. For example, the second direction DR2 may be perpendicular to the first direction DR1. The third direction DR3 may be perpendicular to the upper surface of the substrate 110 and may be referred to as a vertical direction. The memory cells may be stacked in the third direction DR3. Each memory cell may be connected to a bit line BL and two word lines WL.

[0025] The bit line BL may extend in the third direction DR3. The memory cells stacked in the third direction DR3 may be commonly connected to the bit line BL. The bit line BL may be arranged in the first direction DR1. The bit line BL may be arranged in the second direction DR2.

[0026] The word line WL may extend in the first direction DR1. The memory cells arranged in the first direction DR1 may be commonly connected to the word line WL. The word line WL may be arranged in the third direction DR3. Each memory cell may be connected to two adjacent word lines WL arranged in the third direction DR3. The word line WL may be arranged in the second direction DR2.

[0027] Figure 1 A memory cell and a bit line BL and two word lines WL connected to the memory cell are shown, and other memory cells are omitted for ease of description. Figure 1 Shown is Figure 2 the cells of the layer of the stacked structure SS shown in

[0028] Figure 2 Three memory cells commonly connected to a bit line BL and stacked in the third direction DR3 are shown. Figure 2 Further shown are the memory cells arranged in the third direction DR3 omitted in Figure 1 Shown is Figure 2 The stacked structure SS is shown to include three layers, but is not limited thereto. According to various exemplary embodiments, the stacked structure SS may include a greater number of layers. Figure 2 Shown is that each layer of the stacked structure SS includes one memory cell, but is not limited thereto. According to various exemplary embodiments, each layer of the stacked structure SS may include a greater number of cells. For example, each layer of the stacked structure SS may further include memory cells that are mirror-symmetric to the structure of the memory cells shown in Figure 2 Shown is Figure 2A stacked structure SS that is mirror-symmetric can be further disposed on the substrate 110. The stacked structure SS and the stacked structure that is symmetrically mirrored to the stacked structure SS can form a pair. A pair of stacked structures can share a second electrode 330 of the data storage pattern DS to be described.

[0029] Referring Figure 1 and Figure 2 FIGS. and, the semiconductor device 100 may include a substrate 110, bit lines BL extending in a third direction DR3 perpendicular to the substrate 110, semiconductor patterns 200 connected to the bit lines BL, a pair of word lines WL disposed above / below the respective semiconductor patterns 200, and a data storage pattern DS connected to the respective semiconductor patterns. According to various example embodiments, a first end of the respective semiconductor pattern 200 may be connected to the bit line BL and spaced apart in the third direction DR3, and a second end may be connected to the data storage pattern DS.

[0030] According to various example embodiments, the stacked structure SS may be disposed on the substrate 110. The substrate 110 may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. However, the example embodiments are not limited thereto. The stacked structure SS may construct a memory cell array of the semiconductor device. Although not shown, peripheral circuits for operating the memory cell array may be disposed on the substrate 110. Wires electrically connected to the bit lines BL and the word lines WL may be disposed on the stacked structure SS and connected to the peripheral circuits.

[0031] The bit line BL and the first interlayer insulating layer 120 may be disposed on a side surface of the stacked structure SS. The bit line BL may extend in the third direction DR3. The bit line BL may have a linear form or a column form extending in the third direction DR3.

[0032] The bit line BL may be electrically connected to the semiconductor pattern 200. The bit line BL may contact the semiconductor pattern 200.

[0033] The bit line BL may include a conductive material. The conductive material may be, for example, a doped semiconductor material (such as doped silicon or doped germanium), a conductive metal nitride (such as titanium nitride or tantalum nitride), a metal (such as tungsten, titanium, or tantalum), and a metal-semiconductor compound (such as tungsten silicide, cobalt silicide, or titanium silicide). However, the example embodiments are not limited thereto.

[0034] The first interlayer insulating layer 120 may extend in the third direction DR3. The first interlayer insulating layer 120 may extend in a first direction DR1. The first interlayer insulating layer 120 may cover the bit line BL. The first interlayer insulating layer 120 may extend into a space between the bit lines BL arranged in the first direction DR1. Through the first interlayer insulating layer 120, the bit lines BL arranged in the first direction DR1 may be insulated from each other.

[0035] The first interlayer insulating layer 120 may include at least one of, for example, a silicon nitride layer, a silicon oxynitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, and a carbon-containing silicon oxynitride layer. However, the exemplary embodiments are not limited thereto.

[0036] The stacked structure SS may include multiple layers. For example, the stacked structure SS may include a first layer L1, a second layer L2, and a third layer L3 sequentially stacked on the substrate 110. The first layer L1, the second layer L2, and the third layer L3 may be stacked in the third direction DR3. The first layer L1, the second layer L2, and the third layer L3 may each include a semiconductor pattern 200, a pair of word lines WL disposed above / below the semiconductor pattern 200, and a data storage pattern DS connected to the semiconductor pattern 200.

[0037] The second interlayer insulating layer 150 may be disposed between two adjacent layers. The second interlayer insulating layer 150 may be disposed between the first layer L1 and the second layer L2, and may be disposed between the second layer L2 and the third layer L3. The word lines WL, the semiconductor patterns 200, and the data storage patterns DS on the corresponding layers may be disposed on the second interlayer insulating layer 150. The word line WL disposed on the upper layer and the word line WL disposed on the lower layer may be spaced apart in the third direction DR3 by the second interlayer insulating layer 150. The semiconductor pattern 200 on the upper layer and the semiconductor pattern 200 on the lower layer may be spaced apart in the third direction DR3 by the second interlayer insulating layer 150. The data storage pattern DS on the upper layer and the data storage pattern DS on the lower layer may be spaced apart in the third direction DR3 by the second interlayer insulating layer 150.

[0038] The second interlayer insulating layer 150 may be disposed between the lowermost layer of the stacked structure SS and the substrate 110.

[0039] The second interlayer insulating layer 150 may include at least one of, for example, a silicon nitride layer, a silicon oxynitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, and a carbon-containing silicon oxynitride layer. However, the exemplary embodiments are not limited thereto.

[0040] The word line WL may extend in the first direction DR1. The word line WL may have a linear form extending in the first direction DR1. Each layer may include two word lines WL. The first word line WL1 and the second word line WL2 may be spaced apart from each other in the third direction DR3 in each layer. For example, the first word line WL1 may be disposed closer to the substrate 110 than the second word line WL2.

[0041] The word line WL may include a conductive material. For example, the conductive material may be one of a semiconductor material, a conductive metal nitride, a metal, and a metal-semiconductor compound. However, the exemplary embodiments are not limited thereto.

[0042] The spacer 140 may be disposed between the word line WL and the bit line BL. The spacer 140 may include an insulating material and may insulate the bit line BL and the word line WL.

[0043] The gate insulating layer Gox may surround the exposed surfaces of the word line WL and the spacer 140. The gate insulating layer Gox may conformally cover the word line WL and the spacer 140. The gate insulating layer Gox may cover the upper surface, the lateral surfaces, and the bottom surface of the word line WL. The gate insulating layer Gox may cover the upper surface and the bottom surface of the spacer 140.

[0044] The gate insulating layer Gox may contact the bit line BL. The portions of the gate insulating layer Gox covering the upper surface of the spacer 140 and the upper surface of the word line WL and the portions of the gate insulating layer Gox covering the bottom surface of the spacer 140 and the bottom surface of the word line WL may contact the bit line BL.

[0045] The gate insulating layer Gox may include at least one of a high-k dielectric layer, a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The high-k dielectric layer may include, for example, at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. However, the exemplary embodiments are not limited thereto.

[0046] The gate insulating layer Gox may include a first gate insulating layer Gox1 disposed between the first word line WL1 and the semiconductor pattern 200 and a second gate insulating layer Gox2 disposed between the second word line WL2 and the semiconductor pattern 200. The semiconductor pattern 200 may be spaced apart from the first word line WL1 by the first gate insulating layer Gox1. The semiconductor pattern 200 may be spaced apart from the second word line WL2 by the second gate insulating layer Gox2. The first gate insulating layer Gox1 may surround the first word line WL1 and the spacer 140 disposed between the first word line WL1 and the bit line BL. The second gate insulating layer Gox2 may surround the second word line WL2 and the spacer 140 disposed between the second word line WL2 and the bit line BL. The first gate insulating layer Gox1 and the second gate insulating layer Gox2 may respectively contact the bit line BL.

[0047] According to various exemplary embodiments, the semiconductor pattern 200 may be disposed between a pair of word lines in each layer. The semiconductor pattern 200 may be disposed between the first word line WL1 and the second word line WL2. The semiconductor pattern 200 may be disposed between the first gate insulating layer Gox1 and the second gate insulating layer Gox2. The first end of the semiconductor pattern 200 may be connected to the bit line BL. The second end of the semiconductor pattern 200 may be connected to the data storage pattern DS. The semiconductor pattern 200 may be disposed in a space surrounded by the upper surface of the first gate insulating layer Gox1, the bottom surface of the second gate insulating layer Gox2, and the lateral surface of the bit line BL.

[0048] According to various example embodiments, the semiconductor pattern 200 may include a first portion 210 connected to the bit line BL, a second portion 230 connected to the data storage pattern DS, and a third portion 220 disposed between the first portion 210 and the second portion 230. The first portion 210 may include polysilicon. The second portion 230 may include an oxide semiconductor material. Since the portion of the semiconductor pattern 200 in contact with the data storage pattern DS includes an oxide semiconductor material instead of polysilicon, the gate-induced drain leakage (GIDL) current can be reduced.

[0049] According to various example embodiments, the oxide semiconductor material included in the second portion 230 may include a material having a high indium composition ratio. The oxide semiconductor material may include various materials containing indium, and the composition ratio of indium among the various materials may be high. For example, a high indium composition ratio may mean that when the oxide semiconductor material includes indium and material A, indium / (indium + A) is greater than A / (indium + A). When the composition ratio of indium increases, the contact resistance between the semiconductor pattern 200 and the data storage pattern DS can be improved. For example, the oxide semiconductor material included in the second portion 230 may include indium gallium zinc oxide (IGZO), In2O3, indium tin oxide (ITO), indium gallium oxide (IGO), and indium tin gallium oxide (ITGO), but the example embodiments are not limited thereto.

[0050] According to various example embodiments, the third portion 220 may include a metal silicide material. The metal silicide material included in the third portion 220 may be, for example, titanium silicide (TiSi2), cobalt silicide (CoSi2), nickel silicide (NiSi2), hafnium silicide (HfSi2), molybdenum silicide (MoSi2), or tungsten silicide (WSi2). However, the example embodiments are not limited thereto.

[0051] According to various example embodiments, the first portion 210, the third portion 220, and the second portion 230 may be sequentially disposed between the bit line BL and the data storage pattern DS in a second direction DR2. According to the above, the first portion 210 may be connected to the bit line BL, and the second portion 230 may be connected to the data storage pattern DS. The first portion 210 and the second portion 230 may be spaced apart in the second direction DR2 by the third portion 220. One of the surfaces of the first portion 210 facing each other in the second direction DR2 may contact the bit line BL, and the other may contact the third portion 220. One of the surfaces of the second portion 230 facing each other in the second direction DR2 may contact the data storage pattern DS, and the other may contact the third portion 220. The first portion 210 including polysilicon is spaced apart from the second portion 230 including an oxide semiconductor material, thereby restricting and / or preventing the generation of silicon oxide at the interface between the first portion 210 and the second portion 230. Restricting and / or preventing the generation of silicon oxide at this interface may prevent an increase in the resistance of the semiconductor pattern 200.

[0052] According to various example embodiments, a region of the first portion 210 disposed close to the third portion 220 may include n-type impurities. The n-type impurities may be doped in a region of the first portion 210 that contacts the third portion 220. The n-type impurities may include, for example, phosphorus (P) or arsenic (As). However, the example embodiments are not limited thereto.

[0053] According to various example embodiments, at least a portion of the semiconductor pattern 200 may be stacked with a pair of word lines WL in a third direction DR3. At least a portion of the second portion 230 of the semiconductor pattern 200 may be stacked with the first word line WL1 and the second word line WL2 in the third direction DR3. The entire portion of the third portion 220 of the semiconductor pattern 200 may be stacked with the first word line WL1 and the second word line WL2 in the third direction DR3.

[0054] According to various example embodiments, a portion of the second portion 230 may be disposed between the first word line WL1 and the second word line WL2, and another portion of the second portion 230 may protrude away from the bit line BL by a distance between the lateral surfaces of the first word line WL1 and the lateral surfaces of the second word line WL2. A portion of the second portion 230 may contact the third portion 220, and another portion of the second portion 230 may contact the data storage pattern DS. In this case, the portion of the second portion 230 disposed close to the third portion 220 may be stacked with the first word line WL1 and the second word line WL2 in the third direction DR3.

[0055] According to several example embodiments, the second portion 230 may be disposed between the first word line WL1 and the second word line WL2. In this case, the entire portion of the second portion 230 may overlap with the first word line WL1 and the second word line WL2 in the third direction DR3.

[0056] According to various example embodiments, a part of the first portion 210 of the semiconductor pattern 200 may overlap with the first word line WL1 and the second word line WL2 in the third direction DR3. For example, a part of the first portion 210 may be disposed between the first word line WL1 and the second word line WL2, and another part of the first portion 210 may protrude away from the bit line BL between the lateral surfaces of the first word line WL1 and the lateral surface of the second word line WL2. Another part of the first portion 210 may be disposed between the spacer 140 disposed between the first word line WL1 and the bit line BL and the spacer 140 disposed between the second word line WL2 and the bit line BL. A part of the first portion 210 may contact the third portion 220, and another part of the first portion 210 may contact the bit line BL. In this case, the portion of the first portion 210 disposed close to the third portion 220 may overlap with the first word line WL1 and the second word line WL2 in the third direction DR3.

[0057] According to various example embodiments, the length in the second direction DR2 of the portion of the first portion 210 that overlaps with the first word line WL1 and the second word line WL2 may be greater than the length in the second direction DR2 of the portion of the second portion 230 that overlaps with the first word line WL1 and the second word line WL2. The first portion 210 including polysilicon overlaps more with the word line WL than the second portion 230 including an oxide semiconductor material, thereby increasing the electrical reliability of the semiconductor pattern 200.

[0058] According to various example embodiments, the interface between the second portion 230 and the third portion 220 of the semiconductor pattern 200 may be provided between the extension lines of the surfaces of the word line WL that face each other in the second direction DR2 (e.g., between the planes in which the surfaces of the word line WL that face each other in the second direction DR2 are located). The third portion 220 of the semiconductor pattern 200 may be provided between the extension lines of the surfaces of the word line WL that face each other in the second direction DR2. For example, the first word line WL1 may include a first surface and a second surface that face each other in the second direction DR2, and the second word line WL2 may include a third surface and a fourth surface that face each other in the second direction DR2. The first surface and the third surface may be arranged in a row in the third direction DR3, and the second surface and the fourth surface may be arranged in a row in the third direction DR3. The interface between the second portion 230 and the third portion 220 may be provided between the extension lines of the first surface and the third surface and the extension lines of the second surface and the fourth surface. The interface between the first portion 210 and the third portion 220 may be provided between the extension lines of the first surface and the third surface and the extension lines of the second surface and the fourth surface.

[0059] According to various example embodiments, the interface between the second portion 230 and the data storage pattern DS may be farther from the bit line BL than the surfaces of the word line WL that face each other in the second direction DR2. The interface between the second portion 230 and the data storage pattern DS may be, for example, farther from the bit line BL than the second surface and the fourth surface. In this case, a portion of the second portion 230 may overlap with the word line WL in the third direction DR3.

[0060] According to some example embodiments, the interface between the second portion 230 and the data storage pattern DS may be provided closer to the bit line BL than the surfaces of the word line WL that face each other in the second direction DR2. The interface between the second portion 230 and the data storage pattern DS may be provided, for example, closer to the bit line BL than the second surface and the fourth surface. In this case, the entire portion of the second portion 230 may overlap with the word line WL in the third direction DR3.

[0061] The etch stop layer 130 may be disposed on one side of a pair of word lines WL. The etch stop layer 130 may be disposed on one side of the first word line WL1 and the second word line WL2. The etch stop layer 130 may be disposed on the lateral surfaces of the first gate insulating layer Gox1 and the second gate insulating layer Gox2. The etch stop layer 130 may be disposed on the lateral surface of the first gate insulating layer Gox1 that "covers the lateral surface of the first word line WL1". The etch stop layer 130 may be disposed on the lateral surface of the second gate insulating layer Gox2 that "covers the lateral surface of the second word line WL2". The etch stop layer 130 may include a portion disposed on the lateral surface of the first gate insulating layer Gox1 and a portion disposed on the lateral surface of the second gate insulating layer Gox2. The etch stop layer 130 may include portions separated in the third direction DR3.

[0062] According to various example embodiments, at least a portion of the second portion 230 of the semiconductor pattern 200 may be disposed between the portion of the etch stop layer 130 disposed on the lateral surface of the first gate insulating layer Gox1 and the portion of the etch stop layer 130 disposed on the lateral surface of the second gate insulating layer Gox2. At least a portion of the second portion 230 may overlap with the portions of the etch stop layer 130 disposed on the lateral surfaces of the first gate insulating layer Gox1 and the second gate insulating layer Gox2 in the third direction DR3.

[0063] According to various example embodiments, the interface between the second portion 230 of the semiconductor pattern 200 and the data storage pattern DS may be disposed between the portion of the etch stop layer 130 disposed on the lateral surface of the first gate insulating layer Gox1 and the portion of the etch stop layer 130 disposed on the lateral surface of the second gate insulating layer Gox2.

[0064] The etch stop layer 130 may contact the data storage pattern DS. According to various example embodiments, the interface between the second portion 230 of the semiconductor pattern 200 and the data storage pattern DS and the interface between the etch stop layer 130 and the data storage pattern DS may be arranged in a line, but is not limited thereto. According to some example embodiments, the interface between the second portion 230 and the data storage pattern DS may be disposed closer to the bit line BL than the interface between the etch stop layer 130 and the data storage pattern DS. In this case, a portion of the data storage pattern DS may protrude toward the bit line BL and may be disposed between the portions of the etch stop layer 130 disposed on the corresponding lateral surfaces of the first gate insulating layer Gox1 and the second gate insulating layer Gox2.

[0065] The etch stop layer 130 may include, for example, a material having an etch selectivity with respect to the material of the second portion 230.

[0066] The data storage pattern DS can be electrically connected to the semiconductor pattern 200. The data storage pattern DS can be a memory component for storing data. For example, it can be a memory component using a capacitor, a memory component using a magnetic tunnel junction pattern, or a memory component using a variable resistor including a phase change material. However, the example embodiments are not limited thereto.

[0067] According to various example embodiments, the data storage pattern DS can be a capacitor. According to various example embodiments, the data storage pattern DS can include a first electrode 310, a second electrode 330 spaced apart from the first electrode 310, and a dielectric layer 320 disposed between the first electrode 310 and the second electrode 330.

[0068] According to various example embodiments, the first electrode 310 can include a vertical portion extending in a third direction DR3 and a pair of horizontal portions extending in a second direction DR2. The vertical portion of the first electrode 310 can contact a second portion 230 of the semiconductor pattern 200 and the etch stop layer 130. The vertical portion of the first electrode 310 can cover a lateral surface of the etch stop layer 130 and a lateral surface of the second portion 230, and can extend in the third direction DR3. The horizontal portions of the first electrode 310 can extend in the second direction DR2, and thus are away from the bit line BL from the vertical portion of the first electrode 310. One of the pair of horizontal portions of the first electrode 310 can extend along an upper surface of the second interlayer insulating layer 150 disposed under each layer in the second direction DR2, and the other of the pair of horizontal portions can extend along a bottom surface of the second interlayer insulating layer 150 disposed above each layer in the second direction DR2. The pair of horizontal portions of the first electrode 310 can be spaced apart in the third direction DR3. The first electrode 310 can have a cylindrical shape extending in the second direction DR2.

[0069] According to various example embodiments, the second electrode 330 can be inserted into the first electrode 310 and can be surrounded by the first electrode 310. The second electrode 330 can be inserted into an internal space of the first electrode 310 having a cylindrical shape. The second electrode 330 can penetrate the multilayer and the second interlayer insulating layer 150. The data storage patterns DS of the multilayer stacked in the third direction DR3 can share one second electrode 330. The second electrode 330 can include a vertical portion extending in the third direction DR3 and integrally formed on the layers of the stacked structure SS, and a horizontal portion protruding in the second direction DR2 from the vertical portion and inserted into the first electrode 310.

[0070] The first electrode 310 and the second electrode 330 may include at least one of a metal material (such as titanium, tantalum, tungsten, copper, or aluminum), a conductive metal nitride (such as titanium nitride or tantalum nitride), and a doped semiconductor material (such as doped silicon or doped germanium). However, the exemplary embodiments are not limited thereto.

[0071] The dielectric layer 320 may be disposed between the first electrode 310 and the second electrode 330. The dielectric layer 320 may be conformally formed on the first electrode 310. The dielectric layer 320 may be disposed inside the first electrode 310 and may be surrounded by the first electrode 310. The dielectric layer 320 may have a shape similar to that of the first electrode 310. That is, the dielectric layer 320 may include a vertical portion extending in the third direction DR3 and a pair of horizontal portions extending in the second direction DR2. The vertical portion of the dielectric layer 320 may be disposed between the vertical portion of the first electrode 310 and the second electrode 330. The horizontal portions of the dielectric layer 320 may be disposed between the horizontal portions of the first electrode 310 and the second electrode 330. The dielectric layer 320 may include at least one of a dielectric material, a ferromagnetic material, and an antiferromagnetic material. The dielectric material may include a high-k dielectric material. For example, the dielectric material may include hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. However, the exemplary embodiments are not limited thereto.

[0072] According to various exemplary embodiments, the insulating pattern 340 may be disposed between the first electrode 310 and the second electrode 330. The insulating pattern 340 may be disposed between the horizontal portion of the first electrode 310 and the vertical portion of the second electrode 330. The insulating pattern 340 may be disposed between the dielectric layer 320 and the second interlayer insulating layer 150. That is, the insulating pattern 340 may be surrounded by the first electrode 310, the dielectric layer 320, the second electrode 330, and the second interlayer insulating layer 150. The first electrode 310 may be insulated from the second electrode 330 through the insulating pattern 340.

[0073] The insulating pattern 340 may include, for example, at least one of silicon nitride, silicon oxynitride, carbon-containing silicon oxide, carbon-containing silicon nitride, and carbon-containing silicon oxynitride. However, the exemplary embodiments are not limited thereto.

[0074] According to various exemplary embodiments, the first portion 210 of the semiconductor pattern 200 connected to the bit line BL may include polysilicon, and the second portion 230 of the semiconductor pattern 200 connected to the data storage pattern DS may include an oxide semiconductor material, thereby increasing the electrical reliability of the semiconductor device 100 and reducing the gate-induced drain leakage (GIDL) current.

[0075] According to various example embodiments, the semiconductor pattern 200 may include a third portion 220 including a metal silicide material between a first portion 210 including polysilicon and a second portion 230 including an oxide semiconductor material, thereby restricting and / or preventing the formation of silicon oxide at the interface between the first portion 210 and the second portion 230. Restricting and / or preventing the generation of silicon oxide at this interface improves the contact resistance of the semiconductor device 100.

[0076] Reference will now be made to Figure 3 and Figure 4 to describe a semiconductor device according to various embodiments.

[0077] Figure 3 A cross-sectional view of a semiconductor device according to various example embodiments is shown. Except for adding an antioxidant layer 180 between the semiconductor pattern 200 and the data storage pattern DS of the semiconductor device 100 according to various example embodiments of Figure 1 and Figure 2 , the semiconductor device 101 according to various example embodiments of Figure 3 may have the same components. For convenience, the differences will be mainly described, and the descriptions overlapping with the above descriptions given with reference to Figure 1 and Figure 2 will be omitted or simplified.

[0078] For example, components included in the second layer L2 among the layers from the stacked structure SS will be described, and this can be applied to other layers in the same or similar manner.

[0079] Referring to Figure 3 , the semiconductor device 101 may include an antioxidant layer 180 between the semiconductor pattern 200 and the data storage pattern DS. The antioxidant layer 180 may be disposed between the second portion 230 including the oxide semiconductor material of the semiconductor pattern 200 and the first electrode 310 of the data storage pattern DS. The first electrode 310 may not contact the second portion 230 through the antioxidant layer 180.

[0080] According to various example embodiments, the interface between the second portion 230 of the semiconductor pattern 200 and the antioxidant layer 180 and the interface between the etch stop layer 130 and the antioxidant layer 180 may be arranged in a line, but is not limited thereto. According to some example embodiments, the interface between the second portion 230 and the antioxidant layer 180 may be set closer to the bit line BL than the interface between the etch stop layer 130 and the antioxidant layer 180. In this case, a part of the antioxidant layer 180 may protrude toward the bit line BL and may be disposed between the portions of the etch stop layer 130 disposed on the respective lateral surfaces of the first gate insulating layer Gox1 and the second gate insulating layer Gox2.

[0081] According to various example embodiments, the antioxidant layer 180 may extend over multiple layers. The antioxidant layer 180 may conformally cover at least a portion of the corresponding second interlayer insulating layer 150. The antioxidant layer 180 may conformally cover the second portion 230 of the semiconductor pattern 200 and the etch stop layer 130 (e.g., the lateral surface of the etch stop layer 130). The antioxidant layer 180 covering the second portion 230 of the semiconductor pattern 200 and the etch stop layer 130 in each layer may extend on the bottom surface of the second interlayer insulating layer 150 disposed above each layer and on the upper surface of the second interlayer insulating layer 150 disposed below each layer. The antioxidant layer 180 may extend on the upper surface of the second interlayer insulating layer 150 to the lateral surface of the second interlayer insulating layer 150. The antioxidant layer 180 may extend on the lateral surface of the second interlayer insulating layer 150 to the bottom surface of the second interlayer insulating layer 150. The antioxidant layer 180 may extend on the bottom surface of the second interlayer insulating layer 150 to the lateral surface of the second interlayer insulating layer 150. The antioxidant layer 180 may extend on the lateral surface of the second interlayer insulating layer 150 to the upper surface of the second interlayer insulating layer 150.

[0082] According to various example embodiments, the portion of the antioxidant layer 180 covering the second portion 230 of the semiconductor pattern 200 and the etch stop layer 130 and the portion of the antioxidant layer 180 covering the lateral surface of the second interlayer insulating layer 150 may extend in the third direction DR3. The portion of the antioxidant layer 180 covering at least a portion of the upper surface and the bottom surface of the second interlayer insulating layer 150 may extend in the second direction DR2.

[0083] The antioxidant layer 180 may include, for example, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon carbonitride, but the example embodiments are not limited thereto.

[0084] According to various example embodiments, the thickness of the antioxidant layer 180 may be equal to or less than about 1 nm. Since the antioxidant layer 180 has a thickness equal to or less than about 1 nm, the second portion 230 of the semiconductor pattern 200 may be electrically connected to the first electrode 310.

[0085] According to various example embodiments, the antioxidant layer 180 is disposed between the second portion 230 of the semiconductor pattern 200 including an oxide semiconductor material and the first electrode 310 of the data storage pattern DS, thereby restricting and / or preventing the material of the first electrode 310 from being oxidized. Restricting and / or preventing oxidation at this interface may prevent an increase in contact resistance.

[0086] Figure 4 A cross-sectional view of a semiconductor device according to various example embodiments is shown. Except for adding the conductive layer 190 between the semiconductor pattern 200 and the data storage pattern DS of the semiconductor device 100, according to Figure 4The semiconductor device 102 of various exemplary embodiments has components identical to Figure 1 and Figure 2 For convenience, the differences will be mainly described, and the descriptions overlapping with the above descriptions given with reference to Figure 1 and Figure 2 will be omitted or simplified.

[0087] For example, components included in the second layer L2 among the layers from the stacked structure SS will be described, and this can be applied to other layers in the same or similar manner.

[0088] Referring to Figure 4 , the semiconductor device 102 may include a conductive layer 190 between the semiconductor pattern 200 and the data storage pattern DS. The conductive layer 190 may be disposed between the second portion 230 including an oxide semiconductor material of the semiconductor pattern 200 and the first electrode 310 of the data storage pattern DS.

[0089] The conductive layer 190 may contain a conductive material. The conductive layer 190 may include, for example, a metal nitride (such as titanium nitride (TiN), tungsten nitride (WN), or tungsten carbonitride (WCN)) or a metal material (such as cobalt (Co)), but the exemplary embodiments are not limited thereto.

[0090] According to various exemplary embodiments, the interface between the second portion 230 of the semiconductor pattern 200 and the conductive layer 190 and the interface between the etch stop layer 130 and the conductive layer 190 may be arranged in a line, but not limited thereto. According to some exemplary embodiments, the interface between the second portion 230 and the conductive layer 190 may be arranged closer to the bit line BL than the interface between the etch stop layer 130 and the conductive layer 190. In this case, a part of the conductive layer 190 may protrude toward the bit line BL and may be disposed between the portions of the etch stop layer 130 provided on the respective lateral surfaces of the first gate insulating layer Gox1 and the second gate insulating layer Gox2.

[0091] According to various exemplary embodiments, the conductive layer 190 may conformally cover at least a part of the second interlayer insulating layer 150 that separates the multiple layers. The conductive layer 190 may conformally cover the second portion 230 of the semiconductor pattern 200 and the etch stop layer 130 (e.g., the lateral surface of the etch stop layer 130). The conductive layer 190 covering the second portion 230 of the semiconductor pattern 200 and the etch stop layer 130 in each layer may extend above the bottom surface of the second interlayer insulating layer 150 provided above each layer and above the upper surface of the second interlayer insulating layer 150 provided below each layer.

[0092] According to various example embodiments, the conductive layer 190 may include a vertical portion extending in a third direction DR3 and a pair of horizontal portions extending in a second direction DR2. The second direction DR2 may be perpendicular to the first direction DR1 in which the word line WL extends. The vertical portion of the conductive layer 190 may cover a second portion 230 of the semiconductor pattern 200 and the etch stop layer 130 (e.g., a lateral surface of the etch stop layer 130). The pair of horizontal portions of the conductive layer 190 may cover at least a part of an upper surface and a bottom surface of the second interlayer insulating layer 150. The conductive layer 190 may surround the first electrode 310.

[0093] According to various example embodiments, the insulating pattern 340 may be disposed between the conductive layer 190 and the second electrode 330 and between the first electrode 310 and the second electrode 330. The insulating pattern 340 may be disposed between a horizontal portion of the conductive layer 190 and a portion of the second electrode 330 extending in the third direction DR3. The insulating pattern 340 may be disposed between a horizontal portion of the first electrode 310 and a portion of the second electrode 330 extending in the third direction DR3. Through the insulating pattern 340, the conductive layer 190 may be spaced apart from the second electrode 330, and the first electrode 310 may be spaced apart from the second electrode 330. The insulating pattern 340 may insulate the conductive layer 190 and the second electrode 330, and may insulate the first electrode 310 and the second electrode 330.

[0094] According to various example embodiments, the conductive layer 190 is disposed between a second portion 230 of the semiconductor pattern 200 including an oxide semiconductor material and the first electrode 310 of the data storage pattern DS, thereby reducing a contact resistance between the semiconductor pattern 200 and the data storage pattern DS.

[0095] Now, a method for manufacturing a semiconductor device according to various example embodiments will be described with reference to Figures 5 to 15 FIGs. Figures 5 to 15 A cross-sectional view of a method for manufacturing a semiconductor device according to various example embodiments is shown. Figures 5 to 15 FIGs. show a method for manufacturing a semiconductor device 100 according to Figure 1 and Figure 2 various example embodiments.

[0096] Referring to Figure 5 FIG.

[0097] The bit line BL may include a conductive material. The conductive material may be, for example, a doped semiconductor material (such as doped silicon or doped germanium), a conductive metal nitride (such as titanium nitride or tantalum nitride), a metal (such as tungsten, titanium or tantalum), and a metal-semiconductor compound (such as tungsten silicide, cobalt silicide or titanium silicide). However, the exemplary embodiments are not limited thereto.

[0098] The first interlayer insulating layer 120 may extend in the first direction DR1. The first interlayer insulating layer 120 may extend into the space between the bit lines BL arranged in the first direction DR1 and insulate the bit lines BL.

[0099] On one side of the bit line BL, the second interlayer insulating layer 150, the first sacrificial layer 160, and the first channel material layer 170 may be alternately stacked on the substrate 110. The second interlayer insulating layer 150, the first sacrificial layer 160, and the first channel material layer 170 may be alternately stacked in the third direction DR3. The second interlayer insulating layer 150 and the first channel material layer 170 may contact the bit line BL. The first sacrificial layer 160 may be spaced apart from the bit line BL in the second direction DR2.

[0100] The first interlayer insulating layer 120 and the second interlayer insulating layer 150 may include, for example, at least one of a silicon nitride layer, a silicon oxynitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, and a carbon-containing silicon oxynitride layer. However, the exemplary embodiments are not limited thereto. The first sacrificial layer 160 may include, for example, silicon nitride.

[0101] According to various exemplary embodiments, the first channel material layer 170 may contain polysilicon.

[0102] An etch stop layer 130 may be provided on the surface of the first sacrificial layer 160 facing the bit line BL. Portions of the etch stop layer 130 may be spaced apart and provided in the third direction DR3 through the second interlayer insulating layer 150 and the first channel material layer 170. The etch stop layer 130 may include, for example, a material having an etch selectivity with respect to the first sacrificial layer 160.

[0103] A gate insulating layer Gox may be provided in the space surrounded by the second interlayer insulating layer 150, the etch stop layer 130, and the first channel material layer 170. The gate insulating layer Gox may include at least one of a high dielectric layer, a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. However, the exemplary embodiments are not limited thereto. The high dielectric layer may include, for example, at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. However, the exemplary embodiments are not limited thereto. The gate insulating layer Gox may include a first gate insulating layer Gox1 and a second gate insulating layer Gox2.

[0104] The first gate insulating layer Gox1 can conformally cover the upper surface of the second interlayer insulating layer 150, the bottom surface of the first channel material layer 170, and the lateral surfaces of the etch stop layer 130 disposed between the second interlayer insulating layer 150 and the first channel material layer 170. One lateral surface of the etch stop layer 130 can face the bit line BL.

[0105] The second gate insulating layer Gox2 can conformally cover the upper surface of the first channel material layer 170, the bottom surface of the second interlayer insulating layer 150, and the lateral surfaces of the etch stop layer 130 disposed between the first channel material layer 170 and the second interlayer insulating layer 150. One lateral surface of the etch stop layer 130 can face the bit line BL.

[0106] A pair of word lines WL can be disposed between the second interlayer insulating layers 150. The word lines WL can extend in the first direction DR1. The first direction DR1 and the second direction DR2 can be perpendicular to each other. The pair of word lines WL disposed between the second interlayer insulating layers 150 can include a first word line WL1 and a second word line WL2. The first word line WL1 and the second word line WL2 can be spaced apart and disposed in the third direction DR3. The first word line WL1 and the second word line WL2 can be disposed above / below the first channel material layer 170. The first word line WL1 can be disposed closer to the substrate 110 than the second word line WL2.

[0107] The word line WL can include a conductive material. For example, the conductive material can be one of a semiconductor material, a conductive metal nitride, a metal, and a metal-semiconductor compound. However, the exemplary embodiments are not limited thereto.

[0108] Spacers 140 including an insulating material can be disposed between the first word line WL1 and the bit line BL and between the second word line WL2 and the bit line BL. The spacers 140 can space the first word line WL1 and the second word line WL2 from the bit line BL in the second direction DR2. The first word line WL1 and the second word line WL2 can be insulated from the bit line BL by the spacers 140.

[0109] The first word line WL1 and the spacers 140 disposed on the lateral surface of the bit line BL can be surrounded by the first gate insulating layer Gox1. The first gate insulating layer Gox1 can space the first word line WL1 from the first channel material layer 170. The second word line WL2 and the spacers 140 disposed on the lateral surface of the bit line BL can be surrounded by the second gate insulating layer Gox2. The second gate insulating layer Gox2 can space the second word line WL2 from the first channel material layer 170.

[0110] Refer to Figure 6, a trench can be formed to penetrate the second interlayer insulating layer 150, the first sacrificial layer 160, and the first channel material layer 170 in the third direction DR3, and the first sacrificial layer 160 can be removed through the trench. For example, the first sacrificial layer 160 can be selectively etched by using an etchant having a high etch selectivity to the first sacrificial layer 160. Through the etching process, the first sacrificial layer 160 can be removed and the etch stop layer 130 can be exposed.

[0111] The first channel material layer 170 can be partially removed. For example, the first channel material layer 170 can be selectively etched by using an etchant having a high etch selectivity to the first channel material layer 170. Through the etching process, the first channel material layer 170 can be partially removed and the first portion 210 can be formed. The first portion 210 includes the same material as the first channel material layer 170.

[0112] One of the surfaces of the first portion 210 facing each other in the second direction DR2 can contact the bit line BL, and the other surface of the surfaces of the first portion 210 can be disposed between the extension lines of the surfaces of the first word line WL1 and the second word line WL2 facing each other in the second direction DR2. For example, the first word line WL1 can include a first surface and a second surface facing each other in the second direction DR2, and the second word line WL2 can include a third surface and a fourth surface facing each other in the second direction DR2. The surface of the first portion 210 that "faces the surface contacting the bit line BL in the second direction DR2" (i.e., the other surface of the surfaces of the first portion 210 described above) can be disposed between the extension lines of the first surface and the third surface and the extension lines of the second surface and the fourth surface.

[0113] According to various exemplary embodiments, a part of the first portion 210 can be stacked with the first word line WL1 and the second word line WL2 in the third direction DR3.

[0114] In the above exemplary embodiments, the first sacrificial layer 160 and the first channel material layer 170 are etched by an additional process, but are not limited thereto. In some exemplary embodiments, the first sacrificial layer 160 and the first channel material layer 170 can be etched together until the etch stop layer 130 is exposed, and then the first channel material layer 170 can be additionally etched by another process.

[0115] Before performing Figure 7 the process, n-type impurities can be doped into the region disposed close to the exposed surface of the first portion 210. The n-type impurities can include, for example, phosphorus (P) or arsenic (As).

[0116] Referring to Figure 7, a metal layer 215 can be formed. The metal layer 215 can include, for example, titanium, cobalt, nickel, hafnium, molybdenum, or tungsten. However, the exemplary embodiments are not limited thereto. For example, the metal layer 215 can be formed by a sputtering process or a chemical vapor deposition (CVD) process. However, the exemplary embodiments are not limited thereto, and the metal layer 215 can be deposited by various methods.

[0117] The metal layer 215 can conformally cover the exposed surfaces of the second interlayer insulating layer 150, the etch stop layer 130, the first gate insulating layer Gox1, the second gate insulating layer Gox2, and the first portion 210.

[0118] Referring to Figure 8 , by performing an annealing process, a portion of the contact metal layer 215 of the first portion 210 can be made into a silicide to form a third portion 220. Thus, the third portion 220 of the contact metal layer 215 can include a metal silicide material. Depending on the metal material of the metal layer 215, the metal silicide material can be, for example, titanium silicide (TiSi2), cobalt silicide (CoSi2), nickel silicide (NiSi2), hafnium silicide (HfSi2), molybdenum silicide (MoSi2), or tungsten silicide (WSi2). However, the exemplary embodiments are not limited thereto.

[0119] The third portion 220 can be disposed between the extension lines of the surfaces of the first word line WL1 and the second word line WL2 that face each other in the second direction DR2. For example, the first word line WL1 can include a first surface and a second surface that face each other in the second direction DR2, and the second word line WL2 can include a third surface and a fourth surface that face each other in the second direction DR2. The third portion 220 can be disposed between the extension lines of the first surface and the third surface and the extension lines of the second surface and the fourth surface.

[0120] According to various exemplary embodiments, the entire portion of the third portion 220 can be stacked with the first word line WL1 and the second word line WL2 in the third direction DR3.

[0121] Referring to Figure 9 , the metal layer 215 can be removed. For example, the metal layer 215 can be selectively etched by using an etchant having a high etch selectivity.

[0122] Referring to Figure 10 , a second portion 230 including an oxide semiconductor material can be formed. For example, an oxide semiconductor material layer can be deposited, and the oxide semiconductor material layer can be etched until the etch stop layer 130 is exposed, thereby forming the second portion 230. The oxide semiconductor material layer can be deposited, for example, by a physical vapor deposition (PVD) or a chemical vapor deposition (CVD) process, but the exemplary embodiments are not limited thereto.

[0123] According to various exemplary embodiments, the oxide semiconductor material may include a material having a high indium composition ratio. The oxide semiconductor material may include, for example, indium gallium zinc oxide (IGZO), In2O3, indium tin oxide (ITO), indium gallium oxide (IGO), or indium tin gallium oxide (ITGO), but the exemplary embodiments are not limited thereto.

[0124] One of the surfaces of the second portion 230 that face each other in the second direction DR2 may contact the third portion 220. The interface between the second portion 230 and the third portion 220 may be disposed between the extension lines of the surfaces of the first word line WL1 and the second word line WL2 that face each other in the second direction DR2. For example, the first word line WL1 may include a first surface and a second surface that face each other in the second direction DR2, and the second word line WL2 may include a third surface and a fourth surface that face each other in the second direction DR2. The interface between the second portion 230 and the third portion 220 may be disposed between the extension lines of the first surface and the third surface and the extension lines of the second surface and the fourth surface.

[0125] According to various exemplary embodiments, at least a portion of the second portion 230 may overlap the first word line WL1 and the second word line WL2 in the third direction DR3.

[0126] According to various exemplary embodiments, the semiconductor pattern 200 including the first portion 210, the second portion 230, and the third portion 220 may be formed between the first word line WL1 and the second word line WL2. The first portion 210 includes polysilicon, the second portion 230 includes an oxide semiconductor material, and the third portion 220 includes a metal silicide material between the first portion 210 and the second portion 230. According to various exemplary embodiments, the semiconductor pattern 200 includes the third portion 220, thereby restricting and / or preventing the first portion 210 from being oxidized to generate SiO2 in Figure 10 the process for forming the second portion 230.

[0127] According to various exemplary embodiments, the surface of the second portion 230 exposed in the second direction DR2 and the surface of the etch stop layer 130 exposed in the second direction DR2 may be arranged in a row, but are not limited thereto. For example, when etching the oxide semiconductor material layer, the etch stop layer 130 may be exposed, and then the oxide semiconductor material layer may be further etched. Thus, the surface of the second portion 230 exposed in the second direction DR2 may be arranged closer to the bit line BL than the exposed surface of the etch stop layer 130.

[0128] According to several exemplary embodiments, may be additionally formed Figure 3An antioxidant layer 180. For example, the antioxidant layer may be conformally formed to have a thickness equal to or less than about 1 nm. The antioxidant layer may be formed to conformally cover the exposed surfaces of the second portion 230 of the semiconductor pattern 200, the etch stop layer 130, and the second interlayer insulating layer 150.

[0129] The antioxidant layer may include, for example, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride, but the exemplary embodiments are not limited thereto.

[0130] When performing the processes to be described after additionally forming the antioxidant layer, a semiconductor device 101 according to various exemplary embodiments may be formed. In this case, a first electrode material layer 310_L to be described with reference to Figure 3 may be formed on the antioxidant layer. Figure 11

[0131] According to some exemplary embodiments, a conductive layer 190 may be additionally formed. Figure 4 For example, the conductive layer 190 may be conformally formed to cover the exposed surfaces of the second portion 230 of the semiconductor pattern 200, the etch stop layer 130, and the second interlayer insulating layer 150. The conductive layer 190 may include, for example, a metal nitride (such as titanium nitride (TiN), tungsten nitride (WN), or tungsten carbonitride (WCN)) or a metal material (such as cobalt (Co)), but the exemplary embodiments are not limited thereto.

[0132] When performing the processes to be described after additionally forming the conductive layer 190, a semiconductor device 102 according to various exemplary embodiments may be formed. In this case, a first electrode material layer 310_L to be described with reference to Figure 4 may be formed on the conductive layer 190. When forming the insulating pattern 340 to be described with reference to Figure 11 , a part of the conductive layer 190 may be etched in addition to the first electrode 310. The insulating pattern 340 may cover the surfaces of the etched and exposed portions of the conductive layer 190 and the first electrode 310. Referring to Figure 14 , the insulating pattern 340 may be disposed between the conductive layer 190 and the second electrode 330 and between the first electrode 310 and the second electrode 330. Figure 15

[0133] Referring to Figure 11 , a first electrode material layer 310_L may be formed. For example, the first electrode material layer 310_L may be deposited by an atomic layer deposition (ALD) process, but the exemplary embodiments are not limited thereto.

[0134] According to various exemplary embodiments, the first electrode material layer 310_L may conformally cover the exposed surfaces of the second portion 230 of the semiconductor pattern 200, the etch stop layer 130, and the second interlayer insulating layer 150. ​​

[0135] The first electrode material layer 310_L may include, for example, at least one of a metal material (such as titanium, tantalum, tungsten, copper, or aluminum), a conductive metal nitride (such as titanium nitride or tantalum nitride), and a doped semiconductor material (such as doped silicon or doped germanium). However, the exemplary embodiments are not limited thereto.

[0136] Referring to Figure 12 , a dielectric layer material layer 320_L may be formed. For example, the dielectric layer material layer 320_L may be deposited by an ALD process, but the exemplary embodiments are not limited thereto.

[0137] According to various exemplary embodiments, the dielectric layer material layer 320_L may conformally cover the exposed surface of the first electrode material layer 310_L.

[0138] The dielectric layer material layer 320_L may include, for example, at least one of a dielectric material, a ferromagnetic material, and an antiferromagnetic material. However, the exemplary embodiments are not limited thereto. The dielectric material may include a high dielectric constant material. For example, it may include hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. However, the exemplary embodiments are not limited thereto.

[0139] Referring to Figure 13 , the space that remains empty when the dielectric layer material layer 320_L is formed may be filled with a sacrificial layer material, and a trench for separating the first electrode 310 may be formed. For example, a trench that penetrates the second interlayer insulating layer 150, the first electrode material layer 310_L, the dielectric layer material layer 320_L, and the sacrificial layer material layer in the third direction DR3 may be formed.

[0140] When the trench is formed, the first electrode material layer 310_L, the dielectric layer material layer 320_L, and the sacrificial layer material layer that are connected along the lateral surface of the second interlayer insulating layer 150 may be separately cut. The first electrode 310, the dielectric layer 320, and the sacrificial layer pattern SP may be formed between adjacent second interlayer insulating layers 150.

[0141] According to various exemplary embodiments, the first electrode 310 may include a vertical portion extending in the third direction DR3 and a pair of horizontal portions extending in the second direction DR2. The horizontal portions of the first electrode 310 may extend in the second direction DR2 to be away from the bit line BL from the vertical portion of the first electrode 310. The pair of horizontal portions of the first electrode 310 may be spaced apart and disposed in the third direction DR3. The first electrode 310 may have a cylindrical form extending in the second direction DR2.

[0142] According to various exemplary embodiments, the dielectric layer 320 may have a shape that covers the inner wall of the cylindrical first electrode 310. The sacrificial layer pattern SP may fill the internal space of the cylindrical first electrode 310 that remains when the dielectric layer 320 is formed. The sacrificial layer pattern SP may be surrounded by the dielectric layer 320.

[0143] Referring Figure 14 , a portion of the first electrode 310 may be etched, and an insulating pattern 340 may be formed on the etched portion.

[0144] For example, the first electrode 310 exposed by the trench formed in Figure 13 may be selectively etched. When a portion of the first electrode 310 is removed, a recess including "the second interlayer insulating layer 150 and the dielectric layer 320 as sidewalls and the first electrode 310 as a bottom surface" may be formed. The insulating pattern 340 may be formed in the recess.

[0145] The insulating pattern 340 may include, for example, at least one of silicon nitride, silicon oxynitride, carbon-containing silicon oxide, carbon-containing silicon nitride, and carbon-containing silicon oxide.

[0146] Referring Figure 15 , the sacrificial layer pattern SP may be removed, and the second electrode 330 may be formed. The sacrificial layer pattern SP may be removed by an etching process. When the sacrificial layer pattern SP is removed, the second electrode 330 may be deposited. The second electrode 330 may be formed by, for example, a PVD or CVD process, but the exemplary embodiments are not limited thereto.

[0147] The second electrode 330 may include, for example, at least one of a metal material (such as titanium, tantalum, tungsten, copper, or aluminum), a conductive metal nitride (such as titanium nitride or tantalum nitride), and a doped semiconductor material (such as doped silicon or doped germanium). However, the exemplary embodiments are not limited thereto.

[0148] The second electrode 330 may fill the internal space of the cylindrical first electrode 310 instead of the sacrificial layer pattern SP. The second electrode 330 may be inserted into the internal space of the cylindrical first electrode 310. The second electrode 330 may be surrounded by the dielectric layer 320. A portion of the second electrode 330 surrounded by the dielectric layer 320 may extend in the second direction DR2.

[0149] The second electrode 330 may cover the lateral surfaces of the dielectric layer 320, the insulating pattern 340, and the second interlayer insulating layer 150, and may extend in the third direction DR3.

[0150] According to various example embodiments, the first electrode 310, a portion of the second electrode 330 spaced apart from the first electrode 310, and the dielectric layer 320 disposed between the first electrode 310 and the second electrode 330 may construct a data storage pattern DS. When the first electrode 310 contacts the second portion 230 of the semiconductor pattern 200, the data storage pattern DS may be electrically connected to the semiconductor pattern 200.

[0151] According to various example embodiments, the semiconductor device 100 may include a stacked structure SS in which memory cells are stacked in a third direction DR3. For example, the stacked structure SS may include a first layer L1, a second layer L2, and a third layer L3, which is not limited thereto, and may include a greater number of layers. For example, the second electrodes 330 respectively included in the first layer L1, the second layer L2, and the third layer L3 of the data storage pattern DS may be connected in the third direction DR3. The second electrode 330 may be spaced apart from the first electrode 310 of each layer by the dielectric layer 320 and the insulating pattern 340. The dielectric layer 320 and the insulating pattern 340 may insulate the second electrode 330 from the first electrode 310 of each layer.

[0152] Although the present disclosure has been described in connection with what are presently considered to be practical example embodiments, it is to be understood that the present disclosure is not limited to the disclosed example embodiments. On the contrary, the present disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: A substrate; Bit lines extending in a vertical direction perpendicular to the upper surface of the substrate; A plurality of semiconductor patterns having first ends connected to the bit lines and spaced apart in the vertical direction; Multiple pairs of word lines, each pair of word lines in the plurality of pairs of word lines being above and below the corresponding semiconductor pattern; And A plurality of data storage patterns connected to second ends of the corresponding semiconductor patterns, Wherein each of the plurality of semiconductor patterns includes: a first portion connected to the bit line and including polysilicon; a second portion connected to the corresponding data storage pattern in the plurality of data storage patterns and including an oxide semiconductor material; and a third portion between the first portion and the second portion and including a metal silicide material.

2. The semiconductor device according to claim 1, wherein At least a portion of the second portion of each of the plurality of semiconductor patterns is stacked with the corresponding pair of word lines in the vertical direction.

3. The semiconductor device according to claim 1, wherein The third portion of each of the plurality of semiconductor patterns is stacked with the corresponding pair of word lines in the vertical direction.

4. The semiconductor device according to claim 1, wherein The region of the first portion close to the third portion includes n-type impurities.

5. The semiconductor device according to claim 1, wherein The oxide semiconductor material includes indium gallium zinc oxide, In2O3, indium tin oxide, indium gallium oxide, or indium tin gallium oxide.

6. The semiconductor device according to any one of claims 1 to 5, further comprising: An antioxidant layer between each of the plurality of semiconductor patterns and each of the plurality of data storage patterns, Wherein the antioxidant layer has a thickness equal to or less than 1 nm.

7. The semiconductor device according to any one of claims 1 to 5, wherein Each of the plurality of data storage patterns includes: A first electrode including a vertical portion extending in the vertical direction and a pair of horizontal portions extending in the horizontal direction, the horizontal direction being parallel to the upper surface of the substrate, A second electrode spaced apart from the first electrode; and A dielectric layer between the first electrode and the second electrode.

8. The semiconductor device according to claim 7, further comprising: A conductive layer between each of the plurality of semiconductor patterns and each of the plurality of data storage patterns and surrounding the first electrode, and An insulating pattern between the conductive layer and the second electrode and between the first electrode and the second electrode.

9. The semiconductor device according to claim 7, wherein The dielectric layer includes at least one of a dielectric material, a ferromagnetic material, and an antiferromagnetic material.

10. A semiconductor device, comprising: A substrate; Bit lines extending in a vertical direction perpendicular to the upper surface of the substrate; A plurality of semiconductor patterns having first ends connected to the bit lines and spaced apart in the vertical direction; Multiple pairs of word lines, each pair of word lines in the plurality of pairs of word lines being above and below the corresponding semiconductor pattern and extending in a first direction parallel to the upper surface of the substrate; And A plurality of data storage patterns connected to second ends of the corresponding semiconductor patterns, Each of the plurality of semiconductor patterns includes: a first portion connected to a bit line and including polysilicon; a second portion connected to a corresponding data storage pattern and including an oxide semiconductor material; and a third portion between the first portion and the second portion and including a metal silicide material, and an interface between the second portion and the third portion is between planes in which facing surfaces of a corresponding pair of word lines are located.

11. The semiconductor device according to claim 10, wherein, the third portion is between planes in which facing surfaces of a corresponding pair of word lines are located.

12. The semiconductor device according to claim 10, wherein, an interface between each of the second portions and a corresponding data storage pattern is farther from the bit line than surfaces of a corresponding pair of word lines facing each other in a second direction, the second direction being parallel to an upper surface of the substrate and perpendicular to a first direction.

13. The semiconductor device according to any one of claims 10 to 12, further comprising an anti-oxidation layer between each of the second portions and a corresponding data storage pattern, Among them, the anti-oxidation layer having a conformal shape and a thickness equal to or less than 1 nm.

14. The semiconductor device according to any one of claims 10 to 12, further comprising: a conductive layer between each of the second portions and each of the plurality of data storage patterns, wherein the conductive layer includes a vertical portion extending in a vertical direction and a pair of horizontal portions extending in a second direction, the second direction being parallel to an upper surface of the substrate and perpendicular to a first direction.

15. A semiconductor device, comprising: a substrate; bit lines extending in a vertical direction perpendicular to an upper surface of the substrate; a plurality of semiconductor patterns having first ends connected to the bit lines and spaced apart in the vertical direction; multiple pairs of word lines, each pair of word lines extending above and below a corresponding semiconductor pattern and in a first direction parallel to an upper surface of the substrate; and a plurality of data storage patterns connected to second ends of corresponding semiconductor patterns, wherein each of the plurality of semiconductor patterns includes: a first portion connected to the bit line and including polysilicon, a second portion connected to a corresponding data storage pattern and including an oxide semiconductor material, and a third portion between the first portion and the second portion and including a metal silicide material, and the first portion, the third portion, and the second portion are sequentially arranged between the bit line and a corresponding data storage pattern in a second direction, the second direction being parallel to an upper surface of the substrate and perpendicular to the first direction.

16. The semiconductor device according to claim 15, wherein, a part of the first portion, at least a part of the second portion, and the third portion are stacked with a corresponding pair of word lines in the vertical direction.

17. The semiconductor device according to claim 16, wherein, a length of a part of the first portion stacked with a corresponding pair of word lines in the second direction is greater than a length of a part of the second portion stacked with a corresponding pair of word lines in the second direction.

18. The semiconductor device according to claim 16, further comprising: a pair of gate insulating layers for spacing a corresponding semiconductor pattern from a corresponding pair of word lines, and A pair of etch stop layers, between the pair of gate insulating layers and corresponding data storage patterns.

19. The semiconductor device according to claim 18, wherein, An interface between the second portion and the corresponding data storage pattern is located vertically between the pair of etch stop layers.

20. The semiconductor device according to claim 19, wherein, An interface between the second portion and the corresponding data storage pattern and interfaces between the pair of etch stop layers and the data storage pattern are aligned.

Images