Semiconductor device

Abstract

A semiconductor device includes: an active pattern on a substrate, the active pattern including a central portion and first and second end portions at opposite ends of the central portion; an insulating pattern; first and second pad patterns on first and second end portions of the active pattern, respectively; a bit line structure on the first pad pattern; and a contact plug structure on the second pad pattern. An area of an upper surface of the first pad pattern is larger than an area of a first end portion of the active pattern directly contacting an upper surface of the first pad pattern, and an area of an upper surface of the second pad pattern is larger than an area of a second end portion of the active pattern directly contacting an upper surface of the second pad pattern.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0007130, filed with the Korean Intellectual Property Office on January 17, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments relate to semiconductor devices, and more particularly, to dynamic random access memory (DRAM) devices. Background Art

[0003] A DRAM device may include a gate structure extending through a central portion of an active pattern in a first direction, a bit line extending on a first end portion of the active pattern in a second direction, a contact plug structure on a second end portion of the active pattern, and a capacitor on the contact plug structure.

[0004] As DRAM devices become highly integrated, the contact area between the bit line and the active pattern and the contact area between the contact plug structure and the active pattern may be reduced, which may result in poor electrical connection between the bit line and the active pattern and between the contact plug structure and the active pattern. Summary of the Invention

[0005] Example embodiments provide a semiconductor device having improved characteristics.

[0006] According to an example embodiment, there is provided a semiconductor device. The semiconductor device may include: an active pattern on a substrate, the active pattern including a central portion and first and second end portions at opposite ends of the central portion; an insulating pattern extending into a part of the first end portion of the active pattern and extending into a part of the second end portion of the active pattern; a first pad pattern and a second pad pattern on the first and second end portions of the active pattern, respectively; a gate structure extending into the central portion of the active pattern; a bit line structure on the first pad pattern; a contact plug structure on the second pad pattern; and a capacitor on the contact plug structure. The area of the upper surface of the first pad pattern is greater than the area of the upper surface of the first end portion of the active pattern that directly contacts the first pad pattern, and the area of the upper surface of the second pad pattern is greater than the area of the upper surface of the second end portion of the active pattern that directly contacts the second pad pattern.

[0007] According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device may include: a plurality of active patterns on a substrate, the plurality of active patterns including respective central portions, respective first ends, and respective second ends, the respective first ends and the respective second ends being at opposite ends of the respective central portions. The plurality of active patterns are spaced apart from each other in a first direction and in a second direction. The first direction and the second direction are substantially parallel to the upper surface of the substrate and substantially perpendicular to each other. The semiconductor device includes: a plurality of insulating patterns extending into respective portions of the respective first ends of a first active pattern among the plurality of active patterns and respective portions of the respective second ends of a second active pattern among the plurality of active patterns, wherein the first active pattern and the second active pattern among the plurality of active patterns are adjacent to each other in the first direction; a plurality of first pad patterns respectively on the respective first ends of the plurality of active patterns; a plurality of second pad patterns respectively on the respective second ends of the plurality of active patterns; a plurality of gate structures each extending in the first direction into the respective central portions of the plurality of active patterns, wherein the plurality of gate structures are spaced apart from each other in the second direction; a plurality of bit line structures extending in the second direction on the plurality of first pad patterns, wherein the plurality of bit line structures are spaced apart from each other in the first direction; a plurality of contact plug structures respectively on the plurality of second pad patterns; and a plurality of capacitors respectively on the plurality of contact plug structures.

[0008] According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device may include: an active pattern on a substrate, the active pattern including a central portion and a first end and a second end at opposite ends of the central portion; an insulating pattern extending into a part of the first end of the active pattern and a part of the second end of the active pattern; a first pad pattern and a second pad pattern respectively on the first end and the second end of the active pattern; a gate structure extending into the central portion of the active pattern; a bit line structure on the first pad pattern; a contact plug structure on the second pad pattern; and a capacitor on the contact plug structure. The insulating pattern is substantially coplanar with the uppermost surface of the substrate and the second pad pattern is substantially coplanar with the upper surface of the substrate.

[0009] In the semiconductor device according to the exemplary embodiment, the first pad pattern and the second pad pattern may be respectively on the first end and the second end of the active pattern. The bit line may be electrically connected to the first end of the active pattern through the first pad pattern, and the contact plug structure may be electrically connected to the second end of the active pattern through the second pad pattern. Compared with the case where the bit line and the contact plug structure are in direct contact with the first end and the second end of the active pattern respectively, the electrical connection between the bit line and the contact plug structure and the first end and the second end of the active pattern respectively may be improved. Description of the Drawings

[0010] Figures 1 to 3 is a plan view and a cross-sectional view showing a semiconductor device according to an exemplary embodiment.

[0011] Figures 4 to 35 is a plan view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0012] Figure 36 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment.

[0013] Figures 37 to 40 is a plan view and a cross-sectional view showing a method of manufacturing the semiconductor device referred to Figure 36 shown.

[0014] Figure 41 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment.

[0015] Figures 42 to 46 is a plan view and a cross-sectional view showing a method of manufacturing the semiconductor device referred to Figure 41 shown.

[0016] Figures 47 to 55 is a plan view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0017] Figures 56 to 66 is a plan view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0018] Figure 67 and Figure 68 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment.

[0019] Figure 69 and Figure 70 is a cross-sectional view showing a method of manufacturing the semiconductor device Figure 67 and Figure 68 shown.

[0020] Figure 71 and Figure 72 is a plan view and a cross-sectional view showing a semiconductor device according to an exemplary embodiment.

[0021] Figure 73 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment.

[0022] Figure 74 is a cross-sectional view showing a method of manufacturing the semiconductor device Figure 73 shown. DETAILED DESCRIPTION

[0023] Referring to the accompanying drawings, the above and other aspects and features of a semiconductor device, a method of manufacturing a semiconductor device, and an electronic system including the semiconductor device according to an exemplary embodiment will become readily understood from the following detailed description. It will be understood that although the terms "first," "second," and / or "third" may be used herein to describe various materials, levels (layers), regions, pads, electrodes, patterns, structures, or processes, the levels (layers), regions, pads, electrodes, patterns, structures, or processes should not be limited by these terms. These terms are only used to distinguish one material, level (layer), region, pad, electrode, pattern, structure, or process from another material, level (layer), region, pad, electrode, pattern, structure, or process. Thus, without departing from the teachings of the inventive concept, the first material, the first level (layer), the first region, the first pad, the first electrode, the first pattern, the first structure, or the first process discussed below may be referred to as the second material, the second level (layer), the second region, the second pad, the second electrode, the second pattern, the second structure, or the second process, or the third material, the third level (layer), the third region, the third pad, the third electrode, the third pattern, the third structure, or the third process.

[0024] Hereinafter, two directions among the horizontal directions that are substantially parallel to the upper surface of the substrate and that may be substantially orthogonal to each other and / or substantially intersect each other may be referred to as a first direction D1 and a second direction D2, respectively, and a direction among the horizontal directions that may have an acute angle with respect to the second direction D2 and an obtuse angle with respect to the first direction D1 may be referred to as a third direction D3. Additionally, a direction that is substantially perpendicular to the upper surface of the substrate may be referred to as a vertical direction. Each of the first through third directions D1, D2, and D3 and the vertical direction may represent not only the directions shown in the drawings but also the directions opposite to the shown directions.

[0025] Figures 1 to 3 is a plan view and a cross-sectional view showing a semiconductor device according to an exemplary embodiment. Specifically, Figure 1 is a plan view, Figure 2 including cross-sectional views taken along Figure 1 lines A-A' and B-B', and Figure 3 including cross-sectional views taken along Figure 1 lines C-C' and D-D'.

[0026] Referring to Figures 1 to 3 , the semiconductor device may include an active pattern 105, a first insulating pattern 112, a first pad pattern 123, a second pad pattern 125, a gate structure 170, a first bit line structure, a first contact plug 185, a contact plug structure, and a capacitor 430 on a substrate 100.

[0027] The semiconductor device may further include an isolation pattern 110, a first fence pattern 127, a second fence pattern 195, a buffer layer structure, a second molding layer 310, a second spacer 340, and an etch stop layer.

[0028] The substrate 100 may include silicon, germanium, silicon germanium, or III-V compounds (such as, GaP, GaAs, GaSb, etc.). In some embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0029] The active pattern 105 may be defined on the substrate 100, and the sidewalls of the active pattern 105 may be on, covered by, or stacked with the isolation pattern 110.

[0030] The active pattern 105 may include a central portion, a first end, and a second end. The central portion of the active pattern 105 may extend a specific length in the third direction D3. The first end and the second end may be respectively formed at opposite ends of the central portion of the active pattern 105 in the third direction D3. The first end and the second end may respectively extend a specific length away from the central portion in the second direction D2.

[0031] A plurality of active patterns 105 may be spaced apart from each other in the first direction D1 and the second direction D2 to define an active pattern array. The plurality of active patterns 105 arranged along the first direction D1 of the active pattern array may define an active pattern row. The plurality of active pattern rows may be spaced apart from each other in the second direction D2. The plurality of active patterns 105 arranged along the second direction D2 of the active pattern array may define an active pattern column. The plurality of active pattern columns may be spaced apart from each other in the first direction D1.

[0032] In an exemplary embodiment, the active patterns 105 of the active pattern row may be aligned with each other in the first direction D1. Specifically, the first ends of the active patterns 105 of the active pattern row may be arranged on a straight line extending along the first direction D1, and the second ends of the active patterns 105 of the active pattern row may be arranged on a straight line extending along the first direction D1.

[0033] In an exemplary embodiment, the active patterns 105 of the active pattern column may be aligned with each other in the second direction D2. Specifically, the first ends of the active patterns 105 of the active pattern column may be arranged on a straight line extending along the second direction D2, and the second ends of the active patterns 105 of the active pattern column may be arranged on a straight line extending along the second direction D2.

[0034] The first end of the active pattern 105 of the first active pattern row in the active pattern row may be disposed between the second ends of the active patterns 105 of the second active pattern row adjacent to each other in the first direction D1 in the active pattern row. The first active pattern row and the second active pattern row may be adjacent to each other in the second direction D2.

[0035] The active pattern 105 may include substantially the same material as the substrate 100, and the isolation pattern 110 may include an oxide (e.g., silicon oxide).

[0036] A plurality of first insulating patterns 112 may be spaced apart from each other in a first direction D1 and a second direction D2. A portion of the first insulating patterns 112 may extend through an upper portion of a first end of the first end portion of the active pattern 105 adjacent to the central portion of the active pattern 105 in the first direction D1, and the others of the first insulating patterns 112 may extend through an upper portion of a second end of the second end portion of the active pattern 105 adjacent to the central portion of the active pattern 105 in the first direction D1.

[0037] In some embodiments, the first insulating pattern 112 may have a shape of a line extending in the second direction D2 in a plan view, and the plurality of first insulating patterns 112 may be spaced apart from each other in the first direction D1. Specifically, the first insulating pattern 112 may extend through an upper portion of the central portion of the active pattern 105 of the active pattern column in the second direction D2. The first insulating pattern may also extend through an upper portion of a first end of the first end portion of the active pattern 105 adjacent to the central portion of the active pattern 105 in the first direction D1, and an upper portion of a second end of the second end portion of the active pattern 105 adjacent to the central portion of the active pattern 105 in the first direction D1.

[0038] The area of the upper surface of the first end portion of the active pattern 105 may be reduced by the upper surface of the first end through which the first insulating pattern 112 can pass. In addition, the area of the upper surface of the second end portion of the active pattern 105 may be reduced by the upper surface of the second end through which the first insulating pattern 112 can pass.

[0039] In an exemplary embodiment, the first insulating pattern 112 may include, for example, a low dielectric material (such as silicon oxide, silicon oxycarbide, etc.).

[0040] The first pad pattern 123 and the second pad pattern 125 may be formed on the first end portion and the second end portion of the active pattern 105, respectively. Accordingly, corresponding to the first end portion and the second end portion of the active pattern 105 alternately and repeatedly arranged in the first direction D1, the first pad pattern 123 and the second pad pattern 125 may also be alternately and repeatedly arranged in the first direction D1.

[0041] Referring to Figures 19 to 21 and Figures 1 to 3, the area of the upper surface of the first pad pattern 123 may be greater than the area of the upper surface of the first end portion of the active pattern 105 that the first pad pattern 123 can directly contact. For example, the area of the upper surface of the first pad pattern 123 may be greater than the area of the portion of the upper surface of the first end portion of the active pattern 105 that directly contacts the first pad pattern 123. The area of the upper surface of the second pad pattern 125 may be greater than the area of the upper surface of the second end portion of the active pattern 105 that the second pad pattern 125 can directly contact. For example, the area of the upper surface of the second pad pattern 125 may be greater than the area of the portion of the upper surface of the second end portion of the active pattern 105 that directly contacts the first pad pattern 125.

[0042] A plurality of first pad patterns 123 respectively disposed at the first end portions of the active patterns 105 in the active pattern row may define a first pad pattern row. In an exemplary embodiment, the plurality of first pad pattern rows may be spaced apart from each other in the second direction D2. A plurality of second pad patterns 125 respectively disposed at the second end portions of the active patterns 105 in the active pattern row may define a second pad pattern row. In an exemplary embodiment, the plurality of second pad pattern rows may be spaced apart from each other in the second direction D2. The first pad pattern row and the second pad pattern row may be alternately and repeatedly arranged in the second direction D2.

[0043] In an exemplary embodiment, the upper surface of the first pad pattern 123 may be lower than the upper surface of the second pad pattern 125.

[0044] In an exemplary embodiment, each of the first pad pattern 123 and the second pad pattern 125 may include silicon. Specifically, each of the first pad pattern 123 and the second pad pattern 125 may include polysilicon or amorphous silicon.

[0045] The first fence pattern 127 may be formed between the first pad pattern 123 and the second pad pattern 125 adjacent to each other in the first direction D1, and the first pad pattern 123 and the second pad pattern 125 may be spaced apart from each other. Accordingly, the plurality of first fence patterns 127 may be spaced apart from each other in the first direction D1 and the second direction D2.

[0046] In an exemplary embodiment, a part of the first fence pattern 127 may be stacked with the isolation pattern 110 between adjacent active pattern columns in the active pattern column in the vertical direction, and the other of the first fence patterns 127 may be stacked with the first insulating pattern 112 in the vertical direction.

[0047] In an exemplary embodiment, the lowermost surface of the first fence pattern 127 may be lower than the lowermost surface of each of the first pad pattern 123 and the second pad pattern 125.

[0048] In an exemplary embodiment, the first fence pattern 127 may include, for example, a low dielectric material (such as silicon oxide, silicon oxycarbide, etc.).

[0049] The gate structure 170 may extend through a central portion of the active pattern 105 and an upper portion of the isolation pattern 110 of the rows of active patterns in a first direction D1, and a plurality of gate structures 170 may be spaced apart from each other in a second direction D2. The gate structure 170 may include a first conductive pattern 140, a second conductive pattern 150, and a gate mask 160 sequentially stacked in a vertical direction, and may further include a gate insulating pattern 130 covering sidewalls of the first conductive pattern 140, the second conductive pattern 150, and the gate mask 160, and a lower surface of the first conductive pattern 140 or a gate insulating pattern 130 that is superposed on the sidewalls of the first conductive pattern 140, the second conductive pattern 150, and the gate mask 160 and the lower surface of the first conductive pattern 140.

[0050] The gate insulating pattern 130 may include, for example, an oxide (such as silicon oxide), the first conductive pattern 140 may include, for example, a metal, a metal nitride, a metal silicide, the second conductive pattern 150 may include, for example, polysilicon doped with an n-type impurity or a p-type impurity, and the gate mask 160 may include, for example, an insulating nitride (such as silicon nitride).

[0051] The first bit line structure may include a first bit line 290 and first spacers 240 at opposite sidewalls of the first bit line 290. The first bit line structure may extend in the second direction D2, and a plurality of first bit line structures may be spaced apart from each other in the first direction D1.

[0052] The first bit line 290 may be disposed on an upper surface of the first pad pattern 123 of the first column of pad patterns to extend in the second direction D2, and a plurality of first bit lines 290 may be spaced apart from each other in the first direction D1. Accordingly, the first bit line 290 may be superposed on a first end portion of the active pattern 105 in a vertical direction, and the first pad pattern 123 may be formed between the first bit line 290 and the first end portion of the active pattern 105.

[0053] The first bit line 290 may include a first ohmic contact pattern 260, a third conductive pattern 270, and a first bit line mask 280 sequentially stacked in a vertical direction. In an exemplary embodiment, a plurality of first ohmic contact patterns 260 may be respectively disposed on a plurality of first pad patterns 123 to be spaced apart from each other in the second direction D2.

[0054] The first ohmic contact pattern 260 may include, for example, a metal silicide, the third conductive pattern 270 may include, for example, a metal (such as molybdenum), and the first bit line mask 280 may include, for example, silicon oxide, silicon oxycarbide, etc.

[0055] In an exemplary embodiment, the first bit line 290 may extend through or into an upper portion of the first pad pattern 123. Accordingly, a lower surface of the first bit line 290 may be lower than an upper surface of the second pad pattern 125 and higher than an upper surface of a second end portion of the active pattern 105.

[0056] In an exemplary embodiment, the first bit line 290 may also extend through or into upper portions of the gate structure 170 adjacent to the first pad pattern 123 in the second direction D2 and upper portions of the first fence pattern 127 adjacent to the first pad pattern 123 in the first direction D1.

[0057] The first spacer 240 is shown as a single layer, but the concept of the present invention is not limited thereto. That is, the first spacer 240 may include a plurality of layers each including or comprising different materials.

[0058] In an exemplary embodiment, the first spacer 240 may include, for example, a low dielectric material such as silicon oxide, silicon oxycarbide, or the like.

[0059] Hereinafter, the first bit line 290 and the first spacer 240 on opposite sidewalls of the first bit line 290 in the first direction D1 may be referred to as a first bit line structure.

[0060] The first contact plug 185 may be formed on the second pad pattern 125. Accordingly, the first contact plug 185 may at least partially overlap with a second end portion of the active pattern 105 in a vertical direction, and the second pad pattern 125 may be formed between the first contact plug 185 and the second end portion of the active pattern 105.

[0061] The first contact plug 185 may contact an upper surface of the second pad pattern 125 on the second end portion of the active pattern 105. In an exemplary embodiment, a plurality of first contact plugs 185 may be spaced apart from each other in the second direction D2 between the first bit line structures, and a second fence pattern 195 may be formed between the first contact plugs 185 adjacent to each other in the second direction D2.

[0062] In an exemplary embodiment, the first contact plug 185 may include, for example, doped polysilicon, and the second fence pattern 195 may include, for example, insulating nitride such as silicon nitride.

[0063] The buffer layer structure may include a first buffer layer 210 and a second buffer layer 220 sequentially stacked in a vertical direction on the first contact plug 185 and the second barrier pattern 195. The first buffer layer 210 may include, for example, a low dielectric material (such as silicon oxide, silicon carbon oxide, etc.), and the second buffer layer 220 may include, for example, a low dielectric material (such as silicon nitride, silicon oxycarbonitride, etc.).

[0064] In an exemplary embodiment, the buffer layer structure may extend in a second direction D2 on the first contact plug 185 and the second barrier pattern 195 alternately and repeatedly arranged in the second direction D2, and a plurality of buffer layer structures may be spaced apart from each other in a first direction D1.

[0065] The second molding layer 310 may be formed on the buffer layer structure and the first bit line structure. The second molding layer 310 may include, for example, a low dielectric material (such as silicon oxide or silicon carbon oxide).

[0066] With Figures 1 to 3 referring together Figure 34 and Figure 35 , the contact plug structure may include a second contact plug 330, a second ohmic contact pattern 350, and a third contact plug 360 sequentially stacked in a vertical direction on the bottom of the third opening 320. The third opening 320 extends through the upper portion of the second molding layer 310, the first bit line mask 280, the first spacer 240, the buffer layer structure, and / or the first contact plug 185, or extends into the upper portion of the second molding layer 310, the first bit line mask 280, the first spacer 240, the buffer layer structure, and / or the first contact plug 185.

[0067] In an exemplary embodiment, a plurality of contact plug structures may be spaced apart from each other in each of the first direction D1 and the second direction D2, and may be arranged in a honeycomb pattern in a plan view. Each of the contact plug structures may have a shape such as a circle, an ellipse, a polygon, etc. in a plan view.

[0068] In an exemplary embodiment, the second contact plug 330 may include, for example, polysilicon doped with impurities, the second ohmic contact pattern 350 may include, for example, a metal silicide (such as titanium silicide, cobalt silicide, nickel silicide), and the third contact plug 360 may include, for example, a metal (such as tungsten).

[0069] The second spacer 340 may be formed between the second molding layer 310 and the third contact plug 360. The second spacer 340 may include, for example, a low dielectric material (such as silicon nitride, silicon oxycarbonitride).

[0070] The capacitor 430 may include a lower electrode 400, a dielectric layer 410, and an upper electrode 420 that are sequentially stacked, and the lower electrode 400 may contact the upper surface of the third contact plug 360. Each of the lower electrode 400 and the upper electrode 420 may include, for example, a metal, a metal nitride, a metal silicide, silicon germanium doped with impurities, etc., and the dielectric layer 410 may include, for example, a metal oxide having a high dielectric constant.

[0071] In the semiconductor device, the area of the upper surface of the first end of the active pattern 105 may be reduced by the area of the upper surface of the first end through which or into which the first insulating pattern 112 of the active pattern 105 may pass, and the area of the upper surface of the second end of the active pattern 105 may be reduced by the upper surface of the second end through which or into which the first insulating pattern 112 of the active pattern 105 may pass. Accordingly, the contact area between the first end of the active pattern 105 and the first bit line 290 and the contact area between the second end of the active pattern 105 and the first contact plug 185 may be reduced. Accordingly, the electrical characteristics of the semiconductor device may deteriorate.

[0072] However, in the semiconductor device according to the exemplary embodiment, the first pad pattern 123 may be disposed between the first end of the active pattern 105 and the first bit line 290, and the second pad pattern 125 may be disposed between the second end of the active pattern 105 and the first contact plug 185. The area of the upper surface of the first pad pattern 123 may be larger than the area of the upper surface of the first end of the active pattern 105, and thus, the first bit line 290 and the first pad pattern 123 may have a relatively large contact area. In addition, the area of the upper surface of the second pad pattern 125 may be larger than the area of the upper surface of the second end of the active pattern 105, and thus, the first contact plug 185 and the second pad pattern 125 may have a relatively large contact area. Accordingly, the deterioration of the electrical characteristics of the semiconductor device may be reduced or prevented.

[0073] Figures 4 to 35 are a plan view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0074] Specifically, Figure 4 、 Figure 6 、 Figure 8 、 Figure 10 、 Figure 12 、 Figure 15 、 Figure 17 、 Figure 19 、 Figure 22 、 Figure 25 、 Figure 28 、 Figure 31 and Figure 34 are plan views, Figure 16 and 18 are cross-sectional views taken along line A-A' of the corresponding plan views,Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 20 , Figure 23 , Figure 26 , Figure 29 , Figure 32 and Figure 35 include cross-sectional views taken along lines A-A' and B-B' of the corresponding plan view, and Figure 14 , Figure 21 , Figure 24 , Figure 27 , Figure 30 and Figure 33 include cross-sectional views taken along lines C-C' and D-D' of the corresponding plan view.

[0075] Referring to Figure 4 and Figure 5 , a hard mask layer 10 and a first mask layer can be sequentially formed on the substrate 100 in the vertical direction.

[0076] In an exemplary embodiment, the hard mask layer 10 may include a single layer or multiple layers each having a material different from each other. The hard mask layer 10 may include, for example, metal oxide, silicon oxide, silicon oxynitride, silicon nitride, etc. The first mask layer may include a material having a high etch selectivity with respect to the hard mask layer 10 (e.g., silicon, but not limited thereto).

[0077] A first patterning process may be performed on the first mask layer in a line shape extending in the second direction D2 to form a plurality of preliminary first masks 20a extending in the second direction D2. The preliminary first masks 20a may be spaced apart from each other in the first direction D1.

[0078] Referring to Figure 6 and Figure 7 , a second patterning process may be performed on the preliminary first masks 20a in a line shape extending in the third direction D3. Accordingly, the preliminary first masks 20a may be divided into a plurality of first masks 20 spaced apart from each other in the second direction D2.

[0079] In some embodiments, the second patterning process may be first performed on the preliminary first masks 20a in a line shape extending in the third direction D3, and then the first patterning process may be performed on the first mask layer in a line shape extending in the second direction D2 to form the first masks 20.

[0080] The first masks 20 may correspond to the central portions of the active patterns 105 to be formed later.

[0081] Referring to Figure 8 and Figure 9, a first molding layer 30 and a second mask layer may be sequentially formed on the hard mask layer 10 and the first mask 20 in the vertical direction.

[0082] In an exemplary embodiment, the first molding layer 30 may include, for example, a carbon-containing layer (such as a spin-on hard mask (SOH), silicon oxide, silicon oxynitride, silicon nitride, etc.). The second mask layer may include a material having a high etch selectivity with respect to the first molding layer 30 and the hard mask layer 10 (e.g., silicon, but not limited thereto).

[0083] A patterning process may be performed on the second mask layer to divide the second mask layer into a plurality of second masks 40. Each of the second masks 40 may be vertically stacked with an end portion of the first mask 20 in the third direction D3. Thus, the second masks may be spaced apart from each other in the first direction D1 and the second direction D2.

[0084] The second mask 40 may correspond to a first end portion or a second end portion of an active pattern 105 to be formed later.

[0085] In an exemplary embodiment, the second mask 40 may be formed by a third patterning process performed in a line shape extending in the first direction D1 and a fourth patterning process performed in a line shape extending in the second direction D2. The order of the third patterning process and the fourth patterning process is not limited.

[0086] The order of forming the first mask 20 and the second mask 40 is not limited. That is, the first mask 20 may be formed after the second mask 40 is formed.

[0087] Referring to Figure 10 and Figure 11 , the hard mask layer 10 may be patterned by using the first mask 20 and the second mask 40 as etch masks. The hard mask layer 10 may be divided into a plurality of hard masks 15 by an etching process. The hard masks 15 may be spaced apart from each other in the first direction D1 and the second direction D2.

[0088] Each of the hard masks 15 may include a central portion corresponding to the first mask 20 and first and second end portions each corresponding to the second mask 40. The central portion of the hard mask 15 may extend a specific length in the third direction D3. The first and second end portions of the hard mask 15 may be respectively formed at opposite ends of the central portion in the third direction D3. The first and second end portions of the hard mask 15 may respectively extend a specific length away from the central portion in the second direction D2.

[0089] The first mask 20, the second mask 40, and the first molding layer 30 may be removed.

[0090] Referring to Figures 12 to 14, an etching process using the hard mask 15 as an etching mask may be performed on the upper portion of the substrate 100 to form a first groove. The active pattern 105 may be defined by the first groove on the substrate 100. An isolation pattern 110 may be formed to fill the first groove.

[0091] The active pattern 105 may include a central portion, a first end portion, and a second end portion corresponding to the central portion, the first end portion, and the second end portion of the hard mask 15, respectively.

[0092] A plurality of active patterns 105 may be spaced apart from each other in a first direction D1 and a second direction D2, respectively, to define an active pattern array. The plurality of active patterns 105 arranged along the first direction D1 of the active pattern array may define an active pattern row. The plurality of active pattern rows may be spaced apart from each other in the second direction D2. The plurality of active patterns 105 arranged along the second direction D2 of the active pattern array may define an active pattern column. The plurality of active pattern columns may be spaced apart from each other in the first direction D1.

[0093] Referring to Figure 15 and Figure 16 , the central portion of the active pattern 105 of the active pattern column and the isolation pattern 110 adjacent to the central portion of the active pattern 105 of the active pattern row in the second direction D2 may be removed to form a second groove, and a first insulating pattern 112 may be formed in the second groove.

[0094] The second groove may be formed by partially removing the central portion of the active pattern 105 and the upper portions of the first end portion and the second end portion of the active pattern 105 adjacent to the central portion of the active pattern 105. Accordingly, the first insulating pattern 112 may not only partially extend through the central portion of the active pattern 105 or extend into the central portion of the active pattern 105, but also partially extend through the first end portion and the second end portion of the active pattern 105 adjacent to the central portion of the active pattern 105 or extend into the first end portion and the second end portion of the active pattern 105 adjacent to the central portion of the active pattern 105. Accordingly, in a plan view, the first insulating pattern 112 may be partially overlapped with the first end portion and the second end portion of the active pattern 105.

[0095] In an exemplary embodiment, the first insulating pattern 112 may extend in the second direction D2, and a plurality of first insulating patterns 112 may be spaced apart from each other in the first direction D1.

[0096] Referring to Figure 17 and Figure 18 , a cushion layer may be formed on the active pattern 105, the first insulating pattern 112, and the isolation pattern 110. In an exemplary embodiment, the cushion layer may be formed by a deposition process.

[0097] An etching process may be performed on the cushion layer to divide the cushion layer into a plurality of portions that all extend in the second direction D2 and are spaced apart from each other in the first direction D1.

[0098] Hereinafter, the portion of the cushion layer that overlaps with the first end of the active pattern 105 of the active pattern column may be referred to as the first cushion layer 122, and the portion of the cushion layer that overlaps with the second end of the active pattern 105 of the active pattern column may be referred to as the second cushion layer 124. The first cushion layer 122 and the second cushion layer 124 may be alternately and repeatedly arranged in the first direction D1.

[0099] The first fence layer 126 may be formed to a sufficient height on the first cushion layer 122, the second cushion layer 124, the active pattern 105, and the isolation pattern 110, and a planarization process may be performed until the upper surfaces of the first cushion layer 122 and the second cushion layer 124 are exposed. Accordingly, a plurality of first fence layers 126 that all extend in the second direction D2 may be spaced apart from each other in the first direction D1.

[0100] Refer to Figures 19 to 21 and the upper portions of the first cushion layer 122, the second cushion layer 124, the first fence layer 126, the first insulating pattern 112, the upper portion of the central portion of the active pattern 105, and the upper portion of the isolation pattern 110 adjacent to the central portion of the active pattern 105 in the first direction D1 may be removed to form a third groove.

[0101] The first cushion layer 122 may be divided into a plurality of first pad patterns 123 that are respectively disposed on the first ends of the active patterns 105 of the active pattern column and are spaced apart from each other in the second direction D2, the second cushion layer 124 may be divided into a plurality of second pad patterns 125 that are respectively disposed on the second ends of the active patterns 105 of the active pattern column and are spaced apart from each other in the second direction D2, and the first fence layer 126 may be divided into a plurality of first fence patterns 127 that are spaced apart from each other in the second direction D2.

[0102] The third groove may completely penetrate the first insulating pattern 112 formed on the central portion of the active pattern 105, such that the first insulating pattern 112 is divided in the second direction D2. However, the concept of the present invention is not limited thereto. That is, depending on the depth of the first insulating pattern 112 and the depth of the gate structure 170, the first insulating pattern 112 may not be completely penetrated and may remain on the central portion of the active pattern 105. Accordingly, in a plan view, the first insulating pattern 112 may have the shape of a line extending in the second direction D2.

[0103] The first pad patterns 123 that are respectively disposed on the first ends of the active patterns 105 of the active pattern column and are arranged in the second direction D2 may define a first pad pattern column. A plurality of first pad pattern columns may be spaced apart from each other in the first direction D1.

[0104] The second pad patterns 125, which are respectively disposed on the second ends of the active patterns 105 in the active pattern columns and are arranged in the second direction D2, may define a second pad pattern column. A plurality of second pad pattern columns may be spaced apart from each other in the first direction D1.

[0105] A gate insulating layer may be formed on the inner sidewall of the third groove. A first conductive layer may be formed on the gate insulating layer, and the upper portion of the first conductive layer may be removed to form a first conductive pattern 140. A second conductive layer may be formed on the first conductive pattern 140 and the gate insulating layer, and the upper portion of the second conductive layer may be removed to form a second conductive pattern 150. A gate mask layer may be formed on the second conductive pattern 150 and the gate insulating layer, and a planarization process may be performed on the gate mask layer and the gate insulating layer until the upper surfaces of the first pad pattern 123, the second pad pattern 125, and the upper surface of the first fence pattern 127 are exposed, to respectively form a gate mask 160 and a gate insulating pattern 130.

[0106] The gate insulating pattern 130, the first conductive pattern 140, the second conductive pattern 150, and the gate mask 160 within the third groove may together form a gate structure 170.

[0107] In an exemplary embodiment, the gate structure 170 may extend in the first direction D1 through the upper portion of the central part of the active patterns 105 in the active pattern rows, and a plurality of gate structures 170 may be spaced apart from each other in the second direction D2.

[0108] Referring to Figures 22 to 24 , a first contact plug layer 180 may be formed on the first pad pattern 123, the second pad pattern 125, the first fence pattern 127, and the gate structure 170.

[0109] The first contact plug layer 180 may be etched to form a first opening exposing the upper surface of the gate structure 170. Accordingly, the first contact plug layer 180 may be divided into a plurality of portions extending in the first direction D1 and spaced apart from each other in the second direction D2.

[0110] The second fence layer 190 may be formed to a sufficient height within the first opening, and a planarization process may be performed on the upper portion of the second fence layer 190 until the upper surface of the first contact plug layer 180 is exposed. Accordingly, the second fence layer 190 may be divided into such a plurality of portions: each extending in the first direction D1 between the first contact plug layers 180 adjacent to each other in the second direction D2 on the gate structure 170 and spaced apart from each other in the second direction D2 by the first contact plug layer 180.

[0111] Referring to Figures 25 to 27, a first buffer layer 210 and a second buffer layer 220 may be sequentially formed on the first contact plug layer 180 and the second fence layer 190 in a vertical direction. The first buffer layer 210 and the second buffer layer 220 may together form a buffer layer structure.

[0112] An etching process may be performed to form such a second opening 230 that extends through the buffer layer structure, the first contact plug layer 180, the second fence layer 190, the upper part of the gate structure 170, the upper part of the first pad pattern 123, and the upper part of the first fence pattern 127, or extends into the buffer layer structure, the first contact plug layer 180, the second fence layer 190, the upper part of the gate structure 170, the upper part of the first pad pattern 123, and the upper part of the first fence pattern 127. In an exemplary embodiment, the second opening 230 may extend in a second direction D2, and a plurality of second openings 230 may be spaced apart from each other in a first direction D1. Accordingly, the upper surface of the first pad pattern 123 in the first pad pattern column and the upper surface of the gate structure 170 adjacent to the upper surface of the first pad pattern 123 in the first pad pattern column in the second direction D2 may be exposed through the second opening 230.

[0113] In an exemplary embodiment, the second opening 230 may further expose the upper surface of the first fence pattern 127 adjacent to the first pad pattern 123 in the first direction D1.

[0114] Through the etching process, the first contact plug layer 180 may be divided into a plurality of first contact plugs 185 spaced apart from each other in the first direction D1, and the second fence layer 190 may be divided into a plurality of second fence patterns 195 spaced apart from each other in the first direction D1.

[0115] In an exemplary embodiment, the first contact plugs 185 may be respectively formed on the second pad patterns 125 and be spaced apart from each other in the first direction D1 and the second direction D2. The second fence patterns 195 may be respectively formed between the second pad patterns 125 adjacent to each other in the second direction D2, and the second fence patterns 195 may be spaced apart from each other in the first direction D1 and the second direction D2.

[0116] Referring to Figures 28 to 30 , a first spacer layer may be conformally formed, for example, on the bottom and sidewalls of the second opening 230 and the second buffer layer 220, and a part of the first spacer layer on the bottom of the second opening 230 may be removed by performing an anisotropic etching process on the first spacer layer. Accordingly, the upper surface of the first pad pattern 123 in the first pad pattern column and the upper surface of the gate structure 170 adjacent to the upper surface of the first pad pattern 123 in the first pad pattern column in the second direction D2 may be exposed again. The first spacer layer may be transformed into a first spacer 240 on the sidewall of the second opening 230 through the etching process.

[0117] Meanwhile, withFigures 28 to 30 Refer to together Figure 17 and Figure 18 , the first pad pattern 123 obtained from the cushion layer formed by the deposition process can be removed through the second opening 230. Accordingly, the upper surface of the first end portion of the active pattern 105 can be exposed, and an epitaxial growth process using the exposed upper surface of the first end portion of the active pattern 105 as a seed can be performed to form the first pad pattern 123 again.

[0118] A first metal layer can be formed on the upper surface of the first pad pattern 123 exposed by the second opening 230, the inner sidewall of the first spacer 240, and the upper surface of the second buffer layer 220, and a heat treatment process can be performed such that the first metal layer and the first pad pattern 123 can react with each other to form a first ohmic contact pattern 260. Then, the unreacted portion of the first metal layer can be removed.

[0119] A third conductive layer can be formed on the first ohmic contact pattern 260 and the first spacer 240, and the upper portion of the third conductive layer can be removed to form a third conductive pattern 270. A first bit line mask layer can be formed on the third conductive pattern 270 and the first spacer 240, and the first bit line mask layer can be planarized until the upper surface of the second buffer layer 220 is exposed to form a first bit line mask 280.

[0120] The first ohmic contact pattern 260, the third conductive pattern 270, and the first bit line mask 280 can together form a first bit line 290.

[0121] Refer to Figures 31 to 33 , a second molding layer 310 can be formed on the second buffer layer 220 and the first bit line 290, and a third opening 320 extending through the second molding layer 310 or extending into the second molding layer 310 can be formed to at least partially expose the upper surface of the first contact plug 185.

[0122] A second contact plug layer can be formed to a sufficient height to fill the third opening 320, and a planarization process can be performed on the upper portion of the second contact plug layer until the upper surface of the second molding layer 310 is exposed. Accordingly, the second contact plug layer can be divided into a plurality of second contact plugs 330.

[0123] Refer to Figure 34 and Figure 35 , the upper portion of the second contact plug 330 can be removed. Accordingly, the upper portion of the third opening 320 can be formed again. A second spacer layer can be formed on the upper surface of the second contact plug 330 exposed by the third opening 320, the inner sidewall, and the upper surface of the second molding layer 310, and an anisotropic etching process can be performed on the second spacer layer to form a second spacer 340. The upper surface of the second contact plug 330 can be exposed again.

[0124] A second ohmic contact pattern 350 may be formed on the exposed upper surface of the second contact plug 330. In an exemplary embodiment, the second ohmic contact pattern 350 may be formed by forming a second metal layer on the exposed upper surface of the second contact plug 330 and the second molding layer 310, performing a heat treatment on the second metal layer, and removing unreacted portions of the second metal layer.

[0125] A third contact plug 360 may be formed on the second ohmic contact pattern 350 to fill the third opening 320. In an exemplary embodiment, the third contact plug 360 may be formed by forming a third contact plug layer to a sufficient height to fill the third opening 320 on the second ohmic contact pattern 350 and performing a planarization process on the upper portion of the third contact layer.

[0126] The second contact plug 330, the second ohmic contact pattern 350, and the third contact plug 360 may together form a contact plug structure.

[0127] In an exemplary embodiment, a plurality of contact plug structures may be spaced apart from each other in a first direction D1 and a second direction D2 and may be arranged in a honeycomb pattern in a plan view. In the plan view, each of the contact plug structures may have a shape such as a circle, an ellipse, a polygon, or the like.

[0128] Referring again to Figures 1 to 3 , a third molding layer may be formed on the second molding layer 310 and the third contact plug 360.

[0129] An etching process may be performed on the third molding layer to form a fourth opening exposing the upper surface of the third contact plug 360.

[0130] As the contact plug structures are arranged in a honeycomb pattern in the plan view, a plurality of fourth openings exposing the upper surfaces of the contact plug structures may also be arranged in a honeycomb pattern in the plan view.

[0131] A lower electrode 400 having a columnar shape may be formed in the fourth opening, the third molding layer may be removed, and a dielectric layer 410 and an upper electrode 420 may be sequentially formed on the lower electrode 400 and the second molding layer 310. The sequentially stacked lower electrode 400, dielectric layer 410, and upper electrode 420 may together form a capacitor 430.

[0132] In some embodiments, the lower electrode 400 may be formed to have a cylindrical shape within the fourth opening.

[0133] Thereafter, the manufacturing of the semiconductor device may be completed by additionally forming upper wirings on the capacitor 430.

[0134] As described above, the first pad pattern 123 and the second pad pattern 125 may additionally be formed on the first end portion and the second end portion of the active pattern 105 such that the electrical connection between the first end portion and the first bit line 290 and the electrical connection between the second end portion of the active pattern 105 and the first contact plug 185 may be improved.

[0135] In addition, by the process of forming the gate structure 170 extending in the first direction D1, the first interlayer dielectric 122 and the second interlayer dielectric 124 may be divided in the second direction D2 to form the first pad pattern 123 and the second pad pattern 125. Accordingly, the electrical characteristics of the semiconductor may be improved without adding excessive processes.

[0136] Figure 36 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment. Except for the shapes of the first pad pattern 123, the second pad pattern 125, and the first barrier pattern 127, the semiconductor device may be substantially the same as or similar to Figures 1 to 3 the semiconductor device of

[0137] Refer to Figure 36 and, different from the semiconductor device shown in reference to Figures 1 to 3 , the lowermost surface of each of the first pad pattern 123 and the second pad pattern 125 may be lower than the lowermost surface of the first barrier pattern 127.

[0138] Figures 37 to 40 is a plan view and a cross-sectional view showing a method of forming the semiconductor device shown in reference to Figure 36 . Specifically, Figure 37 and Figure 39 are plan views, and Figure 38 and Figure 40 are cross-sectional views taken along line A-A' of the corresponding plan view. The method may include processes substantially the same as or similar to the processes shown in reference to Figures 1 to 35 , and thus repeated explanations thereof are omitted herein.

[0139] Refer to Figure 37 and Figure 38 , and processes substantially the same as or similar to the processes shown in reference to Figures 4 to 16 may be performed. Thereafter, different from the processes shown in reference to Figure 17 and Figure 18 , a first barrier layer 126 may be formed on the active pattern 105 and the isolation pattern 110.

[0140] An etching process may be performed on the first fence layer 126 to form a fifth opening and a sixth opening. The fifth opening exposes the upper surface of the first end of the active pattern 105 of the active pattern column and the upper surface of the isolation pattern 110 adjacent to the first end of the active pattern 105 of the active pattern column in the second direction D2. The sixth opening exposes the upper surface of the second end of the active pattern 105 of the active pattern column and the upper surface of the isolation pattern 110 adjacent to the second end of the active pattern 105 of the active pattern column in the second direction D2.

[0141] During the etching process, the fifth opening and the sixth opening may partially extend through the upper portions of the first end and the second end of the active pattern 105, respectively.

[0142] In an exemplary embodiment, the fifth opening may expose a portion of the upper surface of the first insulating pattern 112 adjacent to the first end of the active pattern 105 in the first direction D1, and the sixth opening may expose a portion of the upper surface of the first insulating pattern 112 adjacent to the second end of the active pattern 105 in the first direction D1.

[0143] In an exemplary embodiment, the fifth opening may extend in the second direction D2, and a plurality of fifth openings may be spaced apart from each other in the first direction D1. The sixth opening may extend in the second direction D2, and a plurality of sixth openings may be spaced apart from each other in the first direction D1. The fifth opening and the sixth opening may be formed alternately and repeatedly along the first direction D1.

[0144] The first fence layer 126 may be divided into a plurality of portions that all extend in the second direction D2 and are spaced apart from each other in the first direction D1.

[0145] Refer to Figure 39 and Figure 40 , for example, a deposition process may be performed to form a cushion layer to a sufficient height to fill the fifth opening and the sixth opening, and a planarization process may be performed on the upper portion of the cushion layer until the upper surface of the first fence layer 126 is exposed. Thus, the first cushion layer 122 may be formed in the fifth opening, and the second cushion layer 124 may be formed in the sixth opening.

[0146] The first cushion layer 122 may extend in the second direction D2 to contact the upper surface of the first end of the active pattern 105 of the active pattern column, and the second cushion layer 124 may extend in the second direction D2 to contact the upper surface of the second end of the active pattern 105 of the active pattern column.

[0147] The first cushion layer 122 and the second cushion layer 124 may also be arranged alternately and repeatedly in the direction D1 corresponding to the fifth opening and the sixth opening.

[0148] In some embodiments, an epitaxial growth process may be performed using the upper surfaces of the first end portion and the second end portion of the active pattern 105 exposed by the fifth opening and the sixth opening as seeds to form the first cushion layer 122 and the second cushion layer 124. Accordingly, a plurality of first cushion layers 122 may be respectively formed on the first end portion of the active pattern 105 exposed by the fifth opening such that the first cushion layers 122 may be spaced apart from each other in the second direction D2, and a plurality of second cushion layers 124 may be respectively formed on the second end portion of the active pattern 105 exposed by the sixth opening such that the second cushion layers 124 may be spaced apart from each other in the second direction D2.

[0149] Thereafter, the manufacturing of the semiconductor device may be completed by performing a process substantially the same as or similar to the process Figures 19 to 35 and Figures 1 to 3 shown.

[0150] Figure 41 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment. Except for the shapes and arrangements of the first insulating pattern 112, the first pad pattern 123, the second pad pattern 125, and the first fence pattern 127, the semiconductor device may be substantially the same as or similar to the Figures 1 to 3 semiconductor device, and thus, repeated explanations are omitted herein.

[0151] Referring to Figure 41 , the uppermost surface of the first insulating pattern 112 may be substantially coplanar with the upper surfaces of the second pad pattern 125 and the first fence pattern 127.

[0152] The first pad pattern 123 and the second pad pattern 125 facing each other in the first direction D1 and the portion of the first insulating pattern 112 between the first pad pattern 123 and the second pad pattern 125 may be defined as a first repeating unit. A plurality of first repeating units may be spaced apart from each other in the first direction D1 and the second direction D2. The first fence pattern 127 may be formed between the first repeating units adjacent to each other in the first direction D1.

[0153] In the exemplary embodiment, the first fence pattern 127 may overlap with the portion between the active pattern columns adjacent to each other in the first direction D1 of the isolation pattern 110 in the vertical direction.

[0154] Figures 42 to 46 is a plan view and a cross-sectional view showing a method of forming a semiconductor device according to an exemplary embodiment. Specifically, Figure 42 and Figure 45 are plan views, and Figure 43 , Figure 44 and Figure 46 are cross-sectional views taken along the line A-A' of the corresponding plan view. The method may include the process substantially the same as or similar to the process Figures 1 to 35The processes shown are substantially the same or similar processes, and thus, their repeated explanations are omitted herein.

[0155] Referring to Figure 42 and Figure 43 , a process substantially the same or similar to the process shown in the reference to Figures 4 to 16 can be performed. Thereafter, different from the processes shown in the reference to Figure 17 and Figure 18 , a fourth molding layer 500 can be formed on the active pattern 105 and the isolation pattern 110.

[0156] Thereafter, an etching process can be performed on the fourth molding layer 500 to form a seventh opening that extends through the central portion of the active pattern 105 and the upper portion of the isolation pattern 110 adjacent to the central portion of the active pattern 105 in the second direction D2, or extends into the central portion of the active pattern 105 and the upper portion of the isolation pattern 110 adjacent to the central portion of the active pattern 105 in the second direction D2.

[0157] The fourth molding layer 500 can be divided into a plurality of portions that all extend in the second direction D2 and are spaced apart from each other in the first direction D1 by an etching process.

[0158] A first insulating pattern 112 can be formed in the seventh opening. The first insulating pattern 112 can be formed by forming a first insulating layer to a sufficient height within the seventh opening and performing a planarization process on the upper portion of the first insulating layer until the upper surface of the fourth molding layer 500 is exposed.

[0159] In an exemplary embodiment, the first insulating pattern 112 can extend through the central portion of the active pattern 105 of the active pattern column and the upper portion of the isolation pattern 110 adjacent to the central portion of the active pattern 105 of the active pattern column in the second direction D2, and the plurality of first insulating patterns 112 can be spaced apart from each other in the first direction D1. The first insulating pattern 112 can also extend through the portions of the first end and the second end of the active pattern 105 adjacent to the central portion of the active pattern 105.

[0160] Referring to Figure 44 , the fourth molding layer 500 can be removed. Accordingly, the upper surfaces of the first end and the second end of the active pattern 105 and the upper surfaces of the isolation pattern 110 adjacent to the upper surfaces of the first end and the second end of the active pattern 105 in the second direction D2 can be exposed.

[0161] A cushion layer can be conformally formed, for example, on the upper surface and the opposing sidewalls of the first insulating pattern 112, the upper surfaces of the first end and the second end of the active pattern 105, and the upper surfaces of the isolation pattern 110.

[0162] Referring toFigure 45 and Figure 46 An anisotropic etching process can be performed on the cushion layer. Accordingly, a first cushion layer 122 and a second cushion layer 124 can be formed on opposite sidewalls of the first insulating pattern 112, respectively.

[0163] The first cushion layer 122 can extend in a second direction D2 along an upper surface of a first end portion of the active pattern 105 of the active pattern column, and the second cushion layer 124 can extend in the second direction D2 along an upper surface of a second end portion of the active pattern 105 of the active pattern column.

[0164] Hereinafter, the first insulating pattern 112 and the first cushion layer 122 and the second cushion layer 124 on opposite sidewalls of the first insulating pattern 112, respectively, may be referred to as an extension structure. In an exemplary embodiment, the extension structure can extend in the second direction D2, and a plurality of extension structures can be spaced apart from each other in the first direction D1.

[0165] A first barrier layer 126 can be formed in the seventh opening. The first barrier layer 126 can be formed by, for example, forming the first barrier layer 126 to a sufficient height to fill the seventh opening and performing a planarization process on an upper portion of the first barrier layer 126 until an upper surface of the extension structure is exposed.

[0166] In an exemplary embodiment, the first barrier layer 126 can extend in the second direction D2 between extension structures adjacent to each other in the second direction D2, and thus, a plurality of first barrier layers 126 can be spaced apart from each other in the first direction D1.

[0167] Thereafter, the manufacturing of the semiconductor device can be completed by performing a process substantially the same as or similar to the process shown with reference to Figures 19 to 35 and Figures 1 to 3 FIGs.

[0168] Figures 47 to 55 FIGs. Figure 47 、 Figure 50 and Figure 53 are plan views, Figure 48 、 Figure 51 and Figure 54 include cross-sectional views taken along lines A-A' and B-B' of the corresponding plan views, and Figure 49 、 Figure 52 and Figure 55 include cross-sectional views taken along lines C-C' and D-D' of the corresponding plan views.

[0169] Except for the processes of forming the first contact plug 185, the second barrier pattern 195, and the first bit line 290 shown with reference to Figures 22 to 30 FIGs., the method can include the same processes as those shown with reference to Figures 1 to 35The processes shown are basically the same or similar processes, so their repeated explanations are omitted here.

[0170] Referring to Figures 47 to 49 , after performing a process that is basically the same or similar to the process shown in reference Figures 4 to 21 , a first contact plug layer 180 and a buffer layer structure can be sequentially formed on the first pad pattern 123, the second pad pattern 125, and the first fence pattern 127 in the vertical direction. The buffer layer structure can include a first buffer layer 210 and a second buffer layer 220 that are sequentially stacked in the vertical direction.

[0171] An etching process can be performed on the buffer layer structure and the first contact plug layer 180 to form a second opening 230 that exposes the upper surface of the first end of the active pattern 105 of the active pattern column.

[0172] The first contact plug layer 180 can be divided into a plurality of portions that all extend in the second direction D2 and are spaced apart from each other in the first direction D1 by an etching process.

[0173] Referring to Figures 50 to 52 , a first spacer 240 can be formed on the sidewall of the second opening 230. Thereafter, a first bit line 290 including a first ohmic contact pattern 260, a third conductive pattern 270, and a first bit line mask 280 that are sequentially stacked on the bottom of the second opening 230 can be formed.

[0174] Hereinafter, the first bit line 290 and the first spacers 240 formed on the opposite sidewalls of the first bit line 290 may be collectively referred to as the first bit line structure.

[0175] Referring to Figures 53 to 55 , an etching process can be performed to remove the portions of the first contact plug layer 180 and the buffer layer structure that are vertically stacked with the gate structure 170 to form an eighth opening that exposes the upper surface of the gate structure.

[0176] By an etching process, a plurality of eighth openings spaced apart from each other in the second direction D2 can be formed between the first bit line structures adjacent to each other in the first direction D1. Accordingly, the first contact plug layer 180 can be divided into a plurality of first contact plugs 185 spaced apart from each other in the second direction D2.

[0177] A second fence pattern 195 can be formed in the eighth opening. The second fence pattern 195 can be formed, for example, by forming the second fence layer 190 to a sufficient height to fill the eighth opening and performing a planarization process on the upper portion of the second fence layer 190 until the upper surfaces of the second buffer layer 220, the first spacer 240, and the first bit line 290 are exposed.

[0178] Thereafter, by performing the same as that in reference Figures 31 to 35and Figures 1 to 3 fabricate a semiconductor device by a process that is substantially the same as or similar to the process shown.

[0179] Figures 56 to 66 are a plan view and a cross-sectional view showing a method of forming a semiconductor device according to an exemplary embodiment. Specifically, Figure 56 、 Figure 59 and Figure 64 are plan views, Figure 57 、 Figure 60 、 Figure 62 and Figure 65 include cross-sectional views taken along lines A-A' and B-B' of the corresponding plan views, and Figure 58 、 Figure 61 、 Figure 63 and Figure 66 include cross-sectional views taken along lines C-C' and D-D' of the corresponding plan views.

[0180] Except for the processes of forming the first contact plug 185, the second spacer pattern 195, and the second bit line 550 formed in place of the first bit line 290 as shown with reference to Figures 22 to 30 , the method may include processes that are substantially the same as or similar to the processes shown with reference to Figures 1 to 35 , and thus repeated explanations thereof are omitted herein.

[0181] With reference to Figures 56 to 58 , after performing processes that are substantially the same as or similar to the processes shown with reference to Figures 4 to 21 , a buffer layer structure may be formed on the first pad pattern 123, the second pad pattern 125, and the first spacer pattern 127. The buffer layer structure may include a first buffer layer 210 and a second buffer layer 220 stacked in sequence in a vertical direction.

[0182] An etching process may be performed to form a second opening 230 that extends through the buffer layer structure, the gate structure 170, the first pad pattern 123, and the first spacer pattern 127 or extends into the buffer layer structure, the gate structure 170, the first pad pattern 123, and the first spacer pattern 127. The second opening 230 may expose the upper surface of the first pad pattern 123 of the first pad pattern column and the gate structure 170 adjacent to the upper surface of the first pad pattern 123 of the first pad pattern column in the second direction D2.

[0183] With reference to Figures 59 to 61 , a fourth conductive layer, a barrier layer, a fifth conductive layer, and a second bit line mask layer may be sequentially formed on the second buffer layer 220 and the first pad pattern 123, the first spacer pattern 127, and the gate structure 170 exposed by the second opening 230. Thereafter, the second bit line mask layer, the fifth conductive layer, the barrier layer, and the fourth conductive layer may be sequentially etched.

[0184] The fourth conductive pattern 510, the barrier pattern 520, the fifth conductive pattern 530, and the second bit line mask 540 that are sequentially stacked may be formed on the bottom of the second opening through an etching process.

[0185] The fourth conductive pattern 510, the barrier pattern 520, the fifth conductive pattern 530, and the second bit line mask 540 that are sequentially stacked may together form the second bit line 550. In an exemplary embodiment, the second bit line 550 may extend on the substrate 100 in the second direction D2, and multiple second bit lines 550 may be spaced apart from each other in the first direction D1.

[0186] Referring to Figure 62 and Figure 63 , a third spacer layer may be formed on the substrate 100 on which the second bit line 550 is to be formed, and a second insulating layer and a third insulating layer may be sequentially formed on the third spacer layer. The second insulating layer and the third insulating layer may fill the remaining portion of the second opening 230.

[0187] The second insulating layer and the third insulating layer may be etched through an etching process. Portions of the second insulating layer and the third insulating layer other than their portions in the second opening 230 may be removed. Accordingly, most of the surface of the third spacer layer (i.e., all portions of the surface of the third spacer layer other than its portion in the second opening 230) may be exposed, and the second insulating layer and the third insulating layer remaining in the second opening 230 may respectively form a second insulating pattern 610 and a third insulating pattern 620.

[0188] A fourth spacer layer may be formed on the exposed surface of the third spacer layer in the second opening 230 and on the second insulating pattern 610 and the third insulating pattern 620. The fourth spacer layer may be anisotropically etched to form a fourth spacer 630 that covers the sidewalls of the second bit line 550 or that is stacked with the sidewalls of the second bit line 550 on the surface of the third spacer layer and on the second insulating pattern 610 and the third insulating pattern 620.

[0189] An etching process using the second bit line mask 540 and the fourth spacer 630 as an etching mask may be performed to form a ninth opening 640 that exposes the upper surface of the second pad pattern 125. In an exemplary embodiment, the ninth opening 640 may extend in the second direction D2, and multiple ninth openings 640 may be spaced apart from each other in the first direction D1. Accordingly, the ninth opening 640 may expose the upper surface of the second pad pattern 125 of the second pad pattern column and the upper surface of the gate structure 170 adjacent to the upper surface of the second pad pattern 125 of the second pad pattern column in the second direction D2.

[0190] In an exemplary embodiment, the upper surface of the first fence pattern 127 adjacent to the second pad pattern 125 in the first direction D1 may also be exposed by the ninth opening 640.

[0191] Through an etching process, a part of the third spacer layer on the upper surface of the second bit line mask 540 and the upper surface of the second buffer layer 220 can be removed, thereby forming a third spacer 600 that covers the sidewall of the second bit line 550 or is stacked with the sidewall of the second bit line 550.

[0192] Referring to Figures 64 to 66 , a fifth spacer layer can be formed on the upper surface of the second bit line mask 540, the outer sidewall of the fourth spacer 630, the upper surface portions of the second insulating pattern 610 and the third insulating pattern 620, and the upper surface of the second pad pattern 125 exposed by the ninth opening. The fifth spacer layer can be anisotropically etched to form a fifth spacer 650 that covers the sidewall of the second bit line 550 or is stacked with the sidewall of the second bit line 550.

[0193] The third to fifth spacers 600, 630, and 650 sequentially stacked on the sidewall of the second bit line 550 in the horizontal direction can be referred to as a spacer structure 660.

[0194] Referring to Figures 64 to 66 , a first contact plug layer 180 can be formed to fill the ninth opening 640 to a sufficient height, and the upper portion of the first contact plug layer 180 can be planarized until the upper surface of the second bit line mask 540 is exposed. Thus, the first contact plug layer 180 can extend in the second direction D2, and a plurality of first contact plug layers 180 can be spaced apart from each other in the first direction D1 by the second bit line 550.

[0195] An etching process can be performed on the first contact plug layer 180 to form a tenth opening that exposes the upper surface of the gate structure 170. Thus, the first contact plug layer 180 can be transformed into a plurality of first contact plugs 185 spaced apart from each other in the second direction D2. The first contact plugs 185 can be respectively formed on the second pad pattern 125. In an exemplary embodiment, the first contact plugs 185 can be spaced apart from each other in the first direction D1 and the second direction D2.

[0196] The second barrier layer 190 can be formed to a sufficient height in the tenth opening, and the upper portion of the second barrier layer can be planarized until the upper surface of the first contact plug 185 is exposed. Thus, a second barrier pattern 195 can be formed in each of the tenth openings.

[0197] In an exemplary embodiment, the second barrier pattern 195 can overlap a part of the gate structure 170 between the first contact plugs 185 adjacent to each other in the second direction D2 in the vertical direction. In an exemplary embodiment, the second barrier patterns 195 can be spaced apart from each other in the first direction D1 and the second direction D2.

[0198] Figure 67 andFigure 68 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment. Except for not including the first pad pattern 123, the first contact plug 185, and the second barrier pattern 195, the semiconductor device may be substantially the same or similar to the Figures 1 to 3 semiconductor device, and thus, repeated explanations are omitted herein.

[0199] Referring to Figure 67 and Figure 68 , the first bit line structure may extend through or into the upper portions of the first end of the active pattern 105 of the active pattern column, the first insulating pattern 112, and the isolation pattern 110. Accordingly, the lower surface of the first bit line structure may be lower than the upper surface of the second pad pattern 125.

[0200] The second contact plug 330 may be formed in a third opening 320 that extends through the first bit line mask 280, the first spacer 240, the buffer layer structure, the first barrier pattern 127, and / or the second pad pattern 125 or extends into the first bit line mask 280, the first spacer 240, the buffer layer structure, the first barrier pattern 127, and / or the second pad pattern 125. Accordingly, the second contact plug 330 may directly contact the second pad pattern 125.

[0201] Figure 69 and Figure 70 are cross-sectional views showing a method of forming the Figure 67 and Figure 68 shown semiconductor device. Specifically, Figure 69 includes cross-sectional views taken along lines A-A' and B-B' of the corresponding plan view, and Figure 70 includes cross-sectional views taken along lines C-C' and D-D' of the corresponding plan view.

[0202] Except for not performing the process shown with reference to Figures 22 to 24 , the method may include processes substantially the same or similar to the processes shown with reference to Figures 1 to 35 , and thus, repeated explanations thereof are omitted herein.

[0203] Referring to Figure 69 and Figure 70 , different from the process shown with reference to Figures 25 to 27 , a buffer layer structure may be formed on the first pad pattern 123, the second pad pattern 125, the first barrier pattern 127, and the gate structure 170. The buffer layer structure may include a first buffer layer 210 and a second buffer layer 220 sequentially stacked in a vertical direction.

[0204] By performing an etching process, a second opening 230 that extends through the buffer layer structure, the first pad pattern 123, the first fence pattern 127, and the first insulating pattern 112 or extends into the buffer layer structure, the first pad pattern 123, the first fence pattern 127, and the first insulating pattern 112 may be formed to expose a first end of the active pattern 105 of the active pattern column.

[0205] During the etching process, the first pad pattern 123 may be removed, and an upper surface of the first end of the active pattern 105 may be formed to be lower than an upper surface of the second end of the active pattern 105.

[0206] Thereafter, the manufacturing of the semiconductor device may be completed by performing a process that is substantially the same as or similar to the process shown with reference to Figures 28 to 35 and Figures 1 to 3 .

[0207] Figure 71 and Figure 72 are a plan view and a cross-sectional view showing a semiconductor device according to an exemplary embodiment. Except for the arrangement of the contact plug structure and further including a fourth contact plug 370 and a fourth insulating pattern 380, the semiconductor device may be substantially the same as or similar to the semiconductor device of Figure 67 and Figure 68 , and thus, repeated explanations are omitted herein.

[0208] In addition, in Figure 71 , the capacitor 430 is not shown in order to avoid complexity.

[0209] Referring to Figure 71 and Figure 72 , the contact plug structure may be arranged in a grid pattern, for example, in the plan view.

[0210] The fourth contact plug 370 may be formed on the contact plug structure. The fourth contact plug 370 may be arranged in a honeycomb pattern, for example, in the plan view. In the exemplary embodiment, the fourth contact plug 370 may include, for example, a metal pattern and a barrier pattern. The metal pattern includes, for example, a metal, and the barrier pattern covers or overlaps with the lower surface of the metal pattern and includes, for example, a metal nitride.

[0211] The fourth insulating pattern 380 may partially or completely fill the space between the fourth contact plugs 370. The fourth insulating pattern 380 may include, for example, a low dielectric material (such as silicon oxide, silicon oxycarbide, silicon nitride, silicon oxynitride, etc.).

[0212] Figure 73is a cross-sectional view showing a semiconductor device according to an exemplary embodiment. Except for the shape of the lower electrode 400 and excluding the second molding layer 310, the second contact plug 330, the second spacer 340, the second ohmic contact pattern 350, and the third contact plug 360, the semiconductor device may be substantially the same as or similar to the semiconductor device of Figures 1 to 3 , and thus, repeated explanations are omitted herein.

[0213] Referring to Figure 73 , the lower electrode 400 may extend through the buffer layer structure, the upper part of the first spacer 240, and the upper part of the first bit line mask 280, or extend into the buffer layer structure, the upper part of the first spacer 240, and the upper part of the first bit line mask 280 to directly contact the first contact plug 185.

[0214] Figure 74 is a cross-sectional view showing a method of forming the semiconductor device shown in reference to Figure 73 Specifically, Figure 74 is a cross-sectional view taken along line A-A' of the corresponding plan view.

[0215] Except that the process shown in reference to Figures 31 to 35 is not performed, the method may include processes substantially the same as or similar to the processes shown in reference to Figures 1 to 35 , and thus, repeated explanations are omitted herein.

[0216] Referring to Figure 74 , processes substantially the same as or similar to the processes described in reference to Figures 4 to 30 may be performed. Thereafter, different from the process shown in reference to Figures 1 to 3 , a fifth molding layer 700 may be formed on the second buffer layer 220, the first bit line 290, and the first spacer 240.

[0217] An eleventh opening 710 may be formed to extend through the first buffer layer 210 and the second buffer layer 220, and the upper part of the first spacer 240, the first bit line mask 280, and the first contact plug 185, or extend into the first buffer layer 210 and the second buffer layer 220, and the upper part of the first spacer 240, the first bit line mask 280, and the first contact plug 185, and the lower electrode 400 may be formed within the eleventh opening 710. Thus, the lower electrode 400 may directly contact the first contact plug 185.

[0218] Although the exemplary embodiments have been specifically shown and described, those of ordinary skill in the art will understand that changes in form and details may be made therein without departing from the spirit and scope of the claims.

Claims

1. A semiconductor device, comprising: An active pattern on a substrate, the active pattern including a central portion and a first end portion and a second end portion at opposite ends of the central portion; An insulating pattern extending into a part of the first end portion of the active pattern and extending into a part of the second end portion of the active pattern; A first pad pattern and a second pad pattern respectively on the first end portion and the second end portion of the active pattern; A gate structure extending into the central portion of the active pattern; A bit line structure on the first pad pattern; A contact plug structure on the second pad pattern; And A capacitor on the contact plug structure, wherein, the area of the upper surface of the first pad pattern is larger than the area of the part of the upper surface of the first end portion of the active pattern that directly contacts the first pad pattern, and the area of the upper surface of the second pad pattern is larger than the area of the part of the upper surface of the second end portion of the active pattern that directly contacts the second pad pattern.

2. The semiconductor device according to claim 1, wherein, The gate structure extends in a first direction, and the bit line structure extends in a second direction, wherein, the first direction and the second direction are parallel to the upper surface of the substrate and perpendicular to each other, wherein, the central portion of the active pattern extends in a third direction, and the first end portion and the second end portion of the active pattern respectively extend away from the central portion of the active pattern in the second direction, and wherein, the third direction has an acute angle with respect to the second direction and an obtuse angle with respect to the first direction.

3. The semiconductor device according to claim 2, wherein, The part of the insulating pattern of the first end portion of the active pattern that extends into it is the first end in the first direction of the first end portion of the active pattern, and the part of the insulating pattern of the second end portion of the active pattern that extends into it is the second end in the first direction of the second end portion of the active pattern.

4. The semiconductor device according to claim 1, wherein, Each of the first pad pattern and the second pad pattern includes silicon.

5. The semiconductor device according to claim 1, wherein, A plurality of active patterns including the active pattern are spaced apart from each other in the first direction and the second direction, wherein, the first direction and the second direction are parallel to the upper surface of the substrate and perpendicular to each other, and wherein, the first active pattern arranged in the first direction among the plurality of active patterns is included in an active pattern row, and the second active pattern arranged in the second direction among the plurality of active patterns is included in an active pattern column.

6. The semiconductor device according to claim 5, wherein, The corresponding first end portions of the first active pattern of the active pattern row are arranged on a straight line extending in the first direction, and the corresponding second end portions of the first active pattern of the active pattern row are arranged on a straight line extending in the first direction, and wherein, the corresponding first end portions of the second active pattern of the active pattern column are arranged on a straight line extending in the second direction, and the corresponding second end portions of the second active pattern of the active pattern column are arranged on a straight line extending in the second direction.

7. The semiconductor device according to claim 6, wherein, A plurality of active pattern rows including the active pattern row are spaced apart from each other in the second direction, and the corresponding first end portions of the first active pattern of the first active pattern row among the plurality of active pattern rows and the corresponding second end portions of the first active pattern of the second active pattern row among the plurality of active pattern rows are alternately and repeatedly arranged in the first direction, and wherein, the first active pattern row and the second active pattern row are adjacent to each other in the second direction.

8. A semiconductor device, comprising: A plurality of active patterns on a substrate, the plurality of active patterns including respective central portions, respective first ends, and respective second ends, the respective first ends and respective second ends being at opposite ends of the respective central portions, wherein the plurality of active patterns are spaced apart from each other in a first direction and in a second direction, and wherein the first direction and the second direction are parallel to the upper surface of the substrate and perpendicular to each other; A plurality of insulating patterns extending into respective portions of the respective first ends of a first active pattern among the plurality of active patterns and respective portions of the respective second ends of a second active pattern among the plurality of active patterns, wherein the first active pattern and the second active pattern are adjacent to each other in the first direction; A plurality of first pad patterns respectively on the respective first ends of the plurality of active patterns; A plurality of second pad patterns respectively on the respective second ends of the plurality of active patterns; A plurality of gate structures each extending in the first direction into the respective central portions of the plurality of active patterns, wherein the plurality of gate structures are spaced apart from each other in the second direction; A plurality of bit line structures extending in the second direction on the plurality of first pad patterns, wherein the plurality of bit line structures are spaced apart from each other in the first direction; A plurality of contact plug structures respectively on the plurality of second pad patterns; and A plurality of capacitors respectively on the plurality of contact plug structures.

9. The semiconductor device according to claim 8, wherein, The respective central portions of the plurality of active patterns extend in a third direction, the third direction having an acute angle with respect to the second direction and an obtuse angle with respect to the first direction.

10. The semiconductor device according to claim 8, wherein, Each of the plurality of first pad patterns and the plurality of second pad patterns includes silicon.

11. The semiconductor device according to claim 8, wherein, The active patterns arranged in the first direction are included in active pattern rows, and a plurality of active pattern rows including the active pattern rows are spaced apart from each other in the second direction, and wherein the respective first ends of the active patterns of a first active pattern row among the plurality of active pattern rows and the respective second ends of the active patterns of a second active pattern row among the plurality of active pattern rows are alternately and repeatedly arranged in the first direction, and wherein the first active pattern row and the second active pattern row are adjacent to each other in the second direction.

12. The semiconductor device according to claim 11, wherein, The plurality of first pad patterns and the plurality of second pad patterns are alternately and repeatedly arranged in the first direction corresponding to the respective first ends and respective second ends of the plurality of active patterns.

13. The semiconductor device according to claim 12, further comprising: Fence patterns between a first pad pattern and a second pad pattern adjacent to each other in the first direction.

14. The semiconductor device according to claim 13, wherein, The lower surfaces of the first pad pattern and the second pad pattern are closer to the substrate than the lower surface of the fence pattern.

15. The semiconductor device according to claim 13, wherein, The lower surfaces of the first pad pattern and the second pad pattern are farther from the substrate than the lower surface of the fence pattern.

16. The semiconductor device according to any one of claims 8 to 15, wherein, Each of the plurality of first pad patterns and the plurality of second pad patterns is stacked with a corresponding one of the plurality of insulating patterns in a vertical direction perpendicular to the upper surface of the substrate.

17. A semiconductor device, comprising: An active pattern on a substrate, the active pattern including a central portion and a first end and a second end at opposite ends of the central portion; An insulating pattern extending into a portion of a first end of the active pattern and into a portion of a second end of the active pattern; A first pad pattern and a second pad pattern on the first end and the second end of the active pattern, respectively; A gate structure extending into a central portion of the active pattern; A bit line structure on the first pad pattern; A contact plug structure on the second pad pattern; And A capacitor on the contact plug structure, wherein the insulating pattern is coplanar with the uppermost surface of the substrate and the second pad pattern is coplanar with the upper surface of the substrate.

18. The semiconductor device according to claim 17, wherein, The gate structure extends in a first direction and the bit line structure extends in a second direction, wherein the first direction and the second direction are parallel to the upper surface of the substrate and perpendicular to each other, and wherein the central portion of the active pattern extends in a third direction, and the first end and the second end of the active pattern extend away from the central portion of the active pattern in the second direction, and wherein the third direction has an acute angle with respect to the second direction and an obtuse angle with respect to the first direction.

19. The semiconductor device according to claim 18, wherein, The portion into which the insulating pattern of the first end of the active pattern extends is the first end of the first end of the active pattern in the first direction, and the portion into which the insulating pattern of the second end of the active pattern extends is the second end of the second end of the active pattern in the first direction.

20. The semiconductor device according to any one of claims 17 to 19, wherein, Each of the first pad pattern and the second pad pattern includes silicon.

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