Semiconductor structure comprising polysilicon as a under layer of a

Abstract

The invention provides a semiconductor structure, comprising a substrate comprising a plurality of fin structures; a dielectric layer disposed over the adjacent fin structure, where an upper surface of the dielectric layer is a substantially flat surface; a bit line structure disposed over the substrate and between adjacent fin structures, where the bit line structure includes a polysilicon layer contacting the upper surface of the dielectric layer; and a spacer structure surrounding the bit line structure, where the spacer structure contacts the upper surface of the dielectric layer. The invention also provides a preparation method of the semiconductor structure.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 202410439656.7, filed on April 12, 2024, with the invention title "Semiconductor Structure Comprising Polysilicon as the Underlying Layer of a Bit Line Structure and Method of Manufacturing the Same". Application No. 202410439656.7 claims the priority and benefits of U.S. Provisional Application No. 18 / 413,376, filed on January 16, 2024, the content of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a method of manufacturing a semiconductor structure. In particular, it relates to an improved patterning result of a bit line structure. Background Art

[0003] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and performing patterning on the various material layers using lithography to form circuit components and devices on the semiconductor substrate. As the semiconductor industry advances to advanced technology process nodes, with the pursuit of greater device density, higher performance, and lower cost, challenges in precisely controlling device dimensions have emerged.

[0004] The above "Background Art" description only provides background information and does not admit that the above "Background Art" description discloses the subject matter of the present disclosure, does not constitute prior art of the present disclosure, and any description of the above "Background Art" should not be taken as any part of this case. Summary of the Invention

[0005] An embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate comprising a plurality of fin structures; a dielectric layer disposed above adjacent fin structures, wherein an upper surface of the dielectric layer is a substantially flat surface; a bit line structure disposed above the substrate and between adjacent fin structures, wherein the bit line structure includes a polysilicon layer contacting the upper surface of the dielectric layer; and a spacer structure surrounding the bit line structure, wherein the spacer structure contacts the upper surface of the dielectric layer.

[0006] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The manufacturing method includes multiple steps. Provide a substrate, wherein the substrate includes a fin structure. A dielectric layer is formed above the substrate, wherein an upper surface of the dielectric layer is substantially flat. A polysilicon layer is formed above the substrate and the dielectric layer. A bit line contact is formed on a top of the fin structure, wherein the bit line contact penetrates the polysilicon layer. A patterned mask is formed above the bit line contact and the polysilicon layer. Pattern the bit line contact and the polysilicon layer, wherein a side wall of the bit line contact is substantially a straight side wall, and after patterning the bit line contact and the polysilicon layer, the upper surface of the dielectric layer remains substantially flat.

[0007] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The manufacturing method includes multiple steps. Provide a substrate, wherein the substrate includes a plurality of fin structures located in an array region of the substrate. An oxide layer is formed above the substrate and covers tops of the fin structures. A plurality of word line structures are formed to be alternately arranged with the plurality of fin structures, wherein an upper surface of the oxide layer is substantially aligned with an upper surface of the plurality of word line structures. A polysilicon layer is formed above the substrate, the plurality of word line structures, the plurality of fin structures, and the oxide layer. A plurality of bit line contacts are formed above the plurality of fin structures and penetrate the polysilicon layer. A patterned layer is formed above the polysilicon layer. Pattern the polysilicon layer using the patterned layer as a mask, thereby forming a patterned polysilicon layer, wherein a side wall of the patterned polysilicon layer is substantially straight.

[0008] The technical features and advantages of the present disclosure have been outlined quite extensively above, so that a better understanding of the detailed description of the present disclosure below can be obtained. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those of ordinary skill in the art to which the present disclosure pertains should understand that the concepts and specific embodiments disclosed below can be quite easily used as a basis for modifying or designing other structures or processes to achieve the same purpose as the present disclosure. Those of ordinary skill in the art to which the present disclosure pertains should also understand that such equivalent structures cannot depart from the spirit and scope of the present disclosure defined by the appended claims. Description of the Drawings

[0009] A more complete understanding of the present disclosure can be obtained by referring to the detailed description and the claims. The present disclosure should also be understood as being associated with the element numbers of the drawings, and the element numbers of the drawings represent similar elements throughout the description.

[0010] Figure 1 is a flowchart schematically illustrating a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0011] Figure 2 is a process schematic diagram, illustrating a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0012] Figure 3 is a 3D schematic diagram, illustrating an intermediate stage of forming a semiconductor structure according to some embodiments of the present disclosure.

[0013] Figures 4 to 36 is a cross-sectional schematic diagram, illustrating an intermediate stage of forming a semiconductor structure according to some embodiments of the present disclosure along Figure 3 the cutting line A-A' shown in Figure 37 or the cutting line B-B' shown in

[0014] Figure 37 is a top-view schematic diagram, illustrating an intermediate stage of forming a semiconductor structure according to some embodiments of the present disclosure.

[0015] Figures 38 to 45 is a cross-sectional schematic diagram, illustrating an intermediate stage of forming a semiconductor structure according to some embodiments of the present disclosure along Figure 37 the cutting line C-C' shown in

[0016] Figure 46 is a cross-sectional schematic diagram, illustrating a semiconductor structure according to some embodiments of the present disclosure along Figure 37 the cutting line C-C' shown in

[0017] Among them, the reference numerals are explained as follows:

[0018] 10: Semiconductor structure

[0019] 11: Substrate

[0020] 12: Silicon material

[0021] 13: Dielectric material

[0022] 14: Dielectric layer

[0023] 20: WL structure

[0024] 21: Multilayer structure

[0025] 22: First layer

[0026] 23: Second layer

[0027] 24: Third layer

[0028] 25: Fourth layer

[0029] 27: Spacer structure

[0030] 28: Dielectric layer

[0031] 31: Polysilicon layer

[0032] 32: BL structure

[0033] 33: Cover layer

[0034] 34: Multi - layer mask structure

[0035] 35: Contact material layer

[0036] 36: BL structure

[0037] 37: Mask stack structure (multi - layer structure)

[0038] 39: Spacer structure

[0039] 41: Spacer structure

[0040] 42: Opening

[0041] 43: Opening

[0042] 44: Opening

[0043] 45: Groove

[0044] 46: Metal contact

[0045] 50: Word line structure

[0046] 50A: Upper surface

[0047] 51: Dielectric layer

[0048] 52: Conductive material

[0049] 53: Dielectric layer

[0050] 54: Barrier layer

[0051] 55: Step

[0052] 56: Step

[0053] 57: Step

[0054] 58: Step

[0055] 59: Step

[0056] 111: Upper surface

[0057] 121: Silicon part (fin structure)

[0058] 122: Silicon part

[0059] 123: Silicon part

[0060] 131: Dielectric part

[0061] 132: Dielectric part

[0062] 133: Dielectric layer

[0063] 141: Dielectric layer

[0064] 141A: Upper surface

[0065] 142: Dielectric layer

[0066] 143: Dielectric layer

[0067] 144: Patterned dielectric layer

[0068] 221: Patterned first layer

[0069] 231: First sub - layer

[0070] 232: Second sub - layer

[0071] 233: Patterned second layer

[0072] 241: Patterned third layer

[0073] 261: Photoresist layer (patterned mask layer)

[0074] 262: Photoresist layer

[0075] 263: Photoresist layer

[0076] 264: Photoresist layer

[0077] 265: Photoresist layer

[0078] 266: Photoresist layer

[0079] 267: Mask layer

[0080] 268: Patterned mask layer

[0081] 281: Patterned dielectric layer

[0082] 311: Doped portion

[0083] 312: Doped portion

[0084] 313: Undoped portion

[0085] 313A: Upper surface

[0086] 314: Undoped portion

[0087] 315: Section

[0088] 317: Distance

[0089] 321: Layer

[0090] 321': Section

[0091] 322: Layer

[0092] 322': Section

[0093] 323: Layer

[0094] 323': Section

[0095] 324: Linear layer

[0096] 324': Section

[0097] 325: Hard layer

[0098] 325': Section

[0099] 325': Patterned mask layer

[0100] 326: Patterned layer

[0101] 332: Remaining cover layer

[0102] 335: Opening

[0103] 341: First layer

[0104] 342: Second layer

[0105] 343: Third layer

[0106] 344: Opening

[0107] 351: BL contact

[0108] 351A: Upper surface

[0109] 352: BL contact

[0110] 371: Layer

[0111] 371': Section

[0112] 372: Layer

[0113] 373: Layer

[0114] 374: Layer

[0115] 376: Spacer sub-layer

[0116] 377: Spacer sub-structure

[0117] 378: Photoresist layer

[0118] 381: Spacer sub-layer

[0119] 382: Spacer sub-layer

[0120] 383: Compensation layer

[0121] 391: Inner nitride layer

[0122] 392: Oxide layer

[0123] 393: Outer nitride layer

[0124] 411: Inner nitride layer

[0125] 412: Oxide layer

[0126] 413: Outer nitride layer

[0127] 521: First contact layer

[0128] 522: Second contact layer

[0129] 525: Designed upper surface

[0130] 526: Distance

[0131] 527: Section line

[0132] 531: Dielectric part

[0133] 541: Spacer layer

[0134] 551: Step

[0135] 552: Step

[0136] A - A': Section line

[0137] B - B': Section line

[0138] B32: Lower surface

[0139] B33: Lower surface

[0140] B391: Lower surface

[0141] C - C': Section line

[0142] H59: Height

[0143] R1: Array region

[0144] R2: Peripheral region

[0145] S1: Preparation method

[0146] S2: Preparation method

[0147] S11: Step

[0148] S12: Step

[0149] S13: Step

[0150] S14: Step

[0151] S15: Step

[0152] S16: Step

[0153] S21: Step

[0154] S22: Step

[0155] S23: Step

[0156] S24: Step

[0157] S25: Step

[0158] S26: Step

[0159] S27: Step

[0160] S32: Side wall

[0161] S33: Side wall

[0162] S315: Side wall

[0163] S321: Side wall

[0164] S322: Side wall

[0165] S323: Side wall

[0166] T352: Upper surface

[0167] Y: Direction Detailed implementation manners

[0168] The following describes specific examples of components and configurations to simplify the embodiments of the present disclosure. Of course, these embodiments are only for illustration and are not intended to limit the scope of the present disclosure. For example, when it is described that the first component is formed on the second component, it may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components are formed between the first and second components so that the first and second components are not in direct contact. Additionally, the embodiments of the present disclosure may repeat reference numerals and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specifically stated in the text, they do not themselves represent a specific relationship between various embodiments and / or the configurations discussed.

[0169] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. On the contrary, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present disclosure, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section.

[0170] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0171] As the semiconductor industry has advanced to advanced technology process nodes in pursuit of higher device density, it has achieved the ability to provide advanced precision in lithography. To further reduce the device size, the size of the devices and the distance between the devices must be proportionally reduced. However, as the device size and the distance between the devices are reduced, challenges in the precise control of the size and the distance arise. For example, if one sidewall of a bit line structure cannot be precisely controlled to be straight, a bonding pad or a contact formed between the bit line structures may be inadvertently altered.

[0172] Figure 1 is a process flow diagram illustrating a method S1 for fabricating a semiconductor structure according to some embodiments of the present disclosure. The fabrication method S1 includes a plurality of steps (S11, S12, S13, S14, S15, and S16), and the description and the drawings are not to be construed as limiting the order of the steps. In step S11, a substrate is provided, wherein the substrate includes a fin structure. In step S12, a dielectric layer is formed over the substrate, wherein an upper surface of the dielectric layer is substantially flat. In step S13, a polysilicon layer is formed over the substrate and the dielectric layer. In step S14, a bit line contact is formed on a top of the fin structure, wherein the bit line contact penetrates the polysilicon layer. In step S15, a patterned mask is formed over the bit line contact and the polysilicon layer. In step S16, the bit line contact and the polysilicon layer are patterned, wherein one sidewall of the bit line contact is substantially a straight sidewall, and after patterning the bit line contact and the polysilicon layer, the upper surface of the dielectric layer remains substantially flat. It should be understood that the steps of the fabrication method S1 can be reconfigured or otherwise modified within the scope of various aspects. Additional processes can be provided before, during, and after the fabrication method S1, and only some other processes are simply described herein. Therefore, other embodiments are possible within the scope of the various aspects described herein.

[0173] Figure 2It is a process schematic diagram, illustrating the manufacturing method S2 of a semiconductor structure according to some embodiments of the present disclosure. The manufacturing method S2 includes multiple steps (S21, S22, S23, S24, S25, S26, and S27), and the description and the drawings are not regarded as a limitation on the order of the steps. In step S21, a substrate is provided, wherein the substrate includes multiple fin structures in an array region of the substrate. In step S22, an oxide layer is formed above the substrate and covers the tops of the fin structures. In step S23, multiple word line structures are formed to be alternately arranged with the multiple fin structures, wherein an upper surface of the oxide layer is substantially aligned with an upper surface of the multiple word line structures. In step S24, a polysilicon layer is formed above the substrate, the multiple word line structures, the multiple fin structures, and the oxide layer. In step S25, multiple bit line contacts are formed above the multiple fin structures, and the multiple bit line contacts penetrate the polysilicon layer. In step S26, a patterned layer is formed above the polysilicon layer. In step S27, the patterned layer is used as a mask to pattern the polysilicon layer, thereby forming a patterned polysilicon layer, wherein a sidewall of the patterned polysilicon layer is substantially straight. It should be noted that the steps of the manufacturing method S2 can be reconfigured or otherwise modified within the scope of various aspects. Additional processes can be provided before, during, and after the manufacturing method S2, and only some other processes can be simply described herein. Therefore, other embodiments are possible within the scope of various aspects described herein.

[0174] The manufacturing method S1 and the manufacturing method S2 belong to the same concept of the present disclosure. To further illustrate the details of the manufacturing method S1 and the manufacturing method S2 and the concept of the present disclosure, the manufacturing method S1 and the manufacturing method S2 are comprehensively described in combination with the embodiments of the present disclosure.

[0175] Figures 3 to 46 It is a schematic diagram, illustrating different manufacturing stages of the manufacturing method S1 and / or the manufacturing method S2 configured for manufacturing the semiconductor structure 10 according to some embodiments of the present disclosure. Figures 3 to 46 The stages shown are also Figure 1 or Figure 2 schematically shown in the process flow of. In the subsequent discussion, the manufacturing stages shown in Figure 1 and Figure 2 are discussed with reference to the process steps in Figures 3 to 46 .

[0176] Please refer to Figure 3 and Figure 4 , Figure 3 is a 3D schematic diagram of the stage of the manufacturing method S1 and / or the manufacturing method S2 of the embodiment of the present disclosure, Figure 4 is along the present disclosure Figure 3Schematic cross-sectional view along the A-A' section line. In step S11 and / or step S21, a substrate 11 is provided, received, or formed.

[0177] In some embodiments, the substrate 11 may have a multi-layer structure, or the substrate 11 may include a multi-layer compound semiconductor structure. In some embodiments, the substrate 11 includes semiconductor elements, electronic components, electronic elements, or combinations thereof. In some embodiments, the substrate 11 includes transistors or functional units of transistors. In some embodiments, the substrate 11 includes active elements, passive elements, and / or conductive elements. The active elements may include a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a logic die (e.g., a system on chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), a microcontroller, etc.), a radio frequency (RF) die, a sensor die, a microelectromechanical systems (MEMS) die, a signal processing chip (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), or other active elements. Each active element may include multiple transistors. The transistors may include planar transistors, multi-gate transistors, gate-all-around field-effect transistors (GAAFETs), fin field-effect transistors (FinFETs), vertical transistors, nanosheet transistors, nanowire transistors, or combinations thereof. The passive elements may include capacitors, resistors, inductors, fuses, or other passive elements. The conductive elements may include metal lines, metal islands, conductive vias, contacts, or other conductive elements.

[0178] The active elements, passive elements, and / or conductive elements as described above may be formed in and / or on a semiconductor substrate. The semiconductor substrate may be a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The semiconductor substrate may include an elemental semiconductor containing silicon or germanium in a single-crystalline form, a polycrystalline form, or an amorphous form; a compound semiconductor material including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or combinations thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy having a graded Si:Ge profile, where the Si and Ge compositions change from one ratio at one location of the graded SiGe profile to another ratio at another location. In another embodiment, the SiGe alloy is formed on a silicon substrate. In some embodiments, the SiGe alloy may be mechanically strained by another material in contact with the SiGe alloy.

[0179] For simplicity, Figure 3 and Figure 4 the substrate 11 shown may be the topmost portion of a multi-layer structure of the substrate 11. The substrate 11 may include an array region R1 and a peripheral region R2 surrounding the array region R1. In some embodiments, active elements or transistors are mainly formed in the array region R1, while the peripheral region R2 is used for circuit wiring and may include passive elements. In some embodiments, the substrate 11 includes a silicon material 12 and a dielectric material 13. The dielectric material 13 may include a plurality of dielectric portions 131 in the array region R1. The dielectric portions 131 serve as multiple isolations in the silicon material 12. In some embodiments, the dielectric portions 131 may have a column-like structure and may be inserted into the silicon material 12 to define a plurality of column-like silicon portions 121 that are alternately arranged with the plurality of dielectric portions 131 in the array region R1. The column-like silicon portions 121 may be referred to as fin structures 121.

[0180] The silicon material 12 may further include one or more silicon portions 122, disposed in the peripheral region R2 adjacent to the array region R1, for separating the elements in the array region R1 and the peripheral region R2. The silicon material 12 may further include one or more silicon portions 123 (as Figure 3 shown), disposed in the peripheral region R2 away from the array region R1, for the purpose of forming peripheral circuits or elements. The dielectric material 13 may further include one or more dielectric portions 132 in the peripheral region R2. In some embodiments, a dielectric layer 133 is optionally embedded in the dielectric portions 132.

[0181] Memory cells or elements may be formed in the array region R1 of the substrate 11 (not shown in the figure). For illustrative purposes, the figure schematically shows the portion of the substrate 11 located above the memory cells or memory elements, and in subsequent processing, Figure 3 and Figure 4 a word line (WL) structure and a bit line (BL) structure are formed in the topmost portion of the substrate 11 shown. In some embodiments, from a top view perspective, each of the dielectric portions 131 and the silicon portions 121 extends along the Y direction in the array region R1. In some embodiments, a plurality of WL structures extending along the Y direction are subsequently formed in the array region R1 to electrically connect to the memory cells or memory elements.

[0182] In step S12 or S22, an interlayer dielectric layer 141 may be formed above an upper surface 111 of a substrate 11. In some embodiments, the interlayer dielectric layer 141 is conformal to the upper surface 111 of the substrate 11. In some embodiments, the interlayer dielectric layer 141 is formed in both the array region R1 and the peripheral region R2. The interlayer dielectric layer 141 may have a substantially flat upper surface 141A. In some embodiments, the upper surface 141A is a flat surface extending along the X-Y plane. In some embodiments, the interlayer dielectric layer 141 includes an oxide, such as silicon oxide. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), or any other suitable process is used to form the interlayer dielectric layer 141. In some embodiments, the thickness of the interlayer dielectric layer 141 is in the range of 2 to 10 nanometers (nm). In some embodiments, the thickness of the interlayer dielectric layer 141 is about 5 nm.

[0183] Please refer to Figure 5 , Figure 5 FIG. A-A' taken along the Figure 3 center line of the preparation method S1 and / or the preparation method S2 stage of the embodiments of the present disclosure. Another interlayer dielectric layer 142 is formed above the interlayer dielectric layer 141. In some embodiments, the interlayer dielectric layer 142 includes an oxide, such as silicon oxide. In some embodiments, CVD, PVD, or any other suitable process is used to form the interlayer dielectric layer 142. The interlayer dielectric layer 142 may be conformal to the interlayer dielectric layer 141. In some embodiments, the interlayer dielectric layer 142 has a substantially flat upper surface. In some embodiments, the thickness of the interlayer dielectric layer 142 is in the range of 10 to 20 nm. In some embodiments, the thickness of the interlayer dielectric layer 142 is about 15 nm.

[0184] A dielectric layer 143 may be selectively formed above the interlayer dielectric layer 142. The dielectric layer 143 may be conformal to the interlayer dielectric layer 142. In some embodiments, the dielectric layer 143 has a substantially flat upper surface. In some embodiments, the dielectric layer 143 includes a nitride, such as silicon nitride. The purpose of the dielectric layer 143 is to prevent the peeling of a carbon layer (e.g., Figure 6 22 in

[0185] Please refer toFigure 6 , Figure 6 is a schematic cross-sectional view along the Figure 3 center line A-A' in the first stage of the preparation method S1 and / or the preparation method S2 according to the embodiments of the present disclosure. After step S12 and / or step S22, a multi-layer structure 21 is formed above the substrate 11 and the dielectric layer 14.

[0186] The multi-layer structure 21 may be a hard mask structure and may include a plurality of layers stacked on top of each other. In some embodiments, the multi-layer structure 21 includes a first layer 22, a second layer 23, a third layer 24, and a fourth layer 25. In some embodiments, the first layer 22, the second layer 23, the third layer 24, and the fourth layer 25 are sequentially formed above the dielectric layer 14.

[0187] In some embodiments, the first layer 22 is disposed on the dielectric layer 14. In some embodiments, the first layer 22 includes carbon. In some embodiments, the fabrication technique of the first layer 22 includes CVD, PVD, or any other suitable process. In some embodiments, the second layer 23 is disposed above the first layer 22. In some embodiments, the second layer 23 is an anti-reflection coating (ARC). The second layer 23 may include magnesium fluoride, silicon nitride, silicon dioxide, titanium dioxide, aluminum oxide, other suitable materials, or a combination thereof. In some embodiments, the fabrication technique of the second layer 23 may include a plasma-enhanced CVD (PECVD) process.

[0188] The second layer 23 may include a first sub-layer 231 and a second sub-layer 232. In some embodiments, the first sub-layer 231 is an oxide-rich layer, and the second sub-layer 232 is a silicon-rich layer. In some embodiments, a thickness of the first sub-layer 231 is greater than a thickness of the second sub-layer 232.

[0189] The third layer 24 and the fourth layer 25 may be respectively similar to the first layer 22 and the first sub-layer 231. In some embodiments, the third layer 24 includes carbon. In some embodiments, the third layer 24 is disposed above the second layer 23. In some embodiments, the fourth layer 25 is an ARC layer. In some embodiments, the fourth layer 25 is a single-layer structure. In some embodiments, the fourth layer 25 is an oxide-rich layer. In some embodiments, a thickness of the first layer 22 is greater than a thickness of the third layer 24. In some embodiments, a thickness of the fourth layer 25 is substantially equal to a thickness of the first sub-layer 231 of the second layer 23.

[0190] The formation and materials of the third layer 24 and the fourth layer 25 can be similar to those of the first layer 22 and the first sub-layer 231 respectively, and will not be described repeatedly herein. In some embodiments, the deposition of each of the first layer 22, the second layer 23, the third layer 24, and the fourth layer 25 can be performed in-situ to save processing time and reduce the possibility of contamination. As used herein, the term "in-situ" is used to refer to a process in which the substrate 11 being processed is not exposed to an external ambient (e.g., the outside of the processing system) environment.

[0191] The multi-layer structure 21 serves as a hard mask to define a pattern of the WL structure to be formed in the substrate 11. In some embodiments, the fourth layer 25 is the topmost layer of the multi-layer structure 21 and is formed before the photoresist layer 261 is formed. In some embodiments, the fourth layer 25 is formed between the third layer 24 and the photoresist layer 261 to eliminate problems related to light reflection during the exposure of the photoresist layer 261. After the multi-layer structure 21 is formed, Figure 6 the photoresist layer 261 is formed and patterned as shown. In some embodiments, the photoresist layer 261 is referred to as a patterned mask layer 261.

[0192] Please refer to Figure 7 , according to the preparation method S1 and / or the preparation method S2, after the steps shown in Figure 6 , a spacer structure 27 is formed around each of a plurality of portions of the photoresist layer 261. The fabrication technique of the spacer structure 27 can include any suitable process. For example, a layer of spacer material (e.g., oxide, nitride, oxynitride, or a combination thereof) is conformally deposited on the photoresist layer 261, and a spacer etch operation is performed on the layer of spacer material. After the spacer structure 27 is formed, the photoresist layer 261 is removed. The pattern of the spacer structure 27 is aligned with the position of the WL structure to be formed in the subsequent process.

[0193] Before the formation of the WL structure in step S23, the pattern of the spacer structure 27 is transferred to the multi-layer structure 21. Figures 8 to 13 Illustrate the steps of patterning the multi-layer structure 21.

[0194] Please refer to Figure 8 , the pattern of the spacer structure 27 is transferred to the third layer 24 by a patterning operation to form a patterned third layer 241. In some embodiments, during the patterning operation on the third layer 24, the fourth layer 25 is patterned simultaneously. In some embodiments, after the patterning operation, the spacer structure 27 and the fourth layer 25 are removed. In some embodiments, a suitable etch operation is performed to pattern the fourth layer 25 and the third layer 24. Thus, a patterned third layer 241 having a pattern substantially the same as the pattern of the spacer structure 27 is formed.

[0195] Please refer toFigure 9 , after the patterning operation shown in Figure 8 , a dielectric layer 28 is formed over the patterned third layer 241. In some embodiments, the fabrication technique of the dielectric layer 28 is a blanket deposition. In some embodiments, the dielectric layer 28 at least fills the spaces between multiple portions of the patterned third layer 241. In some embodiments, the dielectric layer 28 is disposed over and between such portions of the patterned third layer 241. In some embodiments, a thickness of the dielectric layer 28 is substantially greater than one-half of a distance 317 between adjacent portions of the patterned third layer 241 for filling the spaces between such portions of the patterned third layer 241. In some embodiments, the formation of the dielectric layer 28 includes CVD, PVD, or a combination thereof. In some embodiments, the dielectric layer 28 includes one or more dielectric materials. The dielectric material of the dielectric layer 28 may be selected from oxides or nitrides.

[0196] Please refer to Figure 10 , after forming the dielectric layer 28, a spacer etch operation is performed on the dielectric layer 28. Figure 9 The patterned third layer 241 shown in

[0197] Please refer to Figure 11 , a photoresist layer 262 is formed over the patterned dielectric layer 281 in the peripheral region R2. In some embodiments, the photoresist layer 262 fills the spaces between multiple portions of the patterned dielectric layer 281 in the peripheral region R2. In some embodiments, the photoresist layer 262 covers the entire peripheral region R2.

[0198] Please refer to Figure 12 , an etch operation is performed on the second layer 23 and the first layer 22 in the array region R1 to form a patterned second layer 233 and a patterned first layer 221. The patterned second layer 233 defines multiple openings 42, and the patterned first layer 221 defines multiple openings 43. In some embodiments, Figure 12 the etch operation shown in

[0199] Figure 12The etching operation shown may include one or more etching steps. In some embodiments, the etching operation includes an etching step having a low selectivity between the materials of the second layer 23 and the first layer 22. In some embodiments, the etching step includes a high selectivity for the materials of the second layer 23 and the first layer 22. In some embodiments, the etching step includes a low selectivity for the material of the dielectric layer 14. Accordingly, the overall pattern of the patterned dielectric layer 281 in the array region R1 is transferred to the first layer 22 to form the patterned first layer 221.

[0200] Please refer to Figure 13 , after forming the openings 43 and the patterned first layer 221, the photoresist layer 262, the patterned dielectric layer 281, and the patterned second layer 233 are removed. A pattern of the patterned first layer 221 is transferred onto the substrate 11. In some embodiments, an etching operation is performed to pattern the dielectric layer 14 and the substrate 11. In some embodiments, the fabrication techniques for the plurality of openings 44 and the plurality of trenches 45 include Figure 13 the etching operation shown. In some embodiments, each opening 44 is defined by the dielectric layer 14 and penetrates the dielectric layer 14. Each opening 44 is surrounded by the dielectric layer 14, thereby forming the patterned dielectric layer 144.

[0201] In some embodiments, the trenches 45 are defined by a plurality of silicon portions 121 of the substrate 11 in the array region R1 and a plurality of dielectric portions 131 adjacent to the silicon portions 121. In some embodiments, the fabrication technique for the trenches 45 includes a dry etching operation. In some embodiments, the dry etching operation has a low selectivity between a material of the silicon portion 121 and a material of the dielectric portion 131. In some embodiments, Figure 13 the etching operation shown includes one or more etching steps. In some embodiments, Figure 13 the etching operation includes a first etching step for the dielectric material of the dielectric layer 14 and the dielectric portion 131, and a second etching step for the material of the silicon portion 121. In some embodiments, the first etching step includes a high selectivity for the materials of the dielectric layer 14 and the dielectric portion 131. In some embodiments, the second etching step includes a high selectivity for the material of the silicon portion 121. The trenches 45 may define the position and configuration of the WL structure. In some embodiments, the depth of the trenches 45 is controlled for the purpose of forming the WL structure.

[0202] Please refer to Figure 14 , in Figure 13After the etching operation shown, for example, the patterned first layer 221 is removed by another etching operation, and then a dielectric layer 51 is formed on each exposed sidewall of the silicon portion 121. In some embodiments, the dielectric layer 51 lines the exposed sidewalls of the silicon portion 121 in the trench 45. In some embodiments, the dielectric layer 51 contacts the silicon portion 121. In some embodiments, the fabrication technique of the dielectric layer 51 includes a thermal oxidation. In some embodiments, the dielectric layer 51 includes silicon oxide. In some embodiments, the dielectric layer 51 contacts Figure 14 an edge of the dielectric sub-layer 141 shown. In some embodiments, the materials of the dielectric layer 51 and the dielectric sub-layer 141 are the same.

[0203] Figures 15 to 20 are cross-sectional schematic views of different stages of forming the WL (word line) structure 50 during step S23 of fabrication method S2 or before step S13 of fabrication method S1.

[0204] Please refer to Figure 15 , after forming the dielectric layer 51, a conductive material 52 is formed over the substrate 11 and the patterned dielectric layer 144. The conductive material 52 can fill the openings 44 and the trenches 45. In some embodiments, the conductive material 52 fills the entire trench 45. In some embodiments, the fabrication technique of the conductive material 52 includes a deposition. In some embodiments, the conductive material 52 includes aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium-aluminum alloy (TiAl), titanium-aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum-carbon nitride (TaCN), tantalum-silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), titanium-silicon nitride (TiSiN), other suitable materials, or combinations thereof. In some embodiments, the conductive material 52 is W, TiN, or a combination thereof.

[0205] Please refer to Figure 16 , after forming the conductive material 52, fabrication method S1 or fabrication method S2 may further include removing an upper portion of the conductive material 52. In some embodiments, a plurality of first contact layers 521 are respectively formed in the trenches 45.

[0206] Please refer back to Figure 15 , a dashed line labeled 525 represents Figure 16A designed upper surface of the first contact layer 521 shown. For the purpose of electrical connection, the designed upper surface 525 should be lower than the upper surface 111 of the substrate 11. In other words, a distance 526 from the upper surface 111 of the substrate 11 to the designed upper surface 525 should be greater than zero. However, the range of the distance 526 can be adjusted according to different applications and is not defined herein. Additionally, it should be noted that the figures are only for illustration, and the tops of different first contact layers 521 can be in substantially the same plane.

[0207] Please refer to Figure 17 , a plurality of second contact layers 522 are respectively formed in trenches 45 above the plurality of first contact layers 521. The formation of the second contact layer 522 can be similar to the formation of the first contact layer 521 and will not be elaborated herein. In some embodiments, the second contact layer 522 can include a semiconductor material, such as polysilicon.

[0208] After forming the second contact layer 522, a barrier layer 54 can be formed above the substrate 11. The purpose of the barrier layer 54 is to prevent the loss of gate oxide during the manufacturing process. In some embodiments, the barrier layer 54 includes an oxide, such as silicon oxide. In some embodiments, the manufacturing technique of the barrier layer 54 includes a deposition. In some embodiments, a conformal deposition is performed to form the barrier layer 54. In some embodiments, the manufacturing technique of the barrier layer 54 includes CVD, atomic layer deposition (ALD), PECVD, plasma enhanced atomic layer deposition (PEALD), or a combination thereof. In some embodiments, a thickness of the barrier layer 54 is in the range of 3 - 5 nm. It should be understood that the materials of the barrier layer 54 and the dielectric layer 51 can be the same, and an interface between the barrier layer 54 and the dielectric layer 51 may not be observable.

[0209] Please refer to Figure 18 , an etch operation can be selectively performed on the barrier layer 54 to form a capping layer 541. In some embodiments, Figure 17 a plurality of horizontal portions of the shown barrier layer 54 are removed. In some embodiments, the upper surfaces of the patterned dielectric layer 144 are exposed. In some embodiments, the upper surfaces of the second contact layers 522 are exposed.

[0210] Please refer to Figure 19 , a dielectric layer 53 is formed above the substrate 11 and covers the second contact layers 522. In some embodiments, the dielectric layer 53 includes a nitride (e.g., silicon nitride). In some embodiments, the dielectric layer 53 fills the trenches 45 above the second contact layers 522. In some embodiments, the dielectric layer 53 covers the patterned dielectric layer 14. In some embodiments, the dielectric layer 53 is formed in the array region R1 and the peripheral region R2. In some embodiments, the dielectric layer 53 covers the entire substrate 11. In some embodiments, the dielectric layer 53 covers the entire patterned dielectric layer 14.

[0211] Please refer to Figure 20 that a planarization is performed on the dielectric layer 53, and a plurality of dielectric portions 531 are respectively formed in the trenches 45. The planarization may terminate on the dielectric sub-layer 141. It should be understood that the dielectric layer 14 shown in the foregoing figure may be a single layer, and the planarization may terminate when the thickness of the dielectric layer 14 is reduced to about 5 nm. In other words, after the planarization, a dielectric layer 14 with a thickness of about 5 nm is left on the substrate 11. In some embodiments, the remaining dielectric layer 14 covers the entire substrate 11. The planarization may include one or more suitable operations, such as chemical mechanical polishing (CMP), dry etching operation, or wet etching operation. In some embodiments, the upper surfaces of the dielectric portions 531 are substantially aligned with the upper surface 141A of the dielectric sub-layer 141 (or the upper surface of the remaining dielectric layer 14). In some embodiments, the upper surfaces of the dielectric portions 531 are substantially coplanar with the upper surface 141A of the dielectric sub-layer 141 (or the upper surface of the remaining dielectric layer 14). Thereby, a plurality of WL structures 50 are formed in the trenches 45. In some embodiments, each WL structure 50 includes a first contact layer 521, a second contact layer 522, and a dielectric portion 531. In some embodiments, the WL structures 50 are disposed on two opposite sides of one or more silicon portions 121.

[0212] It should be understood that the upper surfaces of the dielectric portions 531 define the upper surfaces 50A of the WL structures 50. Therefore, in some embodiments, the upper surfaces 50A of the WL (word line) contacts 50 are substantially aligned with the upper surface 141A of the dielectric sub-layer 141 (or the upper surface of the remaining dielectric layer 14). In some embodiments, the upper surfaces 50A of the WL structures 50 are substantially coplanar with the upper surface 141A of the dielectric sub-layer 141 (or the upper surface of the remaining dielectric layer 14).

[0213] Please refer to Figure 21 that before forming a polysilicon layer in step S13 of the manufacturing method S1 or step S24 of the manufacturing method S2, a photoresist layer 263 is formed above the substrate 11 and covers the entire substrate 11 in the array region R1. In some embodiments, in order to ensure that all the word line (WL) structures 50 in the array region R1 are covered by the photoresist layer 263, the photoresist layer 263 may further cover a part of the peripheral region R2 adjacent to the array region R1. In some embodiments, a boundary of the photoresist layer 263 is disposed in the peripheral region R2 above the dielectric portion 132 adjacent to the array region R1.

[0214] Please refer to Figure 22, after forming the photoresist layer 263, an etching operation is performed on the exposed portion of the dielectric layer 141. At least a portion of the dielectric layer 141 in the peripheral region R2 is removed. In some embodiments, a step 55 is formed at an upper surface of the dielectric portion 132. In some embodiments, a step 55 has a height approximately equal to the thickness of the dielectric layer 141. In some embodiments, the height of the step 55 is approximately 5 nm. The purpose of removing the dielectric layer 141 in the peripheral region R2 is to form peripheral circuits or components in the Figure 3 silicon portion 123 shown. In some embodiments, the etching operation shown in Figure 22 is performed to expose the silicon portion 123 in the peripheral region R2 (as shown in Figure 3 ). The photoresist layer 263 can be removed after the etching operation or the formation of peripheral components.

[0215] Please refer to Figure 23 , proceeding to step S13 of manufacturing method S1 or step S24 of manufacturing method S2, a polysilicon layer 31 is formed over the substrate 11. In some embodiments, the polysilicon layer 31 is formed in the array region R1 and the peripheral region R2. In some embodiments, the polysilicon layer 31 covers the entire substrate 11. In some embodiments, the polysilicon layer 31 has a configuration conformal to the remaining portions of the dielectric layer 141 and the substrate 11. In some embodiments, the polysilicon layer 31 has a step 56, and the step 56 corresponds to the Figure 22 step 55 shown. In some embodiments, the polysilicon layer 31 is an undoped polysilicon layer 31, which means that the polysilicon layer 31 does not include P-type or N-type dopants. In some embodiments, the polysilicon layer 31 has a neutral conductivity. In some embodiments, a thickness of the polysilicon layer 31 is in the range of 20 - 50 nm.

[0216] Please refer to Figure 24 , after forming the polysilicon layer 31, a photoresist layer 264 is formed to cover the substrate 11 in the array region R1 and selectively cover a portion of the substrate 11 in the peripheral region R2 adjacent to the array region R1. In some embodiments, a boundary of the photoresist layer 264 is disposed in the peripheral region R2 above the dielectric portion 132 adjacent to the array region R1. The photoresist layer 264 can cover or expose the step 56 of the polysilicon layer 31. In some embodiments, as shown in Figure 24 , the step 56 of the polysilicon layer 31 is exposed through the photoresist layer 264.

[0217] Please refer to Figure 25, a doping operation is performed on a part of the polysilicon layer 31 exposed through the photoresist layer 264. Dopants of a first conductivity type (e.g., N-type) are introduced into this part of the polysilicon layer 31 exposed through the photoresist layer 264. As a result, the polysilicon layer 31 at this stage includes an undoped part 313 and a doped part 311. In some embodiments, the undoped part 313 is covered by the photoresist layer 264, and the doped part 311 is exposed through the photoresist layer 264. An annealing operation may be performed after the doping operation for activation. In some embodiments, due to the diffusion of dopants during annealing, the boundary between the undoped part 313 and the doped part 311 may not align with the boundary of the photoresist layer 264. In some embodiments, the doped part 311 may extend under the photoresist layer 264 after the annealing operation. In an alternative embodiment, the boundary between the undoped part 313 and the doped part 311 aligns with the boundary of the photoresist layer 264. The photoresist layer 264 is removed after the doping operation.

[0218] Please refer to Figure 26 , a mask layer 267 and a photoresist layer 265 are formed over the polysilicon layer 31. In some embodiments, the photoresist layer 265 covers at least the silicon part 123 in the peripheral region R2 ( Figure 26 not shown in, please refer to Figure 3 ). The mask layer 267 may include suitable materials, such as oxides, nitrides, oxynitrides, carbon, or combinations thereof. To ensure that the entire undoped part 313 of the polysilicon layer 31 is exposed, the photoresist layer 265 only covers a part of the doped part 311 in the peripheral region R2. In some embodiments, a part of the dielectric part 132 close to the array region R1 is exposed through the photoresist layer 265. In some embodiments, the boundary of the photoresist layer 265 is located within a covered area of the doped part 311 of the polysilicon layer 31. In some embodiments, the boundary of the photoresist layer 265 is farther from the array region R1 than the step 55.

[0219] Please refer to Figure 27 , an etching operation is performed to remove the parts of the mask layer 267 exposed through the photoresist layer 265, and the thickness of a part of the polysilicon layer 31 exposed through the photoresist layer 265 is reduced. Thereby, a patterned mask layer 268 is formed. In some embodiments, the thickness of the exposed part of the polysilicon layer 31 is reduced to about Figure 3 half of the thickness of the polysilicon layer 31 initially formed in. In some embodiments, the thickness of the undoped part 313 is reduced to about 10 to 20 nm. In some embodiments, the thickness of a part of the doped part 311 exposed through the photoresist layer 265 is also reduced to about 10 to 20 nm. In some embodiments, the thickness of the photoresist layer 265 is reduced by the etching operation.

[0220] For illustrative purposes, the portion of the doped portion 311 having a reduced thickness is relabeled as the doped portion 312, and the doped portion 311 refers to the remaining portion of the doped portion 311 having the original thickness. As Figure 27 shown, as a result of the etching operation, a step 57 is formed corresponding to Figure 26 the step 56 shown. In addition to the step 57, the polysilicon layer 31 further includes a step 58 located at a boundary between the doped portion 311 and the doped portion 312. In some embodiments, the step 58 has a sidewall that is substantially aligned with the boundary of the photoresist layer 265 or the patterned mask layer 268. In some embodiments, a height of the step 57 is substantially less than a height of the step 58. In some embodiments, a height of the step 55 is substantially less than a height of the step 58. In some embodiments, a thickness of the doped portion 311 at this stage is substantially the same as Figure 23 the thickness of the polysilicon layer 31 at the stage shown.

[0221] Please refer to Figure 28 , the photoresist layer 265 and the patterned mask layer 268 are removed. This exposes the doped portion 311 in the peripheral region R2.

[0222] Please refer to Figure 29 , a capping layer 33 is formed over the polysilicon layer 31. In some embodiments, a thickness of the capping layer 33 is in the range of 20 to 50 nm. In some embodiments, the capping layer 33 is formed to protect the polysilicon layer 31 during the formation of a plurality of BL contacts 351 in subsequent processes.

[0223] Please refer to Figure 30 , a multi-layer mask structure 34 is formed over the capping layer 33. In some embodiments, the multi-layer mask structure 34 includes a first layer 341, a second layer 342, and a third layer 343 sequentially stacked over the capping layer 33. In some embodiments, the first layer 341 is referred to as a lower layer. In some embodiments, the first layer 341 includes carbon. In some embodiments, a thickness of the first layer 341 is in the range of 60 to 100 nm. In some embodiments, the second layer 342 is an ARC layer. In some embodiments, the second layer 342 includes silicon. In some embodiments, a thickness of the second layer 342 is in the range of 20 to 60 nm. In some embodiments, the third layer 343 includes an oxide. In some embodiments, a thickness of the third layer 343 is in the range of 20 to 60 nm. The third layer 343 can be patterned to have a plurality of openings 344 for defining the positions of the BL contacts 351 to be formed in subsequent processes.

[0224] Please refer to Figure 31 , a pattern of the third layer 343 is transferred to the substrate 11. In some embodiments, duringFigure 30 One or more etching operations are performed on the second layer 342 and the third layer 343 shown. In some embodiments, one or more etching operations are performed on the capping layer 33, the undoped portion 313 of the polysilicon layer 31, the dielectric portion 531, and the silicon portion 121. In some embodiments, an etching operation selective to the oxide material is performed. In some embodiments, an etching operation selective to the silicon material is performed. In some embodiments, a plurality of openings 335 are thereby formed through the capping layer 33, the undoped portion 313 of the polysilicon layer 31, and the dielectric sublayer 141. In some embodiments, a plurality of portions of the capping layer 33 are removed. In some embodiments, the undoped portion 313 of the polysilicon layer 31 is partially removed. In some embodiments, respective portions of the dielectric sublayer 141 are removed. In some embodiments, respective portions of the dielectric portion 531 are removed. In some embodiments, respective upper portions of the silicon portion 121 in the array region R1 are removed.

[0225] Please refer to Figure 32 , proceed to step S14 of manufacturing method S1 or step S25 of manufacturing method S2, and a contact material layer 35 is formed over the dielectric layer 53 and fills the openings 335. In some embodiments, the manufacturing technique of the contact material layer 35 is a deposition. The contact material layer 35 fills each of the openings 335. The contact material layer 35 may also cover an upper surface of the dielectric layer 53. In some embodiments, the contact material layer 35 in the opening 335 contacts the silicon portion 121. In some embodiments, the contact material layer 35 in the opening 335 contacts the dielectric portion 531.

[0226] In some embodiments, a material of the contact material layer 35 includes polysilicon. In some embodiments, the contact material layer 35 is a polysilicon doped with a dopant of a first conductivity type. In some embodiments, the contact material layer 35 is an N-type polysilicon layer. In some embodiments, a concentration of the dopant of the first conductivity type in the contact material layer 35 is substantially equal to or greater than a concentration of the dopant of the first conductivity type in the doped portion 311 of the polysilicon layer 31.

[0227] Please refer to Figure 33, an etching operation is performed to remove an upper portion of the contact material layer 35 and an upper portion of the capping layer 33. In some embodiments, the etching operation is stopped when the thickness of the capping layer 33 remaining on the polysilicon layer 31 is approximately 2 to 5 nm. Thereby, a plurality of BL contacts 351 disposed in the opening 335 are formed, and a remaining capping layer 332 is also formed. In some embodiments, the upper surface 351A of the BL contact 351 is substantially aligned with an upper surface of the remaining capping layer 332 above the undoped portion 313 surrounding the upper surface 351A of the BL contact 351. In some embodiments, the remaining capping layer 332 covers the entire polysilicon layer 31. In some embodiments, a portion of the remaining capping layer 332 above the undoped portion 313 of the polysilicon layer 31 has a thickness of approximately 3 nm. In some embodiments, the thickness of a portion of the remaining capping layer 332 above the doped portion 311 of the polysilicon layer 31 is substantially equal to the thickness of a portion of the remaining capping layer 332 above the undoped portion 313. In some embodiments, the thickness of this portion of the remaining capping layer 332 above the doped portion 311 of the polysilicon layer 31 is approximately 3 nm.

[0228] In some embodiments, the remaining capping layer 332 also covers the steps 57 and 58 of the polysilicon layer 31. In some embodiments, the remaining capping layer 332 covers the entire doped portion 312 between the undoped portion 313 and the doped portion 311. In some embodiments, the remaining capping layer 332 has various thicknesses along a horizontal direction. In some embodiments, a portion of the remaining capping layer 332 above the doped portion 312 near the step 58 has a maximum thickness across the entire remaining capping layer 332.

[0229] Please refer to Figure 34 , remove Figure 33 the remaining capping layer 332 shown. In some embodiments, an etching operation for the remaining capping layer 332 is performed. In some embodiments, the etching operation has a low or zero polysilicon material removal rate. Removing the upper portion of the capping layer 33 and the remaining capping layer 332 separately can prevent damage to the doped portion 311 of the polysilicon layer 31 and the peripheral components.

[0230] It should be understood that, as shown in Figure 33 , since the upper surface 351A of the BL contact 351 is substantially aligned with the upper surface of the remaining capping layer 332 above the undoped portion 313 of the BL contact 351 in the previous stage, a step 59 is generated between the upper surface 351A of the BL contact 351 and an upper surface 313A of the undoped portion 313. In some embodiments, the height H59 of the step 59 is approximately equal to Figure 33The thickness of the remaining capping layer 332 over the undoped portion 313 at that part. In some embodiments, the height H59 of the step 59 is approximately 3 nm. In other words, the upper surface 351A of the BL contact 351 is approximately 3 nm higher than the upper surface 313A of the undoped portion 313 of the polysilicon layer 31 in the array region. For clarity and illustrative purposes, an enlarged Figure 34 portion of the intermediate structure is shown to display the step 59, as Figure 34A shown.

[0231] Please refer to Figure 35 , before step S15 of fabrication method S1 or step S26 of fabrication method S2, a multilayer 321, 322, and 323 is sequentially formed over the BL contact 351 and the undoped portion 313 of the polysilicon layer 31. In some embodiments, the depositions of layers 321, 322, and 323 together define a multilayer structure. In some embodiments, the depositions of layers 321, 322, and 323 are sequentially performed to form layers 321, 322, and 323 covering the entire substrate 11, and then, one or more etching operations are performed on layers 321, 322, and 323 to remove the respective portions of layers 321, 322, and 323 in the peripheral region R2. Thereby forming layers 321, 322, and 323 covering the array region R1 and a part of the peripheral region R2 adjacent to the array region R1 as shown in Figure 35 . In some embodiments, layers 321, 322, and 323 are used as a mask to pattern the polysilicon layer 31, thereby removing the doped portions 311 and 312, as shown in Figure 35 . Additionally, a spacer layer 381 can be selectively formed on the sidewalls of layers 321, 322, and 323 and the undoped portion 313 in the peripheral region R2. The formation of the spacer layer 381 can be achieved by any suitable process. For example, a conformal deposition can be performed, followed by a spacer etch operation to form the spacer layer 381.

[0232] In some embodiments, an upper portion of the dielectric part 132 can be removed during the etching operations of layers 321, 322, and 323, the polysilicon layer 31, and the spacer layer 381. Thus, a step 551 corresponding to the step 55 shown in Figure 34 is formed, as well as a step 552 at a boundary of the spacer layer 381 (or at a boundary of the undoped portion 313 if the spacer layer 381 is not formed).

[0233] Layers 321, 322, and 323 can define a stack of a BL structure in subsequent processing. In some embodiments, layer 321 is a first metal layer of the BL structure. In some embodiments, layer 321 includes titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten silicide (WSi), or a combination thereof. In some embodiments, layer 322 is a second metal layer of the BL structure. In some embodiments, layer 322 includes tungsten (W), other suitable metals, or a combination thereof. In some embodiments, layer 323 is an upper dielectric layer of the BL structure. In some embodiments, layer 323 includes nitrides, other suitable dielectric materials, or a combination thereof. In some embodiments, the spacer layer 381 includes nitrides.

[0234] Please refer to Figure 36 , a spacer layer 382, a liner layer 324, a compensation layer 383, a hard layer 325, and a mask stack structure 37 are formed on Figure 35 the intermediate structure above. The mask stack structure 37 can be referred to as a multi-layer structure 37. In some embodiments, a spacer layer 382 having a dielectric material different from that of the spacer layer 381 is formed on a sidewall of the spacer layer 381. In some embodiments, the spacer layer 382 includes oxides. The formation of the spacer layer 382 can be similar to that of the spacer layer 381 and will not be described in detail herein.

[0235] In some embodiments, the liner layer 324 is formed after the spacer layer 382 is formed. In some embodiments, the liner layer 324 includes nitrides. In some embodiments, the compensation layer 383 is formed after the liner layer 324 is formed. In some embodiments, an upper surface of the compensation layer 383 is substantially at the same plane as an upper surface of the liner layer 324. In some embodiments, the hard layer 325 is formed on the compensation layer 383 and the liner layer 324. In some embodiments, the hard layer 325 includes nitrides.

[0236] The mask stack structure 37 can include multiple layers 371, 372, 373, and 374. The mask stack structure 37 can be similar to Figure 6 the multi-layer structure 21 shown. More specifically, layer 371 can be similar to the first layer 22 or can include the same materials as the first layer 22; layer 372 can be similar to the second layer 23 or can include the same materials as the second layer 23; layer 373 can be similar to the third layer 24 or can include the same materials as the third layer 24; and layer 374 can be similar to the fourth layer 25 or can include the same materials as the fourth layer 25. Repeated descriptions will not be elaborated herein; however, such omissions are not intended to limit the present disclosure. Similar to Figure 6 the second layer 23 shown, layer 372 can include one or more sub-layers according to different applications.

[0237] Next, a photoresist layer 266 is formed over the mask stack structure 37. It should be understood that a pattern of the photoresist layer 266 is for defining the position of the BL structure in subsequent processes. The pattern of the photoresist layer 266 may not be shown in the cross-sectional view of the WL structure.

[0238] Please refer to Figure 37 , Figure 37 which is a top perspective schematic view of an intermediate structure along the cutting line 527 in Figure 36 . In some embodiments, Figures 4 to 36 is a cross-sectional view along the cutting line B - B' shown in Figure 37 . For illustrating the formation of the BL structure, Figures 38 to 45 is a cross-sectional view along the cutting line C - C' shown in Figure 37 .

[0239] Please refer to Figure 38 , and a pattern of the photoresist layer 266 is formed to define the BL structure. In some embodiments, the entire peripheral region R2 is covered by the photoresist layer 266.

[0240] Please refer to Figure 39 , Figure 38 wherein the pattern of the photoresist layer 266 shown in Figure 38 is used as a mask to perform one or more etching operations on the layers 374 and 373. In some embodiments, the layer 374 is removed after the layer 373 is patterned.

[0241] Please refer to Figure 40 , after the layer 373 is patterned, a spacer sub-layer 376 is formed over the layer 373. In some embodiments, the spacer sub-layer 376 is conformal to the layer 373. In some embodiments, the fabrication technique of the spacer sub-layer 376 includes a deposition operation. In some embodiments, the spacer sub-layer 376 includes an oxide.

[0242] Please refer to Figure 41 , a spacer etching operation is performed on the spacer sub-layer 376, thereby forming a spacer structure 377. The spacer structure 377 may include a plurality of segments for defining the position of the BL structure to be formed. In some embodiments, the layer 373 is removed after the spacer etching operation. In some embodiments, after the layer 373 is removed, a photoresist layer 378 is formed over the peripheral region R2. In some embodiments, the photoresist layer 378 contacts the layer 372 in the peripheral region R2.

[0243] Please refer to Figure 42, in step S15 of preparation method S1 or step S26 of preparation method S2, a patterned mask layer 325' is formed. In some embodiments, one or more etching operations are performed on layers 372 and 371, hard layer 325, linear layer 324, and layer 323. In some embodiments, one or more etching operations are sequentially performed by changing the etchant in an injection chamber. In some embodiments, one or more etching operations are sequentially performed in the same chamber. Layer 322 may or may not be removed by one or more etching operations. In some embodiments, Figure 42 one or more of the etching operations shown target a nitride material. In some embodiments, as Figure 42 a side effect of one or more of the etching operations shown, the upper portion of layer 322 is removed. In some embodiments, the exposed portion of layer 322 is partially removed by one or more etching operations. In some embodiments, after one or more etching operations, layer 321 is still covered by layer 322. In some embodiments, spacer structure 377 and photoresist layer 378 are removed after one or more etching operations.

[0244] After one or more etching operations, layer 371 includes a plurality of segments 371' disposed in array region R1. In some embodiments, layer 371 is patterned and the patterned layer 371 is used as a mask to pattern hard layer 325, linear layer 324, and layer 323. In some embodiments, the patterned layer 371 serves as a mask for etching operations performed on layers (e.g., 325, 324, 323, and 322) below the patterned layer 371. After one or more etching operations, hard layer 325 includes a plurality of segments 325' disposed in array region R1 and below segments 371'. After one or more etching operations, linear layer 324 includes a plurality of segments 324' disposed in array region R1 and below segments 325'. After one or more etching operations, layer 323 includes a plurality of segments 323' disposed in array region R1 and below segments 324'. After one or more etching operations, layer 322 becomes a patterned layer 326.

[0245] Please refer to Figure 43 , an etching operation is performed on patterned layer 326. After Figure 43 the etching operation shown, patterned layer 326 includes a plurality of segments 322'. In some embodiments, Figure 43 the etching operation shown targets a metal material. In some embodiments, multiple portions of layer 321 are also removed because layer 321 includes a metal material. After Figure 43 the etching operation shown, layer 321 includes a plurality of segments 321'. In some embodiments, as Figure 43As a side effect of the etching operation shown, multiple portions of the undoped portion 313 of the polysilicon layer 31 are also removed. For illustrative purposes, after the etching operation shown in Figure 43 , the undoped portion 313 is relabeled as 314. In some embodiments, as a side effect of the etching operation, the BL contact 351 may be partially removed while removing multiple portions of the undoped portion 313. It should be noted that the thickness of the layer 371 (including the section 371') may be reduced by Figure 43 the etching operation shown.

[0246] Please refer to Figure 44 , in step S16 of preparation method S1 or step S27 of preparation method S2, an etching operation is performed on the BL contact 351 and the undoped portion 314 of the polysilicon layer 31. After the etching operation shown in Figure 44 , the undoped portion 314 includes multiple sections 315 disposed in the array region R1. For illustrative purposes, after the etching operation shown in Figure 44 , the BL contact 351 is relabeled as the BL contact 352. In some embodiments, Figure 44 the etching operation shown targets a polysilicon material. In some embodiments, the dielectric layer 141 (or the remaining dielectric layer 14) remains substantially unchanged after Figure 44 the etching operation shown. In some embodiments, the upper surface 141A of the dielectric layer 141 (or the remaining dielectric layer 14) remains substantially flat after Figure 44 the etching operation shown. In some embodiments, the dielectric portion 131 remains substantially unchanged after Figure 44 the etching operation shown. The thickness of the layer 371 may be further reduced by Figure 44 the etching operation shown.

[0247] Please refer to Figure 45 , the layer 371 is removed. In some embodiments, each section 315 has a substantially straight sidewall after Figure 44 the etching operation shown. In some embodiments, the upper surface 141A of the dielectric layer 141 (or the remaining dielectric layer 14) is substantially flat after Figure 44 the etching operation shown.

[0248] Please refer to Figure 46, a plurality of BL structures 32 and 36 are formed, thereby forming a semiconductor structure 10. The BL structure 32 includes sections 315, 321', 322', and 323' stacked in sequence on the dielectric layer 141. In some embodiments, depending on different applications, the BL structure 32 may also include sections 324' and 325'. In some embodiments, the linear layer 324 and the hard layer 325 are removed before forming the plurality of spacer structures 39 and 41, and the BL structure 32 does not include sections 324' and 325', as Figure 46 shown. In some embodiments, a sidewall S32 of the BL structure 32 is substantially straight or extends along a vertical direction.

[0249] In some embodiments, a sidewall S315 of the section 315 is substantially straight. In some embodiments, a sidewall S321 of the section 321' is substantially aligned with the sidewall S315 of the section 315. In some embodiments, the sidewall S321 of the section 321' is substantially straight. In some embodiments, a sidewall S322 of the section 322' is substantially aligned with the sidewall S321 of the section 321'. In some embodiments, the sidewall S322 of the section 322' is substantially straight. In some embodiments, a sidewall S323 of the section 323' is substantially aligned with the sidewall S322 of the section 322'. In some embodiments, the sidewall S323 of the section 323' is substantially straight. The sidewalls of the sections 315, 321', 322', and 323' together define a sidewall of the BL structure 32. A lower surface B32 of the BL structure 32 is defined by a lower surface of the section 315. In some embodiments, the lower surface B32 of the BL structure 32 is substantially flat or extends along a horizontal direction.

[0250] The BL structure 36 includes a BL contact 352 and sections 321', 322', and 323' stacked in sequence on the silicon portion 121. In some embodiments, depending on different applications, the BL structure 36 may also include sections 324' and 325'. In some embodiments, the linear layer 324 and the hard layer 325 are removed before forming the plurality of spacer structures 39 and 41, and the BL structure 36 does not include sections 324' and 325', as Figure 46 shown.

[0251] Similar to the BL structure 32, in the BL structure 36, each sidewall of the sections 321', 322' and / or 323' can be substantially straight. In some embodiments, each sidewall of the sections 321', 322' and 323' is substantially aligned along a vertical direction. In some embodiments, the BL contact 352 has a narrower top and a wider bottom. In some embodiments, a width of an upper surface T352 of the BL contact 352 is substantially equal to a width of a lower surface of the section 321'. In some embodiments, the upper surface T352 of the BL contact 352 is substantially aligned with the lower surface of the section 321'. A lower surface of the BL contact 352 defines a lower surface B33 of the BL structure 36. In some embodiments, a width of the lower surface of the BL contact 352 or the lower surface B33 of the BL structure 36 is substantially equal to a width of an upper surface of a silicon portion 121 disposed below the BL contact 352. In some embodiments, the lower surface of the BL contact 352 or the lower surface B33 of the BL structure 36 is substantially coplanar with the upper surface of the silicon portion 121 disposed below the BL contact 352. The sidewalls of the BL contact 352 and the sections 321', 322' and 323' together define a sidewall S33 of the BL structure 36.

[0252] A plurality of spacer structures 39 and 41 can be formed on Figure 45 the intermediate structure or are formed after removing the linear layer 324 and the hard layer 325. The spacer structure 39 surrounds each BL structure 32, and the spacer structure 41 surrounds each BL structure 36.

[0253] In some embodiments, each spacer structure 39 includes an inner nitride layer 391, an oxide layer 392 and an outer nitride layer 393. In some embodiments, the inner nitride layer 391 is disposed on the sidewall S32 of the BL structure 32 and extends along the sidewall S32 of the BL structure 32. In some embodiments, the oxide layer 392 is disposed between the inner nitride layer 391 and the outer nitride layer 393. In some embodiments, the outer nitride layer 393 is disposed along a sidewall of the oxide layer 392. In some embodiments, the outer nitride layer 393 contacts the oxide layer 392. In some embodiments, a lower portion of the outer nitride layer 393 contacts a lower portion of the inner nitride layer 391.

[0254] In some embodiments, a lower surface B391 of the inner nitride layer 391 contacts an upper surface 141A of the dielectric layer 141 (or the remaining dielectric layer 14). In some embodiments, the lower surface B391 of the inner nitride layer 391 is substantially planar. In some embodiments, the lower surface B391 of the inner nitride layer 391 is substantially aligned with a lower surface B32 of the BL structure 32. In some embodiments, the outer nitride layer 393 covers sidewalls of the dielectric layer 141 (or the remaining dielectric layer 14). In some embodiments, a bottom of the oxide layer 392 is lower than an upper surface of the section 315 and higher than the lower surface B32 of the BL structure 32. In some embodiments, the outer nitride layer 393 extends below the inner nitride layer 391. In some embodiments, a bottom of the outer nitride layer 393 is lower than the lower surface B391 of the inner nitride layer 391.

[0255] In some embodiments, an inner sidewall of the spacer structure 39 (or the inner nitride layer 391) surrounding the BL structure 32 is substantially straight. In some embodiments, the inner sidewall of the spacer structure 39 (or the inner nitride layer 391) surrounding the BL structure 32 is substantially flat.

[0256] In some embodiments, each spacer structure 41 includes an inner nitride layer 411, an oxide layer 412, and an outer nitride layer 413. The inner nitride layer 411, the oxide layer 412, and the outer nitride layer 413 may be formed simultaneously or in the same step as the formation of the inner nitride layer 391, the oxide layer 392, and the outer nitride layer 393, respectively.

[0257] In some embodiments, the inner nitride layer 411 is disposed on a sidewall S33 of the BL structure 36 and extends along the sidewall S33 of the BL structure 36. In some embodiments, the oxide layer 412 is disposed between the inner nitride layer 411 and the outer nitride layer 413. In some embodiments, the outer nitride layer 413 is disposed along a sidewall of the oxide layer 412. In some embodiments, the outer nitride layer 413 contacts the oxide layer 412. In some embodiments, the outer nitride layer 413 is disposed along a sidewall of the oxide layer 412. In some embodiments, a lower portion of the outer nitride layer 413 contacts a lower portion of the inner nitride layer 411. In some embodiments, a bottom of the oxide layer 412 is lower than an upper surface T352 of the BL contact 352 and higher than the lower surface B33 of the BL structure 36 or the lower surface of the BL contact 352.

[0258] In some embodiments, a bottom of the inner nitride layer 411 extends below the upper surface 141A of the dielectric layer 141 (or the remaining dielectric layer 14). In some embodiments, the bottom of the inner nitride layer 411 extends below a bottom of the outer nitride layer 413. In some embodiments, the inner nitride layer 411 extends below the outer nitride layer 413. In some embodiments, the bottom of the inner nitride layer 411 is located below the bottom of the oxide layer 412. In some embodiments, the bottom of the outer nitride layer 413 is located above the bottom of the inner nitride layer 411.

[0259] After forming the spacer structure 39, a plurality of metal contacts 46 are formed between adjacent BL structures 32 and 36. In some embodiments, one or more etching operations are performed to expose a plurality of portions of the silicon portion 121. In some embodiments, portions of the silicon portion 121 that are outside the covered regions of the BL structures 32 and 36 are removed. In some embodiments, the metal contacts 46 contact the silicon portion 121, and the silicon portion 121 is exposed after removing portions of the silicon portion 121 that are outside the covered regions of the BL contacts 32 and 36. In some embodiments, the metal contacts 46 are referred to as bonding pads 46. In some embodiments, the top of the metal contacts 46 is lower than the tops of the BL structures 32 and 36.

[0260] The present disclosure provides a novel configuration of a BL structure that includes a polysilicon layer as a lower layer of the BL structure. Due to an etching selectivity of the polysilicon material relative to other dielectric and / or metal materials, a patterning result of the polysilicon layer can be improved. Accordingly, a configuration of the patterned polysilicon layer having a straight sidewall can be provided, and better control over a profile of the metal contact / bonding pad can be achieved.

[0261] An embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate including a plurality of fin structures; a dielectric layer disposed above adjacent fin structures, wherein an upper surface of the dielectric layer is a substantially flat surface; a bit line structure disposed above the substrate and between adjacent fin structures, wherein the bit line structure includes a polysilicon layer contacting the upper surface of the dielectric layer; and a spacer structure surrounding the bit line structure, wherein the spacer structure contacts the upper surface of the dielectric layer.

[0262] In some embodiments, a lower surface of an inner nitride layer of the spacer structure is substantially planar.

[0263] In some embodiments, the bit line structure further includes: a first metal layer stacked above the polysilicon layer; a second metal layer stacked above the first metal layer; and a nitride layer stacked above the second metal layer.

[0264] In some embodiments, one sidewall of the polysilicon layer is substantially aligned with one sidewall of the first metal layer, the second metal layer, or the nitride layer along a vertical direction.

[0265] In some embodiments, the first metal layer includes titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten silicide (WSi), or a combination thereof.

[0266] In some embodiments, the second metal layer includes tungsten (W).

[0267] In some embodiments, the polysilicon layer is an undoped polysilicon layer.

[0268] In some embodiments, one sidewall of the bit line structure is substantially straight.

[0269] In some embodiments, the spacer structure includes: a first nitride layer adjacent to one sidewall of the bit line structure; a second nitride layer surrounding the first nitride layer; and an oxide layer disposed between the first nitride layer and the second nitride layer.

[0270] In some embodiments, a lower surface of the first nitride layer contacts the upper surface of the dielectric layer.

[0271] In some embodiments, the second nitride layer extends below the lower surface of the first nitride layer.

[0272] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The manufacturing method includes multiple steps. Provide a substrate, wherein the substrate includes a fin structure. A dielectric layer is formed above the substrate, wherein an upper surface of the dielectric layer is substantially flat. A polysilicon layer is formed above the substrate and the dielectric layer. A bit line contact is formed on a top of the fin structure, wherein the bit line contact penetrates the polysilicon layer. A patterning mask is formed above the bit line contact and the polysilicon layer. Pattern the bit line contact and the polysilicon layer, wherein one sidewall of the bit line contact is a substantially straight sidewall, and after patterning the bit line contact and the polysilicon layer, the upper surface of the dielectric layer remains substantially flat.

[0273] In some embodiments, the manufacturing method further includes: forming a plurality of word line structures on opposite sides of the fin structure before forming the polysilicon layer.

[0274] In some embodiments, the substrate includes an array region and a peripheral region surrounding the array region, wherein the fin structure is formed in the array region and the dielectric layer is formed in the array region and the peripheral region.

[0275] In some embodiments, the manufacturing method further includes: forming a step on an upper surface of a dielectric portion of the substrate in the peripheral region.

[0276] In some embodiments, the polysilicon layer is formed to conform to the upper surface of the dielectric layer.

[0277] In some embodiments, before forming the patterned mask, an upper surface of the bit line contact is above an upper surface of a portion of the polysilicon layer surrounding the bit line contact.

[0278] In some embodiments, forming the polysilicon layer includes: depositing a polysilicon material film above the substrate; doping a first portion of the polysilicon material film in a peripheral region of the substrate; and reducing a thickness of a second portion of the polysilicon material film in an array region of the substrate surrounded by the peripheral region.

[0279] In some embodiments, the manufacturing method further includes: forming a first multi-layer structure above the substrate before forming the patterned mask.

[0280] In some embodiments, the first multi-layer structure is patterned before patterning the bit line contact and the polysilicon layer.

[0281] In some embodiments, the first multi-layer structure includes a first layer, a second layer, and a third layer, wherein the first layer, the second layer, and the third layer are patterned by different etching operations.

[0282] In some embodiments, forming the patterned mask includes: forming a second multi-layer structure above the substrate; patterning a first layer of the second multi-layer structure, thereby forming a patterned first layer; forming a spacer layer to surround the patterned first layer; performing a spacer etch on the spacer layer, thereby forming a spacer structure; and using the spacer structure as a mask to pattern a second layer of the second multi-layer structure, thereby forming a patterned second layer.

[0283] In some embodiments, the formation of the patterned mask further includes: removing the patterned first layer before patterning the second layer.

[0284] In some embodiments, the patterned second layer becomes the patterned mask, and a pattern of the patterned second layer is transferred to the polysilicon layer and the bit line contact.

[0285] Another embodiment of the present disclosure provides a method for fabricating a semiconductor structure. The fabrication method includes multiple steps. Provide a substrate, wherein the substrate includes a plurality of fin structures in an array region of the substrate. An oxide layer is formed over the substrate and covers the tops of the fin structures. A plurality of word line structures are formed alternating with the plurality of fin structures, wherein an upper surface of the oxide layer is substantially aligned with an upper surface of the plurality of word line structures. A polysilicon layer is formed over the substrate, the plurality of word line structures, the plurality of fin structures, and the oxide layer. A plurality of bit line contacts are formed over the plurality of fin structures and penetrate the polysilicon layer. A patterned layer is formed over the polysilicon layer. The polysilicon layer is patterned using the patterned layer as a mask, thereby forming a patterned polysilicon layer, wherein a sidewall of the patterned polysilicon layer is substantially straight.

[0286] In some embodiments, the substrate includes a peripheral region surrounding the array region, the oxide layer also covers the peripheral region, and the fabrication method further includes: forming a first mask layer covering the array region of the substrate and exposing the peripheral region; partially removing the oxide layer in the peripheral region, thereby forming a step on an isolation of the substrate; forming the polysilicon layer over the array region and the peripheral region, wherein the polysilicon layer is conformal to the step; doping the polysilicon layer in the peripheral region, thereby forming a doped portion of the polysilicon layer; forming a second mask layer to partially cover the doped portion of the polysilicon layer; and reducing a thickness of the polysilicon layer exposed through the second mask layer.

[0287] In some embodiments, before doping the polysilicon layer, the thickness of the polysilicon layer is in the range of 20 to 50 nanometers.

[0288] In some embodiments, the thickness of the polysilicon layer is reduced to the range of 10 to 20 nanometers.

[0289] In some embodiments, after reducing the thickness of the polysilicon layer, the polysilicon layer has a first step conformal to the step of the isolation, and a second step located at a boundary of the second mask layer.

[0290] In some embodiments, a thickness of an undoped portion of the polysilicon layer in the array region is less than a thickness of the doped portion of the polysilicon layer.

[0291] In some embodiments, a thickness of the oxide layer is about 5 nanometers.

[0292] In some embodiments, a material of the bit line contacts includes polysilicon.

[0293] In some embodiments, the patterned layer is used as the mask to pattern the bit line contacts simultaneously with the patterning of the polysilicon layer.

[0294] In some embodiments, the bit line contacts are doped with an N-type dopant.

[0295] In some embodiments, an upper surface of the bit line contacts is approximately 3 nanometers higher than an upper surface of the polysilicon layer in the array region.

[0296] In summary, the present application discloses a semiconductor structure and a method for manufacturing the same. The present disclosure provides a novel configuration of a BL structure, which includes a polysilicon layer as a lower layer of the BL structure. Due to the etching selectivity of the polysilicon material with respect to other dielectric and / or metal materials, the patterning result of the polysilicon layer can be improved. Therefore, a configuration of the patterned polysilicon layer with a straight sidewall can be provided, and better control over the profile of the metal contacts / bonding pads can be achieved.

[0297] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the above-described processes can be implemented in different ways, and many of the above-described processes can be replaced by other processes or combinations thereof.

[0298] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same function or achieve substantially the same result as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A method for fabricating a semiconductor structure, comprising: providing a substrate, wherein the substrate includes a fin structure; forming a dielectric layer over the substrate, wherein an upper surface of the dielectric layer is substantially flat; forming a polysilicon layer over the substrate and the dielectric layer; forming a bit line contact on the fin structure, wherein the bit line contact penetrates the polysilicon layer; forming a patterned mask over the bit line contact and the polysilicon layer; and patterning the bit line contact and the polysilicon layer, wherein a sidewall of the polysilicon layer is substantially straight, and after patterning the bit line contact and the polysilicon layer, the upper surface of the dielectric layer remains substantially flat.

2. The fabrication method according to claim 1, further comprising: forming a plurality of word line structures on opposite surfaces of the fin structure before forming the polysilicon layer.

3. The fabrication method according to claim 2, wherein the substrate includes an array region and a peripheral region surrounding the array region, and the fin structure is formed on the array region, and the dielectric layer is formed in the array region and the peripheral region.

4. The fabrication method according to claim 3, further comprising: forming a first dielectric portion on an upper surface of the substrate in the peripheral region.

5. The fabrication method according to claim 3, wherein the polysilicon layer is conformally formed on the upper surface of the dielectric layer.

6. The fabrication method according to claim 2, wherein before forming the patterned mask, an upper surface of the bit line contact is higher than an upper surface of a portion of the polysilicon layer surrounding the bit line contact.

7. The fabrication method according to claim 3, wherein forming the polysilicon layer includes: depositing a polysilicon material thin film over the substrate; doping a first portion of the polysilicon material thin film located in the peripheral region of the substrate; and reducing a thickness of a second portion of the polysilicon material thin film in the array region of the substrate surrounded by the peripheral region.

8. The fabrication method according to claim 2, further comprising: forming a first multi-layer structure over the substrate before forming the patterned mask.

9. The fabrication method according to claim 8, wherein the first multi-layer structure is patterned before patterning the bit line contact and the polysilicon layer.

10. The fabrication method according to claim 8, wherein the first multi-layer structure includes a first layer, a second layer, and a third layer, and the first layer, the second layer, and the third layer are patterned by different etching operations.

11. The fabrication method according to claim 2, wherein forming the patterned mask includes: forming a second multi-layer structure over the substrate; patterning a first layer of the second multi-layer structure, thereby forming a patterned first layer; forming a spacer layer to surround the patterned first layer; performing a spacer etch on the spacer layer, thereby forming a spacer structure; and using the spacer structure as a mask to pattern a second layer of the second multi-layer structure, thereby forming a patterned second layer.

12. The fabrication method according to claim 11, wherein forming the patterned mask further includes: Before patterning the second layer, remove the patterned first layer.

13. The manufacturing method according to claim 11, wherein the patterned second layer becomes the patterned mask, and a pattern of the patterned second layer is transferred to the polysilicon layer and the bit line contact.

14. A method for manufacturing a semiconductor structure, comprising: providing a substrate including a plurality of fin structures in an array region of the substrate; forming an oxide layer over the substrate, wherein the oxide layer covers the plurality of fin structures; forming a plurality of word line structures alternately arranged with the plurality of fin structures, wherein an upper surface of the oxide layer is aligned with an upper surface of the plurality of word line structures; forming a polysilicon layer over the substrate, the plurality of word line structures, the plurality of fin structures, and the oxide layer; forming a plurality of bit line contacts over the plurality of fin structures, wherein the plurality of bit line contacts penetrate the polysilicon layer; forming a patterned layer over the polysilicon layer; and using the patterned layer as a mask to pattern the polysilicon layer, thereby forming a patterned polysilicon layer, wherein a sidewall of the patterned polysilicon layer is straight, wherein a material of the plurality of bit line contacts includes polysilicon.

15. The manufacturing method according to claim 14, wherein the substrate includes a peripheral region surrounding the array region, the oxide layer also covers the peripheral region, and the manufacturing method further includes: forming a first mask layer covering the array region of the substrate and exposing the peripheral region; partially removing the oxide layer in the peripheral region, thereby forming a step on an isolation of the substrate; forming the polysilicon layer over the array region and the peripheral region, wherein the polysilicon layer is conformal with the step; doping the polysilicon layer in the peripheral region, thereby forming a doped portion of the polysilicon layer; forming a second mask layer to partially cover the doped portion of the polysilicon layer; and and reducing a thickness of a portion of the polysilicon layer exposed through the second mask layer.

16. The manufacturing method according to claim 15, wherein the thickness of the polysilicon layer before doping is 20 to 50 nanometers, and the thickness of the polysilicon layer is reduced to a range of 10 to 20 nanometers.

17. The manufacturing method according to claim 15, wherein after reducing the thickness of the polysilicon layer, the polysilicon layer has a first step conformal with the step of the isolation and a second step at a boundary of the second mask layer.

18. The manufacturing method according to claim 15, wherein a thickness of an undoped portion of the polysilicon layer in the array region is less than a thickness of the doped portion of the polysilicon layer.

19. The manufacturing method according to claim 14, wherein a thickness of the oxide layer is about 5 nanometers, and a material of the plurality of bit line contacts includes polysilicon.

20. The manufacturing method according to claim 14, wherein the patterning of the plurality of bit line contacts is performed while using the patterning layer as a mask to pattern the polysilicon layer, wherein the bit line contacts are doped with a plurality of N-type dopants, and wherein an upper surface of the bit line contacts is about 3 nanometers higher than an upper surface of the polysilicon layer in the array region.

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