Vertical memory device with non-functional posts

Abstract

Solid state memory techniques are disclosed. In one example, a solid state memory component may include a plurality of bit lines, source lines, and a plurality of functional (510) and non-functional (510 ') memory pillars. Each non-functional memory pillar (510 ') is electrically isolated from one or both of the plurality of bit lines and source lines. In another example, a solid state memory component may include a plurality of pillars located at a peripheral portion (553) of the solid state memory component, and a memory cell adjacent each pillar. Associated systems and methods are also disclosed.

Description

Technical Field

[0001] This application is a divisional application of the application with application number: 201780053809.2 and invention name: Vertical Memory Device with Non-Functional Cylinders. The embodiments described herein particularly relate to computer machine memory, and more specifically, to solid-state memory devices. Background Art

[0002] NAND flash memory devices are a common type of flash memory device, named after the logic form used to arrange the basic memory cell configuration. Generally, the memory cell array of a NAND flash memory is arranged such that the control gates of each memory cell in a row of the array are connected to form access lines, such as word lines. The columns of the array include source-to-drain strings of memory cells (commonly referred to as NAND strings) connected in series between a pair of select lines (source select line and drain select line).

[0003] "Column" refers to a group of memory cells commonly coupled to a local data line (such as a local bit line). It does not require any specific orientation or linear relationship, but rather refers to the logical relationship between the memory cells and the data line. The source select line includes a source select gate at each intersection between the NAND string and the source select line, and the drain select line includes a drain select gate at each intersection between the NAND string and the drain select line. Each source select gate is connected to a source line, while each drain select gate is connected to a data line, such as a column bit line.

[0004] One way to increase the density of a memory device is to form a stacked memory array, for example, a three-dimensional (3D) memory array commonly referred to. For example, one type of three-dimensional memory array may include cylinders of stacked memory elements, such as substantially vertical NAND strings. Brief Description of the Drawings

[0005] Through the following detailed description that illustrates various inventive embodiments by way of example in conjunction with the attached Figure 1 drawings, the inventive features and advantages will become apparent; and in which: Figure 1 Shows a portion of a solid-state memory component according to an example; Figure 2 Shows Figure 1 a top view of the memory cylinders and memory cells of the solid-state memory component; Figure 3 Shows Figure 1 a side view of the memory cylinders and memory cells of the solid-state memory component; Figure 4 Shows a portion of a solid-state memory component according to another example; Figure 5AShows a general layout of a solid-state memory component according to an example; Figure 5B Shows Figure 5A a general layout of a memory block of a solid-state memory component; Figure 6 Shows a cross-sectional view of a typical solid-state memory component; Figure 7 Shows a cross-sectional view of a solid-state memory component according to an example; Figure 8A Shows a top view of a memory array portion of a solid-state memory component after pillar formation according to an example; Figure 8B Is an image comparing the memory array portion of a solid-state memory component after pillar formation; Figure 9 Is a schematic diagram of an example memory device; and Figure 10 Is a schematic diagram of an example computing system.

[0006] Reference will now be made to the example embodiments shown, and they will be described herein using specific language. However, it is understood that no limitation of the scope of the disclosure or of a particular inventive embodiment is thereby intended. Detailed Description

[0007] Before disclosing and describing the inventive embodiments, it is to be understood that no limitation to the specific structures, process steps, or materials disclosed herein is intended, but that equivalents thereof, as would be known to those of ordinary skill in the relevant art, are also included. It should also be understood that the terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting. Like reference numerals in different figures represent like elements. The numbers provided in the flowcharts and processes are provided to clarify the steps and operations shown and do not necessarily indicate a particular order or sequence. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains.

[0008] As used in this written description, the singular forms "a", "an", and "the" include explicit support for plural referents, unless the context clearly dictates otherwise. Thus, for example, reference to "a layer" includes a plurality of such layers.

[0009] In this disclosure, terms such as "comprise", "comprising", "contain", and "have" can have the meanings given to them in U.S. patent law and can mean "include", "including", etc., and are generally interpreted as open terms. The term "consisting of" is a closed term and only includes the components, structures, steps, etc. specifically listed in connection with such terms, and is consistent with U.S. patent law. "Consisting essentially of" has the meaning commonly given to it in U.S. patent law. Specifically, such terms are generally closed terms, except for allowing the inclusion of additional items, materials, components, steps, or elements that do not materially affect the basic and novel characteristics or functions of the item(s) with which they are used. For example, trace elements that are present in a composition but do not affect the nature or characteristics of the composition would be permissible if present under the language of "consisting essentially of", even if not explicitly recited in the list of items following such terms. When open terms such as "include" or "comprise" are used in the written description, it should be understood that direct support should also be borne for the language of "consisting essentially of" as well as the language of "consisting of", as if explicitly stated, and vice versa.

[0010] The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims are used to distinguish similar elements and not necessarily to describe a particular sequence or temporal order. It should be understood that such terms are interchangeable under appropriate circumstances such that the embodiments described herein, for example, can operate in sequences other than those shown or otherwise described herein. Similarly, if a method is described herein as comprising a series of steps, the order of such steps provided herein is not necessarily the only order in which such steps can be performed, and certain of the described steps may be omitted and / or certain other steps not described herein may be added to the method.

[0011] The terms "left", "right", "front", "rear", "top", "bottom", "above", "below", etc. (if any) in the description and claims are used for descriptive purposes and not necessarily to describe a permanent relative position. It should be understood that such terms are interchangeable under appropriate circumstances such that the embodiments described herein, for example, can operate in orientations other than those shown or otherwise described herein.

[0012] As used herein, the term "coupled" is defined as directly or indirectly connecting in an electrical or non - electrical manner. Objects described herein as being "adjacent" to each other may be in physical contact with each other, in close proximity to each other, or in the same general field or area, as appropriate to the context in which the term is used.

[0013] As used herein, comparative terms such as "increased", "decreased", "better", "worse", "higher", "lower", "enhanced", "maximized", and "minimized", etc. refer to the attributes of a device, component, or activity that are measurably different in the state of the art from other comparable devices, components, or activities, or different iterations or embodiments of the same device or attribute. For example, a data region with an "increased" risk of corruption may refer to a region of a memory device that is more likely to have a write error than other regions in the same memory device. Multiple factors can contribute to such an increased risk, including location, fabrication process, the number of program pulses applied to the region, etc.

[0014] As used herein, the term "substantially" refers to the complete or nearly complete extent or degree of an action, characteristic, property, state, structure, item, or result. For example, an object that is "substantially" enclosed will mean that the object is completely enclosed or nearly completely enclosed. In some cases, the exact admissible degree of deviation from absolute completeness depends on the specific context. However, generally speaking, being nearly complete will result in the same overall outcome as if absolute and total completeness had been achieved. The use of "substantially" also applies to negative meanings referring to the complete or nearly complete absence of an action, characteristic, property, state, structure, item, or result. For example, a composition that is "substantially free" of particulates will mean that there are no particulates, or so nearly free of particulates that the effect will be the same as if there were no particulates. In other words, a composition that is "substantially free" of a component or element may actually still contain such an item, as long as it has no measurable effect.

[0015] As used herein, the term "about" is used to provide flexibility to the endpoints of a numerical range by indicating that a given value may be "slightly higher" or "slightly lower" than the endpoint.

[0016] As used herein, for convenience, multiple items, structural elements, compositional elements, and / or materials may appear in a common list. However, these lists should be understood as if each member of the list were individually and uniquely identified. Thus, without contrary indication, one should not construe a single member of such a list as a de facto equivalent of any other member of the same list solely based on its presence in a common group.

[0017] Concentrations, quantities, dimensions, and other numerical data may be expressed or presented herein in a range format. It is to be understood that the use of this range format is for convenience and brevity only and should therefore be interpreted flexibly as including not only the numerical values explicitly recited as the limits of the range but also all individual numerical values or sub-ranges subsumed within that range as if each individual numerical value and sub-range were explicitly recited. By way of illustration, a numerical range of "about 1 to about 5" should be interpreted as including not only the explicitly stated values of about 1 to about 5 but also individual values and sub-ranges within the indicated range. Thus, included in this numerical range are individual values such as 2, 3, and 4 and sub-ranges such as from 1 - 3, from 2 - 4, and from 3 - 5, as well as the individual 1, 2, 3, 4, and 5.

[0018] This same principle applies to ranges that recite only one numerical value as a minimum or a maximum. Additionally, this interpretation should apply regardless of the breadth of the range or the nature of the feature being described.

[0019] As used throughout this specification, the term "example" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one embodiment. Thus, the appearances of the phrase "in an example" in various places in this specification are not necessarily all referring to the same embodiment. The phrase "in one example" or "in one aspect" as used herein are not necessarily all referring to the same example or aspect.

[0020] Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In this specification, numerous specific details are provided, such as, for example, layout examples, distances, network examples, etc. However, those of ordinary skill in the relevant art will recognize that many modifications are possible without one or more of the specific details, or using other methods, components, layouts, measurements, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail but are to be considered fully within the scope of the present disclosure.

[0021] Example embodiments A preliminary overview of the technical embodiments is provided below and then the specific technical embodiments are described in more detail. This preliminary overview is intended to help the reader more quickly understand the technology and is not intended to identify the key or essential features of the technology nor to limit the scope of the claimed subject matter.

[0022] Certain processes for manufacturing NAND flash memory devices are susceptible to non-uniformities and misalignments resulting from the formation of memory cell structures in the memory array. Such misalignments can lead to a significant degradation in performance and reliability. Accordingly, solid-state memory components are disclosed that minimize or eliminate non-uniformities and misalignments during manufacturing.

[0023] One exemplary mechanism that can minimize or eliminate such misalignment issues is by including non-functional memory structures in the memory component. In one aspect, a peripheral region outside the memory array includes memory structures to provide such benefits. In one example, a solid-state memory component can include multiple bit lines, source lines, and multiple non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the multiple bit lines and source lines. In another example, a solid-state memory component can include multiple pillars located in the peripheral portion of the solid-state memory component, and memory cells adjacent to each pillar.

[0024] Associated systems and methods are also disclosed.

[0025] Referring Figure 1 , a portion of the solid-state memory component 100 is shown. Generally, this portion of the solid-state memory component includes a memory pillar 110 and memory cells 120a-n (i.e., a string 125 of memory cells, such as a NAND string) located adjacent to the memory pillar 110. Any suitable number of memory cells can be included. The memory pillar 110 can serve as the channel region for the memory cells 120a-n, which can be coupled in series. For example, during the operation of one or more of the memory cells 120a-n in the string, a channel can be formed in the memory pillar 110. The memory pillar 110 and the string of memory cells 120a-n can be vertically oriented, for example, in a three-dimensional memory array. For example, memory cell 120a is located in a vertical plane (e.g., closer to the top of the memory array) above the vertical plane in which memory cell 120n is located (e.g., closer to the bottom of the memory array). The memory cells 120a-n can have any suitable structure. For context and illustrative purposes, a memory cell structure is provided. Thus, it should be recognized that suitable memory cell structures can differ from the memory cell structures disclosed herein.

[0026] Each memory cell 120a-n in this example can have a charge storage structure (e.g., it can be a conductive floating gate, a dielectric charge trap, etc.). For example, as shown in Figure 2 and 3As shown, the memory cell 120 may have a charge storage structure 121. Each memory cell 120a-n may also have a tunnel dielectric inserted between its charge storage structure and the pillar 110. For example, the memory cell 120 may have a tunnel dielectric 113 inserted between the charge storage structure 121 and the pillar 110. In addition, each memory cell 120a-n may have a control gate (e.g., as part of an access line or coupled to an access line, such as a word line). For example, the memory cell 120 may include a control gate 130. Each memory cell may have one or more dielectric materials or dielectric layers inserted between its charge storage structure and the control gate. For example, the memory cell 120 may include dielectric layers 123 and 124 inserted between the charge storage structure 121 and the control gate 130.

[0027] Each memory cell 120 may be a non-volatile memory cell and may have a charge storage structure 121, for example, a floating gate that may be a conductor (such as polysilicon), a charge trap that may be a dielectric, etc. Non-limiting examples of dielectrics suitable for charge trapping include nitrides, high dielectric constant (high-K) dielectrics, such as aluminum oxide (Al2O3) having a K of about 10, which has embedded conductive particles (such as nanoparticles), for example, embedded metal particles or embedded nanocrystals (such as silicon, germanium, or metal crystals), silicon-rich dielectrics, or SiON / Si3N4.

[0028] Further referring to Figure 1 , a dielectric 140 may be inserted between consecutive adjacent memory cells 120a-n in the string 125. For example, the dielectric 140 may be inserted between at least the floating gates 121, dielectrics 123, 124, and the control gate 130 of consecutive adjacent memory cells 120a-n. A dielectric 141 may be inserted between one end of the string 125 (e.g., memory cell 120a) and the select gate 111, and a dielectric 142 may be inserted between the opposite end of the string 125 (e.g., memory cell 120n) and the select gate 112, as Figure 1 shown.

[0029] In some embodiments, the charge storage structure 121 is a charge trap, and the tunnel dielectric 122, charge storage structure 121, and dielectrics 123, 124 may form a continuous structure that may be shared by two or more memory cells 120a-n (e.g., may be common to one or more memory cells). For example, such a structure may be shared or common to all memory cells 120a-n.

[0030] Each memory cell 120a-n may have a thickness (e.g., channel length) 126. For example, memory cells 120a-n may have the same channel length regardless of where the memory cell is located in string 125. In some embodiments, at least one channel length of a memory cell may be different from another channel length of another memory cell.

[0031] In some embodiments, string 125 may be inserted between and serially coupled to "dummy" memory cells (not shown) to form a string of memory cells that includes string 125 and the "dummy" memory cells. For example, one or more "dummy" memory cells may be inserted between and serially coupled to memory cell 120a of string 125 and select gate 111, and / or one or more "dummy" memory cells may be inserted between and serially coupled to memory cell 120n of string 125 and select gate 112. Each "dummy" memory cell may be configured in a manner similar to memory cells 120a-n and may have the same components as them.

[0032] Each memory cell 120a-n of string 125 may be serially coupled to and located between a select gate (e.g., drain select gate) 111 adjacent (e.g., in contact with) pillar 110 and a select gate (e.g., source select gate) 112 adjacent (e.g., in contact with) pillar 110. For a functional memory pillar, pillar 110 is electrically coupled to a data line (e.g., bit line 116), indicated at 117. Thus, select gate 111 may selectively couple string 125 to the data line (e.g., bit line 116). Additionally, for a functional memory pillar, pillar 110 is electrically coupled to source line 118, indicated at 119. Thus, select gate 112 may selectively couple string 125 to source line 118. For example, select gate 111 may be serially coupled to memory cell 120a, and select gate 112 may be serially coupled to memory cell 120n. Select gates 111 and 112 may each include a gate dielectric 113 adjacent (e.g., in contact with) pillar 110 and a control gate 114 adjacent (e.g., in contact with) the corresponding gate dielectric 113.

[0033] In contrast, non-functional or "dummy" memory columns are electrically isolated from the data lines or bit lines 116 and / or from the source lines 118. In other words, the non-functional memory columns are not electrically coupled to the data lines or bit lines 116 at 117a and / or 117b, and / or are not electrically coupled to the source lines 118 at 119a and / or 119b. Thus, in some embodiments, the non-functional memory columns may have some or all of the characteristics of the functional memory columns described above (e.g., the same construction, the same materials, and adjacent memory cells), but differ in that they lack an electrical connection to the data or bit lines 116 and / or lack an electrical connection to the source lines 118. The non-functional columns can be of any suitable size. In one aspect, the size of the non-functional columns can be different from that of the functional columns. In another aspect, the size of the non-functional columns can be the same as, or substantially the same as, the size of the functional columns.

[0034] Figure 4 FIG. 4 shows a portion of a computer memory component 200 according to another example. In this case, strings 225 and 225' of memory cells 220a-n and 220a'-n' can be adjacent (e.g., in contact) to columns 210 and 210', respectively. As shown, columns 210, 210' can be positioned laterally or side-by-side with respect to each other. Each of strings 225 and 225' can include memory cells coupled in series.

[0035] A semiconductor segment 244 (which can be of the same material as columns 210, 210') can physically couple column 210 to column 210' to form a semiconductor structure 215 that includes columns 210 and 210'. The semiconductor segment 244 can be substantially horizontal, in contrast to columns 210, 210', which can be substantially vertical. The semiconductor segment 244 can be a conductor 245, which can generally be formed of one or more conductive materials (e.g., conductive doped polysilicon). When an appropriate bias is applied to conductor 245, the semiconductor segment 244 can electrically couple string 225 in series with string 225'. For example, the semiconductor segment 244 and conductor 245 can form a connector gate 246 that selectively couples string 225 in series with string 225'. The selectively coupled strings 225 and 225' can form part of a single string of memory cells (e.g., memory cells 220a-n of string 225 and memory cells 220a'-n' of string 225').

[0036] The strings of such memory cells can be located between and serially coupled to select gates 211 and 212. For example, each memory cell 220a-n, 220a'-n' can be serially coupled to select gate 211 and select gate 212 and can be located therebetween. For a functional memory stack, stacks 210, 210' are electrically coupled to a data line (e.g., bit line 216), indicated at 217. Thus, select gate 211 can selectively couple strings 225, 225' to bit line 216. Additionally, for a functional memory stack, stacks 210, 210' are electrically coupled to source line 218, indicated at 219. Thus, select gate 212 can selectively couple strings 225, 225' to source line 218. Note that each memory cell 220a-n of string 225 can be located between and serially coupled to select gate 211 and connector gate 246, and each memory cell 220a'-n' of string 225' can be located between and serially coupled to connector gate 246 and select gate 212.

[0037] Conversely, non-functional or "dummy" memory stacks are electrically isolated from the data line or bit line 216 and / or electrically isolated from the source line 218. In other words, non-functional memory stacks are not electrically coupled to the data line or bit line, or both the data line and bit line 216, at 217a and / or 217b, and / or are not electrically coupled to source line 218 at 219a and / or 219b. Thus, in some embodiments, non-functional memory stacks can have some or all of the characteristics of the above-described functional memory stacks (e.g., the same construction, the same materials, and adjacent memory cells), but differ in that they lack an electrical connection to the data or bit line 216 and / or lack an electrical connection to the source line 218.

[0038] Typical solid-state memory components do not include non-functional memory stacks with or without associated memory cell features. In one aspect, the techniques of the present disclosure provide for including non-functional memory stacks and associated memory cell features in solid-state memory components. It should be appreciated that typical solid-state memory components according to the present disclosure can include many non-functional stacks, functional memory stacks, and associated memory cells, bit lines, etc., as shown in Figure 1 and 4 shown.

[0039] Figure 5AAn example of the general layout or arrangement of the solid-state memory component 300 is shown. This planar view shows a memory array region (i.e., the overall or global memory array region generally indicated at 304) and a periphery (i.e., the global peripheral portion or region generally indicated at 305). The overall memory array region 304 is subdivided or partitioned into memory array blocks, where each region has a local or block memory array and a staircase. The staircase facilitates the electrical connection to the word lines connected to the memory cells in the local or block memory array. For example, a typical memory block 350 includes a local or block memory array portion or region 351 and a staircase portion or region 352.

[0040] Figure 5B Shows the general layout or arrangement of the memory block 350. This figure shows the memory array portion 351 and the staircase portion 352 in more detail. In addition, Figure 5BShows a local or block peripheral portion 353 around the memory array portion 351 and the staircase portion 352. The local or block peripheral portion 353 between memory blocks can provide space for CMOS connections and wiring. Generally, memory columns and memory cell features are not located in this area. For example, functional memory columns (i.e., columns connected to bit lines and source lines) are typically located in the memory array portion, and there are no functional or non-functional memory features in the peripheral portion of the memory component. In one aspect, the techniques of the present disclosure prepare for the formation and presence of memory columns and associated memory cell structures not only within the local or block memory array portion 351, but also outside thereof (e.g., in the local or block peripheral portion 353 and / or the global peripheral portion or region 305). Positioning memory structures (i.e., memory columns) in the peripheral portion can provide benefits in manufacturing solid-state memory components. For example, the presence of non-functional memory features in the peripheral portion of the memory component can improve topography uniformity, alignment tolerance, and cell process uniformity and capabilities. Accordingly, the memory structures (i.e., memory columns) in the peripheral portion can be numerous and widely distributed throughout the peripheral portion, sufficient to achieve the manufacturing benefits described herein. Thus, relatively few or isolated memory structures in the peripheral portion may not be sufficient to provide manufacturing benefits. Therefore, when viewed in a plan view or a top view, the manufacturing benefits can be achieved by including sufficient memory structures to occupy a sufficient area of the peripheral portion. In one aspect, the area of the peripheral portion occupied by the memory structures (i.e., memory columns) (e.g., the local or block peripheral portion 353 or the general memory array region 304) can be greater than 25%. In another aspect, the area of the peripheral portion occupied by the memory structures (i.e., memory columns) (e.g., the local or block peripheral portion 353 or the general memory array region 304) can be greater than 50%. In yet another aspect, the area of the peripheral portion occupied by the memory structures (i.e., memory columns) (e.g., the local or block peripheral portion 353 or the general memory array region 304) can be greater than 75%. By any of these minimum peripheral percentage values, it should be recognized that the maximum area occupied by the memory structures can not exceed the actual limit dictated by the geometry of the memory structures. For example, a plurality of memory structures having circular areas in a plan view can not occupy 100% of a rectangular or other polygonal area, so there will be some unoccupied space between adjacent memory structures. Since the benefits of non-functional memory features are realized during manufacturing, these features can optionally be removed before forming the final product.

[0041] In a final product and / or at an appropriate manufacturing stage, functional memory pillars may be located in the local or block memory array portion 351 of the computer memory component 300, and non-functional memory pillars (i.e., electrically isolated or not electrically connected to bit lines and / or source lines) may be located in the peripheral portion of the computer memory component 300 (e.g., local or block peripheral portion 353 and / or global peripheral portion or region 305). In some embodiments, non-functional memory pillars may even be located in the local or block memory array portion 351 of the computer memory component 300 as needed, for example, to fill spaces within the memory array portion 351 that do not have memory features. In one aspect, functional and non-functional memory pillars may be evenly distributed across the computer memory component 300, including the memory array portion and the peripheral portion.

[0042] Memory pillars and memory cells may be formed by any suitable method. For example, pillar openings may be formed by etching through multiple alternating layers of conductive and dielectric material layers. The conductive layer may include any suitable conductive material, such as polysilicon, which may be conductively doped (e.g., to become N+ type conductivity). The dielectric layer may include any suitable dielectric material, such as oxides (e.g., silicon oxide), oxynitrides (e.g., silicon oxynitride), etc. In one aspect, precursors of the solid-state memory component may include pillar openings in the peripheral portion, as well as in the memory array portion.

[0043] After forming the pillar openings, the pillar openings may be filled with a suitable conductor or semiconductor material to form pillars, with or without forming memory cells adjacent to the pillar openings.

[0044] To form functional memory pillars, pillars having associated memory cells may be electrically coupled to bit lines (e.g., at positions 117a or 117b in Figure 1 or at positions 217a or 217b in Figure 4 and to source lines (e.g., at positions 119a or 119b in Figure 1 or at positions 219a or 219b in Figure 4 ). Generally, such electrical connections may be achieved by forming an opening (e.g., by etching) in a dielectric layer (which is disposed on a given conductor) and then disposing a conductive material in the opening, which may then be electrically coupled to the desired component. For example, Figure 1 's pillar 110 may be electrically coupled to bit line 116 by a conductive material disposed in an opening in the dielectric material on opposite sides of the select gate 111 at positions 117a and 117b. Figure 1 's pillar 110 may be electrically coupled to source line 118 by a conductive material disposed in an opening in the dielectric material on opposite sides of the select gate 112 at positions 119a and 119b. Similarly,Figure 4 The cylinder 210 can be electrically coupled to the bit line 216 through a conductive material (which is disposed in an opening of a dielectric material on the opposite side of the select gate 211 passing through positions 217a and 217b). Figure 4 The cylinder 210 can be electrically coupled to the source line 218 through a conductive material (which is disposed in an opening of a dielectric material on the opposite side of the select gate 212 passing through positions 219a and 219b). The conductive material can be any suitable material, such as polysilicon, which can be conductively doped (e.g., to become N+ type conductivity).

[0045] To form a non-functional cylinder, the cylinder with or without an associated memory cell is electrically isolated from the bit line (e.g., at position 117a or 117b in Figure 1 or position 217a or 217b in Figure 4 and / or the source line (e.g., at position 119a or 119b in Figure 1 or position 219a or 219b in Figure 4 ). Generally, the cylinder can be electrically isolated from the bit line and / or the source line by maintaining a dielectric layer between the cylinder and the bit line and / or the source line. For example, by maintaining a dielectric material (i.e., no opening for a conductor) on at least one opposite side of the select gate 111 at positions 117a and 117b, Figure 1 the cylinder 110 can be electrically isolated from the bit line 116. By maintaining a dielectric material (i.e., no opening for a conductor) on at least one opposite side of the select gate 112 at positions 119a and 119b, Figure 1 the cylinder 110 can be electrically isolated from the source line 118. Similarly, by maintaining a dielectric material (i.e., no opening for a conductor) on at least one opposite side of the select gate 211 at positions 217a and 217b, Figure 4 the cylinder 210 can be electrically isolated from the bit line 216. By maintaining a dielectric material (i.e., no opening for a conductor) on at least one opposite side of the select gate 212 at positions 219a and 219b, Figure 4 the cylinder 210 can be electrically isolated from the source line 218.

[0046] If a memory cell is to be formed adjacent to a cylinder (e.g., a functional cylinder or a non-functional cylinder), a series of processes including etching and deposition processes can be performed by accessing the memory cell location through the cylinder opening. The memory cell structures that can be formed include charge storage structures (e.g., floating gates), control gates, tunnel dielectrics, blocking dielectrics, etc. Many processes for forming memory cells can cause the layer or stratification of conductive and dielectric materials to expand or grow, which is called "stratification expansion".

[0047] This expansion occurs in Figure 6is shown, which shows a cross-sectional view of a typical solid-state memory component 400. As shown, the computer memory component 400 includes a memory array portion 451, a stepped portion 452, and a peripheral portion 453. The memory array portion 451 includes functional memory columns 410. No memory columns are located in the peripheral portion 453. The edge region of the memory array portion 451 adjacent to the peripheral portion 453 is indicated at 454. Figure 6 shows the differential expansion in the vertical direction 406 of various regions or portions of the computer memory component 400 due to delamination expansion after forming the column openings.

[0048] In the case where there are no columns in the stepped region 452 or the peripheral portion 453, these regions experience relatively less expansion in the vertical direction 406 compared to the memory array portion 451. The result of this differential vertical expansion can be a surface topography that can lead to non-uniform or inconsistent layer thicknesses, as illustrated by the thickness variations of the topmost layer(s) 455 (e.g., more oxide and poly residual remain at the edge 454 of the memory array and in the periphery 453 compared to the rest of the array). It should be noted that in Figure 6 there is an alternating layer of conductive and dielectric materials above the memory columns 410 for forming a second "deck" of the memory columns, which can be electrically coupled to a lower or first deck of the memory columns 410. Thus, the differential vertical expansion of the memory array portion 451 and the peripheral portion 453 can adversely affect many processes in the manufacture of the finished computer memory component.

[0049] The transition between high-density and low-density column pattern regions can be problematic for certain processes (e.g., resulting in increased topography). As described above, functional memory columns and non-functional memory columns can be evenly distributed across the computer memory component, including the memory array portion and the peripheral portion. This even distribution can minimize or eliminate the transition between high-density and low-density column pattern regions, thereby minimizing or eliminating problems that may occur in certain processes. It should be recognized that due to manufacturing requirements, the columns can be evenly distributed and still have small regions without columns (e.g., between the memory array portion and the peripheral portion).

[0050] In addition to the vertical expansion 406, various regions or portions of the computer memory component 400 can also experience expansion in the horizontal direction 407 due to delamination expansion after forming the column openings. This aspect of delamination expansion is discussed in more detail below.

[0051] Compared with Figure 6 the delamination expansion of a typical solid-state memory component in Figure 7 shows the delamination expansion of a computer memory component 500 according to an example of the present disclosure. Compared withFigure 6 Similar to the typical memory component 400, Figure 7 the memory component 500 includes a memory array section 551, a stepped section 552, and a peripheral section 553. The memory array section 551 includes functional memory columns 510. The edge region of the memory array section 551 near the peripheral section 553 is indicated at 554. In this case, the computer memory component 500 includes memory cells (i.e., non-functional memory cells 510') in the peripheral section 553. As a result, due to the presence of memory columns in both regions, the difference expansion between the memory array section 551 and the peripheral section 553 in the vertical direction 506 is reduced (i.e., reduced topography), which causes these regions with columns to expand in a similar manner.

[0052] Referring to Figure 8A addresses the effect of hierarchical expansion in the horizontal direction 507. Hierarchical expansion can have the effect of causing the columns to become misaligned during subsequent processes. Figure 8A A top view of the memory array section 551 after the columns 510 are formed is shown. At this stage, in order to form the functional memory columns, openings 555 are formed in the dielectric layer above the tops of the columns 510. These openings are typically formed by etching, which uses a mask to position the openings. In a typical memory component configuration where there are no memory structures (i.e., columns) in the peripheral section, hierarchical expansion causes the columns to move horizontally, resulting in misalignment between the tops of the columns and the positions of the mask openings. The increased oxide layer thickness at the memory array edge caused by the topography resulting from vertical expansion also makes it difficult to optically align the openings. As a result, there is a horizontal misalignment between the columns and the openings formed in the dielectric, which becomes more pronounced as the distance from the center of the memory component (e.g., memory block) or wafer increases, such as in the edge region of the memory array or wafer. This is shown in Figure 8B the image of, generally indicated at 556 and 557. After the openings are formed in the dielectric layer, a conductive material is disposed in the openings to form an electrical connection with the bit lines. Due to the horizontal misalignment, these connections may be damaged or lack integrity. Therefore, the horizontal misalignment caused by hierarchical expansion has a negative impact on the electrical connection between the columns and the bit lines. In contrast to the configuration of a typical memory component, the memory component configuration according to the present disclosure, which includes memory structures (i.e., columns) in the peripheral section, can minimize the horizontal misalignment caused by hierarchical expansion. As Figure 8A shown, the columns 510 are aligned with the openings 555 in the dielectric. Figure 8B This situation is also generally shown at 558. This is due to the presence of memory columns in both the memory array section and the peripheral section, which causes this region to expand in a similar (i.e., uniform) manner, thereby minimizing the expansion difference between the central region and the outer region of the memory component or wafer.

[0053] Forming memory pillars (i.e., memory pillar openings) in the memory array portion and the peripheral portion can be beneficial for any process after the formation of the pillars (or pillar openings), such as any dry or wet (e.g., chemical mechanical planarization (CMP)) process that can be used in the manufacture of solid-state memory components. Thus, by forming memory pillars (i.e., memory pillar openings) in the memory array portion and the peripheral portion of the solid-state memory component, either alone or in combination with associated memory cell features, non-uniformities and misalignments during the manufacture of the solid-state memory component can be minimized.

[0054] Although the present invention is provided in the context of a NAND flash memory device, it should be recognized that certain aspects of the present disclosure are also applicable to NOR flash memory devices.

[0055] Figure 9 is a schematic representation of a memory device 601 according to an example of the present disclosure. The memory device may include a substrate 660 and a solid-state memory component 600 operatively coupled to the substrate 660 as disclosed herein. In one aspect, the memory device 601 may include any suitable electronic component 661, such as a CPU, GPU, memory controller, video decoder, audio decoder, video encoder, camera processor, system memory, and / or modem.

[0056] Figure 10 Illustrates an example computing system 702. The computing system 702 may include a memory device 701 as disclosed herein, which is coupled to a motherboard 770. In one aspect, the computing system 702 may further include a processor 771, a memory device 772, a radio 773, a heat sink 774, ports 775, slots, or any other suitable device or component, which may be operatively coupled to the motherboard 770. The computing system 702 may include any type of computing system, such as a desktop computer, a laptop computer, a tablet computer, a smart phone, a wearable device, a server, etc. Other embodiments do not need to include Figure 10 all the features specified in Figure 10 and may include

[0057] The circuits used in electronic components or devices (such as die) of a memory device may include hardware, firmware, program code, executable code, computer instructions, and / or software. The electronic components and devices may include a non-transitory computer-readable storage medium, which may be a computer-readable storage medium that does not include signals. In the case of executing program code on a programmable computer, the computing devices described herein may include a processor, a storage medium readable by the processor (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device. The volatile and non-volatile memory and / or storage elements may be RAM, EPROM, flash drive, optical disk drive, magnetic hard disk drive, solid state drive, or other media for storing electronic data. Nodes and wireless devices may also include a transceiver module, a counter module, a processing module, and / or a clock module or timer module. One or more programs that can implement or utilize any of the techniques described herein may use an application programming interface (API), reusable controls, etc. Such programs may be implemented using a high-level procedural or object-oriented programming language to communicate with a computer system. However, the (one or more) programs may be implemented using assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language and combined with a hardware implementation.

[0058] Example The following examples relate to additional embodiments.

[0059] In one example, a solid-state memory component is provided that includes multiple bit lines, source lines, and multiple non-functional memory columns, each non-functional memory column being electrically isolated from one or both of the multiple bit lines and source lines.

[0060] In one example, a solid-state memory component includes multiple functional memory columns, each functional memory column being electrically coupled to one of the multiple bit lines and one of the source lines.

[0061] In one example of a solid-state memory component, the multiple functional memory columns and the multiple non-functional memory columns are evenly distributed across the solid-state memory component.

[0062] In one example of a solid-state memory component, the multiple functional memory columns are located in the memory array portion of the memory component, and the multiple non-functional memory columns are located in the peripheral portion of the solid-state memory component.

[0063] In one example of a solid-state memory component, the multiple functional memory columns and the multiple non-functional memory columns are vertically oriented.

[0064] In one example of a solid-state memory component, memory cells are adjacent to each functional memory column and non-functional memory column.

[0065] In one example of a solid-state memory component, each memory cell includes a charge storage structure.

[0066] In one example of a solid-state memory component, the charge storage structure is a floating gate.

[0067] In one example of a solid-state memory component, each memory cell includes a control gate.

[0068] In one example of a solid-state memory component, each memory cell includes a tunnel dielectric adjacent to a functional or non-functional memory pillar, a charge storage structure adjacent to the tunnel dielectric, a blocking dielectric adjacent to the charge storage structure, and a control gate adjacent to the blocking dielectric.

[0069] In one example of a solid-state memory component, strings of memory cells adjacent to functional memory pillars are coupled in series.

[0070] In one example of a solid-state memory component, at least some of the plurality of non-functional memory pillars are located in a peripheral portion of the solid-state memory component.

[0071] In one example of a solid-state memory component, a memory cell is adjacent to each non-functional memory pillar.

[0072] In one example, a solid-state memory component is provided that includes a plurality of pillars located in a peripheral portion of the solid-state memory component and memory cells adjacent to each pillar.

[0073] In one example of a solid-state memory component, each memory cell includes a charge storage structure.

[0074] In one example of a solid-state memory component, the charge storage structure is a floating gate.

[0075] In one example of a solid-state memory component, each memory cell includes a control gate.

[0076] In one example of a solid-state memory component, each memory cell includes a tunnel dielectric adjacent to a pillar, a charge storage structure adjacent to the tunnel dielectric, a blocking dielectric adjacent to the charge storage structure, and a control gate adjacent to the blocking dielectric.

[0077] In one example of a solid-state memory component, some of the plurality of pillars are located in a memory array portion of the solid-state memory component.

[0078] In one example of a solid-state memory component, the plurality of pillars are uniformly distributed across the solid-state memory component.

[0079] In one example of a solid-state memory component, at least some of the pillars located in the memory array portion are electrically coupled to bit lines and source lines, and each pillar located in the peripheral portion is electrically isolated from at least one of the bit lines and source lines.

[0080] In one example, a memory device is provided that includes a substrate and a solid-state memory component operatively coupled to the substrate. The solid-state memory component has multiple bit lines, source lines, and a plurality of non-functional memory pillars, and each non-functional memory pillar is electrically isolated from one or both of the multiple bit lines and source lines.

[0081] In one example, the memory device includes a plurality of functional memory pillars, and each functional memory pillar is electrically coupled to one of the multiple bit lines and one of the source lines.

[0082] In one example of the memory device, the plurality of functional memory pillars and the plurality of non-functional memory pillars are evenly distributed across the solid-state memory component.

[0083] In one example of the memory device, the plurality of functional memory pillars are located in the memory array portion of the solid-state memory component, and the plurality of non-functional memory pillars are located in the peripheral portion of the solid-state memory component.

[0084] In one example of the memory device, the plurality of functional memory pillars and the plurality of non-functional memory pillars are vertically oriented.

[0085] In one example of the memory device, memory cells are adjacent to each functional memory pillar and non-functional memory pillar.

[0086] In one example of the memory device, each memory cell includes a charge storage structure.

[0087] In one example of the memory device, the charge storage structure is a floating gate.

[0088] In one example of the memory device, each memory cell includes a control gate.

[0089] In one example of the memory device, each memory cell includes a tunnel dielectric adjacent to the functional or non-functional memory pillar, a charge storage structure adjacent to the tunnel dielectric, a blocking dielectric adjacent to the charge storage structure, and a control gate adjacent to the blocking dielectric.

[0090] In one example of the memory device, the strings of memory cells adjacent to the functional memory pillars are coupled in series.

[0091] In one example, a memory device includes a CPU, a GPU, a memory controller, a video decoder, an audio decoder, a video encoder, a camera processor, system memory, a modem, or a combination thereof.

[0092] In one example, a memory device is provided that includes a substrate, a solid-state memory component operatively coupled to the substrate, the solid-state memory component having a plurality of pillars located in a peripheral portion of the solid-state memory component, and memory cells adjacent to each pillar.

[0093] In one example of the memory device, each memory cell includes a charge storage structure.

[0094] In one example of the memory device, the charge storage structure is a floating gate.

[0095] In one example of the memory device, each memory cell includes a control gate.

[0096] In one example of the memory device, each memory cell includes a tunnel dielectric adjacent to the pillar, a charge storage structure adjacent to the tunnel dielectric, a blocking dielectric adjacent to the charge storage structure, and a control gate adjacent to the blocking dielectric.

[0097] In one example of the memory device, some of the plurality of pillars are located in a memory array portion of the solid-state memory component.

[0098] In one example of the memory device, the plurality of pillars are evenly distributed across the solid-state memory component.

[0099] In one example of the memory device, at least some of the pillars located in the memory array portion are electrically coupled to bit lines and source lines, and each pillar located in the peripheral portion is electrically isolated from at least one of the bit lines and source lines.

[0100] In one example, a computing system is provided that includes a motherboard and a memory device operatively coupled to the motherboard. The memory device includes a substrate, a solid-state memory component operatively coupled to the substrate, the solid-state memory component having a plurality of bit lines, source lines, and a plurality of non-functional memory pillars, each non-functional memory pillar being electrically isolated from one or both of the plurality of bit lines and source lines.

[0101] In one example, a computing system is provided that includes a motherboard and a memory device operatively coupled to the motherboard. The memory device includes a substrate, a solid-state memory component operatively coupled to the substrate, the solid-state memory component having a plurality of pillars located in a peripheral portion of the solid-state memory component, and memory cells adjacent to each pillar.

[0102] In an example of a computing system, the computing system includes a desktop computer, a laptop computer, a tablet computer, a smart phone, a wearable device, a server, or a combination thereof.

[0103] In an example of a computing system, the computing system further includes a processor, a memory device, a heat sink, a radio, a slot, a port, or a combination thereof operatively coupled to a motherboard.

[0104] In one example, a method for manufacturing a solid-state memory component is provided, which includes forming a plurality of memory pillars, forming memory cells adjacent to each memory pillar, and electrically coupling only a portion of the plurality of memory pillars to a bit line and a source line such that the remaining portion of the plurality of memory pillars is electrically isolated from one or both of the bit line and the source line.

[0105] In an example of the method for manufacturing a solid-state memory component, the portion of the plurality of memory pillars that is electrically isolated from one or both of the bit line and the source line is located in a peripheral portion of the solid-state memory component.

[0106] In an example of the method for manufacturing a solid-state memory component, the portion of the plurality of memory pillars that is electrically coupled to the bit line and the source line is located in a memory array portion of the solid-state memory component.

[0107] In an example of the method for manufacturing a solid-state memory component, the plurality of memory pillars are evenly distributed across the solid-state memory component.

[0108] In an example of the method for manufacturing a solid-state memory component, forming the memory cells includes forming a charge storage structure.

[0109] In an example of the method for manufacturing a solid-state memory component, the charge storage structure is a floating gate.

[0110] In an example of the method for manufacturing a solid-state memory component, forming the memory cells includes forming a control gate.

[0111] In an example of the method for manufacturing a solid-state memory component, forming the memory cells includes forming a tunnel dielectric adjacent to the memory pillar, forming a charge storage structure adjacent to the tunnel dielectric, forming a blocking dielectric adjacent to the charge storage structure, and forming a control gate adjacent to the blocking dielectric.

[0112] In one example, a method for minimizing misalignment during solid-state memory component manufacturing is provided, which includes forming a plurality of memory pillars in a memory array portion of the solid-state memory component and forming a plurality of memory pillars in a peripheral portion of the solid-state memory component.

[0113] In one example of a method of manufacturing a solid state memory device, a plurality of memory columns are evenly distributed across the solid state memory device.

[0114] In one example, a method of manufacturing a solid state memory device includes forming memory cells adjacent to each memory column.

[0115] In one example of a method of manufacturing a solid state memory device, forming the memory cells includes forming a charge storage structure.

[0116] In one example of a method of manufacturing a solid state memory device, the charge storage structure is a floating gate.

[0117] In one example of a method of manufacturing a solid state memory device, forming the memory cells includes forming a control gate.

[0118] In one example of a method of manufacturing a solid state memory device, forming the memory cells includes forming a tunnel dielectric adjacent to the memory column, forming a charge storage structure adjacent to the tunnel dielectric, forming a blocking dielectric adjacent to the charge storage structure, and forming a control gate adjacent to the blocking dielectric.

[0119] Although the foregoing examples illustrate specific embodiments in one or more particular applications, those skilled in the art will appreciate that many modifications may be made in form, use, and implementation details without departing from the principles and concepts expressed herein.

Claims

1. A solid-state memory component, comprising: Multiple bit lines; A source line; Multiple non-functional memory columns, each non-functional memory column being electrically isolated from one or both of the multiple bit lines and the source line; Multiple functional memory columns, each functional memory column being electrically coupled to one of the multiple bit lines and one of the source lines; Wherein memory cells are adjacent to each of the functional memory columns and the non-functional memory columns; Wherein each memory cell comprises: A tunnel dielectric adjacent to the functional or non-functional memory column; A charge storage structure adjacent to the tunnel dielectric; A blocking dielectric adjacent to the charge storage structure; And A control gate adjacent to the blocking dielectric, Wherein the multiple functional memory columns are located in the memory array portion of the memory component, and at least some of the multiple non-functional memory columns are located in the peripheral portion of the solid-state memory component, Wherein the multiple functional memory columns and the multiple non-functional memory columns are vertically oriented.

2. The solid-state memory component according to claim 1, wherein the strings of the memory cells adjacent to the functional memory columns are coupled in series.

3. A memory device, comprising: A substrate; A solid-state memory component operatively coupled to the substrate, the solid-state memory component having: Multiple bit lines, A source line, Multiple non-functional memory columns, each non-functional memory column being electrically isolated from one or both of the multiple bit lines and the source line; Multiple functional memory columns, each functional memory column being electrically coupled to one of the multiple bit lines and one of the source lines; Wherein memory cells are adjacent to each of the functional memory columns and the non-functional memory columns; and Wherein each memory cell comprises: A tunnel dielectric adjacent to the functional or non-functional memory column; A charge storage structure adjacent to the tunnel dielectric; A blocking dielectric adjacent to the charge storage structure; And A control gate adjacent to the blocking dielectric, Wherein the multiple functional memory columns are located in the memory array portion of the memory component, and at least some of the multiple non-functional memory columns are located in the peripheral portion of the solid-state memory component, Wherein the multiple functional memory columns and the multiple non-functional memory columns are vertically oriented.

4. The memory device according to claim 3, wherein the multiple functional memory columns and the multiple non-functional memory columns are evenly distributed across the solid-state memory component.

5. The memory device according to claim 3, wherein the charge storage structure is a floating gate.

6. The memory device according to claim 3, wherein the strings of the memory cells adjacent to the functional memory columns are coupled in series.

7. The memory device according to claim 3, further comprising a CPU, a GPU, a memory controller, a video decoder, an audio decoder, a video encoder, a camera processor, a system memory, a modem, or a combination thereof.

8. A method for minimizing structural misalignment during the manufacture of a solid-state memory device, comprising: forming a plurality of functional memory pillars in a memory array portion of the solid-state memory device; forming a plurality of non-functional memory pillars in a peripheral portion of the solid-state memory device; forming memory cells adjacent to each of the memory pillars; forming a tunnel dielectric adjacent to the functional or non-functional memory pillars; forming a charge storage structure adjacent to the tunnel dielectric; forming a blocking dielectric adjacent to the charge storage structure; forming a control gate adjacent to the blocking dielectric; and positioning the plurality of functional memory pillars in the memory array portion of the memory device and positioning at least some of the plurality of non-functional memory pillars in the peripheral portion of the solid-state memory device, wherein the plurality of functional memory pillars and the plurality of non-functional memory pillars are vertically oriented.

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