Semiconductor device

Abstract

A semiconductor device includes a first region and a second region around the first region, and includes: a source layer; a stacked structure including a plurality of gate electrodes sequentially stacked in a first direction on the source layer and spaced apart from each other; an interlayer insulating film covering the stacked structure; a channel structure extending in the first direction, the channel structure extending into the stack structure in the first region and connected to the source layer in the first region; and a reflective structure that overlaps the interlayer insulating film in the second region in the first direction.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, methods of manufacturing semiconductor devices, and electronic systems including semiconductor devices. Background Art

[0002] As semiconductor memory devices capable of storing high-capacity data are required in electronic systems, methods of increasing the data storage capacity of semiconductor memory devices are being studied. One of the methods of increasing the data storage capacity of semiconductor memory devices proposes a semiconductor memory device including memory cells arranged three-dimensionally rather than two-dimensionally. Summary of the Invention

[0003] Generally, in some aspects, the present disclosure aims to provide semiconductor devices, electronic systems including semiconductor devices having improved yield and reliability, and methods of manufacturing semiconductor devices, which can produce semiconductor devices having improved yield and reliability.

[0004] According to some embodiments, the present disclosure aims to provide a semiconductor device including a first region and a second region surrounding the first region, the semiconductor device including: a source layer; a stacked structure including a plurality of gate electrodes sequentially stacked on the source layer while being spaced apart from each other in a first direction; an interlayer insulating film covering the stacked structure; a channel structure extending in the first direction to penetrate the stacked structure in the first region and connected to the source layer in the first region; and a reflection structure overlapping the interlayer insulating film in the second region in the first direction, wherein the reflection structure includes one or more first reflection layers and one or more second reflection layers, the one or more first reflection layers having a first refractive index, and the one or more second reflection layers being alternately stacked with the one or more first reflection layers in the first direction and having a second refractive index different from the first refractive index.

[0005] According to some embodiments, the present disclosure aims to provide a semiconductor device, the semiconductor device comprising: a peripheral circuit structure including a peripheral circuit substrate and peripheral circuit elements located on the peripheral circuit substrate; and a memory cell structure stacked on the peripheral circuit structure, the memory cell structure including a first region and a second region surrounding the first region, wherein the memory cell structure includes: a base insulating film having a first surface facing the peripheral circuit structure and a second surface opposite to the first surface; a stacked structure located on the first surface of the base insulating film and including a plurality of gate electrodes sequentially stacked with each other spaced apart; an interlayer insulating film covering the stacked structure; a source layer located on the second surface of the base insulating film; a channel structure intersecting the plurality of gate electrodes in the first region and connected to the source layer in the first region; and a reflection structure interposed between the source layer in the second region and the interlayer insulating film in the second region, and the reflection structure includes one or more first reflection layers and one or more second reflection layers, the one or more first reflection layers having a first refractive index and a first thickness, and the one or more second reflection layers being alternately stacked with the one or more first reflection layers and having a second refractive index different from the first refractive index.

[0006] According to some embodiments, the present disclosure aims to provide a method of manufacturing a semiconductor device, the method comprising: providing a base layer including a first region and a second region surrounding the first region; forming a reflection structure on the base layer, the reflection structure not overlapping with the first region and overlapping with the second region; forming a target layer on the base layer and the reflection structure; and performing a laser annealing process on the target layer, wherein the reflection structure includes one or more first reflection layers and one or more second reflection layers, the one or more first reflection layers having a first refractive index, and the one or more second reflection layers being alternately stacked with the one or more first reflection layers and having a second refractive index different from the first refractive index.

[0007] According to some embodiments, the present disclosure aims to provide an electronic system, the electronic system comprising: a main substrate; a semiconductor memory device located on the main substrate, the semiconductor memory device including a first region and a second region surrounding the first region; and a controller located on the main substrate, the controller being electrically connected to the semiconductor memory device, wherein the semiconductor memory device includes: a source layer; a stacked structure including a plurality of gate electrodes sequentially stacked on the source layer while being spaced apart from each other in a first direction; an interlayer insulating film covering the stacked structure; a channel structure extending in the first direction to penetrate the stacked structure in the first region and connected to the source layer in the first region; and a reflection layer overlapping with the interlayer insulating film in the second region in the first direction, and the reflection structure includes one or more first reflection layers and one or more second reflection layers, the one or more first reflection layers having a first refractive index, and the one or more second reflection layers being alternately stacked with the one or more first reflection layers in the first direction and having a second refractive index different from the first refractive index. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0009] Figure 1 is a cross-sectional view showing an example of a semiconductor device according to some embodiments.

[0010] Figures 2 to 6 is a cross-sectional view showing an example of a method of manufacturing a semiconductor device according to some embodiments.

[0011] Figure 7 is a block diagram showing an example of a semiconductor device according to some embodiments.

[0012] Figure 8 is a circuit diagram showing an example of a semiconductor device according to some embodiments.

[0013] Figure 9 and Figure 10 is a layout diagram showing an example of a semiconductor device according to some embodiments.

[0014] Figure 11 is taken along Figure 10 line A-A according to some embodiments.

[0015] Figures 12A to 12E is according to some embodiments Figure 11 an enlarged cross-sectional view of an example of region R.

[0016] Figures 13 to 16 is a cross-sectional view showing an example of a semiconductor device according to some embodiments.

[0017] Figures 17 to 29 is a cross-sectional view showing an example of an intermediate step of a method for manufacturing a semiconductor device according to some embodiments.

[0018] Figure 30 is a block diagram showing an example of an electronic system according to some embodiments.

[0019] Figure 31 is a perspective view showing an example of an electronic system according to some embodiments.

[0020] Figure 32 is along according to some embodiments Figure 31 cross-sectional view taken along line I-I. Detailed Description

[0021] Hereinafter, example embodiments will be explained in detail with reference to the accompanying drawings. In the present disclosure, the term "same" not only means exactly the same, but also includes the existence of slight differences that may occur due to process margins and the like. In addition, in the present disclosure, although terms such as "first", "second", etc. are used to describe various elements or components, these elements or components are not limited by these terms. These terms are only used to distinguish one element or component from another. Therefore, within the technical spirit of the present disclosure, the first element or component mentioned below may also be the second element or component.

[0022] Figure 1 is a cross-sectional view showing an example of a semiconductor device according to some embodiments. In Figure 1 the semiconductor device includes a base layer 10, a reflective structure 20, and a target layer 30. The base layer 10 may be provided as a substrate for supporting the reflective structure 20 and the target layer 30. The base layer 10 may include: a conductive material such as a metal, a metal nitride, a metal silicide, or a metal silicide nitride film; an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride; or a semiconductor material such as polysilicon, but the present disclosure is not limited thereto. For example, the base layer 10 may include a semiconductor substrate and a multi-layer metal wiring formed on the semiconductor substrate.

[0023] The base layer 10 may include a first region I and a second region II that are different from each other. The second region II may be provided around the first region I. For example, the second region II may surround the perimeter of the first region I.

[0024] The reflective structure 20 can be formed on the second region II of the base layer 10. The reflective structure 20 can expose the first region I of the base layer 10. For example, the reflective structure 20 can not overlap with the first region I of the base layer 10 and can overlap with the second region II of the base layer 10. Here, the expression "overlap" means overlap in the vertical direction perpendicular to the upper surface of the base layer 10.

[0025] The reflective structure 20 can include a distributed Bragg reflector (DBR). For example, the reflective structure 20 can have a multi-layer structure in which one or more first reflective layers 22 and one or more second reflective layers 24 are alternately stacked. The first reflective layer 22 and the second reflective layer 24 can have different refractive indices. For example, the first reflective layer 22 can include a material such as a silicon oxide film or a tetraethyl orthosilicate (TEOS) film, and the second reflective layer 24 can include a material such as a silicon nitride film or a hafnium oxide film.

[0026] The reflective structure 20 is shown as including four first reflective layers 22 and three second reflective layers 24, but the present disclosure is not limited thereto. The number of the first reflective layers 22 and the second reflective layers 24 included in the reflective structure 20 can vary. Additionally, the first reflective layer 22 is shown as being disposed at the uppermost and lowermost portions of the reflective structure 20, but the present disclosure is not limited thereto. In some embodiments, the second reflective layer 24 can be disposed at the uppermost and lowermost portions of the reflective structure 20.

[0027] The reflective structure 20 is shown as being directly formed on the base layer 10, but the present disclosure is not limited thereto. In some embodiments, another intermediate layer or element can exist between the base layer 10 and the reflective structure 20.

[0028] The target layer 30 can be formed on the base layer 10 and the reflective structure 20. For example, the target layer 30 can extend along the upper surface of the base layer 10 and along the side surfaces and the upper surface of the reflective structure 20. In some embodiments, the target layer 30 can conformally extend along the upper surface of the base layer 10 and the profiles of the side surfaces and the top of the reflective structure 20. The reflective structure 20 can be interposed between the second region II of the base layer 10 and the target layer 30.

[0029] The target layer 30 is shown as being directly formed on the base layer 10 and / or the reflective structure 20, but the present disclosure is not limited thereto. In some embodiments, another intermediate layer or element can exist between the base layer 10 and the target layer 30 or between the reflective structure 20 and the target layer 30.

[0030] The target layer 30 can include a target material film to be subjected to a laser annealing process. For example, the target layer 30 can include a semiconductor material film such as a polysilicon film. In some embodiments, the target layer 30 can include an impurity-doped polysilicon film.

[0031] Examples of methods for manufacturing semiconductor devices according to some embodiments will be described below with reference to Figures 1 to 6 FIGs.

[0032] Figures 2 to 6 FIG. Figure 1 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to some embodiments. For convenience, descriptions of content overlapping with that already described with reference to

[0033] In Figure 2 FIG.

[0034] In Figure 3 FIG.

[0035] In Figure 4 FIG.

[0036] In Figure 5 and Figure 6 FIG.

[0037] In some embodiments, the laser annealing process LA may use visible laser light. For example, the wavelength λ of the laser used in the laser annealing process LA may be from about 400 nm to about 700 nm.

[0038] In some embodiments, the energy density of the laser used in the laser annealing process LA may be from about 50 mJ / cm 2 to about 2,000 mJ / cm 2. In some embodiments, the energy density of the laser used in the laser annealing process LA can be about 200 mJ / cm 2 to about 1,200 mJ / cm 2 .

[0039] In the laser annealing process LA, the reflective structure 20 can utilize Fresnel reflection enhancement interference to provide high reflectivity and low transmittance. For example, as Figure 6 shown, the reflective structure 20 can include a first reflective layer 22 and a second reflective layer 24 alternately stacked with the first reflective layer 22. The first refractive index of the first reflective layer 22 can be lower than the second refractive index of the second reflective layer 24. For example, each first reflective layer 22 can include a silicon oxide film, and each second reflective layer 24 can include a silicon nitride film. In this example, the first reflected light RL1 occurring at the surface (e.g., the upper surface) of the second reflective layer 24 can produce constructive interference with the second reflected light RL2 occurring at the surface (e.g., the upper surface) of the first reflective layer 22. Therefore, the reflective structure 20 can selectively block the laser entering the second region II of the base layer 10.

[0040] To cause this constructive interference, the first thickness t1 of the first reflective layer 22 and the second thickness t2 of the second reflective layer 24 can be appropriately selected based on the wavelength of the laser used in the laser annealing process LA. For example, if the first refractive index of the first reflective layer 22 is lower than the second refractive index of the second reflective layer 24, the first thickness t1 of the first reflective layer 22 can be greater than the second thickness t2 of the second reflective layer 24.

[0041] In some embodiments, the first thickness t1 of the first reflective layer 22 can be selected within the range defined by the following formula (1), and the second thickness t2 of the second reflective layer 24 can be selected within the range defined by the following formula (2).

[0042] (where )(1) (where )(2) In formulas (1) and (2), λ represents the wavelength of the light (specifically, the laser) irradiated onto the reflective structure 20 during the laser annealing process LA, n1 represents the first refractive index of the first reflective layer 22, and n2 represents the second refractive index of the second reflective layer 24.

[0043] For example, the wavelength λ of the laser used in the laser annealing process LA can be about 532 nm. At the wavelength λ, the first refractive index n1 of the first reflective layer 22 including silicon oxide can be about 1.46, and the second refractive index n2 of the second reflective layer 24 including silicon nitride can be about 2.02. In this example, the first thickness t1 of the first reflective layer 22 can be in the range of about 82 nm to about 100 nm, and the second thickness t2 of the second reflective layer 24 can be about 60 nm to about 72 nm.

[0044] In some embodiments, the reflective structure 20 may include at least three pairs of the first reflective layer 22 and the second reflective layer 24. Thus, constructive interference can be effectively caused.

[0045] Examples of semiconductor devices according to some embodiments of the present disclosure will be described below with reference to Figures 7 to 16 In the following description, the semiconductor device will be described by taking a NAND flash memory device as an example, but the present disclosure is not limited thereto. In some embodiments, the semiconductor device may also be: other types of non-volatile memory devices (such as phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM)); volatile memory devices (such as dynamic random access memory (DRAM) or static random access memory (SRAM)); or logic devices (such as central processing unit (CPU), graphics processing unit (GPU), controller, application specific integrated circuit (ASIC), or application processor (AP)).

[0046] Figure 7 is a block diagram showing an example of a semiconductor device according to some embodiments. In Figure 7 it, the memory cell array 50 may include a plurality of memory cell blocks BLK1 to BLKn. Each of the memory cell blocks BLK1 to BLKn may include a plurality of memory cells. The memory cell array 50 may be connected to the peripheral circuit 60 through bit lines BL, word lines WL, one or more string selection lines SSL, and one or more ground selection lines GSL. Specifically, the memory cell blocks BLK1 to BLKn may be connected to the row decoder 63 through word lines WL, string selection lines SSL, and ground selection lines GSL. In addition, the memory cell blocks BLK1 to BLKn may be connected to the page buffer 65 through bit lines BL.

[0047] The peripheral circuit 60 can receive an address ADDR, a command CMD, and a control signal CTRL from outside the semiconductor device 40, and can exchange data DATA with an external device outside the semiconductor device 40. The peripheral circuit 60 can include a control logic 67, a row decoder 63, and a page buffer 65. Additionally, the peripheral circuit 60 can further include various sub-circuits, such as an input / output circuit, a voltage generation circuit that generates various voltages required for the operation of the semiconductor device 40, and / or an error correction circuit that corrects errors in the data DATA read from the memory cell array 50.

[0048] The control logic 67 can be connected to the row decoder 63, the input / output circuit, and the voltage generation circuit. The control logic 67 can control the overall operation of the semiconductor device 40. The control logic 67 can generate various internal control signals for the semiconductor device 40 in response to the control signal CTRL. For example, the control logic 67 can adjust the voltage levels to be provided to the word line WL and the bit line BL during a memory operation such as programming or erasing.

[0049] In response to the address ADDR, the row decoder 63 can select at least one memory cell block among the memory cell blocks BLK1 to BLKn, and can select at least one word line WL, at least one string selection line SSL, and at least one ground selection line GSL from the selected memory cell block. In addition, the row decoder 63 can transfer a voltage to the word line WL of the selected memory cell block to perform a memory operation.

[0050] The page buffer 65 can be connected to the memory cell array 50 through the bit line BL. The page buffer 65 can be used as a write driver or a sense amplifier. For example, during a programming operation, the page buffer 65 serves as a write driver and applies a voltage corresponding to the data DATA to be stored in the memory cell array 50 to the bit line BL. Conversely, during a read operation, the page buffer 65 serves as a sense amplifier and detects the data DATA stored in the memory cell array 50.

[0051] Figure 8 is a circuit diagram showing an example of a semiconductor device according to some embodiments. In Figure 8 , a memory cell array (e.g., Figure 7 's memory cell array 50) of a semiconductor device according to some embodiments of the present disclosure includes a common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR.

[0052] The bit lines BL can be arranged two-dimensionally in a plane including a first direction X and a second direction Y. For example, the bit lines BL can extend in the second direction Y and can be spaced apart from each other along the first direction X. The cell strings CSTR can be connected in parallel to the bit lines BL. The cell strings CSTR can be commonly connected to a common source line CSL. That is, the cell strings CSTR can be disposed between the bit lines BL and the common source line CSL.

[0053] Each cell string CSTR can include: a ground selection transistor GST connected to the common source line CSL, a string selection transistor SST connected to the bit line BL, and a plurality of memory cell transistors MCT disposed between the ground selection transistor GST and the string selection transistor SST. Each memory cell transistor MCT can include a data storage element. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT can be connected in series in a third direction Z intersecting the first direction X and the second direction Y.

[0054] The common source line CSL can be commonly connected to the source of the ground selection transistor GST. Additionally, a ground selection line GSL, a plurality of word lines (WL11 to WL1n and WL21 to WL2m), and a string selection line SSL can be disposed between the common source line CSL and the bit lines BL. The ground selection line GSL can serve as the gate electrode of the ground selection transistor GST, the word lines WL1 to WLn can serve as the gate electrodes of the memory cell transistors MCT, and the string selection line SSL can serve as the gate electrode of the string selection transistor SST.

[0055] Figure 9 and Figure 10 is a layout diagram showing an example of a semiconductor device according to some embodiments. Figure 11 is along according to some embodiments Figure 10 cross-sectional view taken along line A-A of. Figures 12A to 12E is according to some embodiments of Figure 11 magnified cross-sectional view of an example of region R of.

[0056] In Figures 9 to 12A a semiconductor device includes a memory cell structure CELL and a peripheral circuit structure PERI. The memory cell structure CELL can include a cell array region CA, an extended region EA, and an external region PA.

[0057] In each cell array region CA, a memory cell array including a plurality of memory cells (e.g., Figure 7 memory cell array 50 of) can be formed. For example, a channel structure CH, gate electrodes (112 and 117), a conductive wire 185, and a source layer 300 can be disposed in each cell array region CA.

[0058] The extended region EA can be provided around the cell array region CA. For example, the extended region EA can be adjacent to the cell array region CA in the first direction X. In each extended region EA, gate electrodes (112 and 117), which will be described below, can be stacked in a stepped manner.

[0059] The outer region PA can be a peripheral region surrounding the cell array region CA and the extended region EA. For example, the outer region PA can be adjacent to the cell array region CA and / or the extended region EA in the first direction X and / or the second direction Y. Conductive pads 390, which will be described later, can be provided in the outer region PA.

[0060] The memory cell structure CELL can include a first substrate insulating film 102, a first stacked structure SS1, a first interlayer insulating film 141, a second substrate insulating film 104, a second stacked structure SS2, a second interlayer insulating film 142, a channel structure CH, a cutting pattern WC, a gate contact 162, a source contact 164, a via 166, a cell wiring structure 180, a source layer 300, an upper insulating film 310, a reflective structure 320, a third interlayer insulating film 340, a fourth interlayer insulating film 350, a connection pattern 380, and a conductive pad 390.

[0061] The first substrate insulating film 102 can form an insulating region across the cell array region CA and the extended region EA. The first substrate insulating film 102 can include at least one of silicon oxide, silicon nitride, and silicon oxynitride, but the present disclosure is not limited thereto. For example, the first substrate insulating film 102 can include a silicon oxide film.

[0062] The first substrate insulating film 102 can have a first surface 102a and a second surface 102b opposite to each other. The first surface 102a and the second surface 102b can extend along a horizontal plane (e.g., the XY plane).

[0063] The first stacked structure SS1 can be formed on the first surface 102a of the first substrate insulating film 102. The first stacked structure SS1 can include a plurality of first molded insulating films 110 and a plurality of first gate electrodes 112 stacked alternately with the first molded insulating films 110 on the first substrate insulating film 102. The first molded insulating films 110 and the first gate electrodes 112 can form a layered structure extending along a horizontal plane (e.g., the XY plane). The first gate electrodes 112 can be sequentially stacked with each other spaced apart by the first molded insulating films 110.

[0064] In each extended region EA, the first gate electrodes 112 can be stacked on the first substrate insulating film 102 in a stepped manner. For example, in each extended region EA, the extension length of the first gate electrodes 112 in the first direction X can decrease as it is farther away from the first substrate insulating film 102.

[0065] In some embodiments, the first gate electrode 112 may include one or more ground selection lines ( Figure 8 "GSL") and a plurality of first word lines ( Figure 8 "WL11" to "WL1n") sequentially stacked on the first base insulating film 102. The number and shape of the first molded insulating film 110 and the first gate electrode 112 are merely examples and are not particularly limited.

[0066] The first interlayer insulating film 141 may be formed on the first base insulating film 102 and the first stacked structure SS1. The first interlayer insulating film 141 may cover the first base insulating film 102 and the first stacked structure SS1. The first interlayer insulating film 141 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a dielectric constant less than that of silicon oxide, but the present disclosure is not limited thereto.

[0067] The second base insulating film 104 may be formed on the first interlayer insulating film 141. The second base insulating film 104 may form an insulating region across the cell array region CA and the extension region EA. The second base insulating film 104 may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, but the present disclosure is not limited thereto. For example, the second base insulating film 104 may include a silicon oxide film.

[0068] The second stacked structure SS2 may be formed on the second base insulating film 104. The second stacked structure SS2 may include a plurality of second molded insulating films 115 and a plurality of second gate electrodes 117 alternately stacked on the second base insulating film 104. The second molded insulating films 115 and the second gate electrodes 117 may form a layered structure extending along a horizontal plane (e.g., the XY plane). The second gate electrodes 117 may be sequentially stacked with each other spaced apart by the second molded insulating films 115.

[0069] In each extension region EA, the second gate electrodes 117 may be stacked on the second base insulating film 104 in a stepped manner. For example, in each extension region EA, the extension length of the second gate electrodes 117 in the first direction X may decrease as it is farther from the second base insulating film 104.

[0070] In some embodiments, the second gate electrode 117 may include a plurality of second word lines (e.g., Figure 8 word lines WL21 to WL2m) and one or more string selection lines (e.g., Figure 8 string selection line SSL) sequentially stacked on the second base insulating film 104. The number and shape of the second molded insulating films 115 and the second gate electrodes 117 are merely examples and are not particularly limited.

[0071] The second interlayer insulating film 142 may be formed on the second base insulating film 104 and the second stacked structure SS2. The second interlayer insulating film 142 may cover the second base insulating film 104 and the second stacked structure SS2. The second interlayer insulating film 142 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a dielectric constant less than that of silicon oxide, but the present disclosure is not limited thereto.

[0072] The gate electrodes (112 and 117) may include a conductive material, for example, a metal such as tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), or nickel (Ni); or a semiconductor material such as silicon (Si), but the present disclosure is not limited thereto. For example, the gate electrodes (112 and 117) may include at least one of W, Mo, and Ru. In another example, the gate electrodes (112 and 117) may include polysilicon.

[0073] The molding insulating films (110 and 115) may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride, but the present disclosure is not limited thereto. For example, the molding insulating films (110 and 115) may include a silicon oxide film.

[0074] The channel structure CH may be disposed in the cell array region CA. The channel structure CH may extend in the third direction Z, penetrating the first stacked structure SS1 and the second stacked structure SS2. The channel structure CH may intersect the gate electrodes (112 and 117). For example, the channel structure CH may be in the shape of a pillar (e.g., a cylinder) extending in the third direction Z.

[0075] In some embodiments, the channel structure CH may be arranged in a zigzag manner. As Figure 10 shown, the channel structure CH may be staggered in the first direction X and the second direction Y. The channel structure CH may increase the integration density of the semiconductor device. The number and arrangement of the channel structures CH are merely examples and are not particularly limited.

[0076] In some embodiments, each channel structure CH may have a step difference between the first stacked structure SS1 and the second stacked structure SS2. For example, as Figure 11 shown, the side surface of each channel structure CH may have a curved portion at the boundary between the first interlayer insulating film 141 and the second base insulating film 104. The channel structure CH may include a semiconductor film 130 and a data storage film 132.

[0077] The semiconductor film 130 may extend in a third direction Z and may intersect the gate electrodes (112 and 117). The semiconductor film 130 is shown as cup-shaped, but the present disclosure is not limited thereto. In some embodiments, the semiconductor film 130 may have various other geometries, such as cylindrical, rectangular prism, or filled column shapes. The semiconductor film 130 may include, for example, single-crystalline silicon, polycrystalline silicon, organic semiconductors, and carbon nanostructures, but the present disclosure is not limited thereto.

[0078] The data storage film 132 may be interposed between the semiconductor film 130 and the gate electrodes (112 and 117). For example, the data storage film 132 may extend along the outer surface of the semiconductor film 130. The data storage film 132 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k material having a dielectric constant greater than that of silicon oxide, but the present disclosure is not limited thereto. The high-k material may include, for example, at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0079] In some embodiments, the data storage film 132 may be formed as a multilayer. For example, as Figure 12A shown, each data storage film 132 may include a tunneling insulating film 132a, a charge storage film 132b, and a blocking insulating film 132c that are sequentially stacked on the outer surface of the corresponding semiconductor film 130.

[0080] The tunneling insulating film 132a may include, for example, silicon oxide or a high-k material having a dielectric constant greater than that of silicon oxide (e.g., aluminum oxide (Al2O3) or hafnium oxide (HfO2)). The charge storage film 132b may include, for example, silicon nitride. The blocking insulating film 132c may include, for example, silicon oxide or a high-k material having a dielectric constant greater than that of silicon oxide (e.g., Al2O3 or HfO2).

[0081] In some embodiments, the channel structure CH may further include a filling insulating film 134. The filling insulating film 134 may be formed to fill the inside of the cup-shaped semiconductor film 130. The filling insulating film 134 may include, for example, an insulating material such as silicon oxide, but the present disclosure is not limited thereto.

[0082] In some embodiments, the channel structure CH may further include a channel pad 136. The channel pad 136 may be formed to be connected to an end portion (e.g., the lower end portion) of the semiconductor film 130. The channel pad 136 may contain a conductive material such as doped polycrystalline silicon, metal, or metal silicide, but the present disclosure is not limited thereto.

[0083] In some embodiments, a dummy channel structure DCH may be formed within the extension region EA. The dummy channel structure DCH may extend in the third direction Z and penetrate at least a portion of the first stack structure SS1 and the second stack structure SS2.

[0084] The dummy channel structure DCH may be formed at the same height or a different height from the channel structure CH. For example, if formed at the same height as the channel structure CH, the dummy channel structure DCH may further include a semiconductor film 130, a data storage film 132, a filling insulating film 134, and a channel pad 136. In some embodiments, if formed at a different height from the channel structure CH, the dummy channel structure DCH may be filled with an insulating material and / or a conductive material. The size (e.g., width) of the dummy channel structure DCH may be the same as or different from the size of the channel structure CH. In some embodiments, the size of the dummy channel structure DCH may be greater than the size of the channel structure CH.

[0085] The cutting pattern WC may be formed across the cell array region CA and the extension region EA. The cutting pattern WC may extend longitudinally in the first direction X to cut the first stack structure SS1 and the second stack structure SS2. In addition, the cutting patterns WC may be spaced apart from each other in the second direction Y and extend parallel to each other in the first direction X. The first stack structure SS1 and the second stack structure SS2 may be separated by the cutting pattern WC, thereby forming a plurality of memory cell blocks (e.g., Figure 7 memory cell blocks BLK1 to BLKn). For example, two adjacent cutting patterns WC may define a single memory cell block therebetween. A plurality of channel structures CH may be provided in each memory cell block defined by the cutting pattern WC.

[0086] In some embodiments, the cutting pattern WC may include an insulating material, such as at least one of silicon oxide, silicon nitride, and silicon oxynitride, but the present disclosure is not limited thereto. For example, the cutting pattern WC may include a silicon oxide film.

[0087] In some embodiments, a separation pattern SC may be formed within the second stack structure SS2. The separation pattern SC may extend in the first direction X to cut the string selection line (e.g., Figure 8 the string selection line SSL) of the second stack structure SS2 (e.g., the bottommost second gate electrode 117). Each of the memory cell blocks defined by the cutting pattern WC may be divided by the separation pattern SC to form a plurality of string regions. For example, one separation pattern SC may define two string regions within a single memory cell block. The separation pattern SC may include an insulating material, such as at least one of silicon oxide, silicon nitride, and silicon oxynitride, but the present disclosure is not limited thereto.

[0088] The gate contact 162 may be disposed in the extended region EA. The gate contact 162 may be electrically connected to corresponding gate electrodes (112 and 117). For example, the gate contact 162 may extend in the third direction Z, penetrate the first interlayer insulating film 141 and / or the second interlayer insulating film 142, and may be connected to the corresponding gate electrodes (112 and 117). In some embodiments, the width of the gate contact 162 may decrease as it gets closer to the gate electrodes (112 and 117).

[0089] The source contact 164 and the via 166 may be disposed in the external region PA. The source contact 164 and the via 166 may extend in the third direction Z, penetrate the first interlayer insulating film 141 and / or the second interlayer insulating film 142. In some embodiments, the widths of the source contact 164 and the via 166 may decrease as they get closer to the upper insulating film 310.

[0090] The unit wiring structure 180 may be formed on the second interlayer insulating film 142. The unit wiring structure 180 may be electrically connected to the channel structure CH, the gate contact 162, the source contact 164, and / or the via 166. For example, a first inter-wiring insulating film 144 may be formed on the second interlayer insulating film 142. The unit wiring structure 180 may be formed within the first inter-wiring insulating film 144 and may thus be connected to the channel structure CH, the gate contact 162, the source contact 164, and / or the via 166. The number of layers and the arrangement of the unit wiring structure 180 are merely examples and are not limited to the depicted ones.

[0091] The unit wiring structure 180 may include a conductive material such as aluminum (Al), copper (Cu), W, Mo, Co, Ru, or an alloy thereof, but the present disclosure is not limited thereto. For example, the unit wiring structure 180 may include Cu wiring.

[0092] In some embodiments, the unit wiring structure 180 may include conductive lines 185 disposed in the unit array region CA. The conductive lines 185 may extend longitudinally in the second direction Y. Further, the conductive lines 185 may be spaced apart from each other in the first direction X and extend parallel to each other in the second direction Y.

[0093] The conductive lines 185 may be electrically connected to the channel structures CH arranged along the second direction Y. For example, the conductive lines 185 may be connected to the end (e.g., the lower end) of the semiconductor film 130 through the channel pads 136. The conductive lines 185 may be provided as bit lines (e.g., Figure 8 bit line BL).

[0094] The source layer 300 may be formed on the second surface 102b of the first base insulating film 102. The source layer 300 may be electrically connected to the channel structure CH. For example, the other end (e.g., the upper end) of the semiconductor film 130 may be exposed from the data storage film 132 and may be connected to the source layer 300.

[0095] The source layer 300 may include a conductive material such as doped polysilicon, metal, or metal silicide, but the present disclosure is not limited thereto. For example, the source layer 300 may include polysilicon (poly-Si) doped with an N-type impurity such as phosphorus (P) or arsenic (As). The source layer 300 may be provided as a common source line (e.g., Figure 8 the common source line CSL).

[0096] In some embodiments, the channel structure CH may protrude above the first base insulating film 102. For example, as Figure 12A shown, the other end (e.g., the upper end) of the semiconductor film 130 may be formed to be higher than the second surface 102b of the first base insulating film 102. The semiconductor film 130 may increase the contact area with the source layer 300, thereby reducing the contact resistance.

[0097] In some embodiments, the cutting pattern WC may also protrude above the first base insulating film 102. As Figure 12A shown, the upper surface of the cutting pattern WC may be formed to be higher than the second surface 102b of the first base insulating film 102.

[0098] In some embodiments, the source layer 300 may conformally extend along the protruding portion of the channel structure CH, the protruding portion of the cutting pattern WC, and the contour of the second surface 102b of the first base insulating film 102.

[0099] The upper insulating film 310 may be formed on the second surface 102b of the first base insulating film 102. The upper insulating film 310 may form an insulating region across the extended region EA and the external region PA. The upper insulating film 310 may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, but the present disclosure is not limited thereto. For example, the upper insulating film 310 may include a silicon oxide film.

[0100] The reflective structure 320 may be formed on the upper insulating film 310. The reflective structure 320 may be disposed in the extended area EA and / or the external area PA. The reflective structure 320 may overlap with the portions of the first stacked structure SS1 and the second stacked structure SS2 located in the extended area EA and the portions of the first interlayer insulating film 141 and the second interlayer insulating film 142 located in the extended area EA, and / or may overlap with the portions of the first interlayer insulating film 141 and the second interlayer insulating film 142 located in the external area PA. The term "overlap" means an overlap in the third direction Z. The reflective structure 320 is shown as completely covering the extended area EA and the external area PA, but the present disclosure is not limited thereto. In some embodiments, the reflective structure 320 may be disposed in a part of the extended area EA and / or a part of the external area PA.

[0101] The reflective structure 320 may not be disposed in the cell array region CA. For example, the reflective structure 320 may expose the first base insulating film 102, the channel structure CH, and the cutting pattern WC in the cell array region CA. Additionally, the reflective structure 320 may not overlap with the portions of the first stacked structure SS1 and the second stacked structure SS2 located in the cell array region CA and the portions of the first interlayer insulating film 141 and the second interlayer insulating film 142 located in the cell array region CA in the third direction Z.

[0102] The reflective structure 320 may include a DBR (Distributed Bragg Reflector). The reflective structure 320 may provide a high reflectivity and a low transmittance by utilizing Fresnel reflection enhancement interference. The reflective structure 320 may have a multilayer structure in which one or more first reflective layers 322 and one or more second reflective layers 324 having a refractive index different from that of the first reflective layer 322 are alternately stacked. For example, the first reflective layer 322 may include a material such as a silicon oxide film or a TEOS film, and the second reflective layer 324 may include a material such as a silicon nitride film or a hafnium oxide film. In some embodiments, the reflective structure 320 may include at least three pairs of the first reflective layer 322 and the second reflective layer 324.

[0103] To cause such constructive interference, the first thickness t1 of the first reflective layer 322 and the second thickness t2 of the second reflective layer 324 may be appropriately selected. The first thickness t1 of the first reflective layer 322 may be selected within the range defined by the above formula (1), and the second thickness t2 of the second reflective layer 324 may be selected within the range defined by the above formula (2). The reflective structure 320 may correspond to Figures 1 to 6 the reflective structure 20, and thus, its detailed description will be omitted.

[0104] In some embodiments, the source layer 300 may further extend along at least a portion of the reflective structure 320. For example, the source layer 300 may further extend along the side surfaces and the upper surface of the upper insulating film 310 and the reflective structure 320. That is, at least a portion of the reflective structure 320 may be interposed between the source layer 300 and the upper insulating film 310.

[0105] In some embodiments, the reflective structure 320 may be interposed between the source layer 300 and the upper insulating film 310 in the extension region EA. In some embodiments, the source layer 300 may not be disposed within the external region PA.

[0106] In some embodiments, the first reflective layer 322 may include a lowermost reflective layer disposed at the lowermost portion of the reflective structure 320. For example, the bottom surface of the lowermost first reflective layer 322 disposed at the lowermost portion of the reflective structure 320 may contact the upper insulating film 310.

[0107] In some embodiments, the first reflective layer 322 may include an uppermost reflective layer disposed at the uppermost portion of the reflective structure 320. For example, the upper surface of the uppermost first reflective layer 322 disposed at the uppermost portion of the reflective structure 320 may contact the source layer 300.

[0108] The third interlayer insulating film 340 may be formed on the source layer 300, the reflective structure 320, and / or the upper insulating film 310. The third interlayer insulating film 340 may cover the source layer 300, the reflective structure 320, and / or the upper insulating film 310. The fourth interlayer insulating film 350 may be formed on the third interlayer insulating film 340. The third interlayer insulating film 340 and the fourth interlayer insulating film 350 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a dielectric constant less than that of silicon oxide, but the present disclosure is not limited thereto.

[0109] The connection pattern 380 may be formed in the fourth interlayer insulating film 350. The connection pattern 380 may be electrically connected to the source contact 164 and the source layer 300. For example, a first contact pad 312 connected to the source contact 164 may be formed in the upper insulating film 310. In addition, a first contact pattern 362 passing through the third interlayer insulating film 340 to connect the source layer 300 and the connection pattern 380 may be formed, and a second contact pattern 364 passing through the reflective structure 320 and / or the third interlayer insulating film 340 to connect the first contact pad 312 and the connection pattern 380 may be formed.

[0110] The conductive pad 390 may be formed in the fourth interlayer insulating film 350 in the external region PA. The conductive pad 390 may be electrically connected to the through-via 166. For example, a second contact pad 314 connected to the through-via 166 may be formed in the upper insulating film 310. In addition, a third contact pattern 366 may be formed to connect the second contact pad 314 and the conductive pad 390 through the reflective structure 320 and / or the third interlayer insulating film 340.

[0111] The peripheral circuit structure PERI may include a peripheral circuit substrate 200, peripheral circuit elements PT, and a peripheral circuit wiring structure 280. The peripheral circuit substrate 200 may include a semiconductor substrate, such as an Si, germanium (Ge), or silicon germanium (SiGe) substrate. In some embodiments, the peripheral circuit substrate 200 may include a silicon-on-insulator (SOI) or germanium-on-insulator (GOI) substrate.

[0112] The peripheral circuit elements PT may be formed on the peripheral circuit substrate 200. The peripheral circuit elements PT may form a peripheral circuit (e.g., Figure 7 the peripheral circuit 60) that controls the operation of the semiconductor memory device according to some embodiments of the present disclosure. For example, the peripheral circuit elements PT may include control logic (e.g., Figure 7 the control logic 67), a row decoder (e.g., Figure 7 the row decoder 63), and a page buffer (e.g., Figure 7 the page buffer 65). The surface of the peripheral circuit substrate 200 on which the peripheral circuit elements PT are provided may be referred to as the front surface of the peripheral circuit substrate 200. In contrast, the surface of the peripheral circuit substrate 200 opposite to the front surface of the peripheral circuit substrate 200 may be referred to as the back surface of the peripheral circuit substrate 200.

[0113] The peripheral circuit elements PT may include, for example, transistors, but the present disclosure is not limited thereto. The peripheral circuit elements PT may include not only active elements such as transistors but also passive elements such as capacitors, resistors, or inductors.

[0114] The peripheral circuit wiring structure 280 may be formed on the peripheral circuit elements PT. For example, a second inter-wiring insulating film 244 may be formed on the front surface of the peripheral circuit substrate 200. The peripheral circuit wiring structure 280 may be formed in the second inter-wiring insulating film 244 and may be electrically connected to the peripheral circuit elements PT. The number of layers and the arrangement of the peripheral circuit wiring structure 280 are merely examples and are not particularly limited.

[0115] In some embodiments, the memory cell structure CELL may be stacked on the peripheral circuit structure PERI. For example, the memory cell structure CELL may be stacked on the second inter-wiring insulating film 244.

[0116] In some embodiments, the first surface 102a of the first base insulating film 102 may face the peripheral circuit structure PERI. For example, the first stacked structure SS1 and the second stacked structure SS2 may be interposed between the source layer 300 and the peripheral circuit structure PERI.

[0117] In some embodiments, a semiconductor device may have a chip-to-chip (C2C) structure. The C2C structure involves: fabricating an upper chip including a memory cell structure CELL on a first wafer; fabricating a lower chip including a peripheral circuit structure PERI on a second wafer different from the first wafer; and bonding the upper chip and the lower chip together.

[0118] For example, the upper chip and the lower chip may be bonded together by connecting a first bonding metal 190 (and / or a first bonding insulating film 146) formed in the uppermost metal layer of the upper chip and a second bonding metal 290 (and / or a second bonding insulating film 246) formed in the uppermost metal layer of the lower chip. For example, if the first bonding metal 190 and the second bonding metal 290 are formed of Cu, the upper chip and the lower chip may be bonded by a Cu-Cu bonding method, but the present disclosure is not limited thereto. The first bonding metal 190 and the second bonding metal 290 may be formed of various other metals such as Al or W.

[0119] When the first bonding metal 190 and the second bonding metal 290 are bonded together, the cell wiring structure 180 may be electrically connected to the peripheral circuit wiring structure 280. Accordingly, the memory cells formed in the cell array region CA may be electrically connected to the peripheral circuit elements PT.

[0120] In the C2C structure, since the upper chip and the lower chip are connected by bonding, a common source line (e.g., the source layer 300) of the upper chip may be disposed on top of the semiconductor device.

[0121] Meanwhile, a laser annealing process may be performed on the common source line to activate impurities included in the common source line. However, the laser used in the laser annealing process may penetrate regions having a high laser transmittance below the common source line (e.g., portions of the first interlayer insulating film 141 and the second interlayer insulating film 142 in the extended region EA and / or the external region PA), thereby causing damage to the underlying multi-layer metal wiring (e.g., the cell wiring structure 180 and the peripheral circuit wiring structure 280).

[0122] In contrast, the semiconductor device can use the reflective structure 320 to prevent damage that may be caused by the laser to the metal wiring. Specifically, as described above, the reflective structure 320 can be disposed in the extended area EA and / or the external area PA to overlap the first interlayer insulating film 141 and the second interlayer insulating film 142 in the third direction Z. The reflective structure 320 can selectively block the laser entering the extended area EA and / or the external area PA during the laser annealing process, thereby preventing damage to the cell wiring structure 180 and / or the peripheral circuit wiring structure 280. Therefore, a semiconductor device with improved yield and reliability can be provided.

[0123] In Figure 11 , Figure 12B and Figure 12C of, the first reflective layer 322 can include the uppermost first reflective layer 322t disposed on top of the reflective structure 320. For example, the upper surface of the uppermost first reflective layer 322t can contact the source layer 300. To ensure the high reflectivity and low transmittance of the reflective structure 320, the third thickness t3 of the uppermost first reflective layer 322t can be appropriately selected. In some embodiments, the third thickness t3 of the uppermost first reflective layer 322t can be different from the first thickness t1. For example, as Figure 12B shown, the third thickness t3 of the uppermost first reflective layer 322t can be less than the first thickness t1. In some embodiments, as Figure 12C shown, the third thickness t3 of the uppermost first reflective layer 322t can be greater than the first thickness t1.

[0124] In some embodiments, the third thickness t3 of the uppermost first reflective layer 322t can be selected within the range defined by the following formula (3).

[0125] (where ) (3) In formula (3), λ represents the wavelength of the light (or laser) irradiated onto the reflective structure 320 during the laser annealing process for the source layer 300, and n3 represents the third refractive index of the uppermost first reflective layer 322t.

[0126] For example, the wavelength λ of the laser used in the laser annealing process can be about 532 nm. At the wavelength λ, the third refractive index n3 of the uppermost first reflective layer 322t including the silicon oxide film can be about 1.46. In this example, the third thickness t3 of the uppermost first reflective layer 322t can be in the range of about 9 nm to about 220 nm. Preferably, the third thickness t3 of the uppermost first reflective layer 322t can be in the range of about 40 nm to about 210 nm.

[0127] In some embodiments, the third thickness t3 of the uppermost first reflective layer 322t may be in the range of about 40 nm to about 120 nm, or about 190 nm to about 210 nm. In some embodiments, the third thickness t3 of the uppermost first reflective layer 322t may be in the range of about 700 nm to about 900 nm.

[0128] In Figure 11 and Figure 12D , the second reflective layer 324 includes the lowermost reflective layer 324 disposed at the bottom of the reflective structure 320. For example, the bottom surface of the lowermost second reflective layer 324 disposed at the bottom of the reflective structure 320 may contact the upper insulating film 310.

[0129] In Figure 11 and Figure 12E , the second reflective layer 324 includes the uppermost second reflective layer 324t disposed at the top of the reflective structure 320. For example, the upper surface of the uppermost second reflective layer 324t may contact the source layer 300. To ensure a high reflectivity and low transmittance of the reflective structure 320, the thickness of the uppermost second reflective layer 324t may be appropriately selected. The uppermost second reflective layer 324t may be similar to Figure 12B and Figure 12C 's uppermost first reflective layer 322t, and its detailed description will be omitted.

[0130] Figures 13 to 16 is a cross-sectional view showing an example of a semiconductor device according to some embodiments. For convenience, descriptions of content overlapping with that described above with reference to Figures 1 to 12E will be simplified or omitted.

[0131] In Figure 13 , the reflective structure 320 is not provided in the external region PA. For example, the reflective structure 320 may expose a portion of the upper insulating film 310 located in the external region PA. In addition, the reflective structure 320 may not overlap with portions of the first interlayer insulating film 141 and the second interlayer insulating film 142 located in the external region PA in the third direction Z.

[0132] In Figure 14 , in some embodiments, the reflective structure 320 may be provided in a portion of the extended region EA. For example, the reflective structure 320 may expose a portion of the upper insulating film 310 located in the extended region EA. Additionally, the reflective structure 320 may not overlap with portions of the first stacked structure SS1 and the second stacked structure SS2 located in the extended region EA and portions of the first interlayer insulating film 141 and the second interlayer insulating film 142 located in the extended region EA in the third direction Z.

[0133] In some embodiments, a first contact pattern 362 may be disposed in the cell array region CA. The first contact pattern 362 may connect the source layer 300 of the cell array region CA and the connection pattern 380 by penetrating the third interlayer insulating film 340.

[0134] In Figure 15 , a conductive plate 305 may also be included. The conductive plate 305 may be formed on the source layer 300. For example, the conductive plate 305 may extend conformally along the upper surface of the source layer 300. The conductive plate 305 may be electrically connected to the source layer 300. The conductive plate 305 may include a conductive material, such as a metal or metal silicide such as W, Co, or Ni, but the present disclosure is not limited thereto. The conductive plate 305 may be used to reduce the resistance of a common source line including the source layer 300 (e.g., Figure 8 the common source line CSL).

[0135] In Figure 16 , the gate contact 162 penetrates the first stacked structure SS1 and the second stacked structure SS2. For example, in the extended region EA, a plurality of third contact pads 316 may be formed in the upper insulating film 310. The gate contact 162 may be electrically connected to the third contact pads 316 by penetrating the first stacked structure SS1 and the second stacked structure SS2, respectively. In some embodiments, each gate contact 162 may include a first through portion 162a, a second through portion 162b, and a protruding portion 162p.

[0136] The first through portion 162a may extend in the third direction Z to penetrate the first base insulating film 102, the first stacked structure SS1, and the first interlayer insulating film 141. The second through portion 162b may be connected to the first through portion 162a by penetrating the second base insulating film 104, the second stacked structure SS2, and the second interlayer insulating film 142. The protruding portion 162p may protrude from a side surface of the first through portion 162a or a side surface of the second through portion 162b to contact at least one of the plurality of gate electrodes (112 and 117). In some embodiments, the protruding portion 162p may contact the lowermost gate electrode (hereinafter, the selected gate electrode) disposed at the bottom of a corresponding step formed by the gate electrodes (112 and 117) in the extended region EA.

[0137] Gate electrodes (112 and 117) other than the selected gate electrode (i.e., non-selected gate electrodes) may be spaced apart from the gate contact 162. For example, a first insulating ring 160a may be formed between the first gate electrode 112 and each first through portion 162a, and a second insulating ring 160b may be formed between the second gate electrode 117 and each second through portion 162b. The first insulating ring 160a or the second insulating ring 160b may be interposed between the gate contact 162 and the non-selected gate electrode, and may not be interposed between the gate contact 162 and the selected gate electrode.

[0138] In some embodiments, the gate contact 162 may have a step difference between the first stacked structure SS1 and the second stacked structure SS2. For example, the width of the first through portion 162a may decrease as it gets closer to the third contact pad 316, and the width of the second through portion 162b may decrease as it gets closer to the first through portion 162a. Additionally, at the boundary between the first interlayer insulating film 141 and the second substrate insulating film 104, the width of the first through portion 162a may be greater than the width of the second through portion 162b.

[0139] In some embodiments, the source contact 164 may have a step difference between the first stacked structure SS1 and the second stacked structure SS2. For example, the source contact 164 may include a third through portion 164a and a fourth through portion 164b. The third through portion 164a may be connected to the first contact pad 312 by penetrating the first interlayer insulating film 141. The fourth through portion 164b may be connected to the third through portion 164a by penetrating the second interlayer insulating film 142. The width of the third through portion 164a may decrease as it gets closer to the first contact pad 312, and the width of the fourth through portion 164b may decrease as it gets closer to the third through portion 164a. Further, at the boundary between the first interlayer insulating film 141 and the second interlayer insulating film 142, the width of the third through portion 164a may be greater than the width of the fourth through portion 164b.

[0140] In some embodiments, the through-via 166 may have a step difference between the first stacked structure SS1 and the second stacked structure SS2. For example, the through-via 166 may include a fifth through portion 166a and a sixth through portion 166b. The fifth through portion 166a may be connected to the second contact pad 314 by penetrating the first interlayer insulating film 141. The sixth through portion 166b may be connected to the fifth through portion 166a by penetrating the second interlayer insulating film 142. The width of the fifth through portion 166a may decrease as it gets closer to the second contact pad 314, and the width of the sixth through portion 166b may decrease as it gets closer to the fifth through portion 166a. In addition, at the boundary between the first interlayer insulating film 141 and the second interlayer insulating film 142, the width of the fifth through portion 166a may be greater than the width of the sixth through portion 166b.

[0141] Figures 17 to 29 is a cross-sectional view showing an example of an intermediate step of a method of manufacturing a semiconductor device according to some embodiments. For convenience, the description of the content overlapping with what has been described with reference to Figures 1 to 16 will be simplified or omitted.

[0142] In Figure 17 , a first base insulating film 102, a first preliminary stack pSS1, and a first preliminary channel pCH1 are formed on a base substrate 100. The base substrate 100 may include, for example, a semiconductor substrate such as a Si substrate, a Ge substrate, or a SiGe substrate. Optionally, the base substrate 100 may include a SOI substrate or a GOI substrate.

[0143] The base substrate 100 may include a third surface 100a and a fourth surface 100b that are opposite to each other. The third surface 100a may also be referred to as the front surface of the base substrate 100, and the fourth surface 100b may also be referred to as the back surface of the base substrate 100.

[0144] The first base insulating film 102 and the first preliminary stack pSS1 may be sequentially stacked on the third surface 100a of the base substrate 100. The first preliminary stack pSS1 may include a plurality of first molded insulating films 110 and a plurality of first molded sacrificial films 111 that are alternately stacked on the first base insulating film 102. The first molded sacrificial films 111 may include a material having an etching selectivity with respect to the first molded insulating films 110. For example, each first molded insulating film 110 may include a silicon oxide film, and each first molded sacrificial film 111 may include a silicon nitride film.

[0145] The first preliminary channel pCH1 can penetrate the first base insulating film 102 and the first preliminary stack pSS1. Additionally, the first preliminary channel pCH1 can be connected to the base substrate 100. For example, a first interlayer insulating film 141 covering the first base insulating film 102 and the first preliminary stack pSS1 can be formed on the base substrate 100. The first preliminary channel pCH1 can penetrate the first interlayer insulating film 141, the first preliminary stack pSS1, and the first base insulating film 102, thereby being connectable to the base substrate 100. In some embodiments, the bottom surface of the first preliminary channel pCH1 can be formed to be lower than the third surface 100a of the base substrate 100.

[0146] The first preliminary channel pCH1 can include a material having an etching selectivity with respect to the first molded insulating film 110 and the first molded sacrificial film 111. For example, the first preliminary channel pCH1 can include poly-Si.

[0147] In Figure 18 it, a second base insulating film 104, a second preliminary stack pSS2, and a second preliminary channel pCH2 are formed on the first interlayer insulating film 141. The second base insulating film 104 and the second preliminary stack pSS2 can be sequentially stacked on the first interlayer insulating film 141. The second preliminary stack pSS2 can include a plurality of second molded insulating films 115 and a plurality of second molded sacrificial films 116 stacked alternately with the second molded insulating films 115 on the second base insulating film 104. The formation of the second preliminary stack pSS2 can be similar to the formation of the first preliminary stack pSS1, and its detailed description will be omitted.

[0148] The second preliminary channel pCH2 can penetrate the second base insulating film 104 and the second preliminary stack pSS2. Additionally, the second preliminary channel pCH2 can be connected to the first preliminary channel pCH1. The formation of the second preliminary channel pCH2 can be similar to the formation of the first preliminary channel pCH1, and thus, its detailed description will be omitted.

[0149] In Figure 19 it, a channel structure CH is formed. For example, the first preliminary channel pCH1 and the second preliminary channel pCH2 can be selectively removed. Thereafter, the channel structure CH can be formed in the region where the first preliminary channel pCH1 and the second preliminary channel pCH2 have been removed. In this way, a channel structure CH that penetrates the first preliminary stack pSS1 and the second preliminary stack pSS2 and is connected to the base substrate 100 can be formed. In some embodiments, the channel structure CH can include a semiconductor film 130, a data storage film 132, a filling insulating film 134, and a channel pad 136.

[0150] In Figure 20Therein, a cutting region WCh is formed. The cutting region WCh may extend in the first direction X and may cut the first preliminary stack pSS1 and the second preliminary stack pSS2. In some embodiments, the bottom surface of the cutting region WCh may be formed to be lower than the third surface 100a of the base substrate 100.

[0151] In Figure 21 therein, a plurality of gate electrodes (112 and 117) are formed. For example, the molded sacrificial films (111 and 116) exposed by the cutting region (WCh) may be selectively removed. Thereafter, the gate electrodes (112 and 117) may be formed in the regions where the molded sacrificial films (111 and 116) have been removed. Accordingly, a first stack structure SS1 and a second stack structure SS2 including molded insulating films (110 and 115) and gate electrodes (112 and 117) may be formed. In some embodiments, after the first stack structure SS1 and the second stack structure SS2 are formed, the cutting region WCh may be filled with an insulating material. Accordingly, a cutting pattern WC that cuts the first stack structure SS1 and the second stack structure SS2 may be formed.

[0152] In Figure 22 therein, a gate contact 162, a source contact 164, a via 166, a first interlayer insulating film 144, a cell wiring structure 180, a first bonding insulating film 146, and a first bonding metal 190 are formed. The gate contact 162 may be disposed in the extension region EA. A plurality of gate contacts 162 may pass through the first interlayer insulating film 141 and the second interlayer insulating film 142 to be connected to corresponding gate electrodes (112 and 117).

[0153] The source contact 164 and the via 166 may be disposed in the external region PA. The source contact 164 and the via 166 may pass through the first interlayer insulating film 141 and the second interlayer insulating film 142 to be connected to the base substrate 100.

[0154] The first interlayer insulating film 144 and the cell wiring structure 180 may be formed on the second interlayer insulating film 142. The cell wiring structure 180 may be electrically connected to the channel structure CH, the gate contact 162, the source contact 164, and / or the via 166.

[0155] The first bonding insulating film 146 and the first bonding metal 190 may be formed on the first interlayer insulating film 144. The first bonding metal 190 may be electrically connected to the cell wiring structure 180.

[0156] In Figure 23In [the structure], a memory cell structure CELL is stacked on a peripheral circuit structure PERI. In some embodiments, the memory cell structures CELL may be stacked such that a third surface 100a of a base substrate 100 may face the peripheral circuit structure PERI. For example, a first bonding metal 190 and / or a first bonding insulating film 146 formed in the uppermost metal layer of the memory cell structure CELL may be bonded to a second bonding metal 290 and / or a second bonding insulating film 246 formed in the uppermost metal layer of the peripheral circuit structure PERI.

[0157] In Figure 24 [the structure], at least a portion of the base substrate 100 is removed. For example, a planarization process and / or a recess process may be performed on a fourth surface 100b of the base substrate 100. As a result, an end portion (e.g., an upper end portion) of the channel structure CH may be exposed.

[0158] In Figure 25 [the structure], an upper insulating film 310, a first contact pad 312, a second contact pad 314, and a reflective structure 320 are formed on a first base insulating film 102 and a first interlayer insulating film 141. The upper insulating film 310 may cover the first base insulating film 102 and the first interlayer insulating film 141 across a cell array region CA, an extension region EA, and an external region PA. The first contact pad 312 and the second contact pad 314 may be formed in the upper insulating film 310. The first contact pad 312 may be connected to a source contact 164, and the second contact pad 314 may be connected to a via 166.

[0159] The reflective structure 320 may cover the upper insulating film 310 across the cell array region CA, the extension region EA, and the external region PA. The reflective structure 320 may have a multilayer structure in which one or more first reflective layers 322 and one or more second reflective layers 324 having a refractive index different from that of the first reflective layer 322 are alternately stacked. In some embodiments, the reflective structure 320 may include at least three pairs of the first reflective layer 322 and the second reflective layer 324.

[0160] In Figure 26 [the structure], the upper insulating film 310 and the reflective structure 320 are patterned. For example, a lithography process may be performed on the upper insulating film 310 and the reflective structure 320. The patterned upper insulating film 310 and the patterned reflective structure 320 may be disposed in the extension region EA and / or the external region PA and may not be disposed within the cell array region CA. Accordingly, the first base insulating film 102, the channel structure CH, and the dicing pattern WC may be exposed in the cell array region CA.

[0161] In Figure 27In [description], the upper portion of the data storage film 132 is removed. For example, an etching process may be performed on the data storage film 132 exposing the channel structure CH. As a result, the end portion (e.g., the upper end portion) of the semiconductor film 130 of the channel structure CH may be exposed.

[0162] In Figure 28 In [description], a source electrode layer 300 is formed. The source electrode layer 300 may be formed on the first substrate insulating film 102, the channel structure CH, the cutting pattern WC, and the reflection structure 320. In some embodiments, the source electrode layer 300 may extend conformally.

[0163] The source electrode layer 300 may be connected to the end portion (e.g., the upper end portion) of the exposed semiconductor film 130. The source electrode layer 300 may include a conductive material such as doped polysilicon, metal, or metal silicide, but the present disclosure is not limited thereto. For example, the source electrode layer 300 may include poly-Si doped with an N-type impurity such as P or As.

[0164] In Figure 29 In [description], a laser annealing process LA is performed on the source electrode layer 300. When the laser annealing process LA is performed, crystallization of the source electrode layer 300 may be induced, or impurities included in the source electrode layer 300 may be activated. Different from a general annealing process, the laser annealing process LA may be locally performed on the source electrode layer 300, thereby minimizing damage to the semiconductor device.

[0165] In addition, as described above, the reflection structure 320 may selectively block the laser entering the extended region EA and / or the external region PA during the laser annealing process LA, thereby preventing damage to the cell wiring structure 180 and / or the peripheral circuit wiring structure 280. Accordingly, a method of manufacturing a semiconductor device with improved yield and reliability may be provided.

[0166] Subsequently, in Figure 11 In [description], a patterning process is performed on the source electrode layer 300. Thereafter, a third interlayer insulating film 340, a first contact pattern 362, a second contact pattern 364, a third contact pattern 366, a fourth interlayer insulating film 350, a connection pattern 380, and a conductive pad 390 may be formed on the patterned source electrode layer 300. Accordingly, a Figures 7 to 11 semiconductor device may be obtained.

[0167] Figure 30 is a block diagram showing an electronic system according to some embodiments. Figure 31 is a perspective view showing an example of an electronic system according to some embodiments. Figure 32 is a cross-sectional view taken along line I-I of Figure 31 according to some embodiments. For convenience, descriptions of content overlapping with that described with reference to Figures 1 to 29 will be simplified or omitted.

[0168] In Figure 30 , the electronic system 1000 may include a semiconductor memory device 1100 and a controller 1200 electrically connected to the semiconductor memory device 1100. The electronic system 1000 may be a storage device including at least one semiconductor memory device 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive (SSD) device including at least one semiconductor memory device 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device.

[0169] The semiconductor memory device 1100 may be a non-volatile memory device (e.g., a NAND flash memory device) and may include, for example, Figures 7 to 16 at least one semiconductor device as depicted in

[0170] The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110 (e.g., Figure 7 row decoder 63 of Figure 7 ), a page buffer 1120 (e.g., Figure 7 page buffer 65 of Figures 7 to 16 ), and a logic circuit 1130 (e.g.,

[0171] The second structure 1100S may include a common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR as described above with reference to Figure 8 ). The cell strings CSTR may be connected to the decoder circuit 1110 through word lines WL, one or more string selection lines SSL, and one or more ground selection lines GSL. In addition, the cell strings CSTR may be connected to the page buffer 1120 through the bit lines BL. The second structure 1100S may correspond to a storage cell structure CELL of, for example, Figures 7 to 16 any one of

[0172] In some embodiments, the common source line CSL and the cell strings CSTR may be electrically connected to the decoder circuit 1110 through a first connection line 1115 extending from the first structure 1100F to the second structure 1100S.

[0173] In some embodiments, the bit lines BL may be electrically connected to the page buffer 1120 through a second connection line 1125.

[0174] The semiconductor memory device 1100 may be electrically connected to the logic circuit 1130 (e.g., Figure 7The input / output pad 1101 of the control logic 67) communicates with the controller 1200. The input / output pad 1101 can correspond to the conductive pad 390 of any one of Figures 7 to 16 The input / output pad 1101 can be electrically connected to the logic circuit 1130 through an input / output connection line 1135 extending from the first structure 1100F to the second structure 1100S. The input / output connection line 1135 can correspond to, for example, the vias 166 of any one of Figures 7 to 16 The through vias 166 of any one of

[0175] The controller 1200 can include a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the electronic system 1000 can include multiple semiconductor memory devices 1100. In this case, the controller 1200 can control the multiple semiconductor memory devices 1100.

[0176] The processor 1210 can control the operation of the entire electronic system 1000 including the controller 1200. The processor 1210 can operate according to specific firmware and can control the NAND controller 1220 to access the semiconductor memory device 1100. The NAND controller 1220 can include a NAND interface 1221, and the NAND interface 1221 processes the communication with the semiconductor memory device 1100. The control commands for controlling the semiconductor memory device 1100, the data to be written to the memory cell transistors MCT of the semiconductor memory device 1100, and the data to be read from the memory cell transistors MCT of the semiconductor memory device 1100 can be transmitted through the NAND interface 1221. The host interface 1230 can provide the communication ability between the electronic system 1000 and an external host. In response to receiving a control command from the external host through the host interface 1230, the processor 1210 can control the semiconductor memory device 1100.

[0177] In Figure 31 and Figure 32 the electronic system 2000 can include a main substrate 2001, a main controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 can be connected to the main controller 2002 via a wiring pattern 2005 formed on the main substrate 2001.

[0178] The main substrate 2001 may include a connector 2006, and the connector 2006 includes a plurality of pins to be coupled to an external host. The number and arrangement of the pins in the connector 2006 may vary according to the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 may communicate with the external host according to one of the following interfaces: USB, PCI-Express, SATA, and M-Phy for UFS. In some embodiments, the electronic system 2000 may operate relying on the power supplied by the external host through the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC), which distributes the power supplied from the external host to the main controller 2002 and the semiconductor package 2003.

[0179] The main controller 2002 may write data to the semiconductor package 2003 or read data from the semiconductor package 2003. The main controller 2002 may increase the operation speed of the electronic system 2000.

[0180] The DRAM 2004 may be used as a buffer memory to mitigate the speed difference between the semiconductor package 2003 as a data storage space and the external host. The DRAM 2004 included in the electronic system 2000 may be used as a cache memory and may provide a temporary storage space for the control operation of the semiconductor package 2003. If the electronic system 2000 includes the DRAM 2004, in addition to the NAND controller for controlling the semiconductor package 2003, the main controller 2002 may also include a DRAM controller for controlling the DRAM 2004.

[0181] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Both the first semiconductor package 2003a and the second semiconductor package 2003b may be semiconductor packages including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 located on the package substrate 2100, an adhesive layer 2300 provided on the bottom surface of the semiconductor chips 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0182] The package substrate 2100 may be a PCB including package upper pads 2130. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to Figure 30 the input / output pads 1101.

[0183] In some embodiments, the connection structure 2400 may be a bonding wire that electrically connects the input / output pad 2210 and the on-package pad 2130. Accordingly, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other through the bonding wire and may also be electrically connected to the on-package pads 2130 of the package substrate 2100. In some embodiments, the semiconductor chips 2200 in each of the first semiconductor package 2003a and the second semiconductor package 2003b may be electrically connected to each other through a connection structure including through-silicon vias (TSVs) instead of the connection structure 2400 that is a bonding wire.

[0184] In some embodiments, the main controller 2002 and the semiconductor chips 2200 may be included in a single package. In some embodiments, the main controller 2002 and the semiconductor chips 2200 may be mounted on an insertion substrate separated from the main substrate 2001 and may be connected to each other through lines formed on the insertion substrate.

[0185] In some embodiments, the package substrate 2100 may be a PCB. The package substrate 2100 may include a package substrate body 2120, on-package pads 2130 disposed on the upper surface of the package substrate body 2120, lower pads 2125 disposed on the bottom surface of the package substrate body 2120 or exposed through the bottom surface of the package substrate body 2120, and internal lines 2135 electrically connecting the on-package pads 2130 and the lower pads 2125 within the package substrate body 2120. The on-package pads 2130 may be electrically connected to the connection structure 2400. The lower pads 2125 may be connected to the wiring pattern 2005 of the main substrate 2001 of the electronic system 2000 as shown by a conductive connector 2800. Figure 31 as shown.

[0186] In the electronic system 2000, each semiconductor chip 2200 may include Figures 7 to 16 any of the semiconductor devices depicted in. For example, each semiconductor chip 2200 may include a memory cell structure CELL and a peripheral circuit structure PERI. For example, the memory cell structure CELL may include a first stacked structure SS1, a second stacked structure SS2, a channel structure CH, a cut pattern WC, a through via 166, a cell wiring structure 180, a source layer 300, an upper insulating film 310, and a reflective structure 320, as shown by Figures 7 to 16 as shown. The peripheral circuit structure PERI may include a peripheral circuit substrate 200 and a peripheral circuit wiring structure 280. The memory cell structure CELL and the peripheral circuit structure PERI may be joined to each other through a first bonding metal 190 and a second bonding metal 290.

[0187] Although this disclosure contains many specific implementation details, these should not be construed as limitations on the scope that can be claimed. Certain features described in the context of separate embodiments in this disclosure can also be implemented combinatorially in a single embodiment. Conversely, the various features described in the context of a single embodiment can also be implemented separately in multiple embodiments or in any suitable sub-combination. In addition, although the features may be described above as acting in certain combinations, in some cases, one or more features from a combination can be removed from the combination, and the combination can be intended to provide a sub-combination or a variation of a sub-combination.

Claims

1. A semiconductor device, the semiconductor device comprising: A source layer; A stacked structure including a plurality of gate electrodes, the plurality of gate electrodes being sequentially stacked on the source layer in a first direction and spaced apart from each other; An interlayer insulating film covering the stacked structure; A channel structure extending in the first direction, the channel structure extending into the stacked structure in a first region and connected to the source layer in the first region; And A reflection structure overlapping the interlayer insulating film in a second region surrounding the first region in the first direction, Wherein the reflection structure includes one or more first reflection layers and one or more second reflection layers, each of the first reflection layers having a first refractive index, the one or more second reflection layers being alternately stacked with the one or more first reflection layers in the first direction, and each of the second reflection layers having a second refractive index different from the first refractive index.

2. The semiconductor device according to claim 1, wherein, The reflection structure does not overlap the stacked structure in the first region.

3. The semiconductor device according to claim 1, wherein, At least a part of the reflection structure is between the source layer in the second region and the interlayer insulating film in the second region.

4. The semiconductor device according to claim 1, wherein, The reflection structure includes at least three pairs of the first reflection layers and the second reflection layers.

5. The semiconductor device according to claim 1, Among them, The first refractive index is less than the second refractive index, and Wherein a first thickness of the one or more first reflection layers is greater than a second thickness of the one or more second reflection layers.

6. The semiconductor device according to claim 5, Among them, The one or more first reflection layers include a silicon oxide film, and Wherein the one or more second reflection layers include a silicon nitride film.

7. The semiconductor device according to claim 1, wherein, The first thickness t1 of the one or more first reflection layers is selected within a range defined by Equation (1), and the second thickness t2 of the one or more second reflection layers is selected within a range defined by Equation (2): , wherein , (1) , where , (2) where λ represents the wavelength of the light irradiated onto the reflection structure, represents the first refractive index, represents the second refractive index.

8. The semiconductor device according to claim 7, Among them, The one or more first reflection layers include a top reflection layer provided at the top of the reflection structure, and Wherein a third thickness t3 of the top reflection layer is selected within a range defined by Equation (3): , where , (3) Where λ represents the wavelength of light irradiated onto the reflection structure, and n3 represents the refractive index of the top reflection layer.

9. The semiconductor device according to claim 1, wherein, The source layer includes a polysilicon film doped with impurities.

10. The semiconductor device according to claim 1, Among them, The channel structure includes: a semiconductor film extending in the first direction and intersecting the plurality of gate electrodes; and a data storage film interposed between the semiconductor film and the plurality of gate electrodes, and Wherein an end of the semiconductor film is in contact with the source layer.

11. The semiconductor device according to claim 1, the semiconductor device further comprising: An outer circuit structure including an outer circuit substrate and outer circuit elements located on the outer circuit substrate, Wherein, the stacked structure is interposed between the source layer and the peripheral circuit structure.

12. A semiconductor device, the semiconductor device comprising: A peripheral circuit structure, the peripheral circuit structure including a peripheral circuit substrate and peripheral circuit elements located on the peripheral circuit substrate; And A memory cell structure, the memory cell structure stacked on the peripheral circuit structure, the memory cell structure including a first region and a second region surrounding the first region, Wherein, the memory cell structure includes: A base insulating film, the base insulating film having a first surface facing the peripheral circuit structure and a second surface opposite to the first surface; A stacked structure, the stacked structure located on the first surface of the base insulating film and including a plurality of gate electrodes stacked sequentially and spaced apart from each other; An interlayer insulating film, the interlayer insulating film covering the stacked structure; A source layer, the source layer located on the second surface of the base insulating film; A channel structure, the channel structure intersecting the plurality of gate electrodes in the first region and connected to the source layer in the first region; and A reflection structure, the reflection structure interposed between the source layer in the second region and the interlayer insulating film in the second region, and Wherein, the reflection structure includes one or more first reflection layers and one or more second reflection layers, the one or more first reflection layers having a first refractive index and a first thickness, the one or more second reflection layers stacked alternately with the one or more first reflection layers and having a second refractive index different from the first refractive index.

13. The semiconductor device according to claim 12, wherein, The reflection structure is not interposed between the source layer in the first region and the stacked structure in the first region.

14. The semiconductor device according to claim 13, Among them, The first refractive index is less than the second refractive index, and Wherein, the first thickness of the one or more first reflection layers is greater than the second thickness of the one or more second reflection layers.

15. The semiconductor device according to claim 14, Among them, The one or more first reflection layers include a silicon oxide film, and Wherein, the one or more second reflection layers include a silicon nitride film.

16. The semiconductor device according to claim 15, Among them, The first thickness is 82 nm to 100 nm, and Wherein, the second thickness is 60 nm to 72 nm.

17. The semiconductor device according to claim 14, Among them, The one or more first reflection layers include a top reflection layer provided at the uppermost part of the reflection structure, and Wherein, the top reflection layer has a third thickness different from the first thickness.

18. The semiconductor device according to claim 17, Among them, The one or more first reflection layers include a silicon oxide film, Wherein, the one or more second reflection layers include a silicon nitride film, Wherein, the first thickness is 82 nm to 100 nm, Wherein, the second thickness is 60 nm to 72 nm, and Wherein, the third thickness is 40 nm to 210 nm.

19. The semiconductor device according to claim 12, wherein, The source layer includes a polysilicon film doped with impurities.

20. The semiconductor device according to claim 12, wherein, The reflection structure includes at least three pairs of the first reflection layer and the second reflection layer.

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