Magnetic memory device and method of manufacturing the same

Abstract

A magnetic memory device and a method of manufacturing the same are provided. The magnetic memory device includes a substrate, an interlayer insulating layer on the substrate, a data storage structure on the interlayer insulating layer, and a plurality of metal oxides on at least one side surface of the data storage structure, the data storage structure includes a lower electrode, a magnetic tunnel junction pattern, and an upper electrode sequentially stacked on the interlayer insulating layer, and at least one of the plurality of metal oxides contacts a side surface of the upper electrode.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0007346, filed with the Korean Intellectual Property Office on January 17, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The disclosed exemplary embodiments relate to a magnetic memory device and a method of manufacturing a magnetic memory device, and more particularly, to a magnetic memory device including a magnetic tunnel junction and a method of manufacturing a magnetic memory device including a magnetic tunnel junction. Background Art

[0003] There has been a need for high-speed and / or low-voltage semiconductor memory devices to implement power-consuming electronic devices. Magnetic memory devices have been developed to meet these needs. Magnetic memory devices have characteristics of high-speed operation and / or non-volatility.

[0004] With the development of the electronics industry, there has been an increasing need for highly integrated and / or low-power magnetic memory devices. Accordingly, various studies are being conducted on magnetic memory devices that can meet the requirements.

[0005] The information disclosed in this background art section has been known or derived by the inventors before or during the process of implementing the embodiments of the present application, or is technical information obtained during the process of implementing the embodiments. Accordingly, this background art section may contain information that does not constitute prior art known to the public. Summary of the Invention

[0006] One or more exemplary embodiments provide a magnetic memory device having improved electrical characteristics and a method of manufacturing a magnetic memory device.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.

[0008] According to an aspect of an exemplary embodiment, a magnetic memory device may include: a substrate; an interlayer insulating layer on the substrate; a data storage structure on the interlayer insulating layer; and a plurality of metal oxides on at least one side surface of the data storage structure, wherein the data storage structure includes a lower electrode, a magnetic tunnel junction pattern, and an upper electrode sequentially stacked on the interlayer insulating layer, and at least one of the plurality of metal oxides contacts a side surface of the upper electrode.

[0009] According to one aspect of an exemplary embodiment, a magnetic memory device may include: a substrate; an interlayer insulating layer on the substrate; a data storage structure on the interlayer insulating layer; and a plurality of metal oxides including a first plurality of metal oxides on an upper surface of the interlayer insulating layer and a second plurality of metal oxides on at least one side surface of the data storage structure, wherein the data storage structure includes a lower electrode, a magnetic tunnel junction pattern, and an upper electrode sequentially stacked on the interlayer insulating layer, the magnetic tunnel junction pattern includes a first magnetic pattern, a tunnel barrier pattern on the first magnetic pattern, and a second magnetic pattern on the tunnel barrier pattern, the second magnetic pattern is between the tunnel barrier pattern and the upper electrode, and some of the second plurality of metal oxides on the at least one side surface of the data storage structure are above the second magnetic pattern.

[0010] According to one aspect of an exemplary embodiment, a method of manufacturing a magnetic memory device may include: providing a substrate; and forming a data storage structure pattern on the substrate, wherein the step of forming the data storage structure pattern includes: forming a data storage structure layer; and etching the data storage structure layer, and wherein the step of forming the data storage structure layer includes: sequentially forming a lower electrode layer, a magnetic tunnel junction layer, and an upper electrode layer on the substrate; forming a hard mask pattern on the upper electrode layer; and performing an oxygen ion implantation process on a portion of the data storage structure layer exposed between the hard mask patterns. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features, and advantages of specific exemplary embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0012] Figure 1 is a diagram showing a unit memory cell of a magnetic memory device according to one or more embodiments.

[0013] Figure 2 is a plan view showing a magnetic memory device according to one or more embodiments.

[0014] Figure 3 is according to one or more embodiments along Figure 2 a cross-sectional view taken along line A-A' in

[0015] Figure 4 is according to one or more embodiments Figure 3 an enlarged view of a portion "CU" of

[0016] Figure 5 is a cross-sectional view showing an example of a magnetic tunnel junction pattern of a magnetic memory device according to one or more embodiments.

[0017] Figure 6is a cross-sectional view showing an example of a magnetic tunnel junction pattern of a magnetic memory device according to one or more embodiments.

[0018] Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A is a plan view showing a manufacturing process of a magnetic memory device according to one or more embodiments.

[0019] Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B and Figure 12B are cross-sectional views taken respectively along Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A of a magnetic memory device according to one or more embodiments.

[0020] Figure 13A and Figure 14A is a plan view showing a manufacturing process of a magnetic memory device according to one or more embodiments.

[0021] Figure 13B and Figure 14B are cross-sectional views taken respectively along Figure 13A and Figure 14A of a magnetic memory device according to one or more embodiments. DETAILED DESCRIPTION

[0022] Hereinafter, the disclosed example embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions thereof will be omitted. The embodiments described herein are example embodiments, and thus, the disclosure is not limited thereto and can be implemented in various other forms.

[0023] As used herein, when an expression such as "at least one of..." precedes a list of elements, it modifies the entire list of elements, rather than individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0024] It will be understood that when an element or layer is referred to as being “on,” “above,” “over,” “under,” “beneath,” “below,” “connected to,” or “coupled to” another element or layer, the element or layer can be directly on, above, over, under, beneath, below, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly above,” “directly over,” “directly under,” “directly beneath,” “directly below,” “directly connected to,” or “directly coupled to” another element or layer, no intervening elements or layers are present.

[0025] Figure 1 is a diagram showing a unit memory cell of a magnetic memory device according to one or more embodiments.

[0026] Referring to Figure 1 , the unit memory cell MC may include a memory element ME and a selection element SE. The memory element ME and the selection element SE may be electrically connected in series with each other. The memory element ME may be disposed between a bit line BL and the selection element SE, and connected to the bit line BL and the selection element SE. The selection element SE may be disposed between the memory element ME and a source line SL and connected to the memory element ME and the source line SL, and the selection element SE may be controlled by a word line WL. The selection element SE may include, for example, a bipolar transistor or a metal oxide semiconductor (MOS) field effect transistor (FET) (MOSFET).

[0027] The memory element ME may include a magnetic tunnel junction (or referred to as “magnetic tunnel junction pattern”) MTJ, the magnetic tunnel junction MTJ including magnetic patterns MP1 and MP2 spaced apart from each other and a tunnel barrier pattern TBR inserted between the magnetic patterns MP1 and MP2.

[0028] Generally, a magnetic memory device may include a magnetic tunnel junction pattern. The magnetic tunnel junction pattern may include two magnetic layers and an insulating layer disposed between the two magnetic layers. The resistance value of the magnetic tunnel junction pattern may change according to the magnetization directions of the two magnetic layers. For example, when the magnetization directions of the two magnetic layers are antiparallel to each other, the magnetic tunnel junction pattern may have a high resistance value. When the magnetization directions of the two magnetic layers are parallel to each other, the magnetic tunnel junction pattern may have a low resistance value. The difference between the high resistance value and the low resistance value of the magnetic tunnel junction pattern can be used to write / read logical data.

[0029] Regardless of the presence or absence of an external magnetic field generated under typical use conditions, one of the magnetic patterns MP1 and MP2 may have a fixed magnetization direction. Accordingly, one of the magnetic patterns MP1 and MP2 can be used as a reference magnetic pattern of the magnetic tunnel junction MTJ, and the other of the magnetic patterns MP1 and MP2 may have a magnetization direction that can be changed to one of two stable magnetization directions by an external magnetic field. Thus, the other of the magnetic patterns MP1 and MP2 can be used as a free magnetic pattern of the magnetic tunnel junction MTJ. The resistance of the magnetic tunnel junction MTJ can be greater when the magnetization directions of the reference magnetic pattern and the free magnetic pattern are antiparallel than when they are parallel. In other words, the resistance of the magnetic tunnel junction MTJ can be controlled by adjusting the magnetization direction of the free magnetic pattern. Accordingly, the difference in the resistance of the magnetic tunnel junction pattern MTJ caused by the difference in the magnetization directions between the reference magnetic pattern and the free magnetic pattern can be used as a data storage mechanism in the memory element ME.

[0030] Figure 2 is a plan view showing a magnetic memory device according to one or more embodiments. Figure 3 is a cross-sectional view taken along line A-A' in Figure 2 according to one or more embodiments.

[0031] Referring to Figure 2 and Figure 3 , a substrate 100 including a cell region CR and a peripheral region may be provided. The substrate 100 may be a semiconductor substrate including silicon (Si), silicon on insulator (SOI), silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), etc. The cell region CR may be a region of the substrate 100 where the memory cells MC are provided, and the peripheral region may be another region of the substrate 100 where peripheral circuits for driving the memory cells MC are provided. Figure 1 and the peripheral region may be another region of the substrate 100 where peripheral circuits for driving the memory cells MC are provided.

[0032] As shown in Figure 2 , a plurality of data storage structures DS may be arranged on the substrate 100 to be spaced apart in a first direction D1 and a second direction D2. A detailed description of the data storage structure DS is provided below.

[0033] The first direction D1 may be defined as a direction parallel to the upper surface 100U of the substrate 100. The second direction D2 may be parallel to the upper surface 100U of the substrate 100 and may be defined as a direction perpendicular to the first direction D1. The third direction D3 may be defined as a direction perpendicular to the upper surface 100U of the substrate 100.

[0034] The interconnect structures 102 and 104 may be disposed on the substrate 100. The interconnect structures 102 and 104 may include lower interconnects 102 and lower contacts 104 connected to the lower interconnects 102. The lower interconnects 102 may be spaced apart from the upper surface 100U of the substrate 100 in a third direction D3. The lower interconnects 102 may be between the substrate 100 and a second lower interlayer insulating layer 110 to be described below.

[0035] The lower contacts 104 may be disposed between the substrate 100 and the lower interconnects 102, and each lower interconnect 102 may be electrically connected to the substrate 100 through a corresponding one of the lower contacts 104. The lower interconnects 102 and the lower contacts 104 may include a metal (e.g., copper).

[0036] The select element SE (e.g., see Figure 1 ) may be disposed on the substrate 100. The select element may be, for example, a FET. Each lower interconnect 102 may be electrically connected to a corresponding terminal (e.g., a drain terminal) of the select element SE through a corresponding one of the lower contacts 104.

[0037] The first lower interlayer insulating layer 106 may be disposed on the substrate 100 to cover the interconnect structures 102 and 104. The first lower interlayer insulating layer 106 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0038] The lower insulating layer 105 may be disposed on the first lower interlayer insulating layer 106. The lower insulating layer 105 may cover the exposed upper surface of the uppermost lower interconnect 102.

[0039] The second lower interlayer insulating layer 110 may be disposed on the lower insulating layer 105. That is, the lower insulating layer 105 may be inserted between the first lower interlayer insulating layer 106 and the second lower interlayer insulating layer 110. In this case, the upper surface of the second lower interlayer insulating layer 110 may have a recess 110R facing the substrate 100. That is, the recess 110R may protrude downward toward the substrate 100.

[0040] The lower insulating layer 105 may include a material having an etching selectivity with respect to the first lower interlayer insulating layer 106 and the second lower interlayer insulating layer 110. The lower insulating layer 105 may include, for example, silicon carbonitride (SiCN). For example, the second lower interlayer insulating layer 110 may include silicon oxide.

[0041] The lower contact plug 150 may be disposed in the second lower interlayer insulating layer 110. The lower contact plug 150 may penetrate the second lower interlayer insulating layer 110 and the lower insulating layer 105, and may be electrically connected to the corresponding lower interconnect 102. The lower contact plug 150 may include at least one of a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, titanium, and / or tantalum), a metal-semiconductor compound (e.g., metal silicide), and a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and / or tungsten nitride).

[0042] The data storage structure DS may be disposed on the second lower interlayer insulating layer 110 and the lower contact plug 150. The data storage structure DS may also be referred to as the data storage structure pattern DS. Each data storage structure DS may be electrically connected to the corresponding lower contact plug 150.

[0043] Each data storage structure DS may include a lower electrode BE, a magnetic tunnel junction pattern MTJ, and an upper electrode TE that are sequentially stacked on the corresponding lower contact plug 150. The lower electrode BE may be disposed between each lower contact plug 150 and the magnetic tunnel junction pattern MTJ, and the magnetic tunnel junction pattern MTJ may be disposed between the lower electrode BE and the upper electrode TE.

[0044] The magnetic tunnel junction pattern MTJ may include a first magnetic pattern MP1, a second magnetic pattern MP2, and a tunnel barrier pattern TBR between the first magnetic pattern MP1 and the second magnetic pattern MP2. The first magnetic pattern MP1 may be disposed between the lower electrode BE and the tunnel barrier pattern TBR, and the second magnetic pattern MP2 may be disposed between the upper electrode TE and the tunnel barrier pattern TBR. That is, the tunnel barrier pattern TBR may be disposed on the first magnetic pattern MP1, and the second magnetic pattern MP2 may be disposed on the tunnel barrier pattern TBR.

[0045] The lower electrode BE and the upper electrode TE may include a metal material (e.g., titanium (Ti), tantalum (Ta), platinum (Pt), palladium (Pd), copper (Cu), tungsten (W), molybdenum (Mo), ruthenium (Ru)) and a conductive metal nitride (e.g., titanium nitride or tantalum nitride).

[0046] The magnetic tunnel junction pattern MTJ may include a metal material (e.g., cobalt (Co), iron (Fe), nickel (Ni), tungsten (W), molybdenum (Mo), tantalum (Ta), ruthenium (Ru), platinum (Pt), zirconium (Zr), copper (Cu), iridium (Ir), and rhodium (Rh)), and a detailed description of the magnetic tunnel junction pattern MTJ will be provided later in Figure 5 and Figure 6 will be described.

[0047] The capping pattern may be disposed between the magnetic tunnel junction pattern MTJ and the upper electrode TE. The capping pattern may include at least one of tantalum (Ta), ruthenium (Ru), molybdenum (Mo), aluminum (Al), copper (Cu), gold (Au), silver (Ag), titanium (Ti), tantalum nitride (TaN), and titanium nitride (TiN).

[0048] The protective insulating layer 170 may be disposed on the upper surface of the second lower interlayer insulating layer 110 to cover the recess 110R. The protective insulating layer 170 may extend on each side surface of the data storage structure DS and surround each side surface of the data storage structure DS in a plan view. That is, the protective insulating layer 170 may cover the side surfaces of the lower electrode BE, the magnetic tunnel junction pattern MTJ, and the upper electrode TE. For example, the protective insulating layer 170 may include silicon nitride. Optionally, the protective insulating layer 170 may conformally cover the top surface of the recess 110R of the second lower interlayer insulating layer 110 and the side surfaces of the data storage structure DS.

[0049] The upper insulating layer 180 may be disposed on the second lower interlayer insulating layer 110. The upper insulating layer 180 may fill the space between the data storage structures DS. In other words, the protective insulating layer 170 may be inserted between the upper insulating layer 180 and each side surface of the data storage structure DS.

[0050] The upper interconnect layer 200 may be disposed on the data storage structure DS and the upper insulating layer 180. The upper interconnect layer 200 may extend in the first direction D1. The data storage structure DS may be electrically connected to the upper interconnect layer 200. Specifically, the upper electrode TE of the data storage structure DS may be connected to the lower surface of the upper interconnect layer 200, and the uppermost surface of the protective insulating layer 170 may contact the lower surface of the upper interconnect layer 200. The upper interconnect layer 200 may be electrically connected to the magnetic tunnel junction pattern MTJ through the upper electrode TE and may be used as a bit line BL (for example, see Figure 1 )

[0051] Figure 4 is an enlarged view of a portion "CU" according to one or more embodiments Figure 3 of.

[0052] Refer to Figure 4, the metal oxide MO can be disposed on the upper surface of the second interlayer insulating layer 110 (e.g., on the upper surface of the recess 110R) and on the side surfaces (e.g., at least one side surface) of the data storage structure DS. According to one or more embodiments, oxygen ions can be disposed together with the metal oxide MO on the upper surface of the second interlayer insulating layer 110 and on the side surfaces of the data storage structure DS. The amount of the metal oxide MO per unit area on the second interlayer insulating layer 110 (e.g., the density of the metal oxide, the concentration of the metal oxide, etc.) can be higher than the amount of the metal oxide MO per unit area on the side surfaces of the data storage structure DS (e.g., the density of the metal oxide, the concentration of the metal oxide, etc.).

[0053] Specifically, the metal oxide MO can contact the recess 110R of the second interlayer insulating layer 110 and the side surfaces of the lower electrode BE, the first magnetic pattern MP1, the tunnel barrier pattern TBR, and the upper electrode TE. That is, a part of the metal oxide MO on the side surfaces of the data storage structure DS can be disposed above the second magnetic pattern MP2. The protective insulating layer 170 can cover the metal oxide MO (e.g., at least a part of the metal oxide MO) on the upper surface of the second interlayer insulating layer 110 and on the side surfaces of the data storage structure DS.

[0054] The metal oxide MO on the side surfaces of the data storage structure DS can have a concentration gradient in the third direction D3. That is, the amount of the metal oxide MO per unit area on the side surfaces of the data storage structure DS (e.g., the density of the metal oxide, the concentration of the metal oxide, etc.) can increase (e.g., in the third direction D3) from the side surface of the lower electrode BE to the side surface of the upper electrode TE.

[0055] Each of the lower electrode BE, the magnetic tunnel junction pattern MTJ, and the upper electrode TE can include a metal material, and the metal oxide MO can be an oxide of at least some (or at least one) of the metal materials. Specifically, in the ion beam etching process ( Figure 11A and Figure 11B ), when the lower electrode layer ( Figure 11A and Figure 11B of BEL), the magnetic tunnel junction layer ( Figure 11A and Figure 11B of MTJL), and the upper electrode layer ( Figure 11A and Figure 11BWhen the oxidation part (190L) is etched, the metal oxide MO can be a redeposited material attached to the side surface of the data storage structure DS and the upper surface of the second interlayer insulating layer 110. As an example, the metal oxide MO can be an oxide of at least one of the following: titanium (Ti), tantalum (Ta), platinum (Pt), palladium (Pd), copper (Cu), tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), iron (Fe), nickel (Ni), zirconium (Zr), copper (Cu), iridium (Ir), and rhodium (Rh).

[0056] Figure 5 is a cross-sectional view showing an example of a magnetic tunnel junction pattern of a magnetic memory device according to one or more embodiments. Figure 6 is a cross-sectional view showing an example of a magnetic tunnel junction pattern of a magnetic memory device according to one or more embodiments.

[0057] Referring to Figure 5 and Figure 6 , the first magnetic pattern MP1 can be a reference layer having a magnetization direction MD1 fixed to a specific direction, and the second magnetic pattern MP2 can be a free layer having a magnetization direction MD2 that can be changed to be parallel or antiparallel to the magnetization direction MD1 of the first magnetic pattern MP1. Figure 5 and Figure 6 shows an example in which the second magnetic pattern MP2 is used as a free layer, but the embodiments are not limited thereto. In one or more embodiments, the first magnetic pattern MP1 can be a free layer and the second magnetic pattern MP2 can be a reference layer.

[0058] Referring to Figure 5, as an example, the magnetization direction MD1 of the first magnetic pattern MP1 and the magnetization direction MD2 of the second magnetic pattern MP2 may be substantially perpendicular to the interface between the tunnel barrier pattern TBR and the second magnetic pattern MP2. In this case, each of the first magnetic pattern MP1 and the second magnetic pattern MP2 may include an intrinsic perpendicular magnetic material or a non-intrinsic perpendicular magnetic material. The intrinsic perpendicular magnetic material may include a material that has perpendicular magnetization properties even in the absence of external factors. The intrinsic perpendicular magnetic material may include, for example, perpendicular magnetic materials (e.g., CoFeTb, CoFeGd, or CoFeDy), perpendicular magnetic materials having an L10 structure, CoPt alloys having a hexagonal close-packed (HCP) lattice structure, or perpendicular magnetic structures. The perpendicular magnetic material having an L10 structure may include, for example, FePt having an L10 structure, FePd having an L10 structure, CoPd having an L10 structure, or CoPt having an L10 structure. The perpendicular magnetic structure may include alternately and repeatedly stacked magnetic layers and non-magnetic layers. As an example, the perpendicular magnetic structure may include at least one of (Co / Pt)n, (CoFe / Pt)n, (CoFe / Pd)n, (Co / Pd)n, (Co / Ni)n, (CoNi / Pt)n, (CoCr / Pt)n, and (CoCr / Pd)n, where "n" represents the number of bilayers. The non-intrinsic perpendicular magnetic material may include a material that has intrinsic in-plane magnetization properties but has perpendicular magnetization properties due to external factors. For example, the non-intrinsic perpendicular magnetic material may have perpendicular magnetization properties due to magnetic anisotropy caused by the combination of the tunnel barrier pattern TBR and the first magnetic pattern MP1 (or the second magnetic pattern MP2). The non-intrinsic perpendicular magnetic material may include, for example, CoFeB.

[0059] Referring to Figure 6 , as another example, the magnetization direction MD1 of the first magnetic pattern MP1 and the magnetization direction MD2 of the second magnetic pattern MP2 may be parallel to the interface between the tunnel barrier pattern TBR and the second magnetic pattern MP2. In this case, each of the first magnetic pattern MP1 and the second magnetic pattern MP2 may include a ferromagnetic material. The first magnetic pattern MP1 may further include an antiferromagnetic material for fixing the magnetization direction of the ferromagnetic material in the first magnetic pattern MP1.

[0060] Each of the first magnetic pattern MP1 and the second magnetic pattern MP2 may include a Co-based Heusler alloy. The tunnel barrier pattern TBR may include at least a magnesium oxide (MgO) layer, a titanium oxide (TiO) layer, an aluminum oxide (AlO) layer, a magnesium zinc oxide (MgZnO) layer, or a magnesium borate (MgBO) layer.

[0061] Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A are plan views showing a manufacturing process of a magnetic memory device according to one or more embodiments. Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B and Figure 12B are cross-sectional views taken along lines B-B' respectively according to one or more embodiments along Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A .

[0062] Referring to Figure 7A and Figure 7B , a substrate 100 can be provided, and a selection element can be formed on the substrate 100. A first interlayer insulating layer 106 can be formed on the upper surface 100U of the substrate 100 to cover the selection element.

[0063] The interconnect structures 102 and 104 can be formed to penetrate the first interlayer insulating layer 106, and the lower insulating layer 105 can be formed to cover the upper surfaces of the interconnect structures 102 and 104 and the upper surface of the first interlayer insulating layer 106.

[0064] A second interlayer insulating layer 110 can be formed on the lower insulating layer 105. Thereafter, a lower contact plug 150 can be formed to penetrate the second interlayer insulating layer 110. The step of forming the lower contact plug 150 can include etching the second interlayer insulating layer 110 and the lower insulating layer 105 until the upper surface of the uppermost lower interconnect 102 is exposed to form a hole, and filling the hole with a metallic material.

[0065] Referring to Figure 8A and Figure 8B , a lower electrode layer BEL and a magnetic tunnel junction layer MTJL can be sequentially formed on the second interlayer insulating layer 110. The magnetic tunnel junction layer MTJL can include a first magnetic layer MP1L, a tunnel barrier layer TBRL, and a second magnetic layer MP2L sequentially stacked on the lower electrode layer BEL. The lower electrode layer BEL and the magnetic tunnel junction layer MTJL can be formed by sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). After forming the magnetic tunnel junction layer MTJL, a capping layer can be formed on the second magnetic layer MP2L.

[0066] Referring to Figure 9A and Figure 9B, an upper electrode layer 190L can be formed on the magnetic tunnel junction layer MTJL. The upper electrode layer 190L can also be referred to as the top electrode layer TEL. When forming the upper electrode layer 190L, a data storage structure layer DSL including the lower electrode layer BEL, the magnetic tunnel junction layer MTJL, and the upper electrode layer 190L can be formed.

[0067] Thereafter, a first hard mask pattern HM1 can be formed on the upper electrode layer 190L. The first hard mask pattern HM1 can define the portion where the data storage structure DS to be formed will be formed Figure 2 and Figure 3 as described in. That is, the region of the data storage structure layer DSL that overlaps with the first hard mask pattern HM1 can be the region where the data storage structure DS to be formed will be formed Figure 2 and Figure 3 as described in.

[0068] Referring to Figure 10A and Figure 10B , an oxygen ion implantation process can be performed on the portion of the data storage structure layer DSL where the first hard mask pattern HM1 is not provided. In other words, an oxygen ion implantation process can be performed on the portion of the data storage structure layer DSL that is exposed between the first hard mask patterns HM1. The concentration of oxygen ions implanted into the data storage structure layer DSL through the oxygen ion implantation process can increase from the lower electrode layer BEL to the upper electrode layer 190L. The ion implantation process can be performed on the upper surface of the data storage structure layer DSL in the third direction D3 in the range of 10 nm to 999 nm. In this case, the ion implantation energy used in the oxygen ion implantation process can be 10 keV to 80 keV.

[0069] When performing the oxygen ion implantation process, some regions of the data storage structure layer DSL where the first hard mask pattern HM1 is not provided can include metal oxides. In other words, when performing the oxygen ion implantation process, metal oxides can be formed on the portion of the data storage structure layer DSL that is not exposed by the first hard mask pattern HM1. According to one or more embodiments, the oxygen ion implantation process can be performed in a vacuum state.

[0070] After removing the first hard mask pattern HM1, a heat treatment process can be performed on the data storage structure layer DSL. The heat treatment process can be performed at a temperature of 200 °C to 400 °C for 1 hour to 2 hours.

[0071] Referring to Figure 11A and Figure 11B , the upper electrode layer 190L can be patterned to form a conductive mask pattern 190. The conductive mask pattern 190 can define the region where the data storage structure DS to be formed will be formed Figure 2 and Figure 3 as described in.

[0072] Thereafter, the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL can be sequentially etched using the conductive mask pattern 190 as an etch mask. When etching the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL, a magnetic tunnel junction pattern MTJ and a bottom electrode BE can be formed on the second interlayer insulating layer 110.

[0073] The step of etching the magnetic tunnel junction layer MTJL can include sequentially etching the second magnetic layer MP2L, the tunnel barrier layer TBRL, and the first magnetic layer MP1L using the conductive mask pattern 190 as an etch mask. The second magnetic layer MP2L, the tunnel barrier layer TBRL, and the first magnetic layer MP1L can be etched to form a second magnetic pattern MP2, a tunnel barrier pattern TBR, and a first magnetic pattern MP1, respectively.

[0074] For example, the etching process for etching the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL can be an ion beam etching process using an ion beam. The ion beam can include inert ions. Recesses 110R can be formed on the upper surface of the second interlayer insulating layer 110 through the etching process.

[0075] After the etching process, at least a part of the conductive mask pattern 190 can remain on the magnetic tunnel junction pattern MTJ. The conductive mask pattern 190 can be used as the top electrode TE. That is, the conductive mask pattern 190 can be referred to as the top electrode TE. The top electrode TE, the magnetic tunnel junction pattern MTJ, and the bottom electrode BE can constitute a data storage structure DS.

[0076] When etching the data storage structure layer DSL to form the data storage structure DS, a metal oxide MO can be redeposited on the side surface of the data storage structure DS and on the upper surface of the recess 110R of the second interlayer insulating layer 110. The metal oxide MO (for example, at least one of the metal oxides MO in the metal oxide MO) can contact the side surface of the top electrode 190 / TE. Therefore, the metal oxide MO with reduced conductivity can adhere to the side surface of the data storage structure DS and the upper surface of the recess 110R, thereby reducing the phenomenon of electrical short circuit of the data storage structure DS.

[0077] Refer to Figure 12A and Figure 12B and, a protective insulating layer 170 can be formed on the second interlayer insulating layer 110. The protective insulating layer 170 can conformally cover the upper surface and the side surface of the data storage structure DS, and cover the recess 110R of the second interlayer insulating layer 110.

[0078] An upper insulating layer 180 can be formed on the protective insulating layer 170. The upper insulating layer 180 can cover the data storage structure DS and fill the space between the data storage structures DS.

[0079] After removing the upper portions of the protective insulating layer 170 and the upper insulating layer 180, an upper interconnect layer 200 can be formed on the upper insulating layer 180 and the data storage structure DS, thereby forming a magnetic memory device as shown in Figure 3 the magnetic memory device shown in

[0080] Figure 13A and Figure 14A are plan views showing a manufacturing process of a magnetic memory device according to one or more embodiments. Figure 13B and Figure 14B are cross-sectional views taken along lines C-C' of Figure 13A and Figure 14A respectively according to one or more embodiments.

[0081] Referring to Figure 8A , Figure 8B , Figure 13A and Figure 13B , a conductive mask pattern 190 can be formed on the magnetic tunnel junction layer MTJL. The conductive mask pattern 190 can define a region where the data storage structure DS will be formed. The step of forming the conductive mask pattern 190 can include forming an upper electrode layer on the magnetic tunnel junction layer MTJL and patterning the upper electrode layer. Figure 3 The step of forming the conductive mask pattern 190 may include forming an upper electrode layer on the magnetic tunnel junction layer MTJL and patterning the upper electrode layer.

[0082] Referring to Figure 14A and Figure 14B , a second hard mask pattern HM2 can be formed on the conductive mask pattern 190. Thereafter, an oxygen ion implantation process can be performed on some regions of the magnetic tunnel junction layer MTJL and the lower electrode layer BEL where the second hard mask pattern HM2 and the conductive mask pattern 190 are not provided. The concentration of oxygen ions implanted into the magnetic tunnel junction layer MTJL and the lower electrode layer BEL through the oxygen ion implantation process can increase from the lower electrode layer BEL to the second magnetic layer MP2L included in the magnetic tunnel junction layer MTJL.

[0083] When the oxygen ion implantation process is performed, the internal regions of the lower electrode layer BEL and the magnetic tunnel junction layer MTJL where the second hard mask pattern HM2 and the conductive mask pattern 190 are not provided may include metal oxides.

[0084] After the oxygen ion implantation process, the second hard mask pattern HM2 can be removed. After removing the second hard mask pattern HM2, a process similar to the process described in Figures 11A to 12A can be performed on the magnetic tunnel junction layer MTJL using the conductive mask pattern 190 as an etching mask, thereby forming the magnetic memory device shown in Figure 3 the magnetic memory device shown in

[0085] In the manufacturing process of a magnetic memory device according to one or more embodiments, an oxygen ion implantation process may be performed on the data storage structure layer before etching the data storage structure layer. When the oxygen ion implantation process is performed, some regions of the data storage structure layer may include metal oxides. When the data storage structure layer is etched to form a data storage structure pattern, the metal oxides may be redeposited on the side surfaces of each data storage structure pattern and on the interlayer insulating layer between the data storage structure patterns. Thus, the metal oxides having reduced conductivity may adhere to the side surfaces of the data storage structure patterns, thereby reducing the phenomenon of electrical short circuits in the data storage structure patterns. In addition, due to the metal oxides on the interlayer insulating layer, the electrical leakage between the data storage structure patterns may be reduced. Therefore, the electrical performance and reliability of the magnetic memory device may be improved.

[0086] A magnetic memory device according to one or more embodiments may be provided with metal oxides on each side surface of the data storage structure. The metal oxides may be oxides of the metal materials included in each data storage structure and may have low conductivity. Due to the metal oxides, the electrical short circuits of the data storage structure may be reduced. Therefore, the electrical characteristics and reliability of the magnetic memory device may be improved.

[0087] Each embodiment provided in the above description does not exclude being related to one or more features of additional examples or additional embodiments that are also provided herein or not provided herein but consistent with the disclosure.

[0088] Although the disclosure has been specifically shown and described with reference to the disclosed embodiments, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A magnetic memory device, comprising: A substrate; An interlayer insulating layer on the substrate; A data storage structure on the interlayer insulating layer; And A metal oxide on at least one side surface of the data storage structure, Wherein the data storage structure includes a lower electrode, a magnetic tunnel junction pattern, and an upper electrode sequentially stacked on the interlayer insulating layer, and Wherein at least a part of the metal oxide contacts the side surface of the upper electrode.

2. The magnetic memory device according to claim 1, wherein, Each of the lower electrode, the magnetic tunnel junction pattern, and the upper electrode includes a metal material, and Wherein the metal oxide is an oxide of at least one of the metal materials.

3. The magnetic memory device according to claim 2, wherein, The metal oxide includes an oxide of at least one of titanium, tantalum, platinum, palladium, copper, tungsten, molybdenum, ruthenium, cobalt, iron, nickel, zirconium, copper, iridium, and rhodium.

4. The magnetic memory device according to any one of claims 1 to 3 further comprises: A protective insulating layer on the upper surface of the interlayer insulating layer, Wherein the protective insulating layer covers at least a part of the metal oxide.

5. The magnetic memory device according to claim 4, wherein, The interlayer insulating layer includes silicon oxide, and Wherein the protective insulating layer includes silicon nitride.

6. A magnetic memory device, comprising: A substrate; An interlayer insulating layer on the substrate; A data storage structure on the interlayer insulating layer; And A metal oxide including a first part on the upper surface of the interlayer insulating layer and a second part on at least one side surface of the data storage structure of the metal oxide, Wherein the data storage structure includes a lower electrode, a magnetic tunnel junction pattern, and an upper electrode sequentially stacked on the interlayer insulating layer, Wherein the magnetic tunnel junction pattern includes a first magnetic pattern, a tunnel barrier pattern on the first magnetic pattern, and a second magnetic pattern on the tunnel barrier pattern, Wherein the second magnetic pattern is between the tunnel barrier pattern and the upper electrode, and Wherein a part of the second part of the metal oxide on the at least one side surface of the data storage structure is above the second magnetic pattern.

7. The magnetic memory device according to claim 6, wherein, The first amount of the metal oxide per unit area on the upper surface of the interlayer insulating layer is higher than the second amount of the metal oxide per unit area on the at least one side surface of the data storage structure.

8. The magnetic memory device according to claim 6, wherein, Each of the lower electrode, the magnetic tunnel junction pattern, and the upper electrode includes a metal material, and Wherein the metal oxide is an oxide of at least one of the metal materials.

9. The magnetic memory device according to claim 6, wherein, The amount of the metal oxide per unit area on the at least one side surface of the data storage structure increases in a first direction from the side surface of the lower electrode to the side surface of the upper electrode, the first direction being perpendicular to a second direction, and the second direction being parallel to the upper surface of the substrate.

10. The magnetic memory device according to any one of claims 6 to 9, further comprising: A lower interconnect between the substrate and the interlayer insulating layer; A contact plug between the lower interconnect and the data storage structure, and An upper interconnect layer on the data storage structure.

11. A method of manufacturing a magnetic memory device, the method comprising: Providing a substrate; And Forming a data storage structure pattern on the substrate, Wherein the step of forming the data storage structure pattern includes: forming a data storage structure layer; and etching the data storage structure layer, and Among them, the steps of forming the data storage structure layer include: sequentially forming a lower electrode layer, a magnetic tunnel junction layer, and an upper electrode layer on a substrate; forming a hard mask pattern on the upper electrode layer; and performing an oxygen ion implantation process on the portion of the data storage structure layer exposed between the hard mask patterns.

12. The method according to claim 11, wherein, In the oxygen ion implantation process, the ion implantation energy implanted into the data storage structure layer is 10 keV to 80 keV.

13. The method according to claim 11 further comprises: After performing the oxygen ion implantation process, a heat treatment process is performed on the data storage structure layer. Among them, the heat treatment process is performed at 200 °C to 400 °C.

14. The method according to claim 11, wherein The step of etching the data storage structure layer includes: performing an ion beam etching process.

15. The method according to claim 11, wherein, The step of etching the data storage structure layer includes: forming a conductive mask pattern by patterning the upper electrode layer; and using the conductive mask pattern as an etching mask to etch the magnetic tunnel junction layer and the lower electrode layer.

16. The method according to claim 11, wherein, The step of performing the oxygen ion implantation process includes: forming a metal oxide on the portion of the data storage structure layer not exposed by the hard mask pattern.

17. The method according to claim 11, wherein The step of performing the oxygen ion implantation process includes: implanting oxygen ions in the range of 10 nm to 999 nm from the upper surface of the data storage structure layer in a first direction, the first direction being perpendicular to a second direction, and the second direction being parallel to the upper surface of the substrate.

18. The method according to claim 11, further comprising, before forming the data storage structure pattern: forming an interlayer insulating layer on the substrate; and forming a contact plug penetrating the interlayer insulating layer.

19. The method according to claim 18, wherein, The step of etching the data storage structure layer includes: forming a recess at the upper surface of the interlayer insulating layer, the recess facing the substrate.

20. The method according to claim 19, further comprising: Form a protective insulating layer on the side surface of the data storage structure pattern and the upper surface of the interlayer insulating layer.

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