High-voltage planar gate IGBT device with low conduction voltage drop

Abstract

The invention, which belongs to the technical field of the semiconductor device, relates to a low-conduction-voltage-drop high-voltage planar gate IGBT device comprising a CT and a Gate, and the CT and the Gate form a square primitive cell structure. Gates are not placed at the four corners of the square primitive cell, and the CTs are located at the four corners of the square primitive cell and located on the outer sides of the Gates; the square primitive cell design can adjust the area ratio of the CT and the Gate, and compromise optimization of conduction voltage drop and short-circuit current is achieved; the Gate is in a polygon design, no Gate is arranged in the middle, and the area without the Gate is also in a polygon shape. According to the low-conduction-voltage-drop high-voltage planar gate IGBT device, a strip-shaped and polygon design combined structure is adopted, the flexibility of key parameter design of breakdown voltage, conduction voltage drop and short-circuit current of the device is improved, and compromise optimization of increasing the breakdown voltage, reducing the conduction voltage drop and improving the short-circuit capacity can be better achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a low on-state voltage high-voltage planar-gate IGBT device. Background Art

[0002] IGBT, that is, insulated gate bipolar transistor, is composed of BJT (bipolar junction transistor) and MOS (insulated gate field effect transistor), and is a composite fully-controlled voltage-driven power semiconductor device. IGBT has the characteristics of high input impedance, low on-state voltage, fast switching speed, high voltage and current handling capabilities, good thermal stability, etc., and is suitable for high-power applications. IGBT is widely used in fields such as electric vehicles, renewable energy systems, industrial drives, and household appliances.

[0003] Figure 1 FIG. is a schematic diagram of the cell structure of a conventional planar-gate IGBT in the prior art, which is a non-punch-through (NPT) type IGBT, and the gate is a planar-gate structure. This structure has a high on-state voltage, but has high short-circuit resistance and avalanche resistance. Figure 2 FIG. is a schematic diagram of the cell structure of a conventional large-cell-size planar-gate IGBT in the prior art. Compared with Figure 1 , the cell size is increased, and a floating P-type region needs to be added in the middle of the cell. One is to ensure the breakdown voltage under the condition of a large cell size, and the other is that the floating P-type region can make the holes injected from the back P+ accumulate here, further increasing the large injection effect of carriers and reducing the on-state voltage. Figure 3 FIG. corresponds to Figure 2 A top view structure diagram of CT (contact hole) and Gate (gate) in a cell of a conventional large-cell-size planar-gate IGBT. CT is connected to the Emitter. This cell is a strip design. For the strip cell design, reducing the on-state voltage will cause a significant increase in the short-circuit current.

[0004] Therefore, to solve the above problems, the present application proposes a low on-state voltage high-voltage planar-gate IGBT device to solve the problems existing above. Compared with the prior art, it adopts a structure combining strip and polygon designs, improving the flexibility of the design of several key parameters such as the breakdown voltage, on-state voltage, and short-circuit current of the device, and can better achieve a trade-off optimization of increasing the breakdown voltage, reducing the on-state voltage, and improving the short-circuit resistance. Summary of the Invention

[0005] In view of the deficiencies of the prior art, the present invention provides a low on-state voltage high-voltage planar-gate IGBT device, which has the advantage of being able to better achieve a trade-off optimization of increasing the breakdown voltage, reducing the on-state voltage, and improving the short-circuit resistance.

[0006] To achieve the above object, the present invention provides the following technical solution: A low on-state voltage high-voltage planar gate IGBT device, including a CT and a Gate, and the CT and the Gate form a square cell structure;

[0007] No Gate is placed at the four corners of the square cell, and the CT is located at the four corners of the square cell, outside the Gate;

[0008] The square cell design can adjust the area ratio of the CT and the Gate, realizing a trade-off optimization of the on-state voltage and the short-circuit current.

[0009] Preferably, the Gate is designed as a polygon, with no Gate in the middle, and the area without Gate is also a polygon, and the side length of the polygon can be flexibly adjusted according to the design parameter requirements.

[0010] Preferably, the areas without Gate in the square cell can all form P-type regions, and there are D dimensions in the horizontal and vertical directions and D1 dimensions at 45 degrees for the spacing of the P-type regions.

[0011] Preferably, the spacing of the P-type regions can be adjusted in different directions, and the breakdown voltage position can be changed by adjusting the D and D1 dimensions, increasing the flexibility of the breakdown voltage design;

[0012] The CT design can be designed as a hole-type structure. The overall area of the hole-type structure CT accounts for a relatively small proportion. An N+ can be formed between the outside of the CT and the middle of the Gate to provide a current path. The N+ channel of the hole-type CT design is relatively small and is suitable for products with a small current density.

[0013] Preferably, the CT can be designed as a plurality of annular strip structures. When the overall area of the annular strip structure CT accounts for a relatively large proportion, the N+ channel is relatively large and is suitable for products with a large current density;

[0014] Compared with the traditional strip cell design, through the square cell design, the area ratio of the CT decreases, the effective channel density decreases, and the on-state voltage increases, but the area ratio of the Gate can be increased, increasing the large carrier injection effect, thereby reducing the on-state voltage.

[0015] Preferably, a JFET resistance is introduced between different P regions of the square cell, and the spacing of the P-type regions can be adjusted. On the one hand, the magnitude and position of the breakdown voltage can be adjusted, and on the other hand, the JFET resistance at different positions can be adjusted to adjust the circuit path, reduce the JFET resistance, and further reduce the on-state voltage.

[0016] Compared with the prior art, the present invention provides a low on-state voltage high-voltage planar gate IGBT device, having the following beneficial effects:

[0017] 1. For this low on - state voltage high - voltage planar - gate IGBT device, the spacing of the P - type regions has horizontal and vertical D dimensions and a 45 - degree square D1 dimension, and these dimensions can be adjusted in different directions. By adjusting the D and D1 dimensions, the position of the breakdown voltage can be flexibly adjusted to meet the specific requirements for the breakdown voltage in different application scenarios, effectively improving the flexibility in the design of the breakdown voltage.

[0018] 2. For this low on - state voltage high - voltage planar - gate IGBT device, compared with the traditional strip - cell design through the square - cell design, although the CT area ratio decreases, the effective channel density decreases, and the on - state voltage increases to some extent, it can increase the Gate area ratio. The increase in the Gate area ratio will enhance the large - injection effect of carriers, thereby reducing the on - state voltage, and to a certain extent, compensating for the increase in the on - state voltage caused by the decrease in the CT area ratio, achieving the advantage of enhancing the large - injection effect of carriers.

[0019] 3. For this low on - state voltage high - voltage planar - gate IGBT device, a JFET resistance is introduced between different P - type regions of the square cell. The adjustment of the spacing of the P - type regions can not only adjust the magnitude and position of the breakdown voltage but also adjust the JFET resistance at different positions. By reasonably adjusting the spacing of the P - type regions, the circuit path can be adjusted, the JFET resistance can be reduced, the on - state voltage can be further reduced, and the on - state performance of the device can be improved.

[0020] 4. For this low on - state voltage high - voltage planar - gate IGBT device, through a variety of innovative structures and flexible parameter - adjustment methods, it has significant advantages in the design of the breakdown voltage, current - density adaptation, on - state voltage, and short - circuit - ability optimization, etc., and can meet the performance requirements in different application scenarios, improving the overall performance and applicability of the device. Description of the Drawings

[0021] Figure 1 is a schematic diagram of the cell structure of a conventional planar - gate IGBT in the prior art;

[0022] Figure 2 is a schematic diagram of the cell structure of a conventional large - cell - size planar - gate IGBT in the prior art;

[0023] Figure 3 is Figure 2 a top - view structure diagram of CT and Gate in a conventional large - cell - size planar - gate IGBT cell shown;

[0024] Figure 4 is a top - view structure diagram of CT and Gate in a large - cell - size planar - gate IGBT cell of the present invention;

[0025] Figure 5 is another top - view structure diagram of CT and Gate in a large - cell - size planar - gate IGBT cell of the present invention. Detailed implementation manners

[0026] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. Specific Embodiment 1:

[0028] As Figures 1-4 shown, in this embodiment, the top view structure diagrams of CT and Gate are square unit cells. Gates are not placed at the four corners of the square unit cell. CTs are located at the four corners of the square unit cell and outside the Gates. Specifically, the Gate is designed as a polygon, with no Gate in the middle, and the area without Gate is also a polygon, and the length of the polygon can be flexibly adjusted according to the design parameter requirements. It should be noted that for the area of the square unit cell without Gate, P-type regions can be formed through P-type implantation. There are D dimensions in the horizontal and vertical directions and D1 dimensions at a 45-degree square for the spacing of the P-type regions. The spacing of the P-type regions can be adjusted in different directions, and the breakdown voltage position can be adjusted by adjusting the D and D1 dimensions, increasing the flexibility of the breakdown voltage design. Among them, the CT is designed as a hole structure, with a smaller CT size, and the formed N+ channel is smaller, which is suitable for low current density design. Compared with the traditional strip unit cell design, the CT area ratio of the square unit cell design decreases, the effective channel density decreases, and the on-state voltage drop increases, but the Gate area ratio can be increased, increasing the large carrier injection effect, thereby reducing the on-state voltage drop. The square unit cell design can adjust the area ratios of CT and Gate to achieve a trade-off optimization between the on-state voltage drop and the short-circuit current.

[0029] It is worth mentioning that a JFET resistance will be introduced between different P regions of the square unit cell. The adjustment of the spacing of the P-type regions can, on the one hand, adjust the magnitude and position of the breakdown voltage, and on the other hand, adjust the JFET resistance at different positions, adjust the circuit path, reduce the JFET resistance, and further reduce the on-state voltage drop. Specific Embodiment 2:

[0031] As Figure 5As shown, in this embodiment, the top-down structural diagrams of CT and Gate are square unit cells. There are no Gates placed at the four corners of the square unit cell, and CTs are located at the four corners of the square unit cell, outside the Gates. Specifically, the Gate is designed as a polygon, with no Gate in the middle, and the area without Gate is also a polygon. The length of the polygon can be flexibly adjusted according to the design parameter requirements. Among them, for the area of the square unit cell without Gate, P-type regions can be formed through P-type implantation. The spacing of the P-type regions has horizontal and vertical D dimensions, as well as a 45-degree square D1 dimension. The spacing of the P-type regions can be adjusted in different directions, and the breakdown voltage position can be adjusted by adjusting the D and D1 dimensions, increasing the flexibility of the breakdown voltage design.

[0032] CT is designed as a circular strip structure and can be composed of multiple circular strip CTs, forming a relatively large N+ channel, which is suitable for high-current density designs.

[0033] It should be noted that compared with the traditional strip unit cell design, the CT area ratio in the square unit cell design decreases, the effective channel density decreases, and the on-state voltage drop increases. However, the Gate area ratio can be increased, enhancing the large carrier injection effect, thereby reducing the on-state voltage drop. The square unit cell design can adjust the area ratios of CT and Gate to achieve a trade-off optimization between the on-state voltage drop and the short-circuit current. The adjustment of the P-type region spacing in the square unit cell can, on the one hand, adjust the magnitude and position of the breakdown voltage, and on the other hand, adjust the JFET resistance at different positions, adjust the circuit path, reduce the JFET resistance, and further reduce the on-state voltage drop.

[0034] In addition, compared with the traditional strip unit cell, the square unit cell design is not only more compact in layout. When arranging traditional strip unit cells, there may be more unused space at the chip edge due to shape limitations, while square unit cells can be arranged more closely together, reducing the blank area on the chip, thereby improving the utilization rate of the chip area. More unit cells can be integrated under the same chip area, enhancing the device integration density and improving the chip area utilization rate.

[0035] It also has the advantage of being convenient for chip layout design. The regular shape of the square unit cell makes it easier to plan and arrange during chip layout design. Chip designers can more intuitively plan the connection relationships between unit cells, reducing the layout complexity and routing difficulty caused by irregular unit cell shapes, and improving the efficiency and accuracy of the in-chip design.

[0036] The working principle of the above embodiment is as follows:

[0037] First, the CTs are located at the four corners of the square unit cell. The structure of its pore type or ring strip determines the size of the conductive channel and the current density. The pore-type CT is suitable for low-current-density designs, forming a relatively small N+ channel; the ring-strip CT is suitable for high-current-density designs, forming a relatively large N+ channel. By adjusting the structure of the CT, the size of the conductive channel can be flexibly controlled to meet different current requirements.

[0038] Next, the Gate is designed as a polygon, and the area without the Gate in the middle is also a polygon. The Gate controls the opening and closing of the conductive channel by applying a voltage, thereby controlling the conduction of the current. In the square unit cell design, increasing the proportion of the Gate area can enhance the large carrier injection effect and reduce the on-state voltage drop.

[0039] Then, in the area of the square unit cell without the Gate, a P-type region is formed by P-type injection. The spacing D in the horizontal and vertical directions and the 45-degree square D1 size of the P-type region can be flexibly adjusted through design parameters.

[0040] The position and magnitude of the breakdown voltage can be achieved by adjusting the spacing of the P-type regions. By adjusting the D and D1 sizes, the breakdown voltage can be flexibly adjusted, increasing the flexibility of the design.

[0041] Finally, a JFET resistor is introduced between different P regions of the square unit cell. The magnitude of the JFET resistor affects the on-state voltage drop. By adjusting the spacing of the P-type regions, the JFET resistors at different positions can be adjusted, thereby adjusting the circuit path and reducing the JFET resistor to further reduce the on-state voltage drop.

[0042] In the square unit cell design, increasing the proportion of the Gate area can enhance the large carrier injection effect. The large carrier injection effect can reduce the on-state voltage drop and improve the on-state performance of the device. By adjusting the area ratios of the CT and the Gate, a trade-off optimization between the on-state voltage drop and the short-circuit current can be achieved. On the premise of ensuring the safety of the device, the on-state voltage drop is reduced as much as possible to improve the efficiency of the device.

[0043] All electrical components mentioned in the text are electrically connected to the main controller and the power supply. The main controller can be a conventional known device such as a computer for control, and the existing publicly disclosed power connection technology will not be elaborated in the text.

[0044] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent in such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

Claims

1. A low on-state voltage high-voltage planar gate IGBT device, characterized in that, It includes a CT and a Gate, and the CT and the Gate form a square unit cell structure; There is no Gate placed at the four corners of the square unit cell, and the CT is located at the four corners of the square unit cell, outside the Gate; The design of the square unit cell can adjust the area ratio of the CT and the Gate, achieving a trade-off optimization between the on-state voltage drop and the short-circuit current.

2. The low on-state voltage high-voltage planar-gate IGBT device according to claim 1, wherein, The Gate is designed as a polygon, with no Gate in the middle, and the area without the Gate is also a polygon, and the side length of the polygon can be flexibly adjusted according to the design parameter requirements.

3. A high-voltage planar-gate IGBT device with low on-state voltage drop according to claim 2, characterized in that, The areas without the Gate in the square unit cell can all form P-type regions. For the spacing of the P-type regions, there are D dimensions in the horizontal and vertical directions, and there is also a D1 dimension in the 45-degree square direction.

4. A low on-state voltage high-voltage planar gate IGBT device according to claim 3, characterized in that, The spacing of the P-type regions can be adjusted in different directions, and the breakdown voltage position can be changed by adjusting the D and D1 dimensions, increasing the flexibility of the breakdown voltage design; The CT can be designed as a hole-type structure. The overall area of the hole-type structure CT is relatively small. An N+ can be formed between the outside of the CT and the middle of the Gate to provide a current path. When the hole-type CT is designed, the N+ channel is relatively small, which is suitable for products with a small current density.

5. A low on-state voltage high-voltage planar gate IGBT device according to claim 4, characterized in that, The CT can be designed as multiple ring-shaped strip structures. When the overall area of the ring-shaped strip structure CT is relatively large, the N+ channel is relatively large, which is suitable for products with a large current density; Compared with the traditional strip unit cell design through the square unit cell design, the area ratio of the CT decreases, the effective channel density decreases, and the on-state voltage drop increases, but the area ratio of the Gate can be increased, increasing the large carrier injection effect, thereby reducing the on-state voltage drop.

6. A low on-state voltage high-voltage planar gate IGBT device according to claim 5, characterized in that, A JFET resistance is introduced between different P regions of the square unit cell. The spacing of the P-type regions can be adjusted. On the one hand, the magnitude and position of the breakdown voltage can be adjusted. On the other hand, the JFET resistance at different positions can be adjusted to adjust the circuit path, reduce the JFET resistance, and further reduce the on-state voltage drop.

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