Silicon controlled rectifier

Abstract

The present disclosure relates to semiconductor structures, and more particularly to device triggered silicon controlled rectifiers (SCRs) and methods of manufacture. The structure includes a first device including a first shallow diffusion region of a first conductivity type within a first well of a second conductivity type and a second shallow diffusion region of the first conductivity type within the first well of the second conductivity type.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly to device-triggered silicon-controlled rectifiers (SCRs) and methods of manufacture. Background Art

[0002] SCRs are used for electrostatic discharge (ESD) protection of integrated circuits (ICs) against sudden currents caused by, for example, contact, electrical short circuit, or dielectric breakdown. Due to the high current handling capacity per unit area of SCRs, ESD devices using SCRs can protect ICs from faults. These devices are most commonly used in high-performance analog and radio frequency (RF) designs of chips with large signal swings, low leakage, and low capacitance. SCRs typically have a high trigger voltage. Summary of the Invention

[0003] In one aspect of the present disclosure, a structure includes: a first device including a first lightly doped diffusion region of a first conductivity type within a first well of a second conductivity type and a second lightly doped diffusion region of the first conductivity type within the first well of the second conductivity type.

[0004] In one aspect of the present disclosure, a structure includes: a first device connected to an anode and a cathode, the first device including: a first lightly doped diffusion region of a first conductivity type within a well of a second conductivity type; and a second lightly doped diffusion region of the first conductivity type within the well of the second conductivity type and spaced apart from the first lightly doped diffusion region; and a second device including: a contact region of a second conductivity type connected to the well of the first conductivity type; the well of the second conductivity type; and the first lightly doped diffusion region of the first conductivity type within the well of the second conductivity type.

[0005] In one aspect of the present disclosure, a method includes: forming a first device including a first lightly doped diffusion region of a first conductivity type within a first well of a second conductivity type; and forming a second device including the first lightly doped diffusion region and a second lightly doped diffusion region of the first conductivity type within the first well of the second conductivity type. Brief Description of the Drawings

[0006] In the following detailed description, reference is made to the numerous drawings referred to, which describe the present disclosure in a non-limiting example of exemplary embodiments of the present disclosure.

[0007] Figure 1A Cross-sectional views of devices and corresponding manufacturing processes according to aspects of the present disclosure are shown.

[0008] Figure 1B Shows Figure 1A a top view of the device along line A-A;

[0009] Figure 2 Shows a device according to another aspect of the present disclosure.

[0010] Figure 3 Shows a device according to yet another aspect of the present disclosure.

[0011] Figure 4 Shows a device according to yet another additional aspect of the present disclosure. Detailed Description

[0012] The present disclosure relates to semiconductor structures, and more particularly to device-triggered silicon-controlled rectifiers (SCRs) and methods of manufacture. More specifically, the SCR includes shallow diffusion regions within wells of opposite conductive types. The trigger device includes a plurality of shallow diffusion regions within wells of opposite conductive types. A first shallow diffusion region among the shallow diffusion regions is coupled to the anode, and a second shallow diffusion region among the shallow diffusion regions is coupled to the cathode. Advantageously, the SCRs described herein exhibit improved trigger current (It2) and adjustable trigger voltage (Vtrigger). Moreover, due to the use of shallow diffusion, the device provides lower capacitance than a standard semiconductor-on-insulator (SOI) SCR. The SCR can also utilize less space on the chip.

[0013] The devices of the present disclosure can be fabricated in a variety of different ways using a variety of different tools. However, generally, methods and tools are used to form structures having micron and nanoscale dimensions. Methods (i.e., techniques) for fabricating the devices of the present disclosure have been adopted in accordance with integrated circuit (IC) technology. For example, these structures are built on a wafer and realized in a material film patterned on top of the wafer by a lithography process. Specifically, the fabrication of the device uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by lithographic imaging; and (iii) selectively etching the film with respect to the mask. In addition, as is known in the art, a pre-clean process can be used to clean any contaminants on the etched surface. In addition, as is known in the art, a rapid thermal annealing process can be used to drive in dopants or material layers when necessary.

[0014] Figure 1A and Figure 1B Shows a device according to an aspect of the present disclosure and a corresponding manufacturing process. More specifically, Figure 1A Shows a cross-sectional view of an SCR (e.g., PNPN) having a trigger device (e.g., NPN); while Figure 1B Shows a top view of the SCR and the trigger device along line A-A.

[0015] More specifically, Figure 1A and Figure 1BThe device 10 shown in

[0016] includes a substrate 12, which may include semiconductor-on-insulator technology. For example, the substrate 12 includes, from bottom to top, a processing substrate 12a, a buried insulator layer 12b, and a top semiconductor layer 12c. The processing substrate 12a provides mechanical support for the buried insulator layer 12b and the top semiconductor layer 12c.

[0017] The processing substrate 12a and the top semiconductor layer 12c may include semiconductor materials such as Si, Ge, SiGe, SiC, SiGeC, III-V compound semiconductors, II-VI compound semiconductors, or any combination thereof. In a preferred embodiment, the top semiconductor layer 12c includes Si having any suitable single crystal orientation (e.g., <100>, <110>, <111>, or <001>). The buried insulator layer 12b may include dielectric materials such as silicon dioxide, silicon nitride, silicon oxynitride, boron nitride, or a combination thereof. In a preferred embodiment, the buried insulator layer 12b is a buried oxide layer (BOX).

[0018] Still referring to Figure 1A and Figure 1B FIGS., the top semiconductor layer 12c includes a plurality of wells and diffusion regions, forming a PNPN device (e.g., an SCR), and the PNPN device can be triggered by an NPN device. The PNPN device (e.g., an SCR) and the NPN device may be lateral devices. For example, the PNPN device includes a P+ contact region 16 located within an N well 18, a P well 20, and a shallow N+ diffusion region 22b located within the P well 20. On the other hand, the NPN device includes shallow N+ diffusion regions 22a, 22b located within the P well 20. In an embodiment, the N+ diffusion regions 22a, 22b may have the same conductivity type and doping concentration. As described in more detail herein, the shallow N+ diffusion region 22a may be connected to the anode 24 and the shallow N+ diffusion region 22b may be connected to the cathode 28.

[0019] In Figure 1A and Figure 1BIn it, the N+ contact region 14 is electrically connected (e.g., adjacent when viewed from a top view) to the N-well 18, and the P+ contact region 26 is electrically connected to the P-well 20. Regarding the latter, for example, the P+ contact region 26 may be within the P-well 20. Both the N+ contact region 14 and the P+ contact region 26 can generate additional well resistances for the corresponding wells 18, 20. In an embodiment, the P+ contact regions 16, 26 and the N+ contact region 14 are heavily doped regions (compared with the N-well 18 and the P-well 20).

[0020] As Figure 1A shown, in an embodiment, the N+ contact region 14, the P+ contact region 16 and the shallow N+ diffusion regions 22a in the P-well 20 can be connected to the anode 24. In addition, the shallow N+ diffusion region 22b and the P+ contact region 26 in the P-well 20 can be electrically connected to the cathode 28.

[0021] The shallow N+ diffusion regions 22a, 22b preferably only partially extend into the P-well 20. For example, the N+ diffusion regions 22a, 22b do not extend to the buried insulator layer 12b and should be isolated from each other through the P-well 20. Moreover, in an embodiment, the N+ diffusion regions 22a, 22b are spaced apart by a distance S1, and the N+ diffusion region 22b is spaced apart from the N-well 18 by a distance S2. In an embodiment, S1 is greater than 0 to ensure that the N+ diffusion regions 22a, 22b are not short-circuited. The distance S2 can also be the minimum critical dimension, as should be understood by those skilled in the art. In an embodiment, the distances S1 and S2 are adjustable to adjust the trigger voltage of the device. For example, a smaller distance S2 results in a lower trigger voltage; while a larger distance S2 results in a higher trigger voltage.

[0022] The wells, diffusion regions and N+ / P+ contact regions can be formed by conventional ion implantation processes. For example, the ion implantation process can introduce concentrations of dopants of different (e.g., opposite) conductive types in the top semiconductor layer 12c. In an embodiment, as is known in the art, corresponding patterned implantation masks can be used to define the selected regions exposed for implantation. The implantation mask can include a photosensitive material layer such as an organic photoresist, which is applied by a spin coating process, pre-baked, exposed to light projected through a photomask, post-exposure baked, and developed with a chemical developer. Each implantation mask has a thickness and stopping power sufficient to block the mask region from receiving a certain dose of implanted ions. The P-well 20 and the P+ contact regions 16, 26 are doped with a p-type dopant, such as boron (B), and the N-well 18, the N+ diffusion regions 22a, 22b and the N+ contact region 14 are doped with an n-type dopant, such as arsenic (As), phosphorus (P) and antimony (Sb), and other suitable examples.

[0023] Still referring to Figure 1A and Figure 1B, a shallow trench isolation structure 30 is formed in the top semiconductor layer 12c. The shallow trench isolation structure 30 can isolate the N+ contact region 14 from the P+ contact region 16 in addition to being adjacent to the N+ contact region 14 and the P+ contact region 16 on either side. In this way, the shallow trench isolation structure 30 isolates the N+ contact region 14 and the P+ contact regions 16, 26.

[0024] The shallow trench isolation structure 30 can be formed by conventional lithography, etching, and deposition methods known to those skilled in the art. For example, the resist formed on the top of the top semiconductor layer 12c is exposed to energy (light) and developed using a conventional resist developer to form a pattern (opening). Using an etching process with selective chemical action, such as reactive ion etching (RIE), the pattern is transferred from the patterned photoresist layer to the top semiconductor layer 12c (extending to the buried insulator layer 12b) to form one or more trenches in the top semiconductor layer 12c. After removing the resist by a conventional oxygen ashing process or other known strippers, an insulator material (e.g., SiO2) can be deposited in the trenches by any conventional deposition process, such as chemical vapor deposition (CVD) process. Any residual material on the surface of the top semiconductor layer 12c can be removed by a conventional chemical mechanical polishing (CMP) process.

[0025] Figure 1A Silicide contacts 32 are also shown on the N+ contact region 14, P+ contact regions 16, 26, and the shallow N+ diffusion regions 22a, 22b. Those skilled in the art should understand that the silicide process begins with depositing a thin transition metal layer, such as nickel, cobalt, or titanium, over a fully formed and patterned semiconductor device (e.g., N+ contact region 14, P+ contact regions 16, 26, and shallow N+ diffusion regions 22a, 22b). After the material is deposited, the structure is heated, allowing the transition metal to react with the exposed silicon (or other semiconductor materials as described herein) in the active regions of the semiconductor device (e.g., source, drain, gate contact regions) to form a low-resistance transition metal silicide. After the reaction, any remaining transition metal is removed by chemical etching, leaving the silicide contacts 32 on the N+ contact region 14, P+ contact regions 16, 26, and shallow N+ diffusion regions 22a, 22b. Those skilled in the art should understand that the N+ diffusion regions 22a, 22b are spaced apart by a distance S2 such that the silicide contacts 32 will not contact each other.

[0026] Figure 1A A wiring structure 34 for connecting between the N+ contact region 14, P+ contact regions 16, 26, shallow N+ diffusion regions 22A, 22b, and the corresponding anodes 24 and cathodes 28 is also shown. The wiring structure 34 can be formed in the interlayer dielectric material using conventional lithography, etching, and deposition methods known in the art, and thus does not require further explanation to fully understand the present disclosure.

[0027] Figure 2 illustrates a device according to another aspect of the present disclosure. In Figure 2 device 10a, a gate structure 36 may be disposed above the P-well 20 and between the shallow N+ diffusion regions 22a, 22b. In an embodiment, the gate structure 36 may be a polysilicon gate structure that is floating or electrically connected to the cathode 28, as shown by the dashed line (e.g., wiring structure) 38. In an embodiment, the gate structure 36 may be used as a silicide block to prevent the silicide contact 32 from being formed on the top semiconductor layer 12c, extending between and contacting the shallow N+ diffusion regions 22a, 22b.

[0028] Figure 3 illustrates a device and a corresponding manufacturing process according to an aspect of the present disclosure. More specifically, device 10c includes a plurality of wells and diffusion regions in the top semiconductor layer 12c, forming an NPNP device (e.g., SCR) that can be triggered by a PNP device. The NPNP device (e.g., SCR) and the PNP device may be lateral devices.

[0029] As Figure 3 shown, the NPNP device and the PNP device are disposed in the top semiconductor layer 12c, on the buried insulator layer 12b, and the buried insulator layer 12b is disposed on the processing substrate 12a. In an embodiment, the NPNP device includes an N+ contact region 116, an N-well 120, and a shallow P+ diffusion region 122b in the P-well 118. On the other hand, the PNP device includes shallow P+ diffusion regions 122a, 122b in the N-well 120. The shallow P+ diffusion region 122b may be connected to the anode 24, and the shallow P+ diffusion region 122a may be connected to the cathode 28.

[0030] In an embodiment, the N+ contact region 116 is located in the P-well 118, and the P+ contact region 114 is electrically connected (e.g., from a top view similar to that shown in Figure 1B to adjacent the P+ contact 16 to the P-well 18) to the P-well 118. The P-well 118 also abuts the N-well 120. The P+ contact region 114, the N+ contact region 116, and the shallow P+ diffusion region 122a in the N-well 120 may be connected to the cathode 28; while the shallow P+ diffusion region 122b in the N-well 120 and the N+ contact region 126 in the N-well 120 may be electrically connected to the anode 24. As in the previous embodiments, the shallow P+ diffusion regions 122a, 122b should preferably not extend into the buried insulator layer 12b and should preferably be isolated from each other by the N-well 120. In addition, in an embodiment, the N+ contact regions 116, 126 and the P+ contact region 114 are heavily doped regions (compared to the P-well 118 and the N-well 120). In addition, in an embodiment, the P+ diffusion regions 122a, 122b may have the same conduction type and doping concentration.

[0031] In another embodiment, the P+ diffusion regions 122a, 122b are spaced apart by a distance S1, and the P+ diffusion region 122b is spaced apart from the P-well 118 by a distance S2. In an embodiment, S1 is greater than 0 to ensure that the P+ diffusion regions 122a, 122b are not short-circuited. The distance S2 can be a minimum critical dimension, as would be understood by those skilled in the art. As in the foregoing structures 10, 10a, the distances S1 and S2 are adjustable to adjust the trigger voltage of the device. For example, a smaller distance S2 results in a lower trigger voltage; while a larger distance S2 results in a higher trigger voltage. Additionally, the well, diffusion regions, and N+ / P+ contact regions can be formed by conventional ion implantation processes.

[0032] Still referring to Figure 3 , a shallow trench isolation structure 30 is formed in the top semiconductor layer 12c. The shallow trench isolation structure 30 can be disposed between and isolate the P+ contact region 114 and the N+ contact region 116, in addition to being adjacent to the P+ contact region 114 and the N+ contact region 116 on either side. In this way, the shallow trench isolation structure 30 isolates the P+ contact region 14 and the N+ contact regions 116, 126.

[0033] Figure 3 Silicide contacts 32 are also shown over the P+ contact region 114, the N+ contact regions 116, 126, and the shallow P+ diffusion regions 122a, 122b. A wiring structure 34 makes connections between the P+ contact region 114, the N+ contact regions 116, 126, and the shallow P+ diffusion regions 122a, 122b and the respective anodes 24 and cathodes 28.

[0034] Figure 4 A device 10c similar to Figure 3 device 10b is shown. In device 10c, a gate structure 36 can be disposed over the N-well 120 and between the shallow P+ diffusion regions 122a, 122b. In an embodiment, the gate structure 36 can be a polysilicon gate structure, which is floating or connected to the anode 24, as shown by the dashed line (e.g., wiring structure) 38. In an embodiment, the gate structure 36 can act as a silicide blocker to prevent the silicide contacts 32 from extending between and contacting both of the shallow P+ diffusion regions 122a, 122b.

[0035] These devices can be used in system-on-chip (SOC) technology. An SoC is an integrated circuit (also known as a "chip") that integrates all components of an electronic system on a single chip or substrate. Since the components are integrated on a single substrate, an SoC consumes much less power and occupies much less area compared to a multi-chip design with equivalent functionality. Therefore, SoCs are becoming a dominant force in mobile computing (e.g., in smartphones) and the edge computing market. SoCs are also used in embedded systems and the Internet of Things.

[0036] The above methods are used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the chips are mounted in the form of single-chip packages (e.g., plastic carriers whose leads are fixed to a motherboard or other higher-level carrier) or multi-chip packages (e.g., ceramic carriers that have one or both of surface interconnects or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with a display, keyboard, or other input device and a central processor.

[0037] The description of various embodiments of the present disclosure has been given for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to a person of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, the practical application, or the technical improvement of technologies found in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure, comprising: A first device, which includes a first lightly doped diffusion region of a first conductivity type within a first well of a second conductivity type and a second lightly doped diffusion region of the first conductivity type within the first well of the second conductivity type.

2. The structure according to claim 1, further comprising a second device, the second device including the first lightly doped diffusion region within the first well.

3. The structure according to claim 2, wherein, The first device includes NPN, and the second device includes PNPN.

4. The structure according to claim 1, wherein, The first lightly doped diffusion region and the second lightly doped diffusion region include N-type dopants, and the first well includes P-type dopants.

5. The structure according to claim 4, wherein, The first lightly doped diffusion region is connected to the cathode, and the second lightly doped diffusion region is connected to the anode.

6. The structure according to claim 2, wherein, The second device includes a P+ contact region electrically connected to an N well and the first lightly doped diffusion region within the first well.

7. The structure according to claim 6, wherein, The first lightly doped diffusion region includes n-type dopants and the first well includes a P well.

8. The structure according to claim 7, wherein, The first lightly doped diffusion region is connected to the cathode.

9. The structure according to claim 1, wherein, The first lightly doped diffusion region and the second lightly doped diffusion region are spaced apart from each other within the first well, are positioned away from and above the underlying buried insulator layer.

10. The structure according to claim 1 further comprises: A gate structure, which is located above the first well and between the first lightly doped diffusion region and the second lightly doped diffusion region.

11. The structure according to claim 10, wherein, The gate structure is floating or connected to the cathode.

12. The structure according to claim 2, wherein, The first device includes PNP and the second device includes NPNP, and wherein the first lightly doped diffusion region and the second lightly doped diffusion region of the first device include P-type dopants, and the first well includes N-type dopants.

13. The structure according to claim 12, wherein, The first lightly doped diffusion region is electrically connected to the anode, and the second lightly doped diffusion region is electrically connected to the cathode.

14. The structure according to claim 12, wherein, The second device includes the first lightly doped diffusion region and an N+ contact region electrically connected to a P well, the first lightly doped diffusion region includes P-type dopants within the first well, and the first well includes an N well.

15. The structure according to claim 1, further comprising a contact region electrically connected to the first well and a second well of the first conductivity type.

16. A structure, comprising: A first device, which is connected to an anode and a cathode, the first device including: A first lightly doped diffusion region of a first conductivity type, which is within a well of a second conductivity type; and The second lightly doped diffusion region of the first conductivity type, which is within the well of the second conductivity type and is spaced apart from the first lightly doped diffusion region; and A second device, which includes: A contact region of a second conductivity type, which is connected to the well of the first conductivity type; The well of the second conductivity type; and The first lightly doped diffusion region of the first conductivity type, which is within the well of the second conductivity type.

17. The structure according to claim 16, further comprising a gate structure located between the first lightly doped diffusion region and the second lightly doped diffusion region.

18. The structure according to claim 16, wherein, The first device includes NPN, and the second device includes PNPN.

19. The structure according to claim 16, wherein, The first device includes PNP, and the second device includes NPNP.

20. A method, comprising: Forming a first device, the first device including a first lightly doped diffusion region of a first conductivity type within a first well of a second conductivity type; And A second device is formed, the second device including the first lightly doped region and a second lightly doped region of the first conductivity type located within the first well of the second conductivity type.

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