Manufacturing method of semiconductor device structure

Abstract

A method of fabricating a semiconductor device structure includes forming a sacrificial gate structure on a portion of a fin structure, the fin structure including first and second semiconductor layers stacked in a staggered manner. The method also includes removing a portion of the fin structure that is not covered by the sacrificial gate structure, exposing exposed surfaces of the first and second semiconductor layers to free radical species, removing edge portions of the second semiconductor layers to form voids between adjacent first semiconductor layers, and forming dielectric spacers between the voids.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to semiconductor devices having nanosheet transistors and methods of manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in the materials and design of integrated circuits have resulted in multiple generations of integrated circuits, each of which has smaller and more complex circuits than the previous generation. During the development of integrated circuits, the functional density (i.e., the number of interconnected devices per wafer area) has generally increased, while the geometric size (i.e., the smallest component (or line width) that can be produced using the process) has decreased. This scaling process generally provides benefits by increasing production efficiency and reducing associated costs. However, this scaling process faces new challenges. For example, transistors using nanostructured channels are used to improve the carrier mobility and drive current in the device. Inner spacers are typically disposed between the metal gate and the source / drain (S / D) structure to protect the source / drain structure from damage by subsequent gate replacement processes. Although the formation of the inner spacer generally serves its intended purpose, it has not been entirely satisfactory in all aspects. Summary of the Invention

[0003] One embodiment of the present disclosure is a method of manufacturing a semiconductor device structure. The method includes forming a sacrificial gate structure on a portion of a fin structure, the fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately. The method also includes removing a portion of the fin structure that is not covered by the sacrificial gate structure, exposing a plurality of exposed surfaces of each of the first semiconductor layer and the second semiconductor layer to an environment of at least one radical species, removing an edge portion of the second semiconductor layer to form a void between two adjacent first semiconductor layers, and forming a dielectric spacer between the voids.

[0004] One embodiment of the present disclosure is a method of manufacturing a semiconductor device structure. The method includes removing a portion of a plurality of first semiconductor layers and a plurality of second semiconductor layers that are stacked alternately, wherein at least two surfaces of each of the second semiconductor layers are respectively disposed between a gate spacer and a sacrificial gate electrode layer, treating exposed surfaces of each of the first semiconductor layers and the second semiconductor layers with a plurality of first radical species and a plurality of second radical species, selectively removing edge portions of each of the second semiconductor layers such that each of the second semiconductor layers has a substantially flat surface along a longitudinal direction of each of the second semiconductor layers, depositing a dielectric spacer between two adjacent first semiconductor layers, wherein the dielectric spacer contacts one of the second semiconductor layers, and forming a plurality of epitaxial source / drain features such that a portion of the epitaxial source / drain features contacts the first semiconductor layer and the dielectric spacer.

[0005] One embodiment of the present disclosure is a method of manufacturing a semiconductor device structure. The method includes providing a fin structure that includes a plurality of first semiconductor layers and a plurality of second semiconductor layers that are stacked alternately, forming a sacrificial gate structure and a gate spacer on a portion of the fin structure, removing, by an etching process, a portion of the fin structure that is not covered by the sacrificial gate structure, wherein a plurality of exposed surfaces of each of the first semiconductor layers and the second semiconductor layers are covered by a plurality of etching residues that are at least from the gate spacer, removing the etching residues by reacting a plurality of first radical species and a plurality of second radical species with the etching residues, and selectively removing a portion of the second semiconductor layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood when the following detailed description is read with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0007] According to some embodiments, Figures 1 to 6 are perspective views of various stages of manufacturing a semiconductor device structure;

[0008] According to some embodiments, Figure 7A is a cross-sectional view taken along cross-section A-A in various stages of manufacturing a semiconductor device structure; Figure 6

[0009] According to some embodiments, Figure 7B is a cross-sectional view taken along cross-section B-B in various stages of manufacturing a semiconductor device structure; Figure 6

[0010] According to some embodiments, Figure 7C is a cross-sectional view taken alongFigure 6 Cross-sectional view taken along cross-section C-C;

[0011] According to some embodiments, Figure 7D In each stage of manufacturing a semiconductor device structure, along Figure 6 Top view taken along cross-section D-D;

[0012] According to some embodiments, Figure 7E Top view showing a semiconductor device structure along Figure 6 Cross-section E-E;

[0013] According to some embodiments, Figure 8A In each stage of manufacturing a semiconductor device structure, along Figure 6 Cross-sectional view taken along cross-section A-A;

[0014] According to some embodiments, Figure 8B In each stage of manufacturing a semiconductor device structure, along Figure 6 Cross-sectional view taken along cross-section B-B;

[0015] According to some embodiments, Figure 8C In each stage of manufacturing a semiconductor device structure, along Figure 6 Cross-sectional view taken along cross-section C-C;

[0016] According to some embodiments, Figure 8D In each stage of manufacturing a semiconductor device structure, along Figure 6 Top view taken along cross-section D-D;

[0017] According to some embodiments, Figure 8E Top view showing a semiconductor device structure along Figure 6 Cross-section E-E;

[0018] According to some embodiments, Figure 9 Showing Figure 8A A portion of the semiconductor device structure in;

[0019] According to some embodiments, Figure 10 Showing after removing the edge portions of each second semiconductor of the semiconductor layer stack Figure 8D A portion of the semiconductor device structure in;

[0020] According to some embodiments, Figure 11A Figures 11A to 18A In each stage of manufacturing a semiconductor device structure, along Figure 6 Cross-sectional view taken along cross-section A-A;

[0021] According to some embodiments, Figures 11B to 18BCross-sectional views taken along cross-section B-B of various stages of fabricating a semiconductor device structure; Figure 6 ;

[0022] According to some embodiments, Figures 11C to 18C Cross-sectional views taken along cross-section C-C of various stages of fabricating a semiconductor device structure; Figure 6 ;

[0023] According to some embodiments, Figures 11D to 18D Upper views taken along cross-section D-D of various stages of fabricating a semiconductor device structure. Figure 6 ;

[0024]

Reference Signs

[0025] 100: Semiconductor device structure

[0026] 101: Substrate

[0027] 104: Semiconductor layer stack

[0028] 106, 106a, 106b, 106c: First semiconductor layer

[0029] 108, 108a, 108b, 108c: Second semiconductor layer

[0030] 108a1, 108b1, 108c1: Upper portion

[0031] 108a2, 108b2, 108c2: Middle portion

[0032] 108a3, 108b3, 108c3: Lower portion

[0033] 108S: Sidewall

[0034] 108-1: First sidewall

[0035] 108-2: Second sidewall

[0036] 108-3: Third sidewall

[0037] 108-4: Fourth sidewall

[0038] 112: Fin structure

[0039] 114, 119: Trenches

[0040] 116: Well portion

[0041] 118: Insulating material

[0042] 120: Isolation region

[0043] 130: Sacrificial gate structure

[0044] 131: Gap

[0045] 132: Sacrificial gate dielectric layer

[0046] 134: Sacrificial gate electrode layer

[0047] 136: Mask layer

[0048] 138: Gate spacer

[0049] 138a: First dielectric layer

[0050] 138b: Second dielectric layer

[0051] 144: Dielectric spacer

[0052] 144a: Dielectric layer

[0053] 146: Epitaxial source / drain (S / D) feature

[0054] 162: Contact etch stop layer (CESL)

[0055] 164: First interlayer dielectric (ILD) layer

[0056] 165: Radical species

[0057] 166: Opening

[0058] 168: Residue

[0059] 175-1: Pretreatment process

[0060] 180: Gate dielectric layer

[0061] 182: Gate electrode layer

[0062] 184: Silicide layer

[0063] 186: Source / drain (S / D) contact

[0064] 190: Replacement gate structure

[0065] A, B, C, D: Bottom feet

[0066] A-A, B-B, C-C, D-D, E-E: Cross-section

[0067] T1: Thickness

[0068] θ1, θ2, θ3, θ4: Angle Detailed implementation

[0069] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first feature is formed in direct contact with the second feature, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0070] In addition, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", and the like may be used herein to describe the relationship of one element or feature illustrated in the figures to another (or other) element or feature. In addition to the orientation depicted in the figures, the spatially relative terms may encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be correspondingly interpreted.

[0071] When embodiments of the present disclosure discuss a nanoscale channel device transistor, embodiments of some aspects of the present disclosure may also be used in other processes and / or other devices, such as planar field-effect transistors (planar FETs), fin field-effect transistors (Fin-FETs), horizontal gate-all-around (HGAA) field-effect transistors, vertical gate-all-around (VGAA) field-effect transistors, and other suitable devices. Those of ordinary skill in the art will readily understand other modifications that can be made within the scope of the present disclosure. In the case of employing a gate-all-around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, one or more photolithography processes, including double patterning or multiple patterning processes, can be used to pattern the structure. Generally speaking, double patterning or multiple patterning processes combine photolithography with self-alignment processes, thereby allowing the generation of patterns having, for example, pitches smaller than those that could be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and the sacrificial layer is patterned using a photolithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0072] Figures 1 to 18D Illustrated is a non-limiting process for manufacturing a semiconductor device structure 100 in accordance with some embodiments of the present disclosure. It should be understood that Figures 1 to 18DOther operations are provided before, during, and after the provided processes, and in other embodiments, some of the operations mentioned below may be replaced or deleted. The order of operations / processes is not restrictive and may be exchanged.

[0073] According to some embodiments, Figures 1 to 6 is a perspective view of each stage for manufacturing the semiconductor device structure 100. As Figure 1 shown, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed on the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include a crystalline semiconductor material such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimonide phosphide (GaSbP), gallium arsenide antimonide (GaAsSb), indium phosphide (InP), or a combination thereof. In one embodiment, the substrate 101 is made of silicon. The substrate 101 may be doped or undoped. The substrate 101 may be a bulk semiconductor substrate, such as a bulk silicon substrate like a wafer, a semiconductor-on-insulator (SOI) substrate, a multi-layered semiconductor substrate, or a graded substrate.

[0074] The substrate 101 may include a plurality of regions doped with dopants (such as dopants having P-type or N-type). Depending on the circuit design, the dopant may be, for example, phosphorus for an N-type field effect transistor (NFET), or boron for a P-type field effect transistor (PFET).

[0075] The semiconductor layer stack 104 includes interleaved semiconductor layers made of different materials to form a nanosheet channel in a multi-gate device (e.g., a nanosheet field-effect transistor). In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108 vertically stacked on a substrate 101. In some embodiments, the semiconductor layer stack 104 includes interleaved first semiconductor layer 106 and second semiconductor layer 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etch selectivities and / or oxidation rates. For example, the first semiconductor layer 106 may be made of silicon, and the second semiconductor layer 108 may be made of silicon germanium. In some instances, the first semiconductor layer 106 may be made of silicon germanium, and the second semiconductor layer 108 may be made of silicon. Alternatively, in some embodiments, either the first semiconductor layer 106 or the second semiconductor layer 108 may be or may include other materials, such as germanium, silicon carbide, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0076] The first semiconductor layer 106 and the second semiconductor layer 108 may be formed by any suitable deposition process, such as an epitaxial process. For example, epitaxial growth of the layers of the semiconductor layer stack 104 may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0077] The first semiconductor layer 106 or a portion thereof may form the nanosheet channel of the semiconductor device structure 100 in a subsequent process stage. As used herein, the term nanosheet is used to denote any material portion having nanoscale or even micron-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of this portion. Thus, this term denotes an elongated material portion having a circular and substantially circular cross-section, as well as a beam or bar-shaped material portion including, for example, a cylindrical or substantially rectangular cross-section. The nanosheet channel of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include a nanosheet transistor. A nanosheet transistor may refer to a nanowire transistor, a gate-all-around (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode surrounding the channel. Details regarding the use of the first semiconductor layer 106 to define the channel of the semiconductor device structure 100 will be further discussed hereinafter.

[0078] Each of the first semiconductor layers 106 may have a width between approximately 5 nanometers and approximately 30 nanometers. Each of the second semiconductor layers 108 may have a width less than, equal to, or greater than the width of the first semiconductor layer 106. In some embodiments, any one of the second semiconductor layers 108 has a width between approximately 2 nanometers and approximately 50 nanometers. Figure 1 Illustrated are three first semiconductor layers 106 and three second semiconductor layers 108 in a stacked arrangement, which is for illustrative purposes and not for limiting beyond what is recited in the claims. It should be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the semiconductor layer stack 104, and the number of layers depends on the number of channels predetermined in the semiconductor device structure 100.

[0079] In Figure 2 , fin structures 112 are formed from the semiconductor layer stack 104. Each of the fin structures 112 has an upper portion and a well portion 116, where the upper portion includes the first semiconductor layer 106 and the second semiconductor layer 108, and the well portion 116 is formed from the substrate 101. A hard mask layer (not shown) formed on the semiconductor layer stack 104 may be patterned using multiple patterning operations, which may include photolithography processes and etching processes. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process may include forming a photoresist layer (not shown) on the hard mask layer, exposing the photoresist layer under a pattern, performing a post-exposure bake, and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, an electron beam (e-beam) lithography process may be performed to pattern the photoresist layer to form the mask element. The etching process forms trenches 114 in unprotected regions of the substrate 101 through the hard mask layer and the semiconductor layer stack 104, leaving a plurality of extended fin structures 112. The trenches 114 extend along the X direction. The trenches 114 may be etched by dry etching (such as RIE), wet etching, and / or a combination thereof.

[0080] In Figure 3In [description], after forming the fin structure 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structures 112 are buried in the insulating material 118. Then, a planarization process is performed to expose the tops of the fin structures 112. The planarization process can be a chemical mechanical polishing (CMP) process and / or an etch-back process. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-k material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), or flowable CVD (FCVD).

[0081] In Figure 4 In [description], the insulating material 118 is recessed to form isolation regions 120. The recessing process of the insulating material 118 exposes a portion of the fin structures 112, such as the semiconductor layer stack 104. The recessing process of the insulating material 118 also exposes the trenches 114 between adjacent fin structures 112. Suitable processes can be used to form the isolation regions 120, such as a dry etching process, a wet etching process, or a combination thereof. The top surface of the insulating material 118 can be flush with or lower than the surface of the second semiconductor layer 108, and the surface of this second semiconductor layer 108 contacts the well portion 116 formed from the substrate 101.

[0082] In Figure 5In [the structure], one or more sacrificial gate structures 130 (only one is illustrated here) are formed on the semiconductor device structure 100. The sacrificial gate structure 130 is formed on a part of the fin structure 112. Each of the sacrificial gate structures 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate structure 130 can be formed by sequentially forming blanket layers of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 and then patterning these layers to form the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136. Then, gate spacers 138 are formed on the sidewalls of the sacrificial gate structure 130. For example, the gate spacers 138 can be formed by conformally depositing one or more layers for forming the gate spacers 138 and then anisotropically etching the one or more layers. Although only one sacrificial gate structure 130 is illustrated here, in some embodiments, two or more sacrificial gate structures 130 can be arranged along the X direction.

[0083] The sacrificial gate dielectric layer 132 may include one or more layers of dielectric material, such as silicon oxide (SiO x ) or silicon-oxide-based materials. The sacrificial gate electrode layer 134 may include silicon, such as polysilicon or amorphous silicon. The mask layer 136 may include more than 1 layer, such as an oxide layer and a nitride layer. The gate spacers 138 can be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon carbon oxide, SiOCN, and / or combinations thereof. In some embodiments, the gate spacers 138 can be a bilayer, which includes a first dielectric layer 138a (such as SiO2) and a second dielectric layer 138b (such as SiN).

[0084] The part of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 can serve as the channel region of the semiconductor device structure 100. The fin structure 112 partially exposed on the opposite side of the sacrificial gate structure 130 defines the source / drain (S / D) regions of the semiconductor device structure 100. In some cases, different transistors can share the S / D regions. For example, different S / D regions can be interconnected and used as multifunctional transistors. It should be understood that the source region and the drain region can be used interchangeably because the epitaxial features formed in these regions are substantially the same. The source / drain regions can represent the source or the drain respectively depending on the context, or collectively represent the source and the drain.

[0085] In Figure 6In [the figure], a portion of the fin structure 112 that is not covered by the sacrificial gate structure 130 is removed to recess a portion of the fin structure 112 in the S / D region (e.g., the region on the opposite side of the sacrificial gate structure 130), such that the portion of the fin structure 112 in the S / D region is below the top surface of the isolation region 120 (or the insulating material 118). A portion of the fin structure 112 can be recessed by an etching process (whether an isotropic or anisotropic etching process) or a further etching process that is selective to one or more crystal planes of the substrate 101. The etching process can be a dry etch (e.g., RIE, NBE, or the like) or a wet etch (e.g., using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant). Recessing a portion of the fin structure 112 causes a trench 119 to form in the S / D region.

[0086] According to some embodiments, Figures 7A to 8A and Figure 11A Figures 11A to 18A are cross-sectional views taken along cross-section A-A Figure 6 during various stages of manufacturing the semiconductor device structure 100. Figures 7B to 8B and Figures 11B to 18B are cross-sectional views taken along cross-section B-B Figure 6 during various stages of manufacturing the semiconductor device structure 100. Figures 7C to 8C and Figures 11C to 18C are cross-sectional views taken along cross-section C-C Figure 6 during various stages of manufacturing the semiconductor device structure 100. Figures 7D to 8D and Figures 11D to 18D are top views taken along cross-section D-D Figure 6 during various stages of manufacturing the semiconductor device structure 100. Cross-section A-A is in a plane along the X direction in the fin structure 112 ( Figure 4 ). Cross-section B-B is in a plane perpendicular to cross-section A-A and along the Y direction in the sacrificial gate structure 130. Cross-section C-C is in a plane perpendicular to cross-section A-A and along the Y direction in the source / drain (S / D) feature 146 ( Figure 13A ). Cross-section D-D is in a plane along the X direction in the second semiconductor layer 108.

[0087] In Figures 7A to 7D , a pre-treatment process 175-1 is performed on the semiconductor device structure 100. According to some embodiments, Figure 7E shows a top view of the semiconductor device structure 100 along cross-section E-E Figure 6 . The purpose of performing the pre-treatment process 175-1 is to remove during the etching process of a portion of the fin structure 112 ( Figure 6)The resulting residue 168. The residue 168 may be deposited on the exposed surfaces of the gate spacer 138 and / or the semiconductor layer stack 104. The residue 168 may include post-etch residues, which may be by-products of the chemical reaction between the etchant and the exposed surfaces of the gate spacer 138 (such as silicon oxycarbide (SiOC)), the semiconductor layer stack 104 (such as silicon oxide (SiO x , x = 1 to 3)), germanium oxide (GeO x , x = 1 to 3), and / or the native oxide layer formed on the exposed surface of the semiconductor layer stack 104 due to exposure to air after the etching process. If the pretreatment process is not performed, the exposed surface of the second semiconductor layer 108 may have significant critical dimension (CD) variations and irregular surface roughness after selective etching. The larger CD variations and poorer roughness of the second semiconductor layer 108 will affect the thickness of the subsequent formed inner spacer, which may cause unexpected damage to the epitaxial S / D feature 146 due to the damaged inner spacer. The degree of uniformity of the surface roughness will be one of the key factors affecting the device performance. The pretreatment process 175-1 removes surface impurities (such as O / C / N signals) to control the CD variations and surface roughness of the second semiconductor layer 108 and improve the EPI damage window. In this way, the electrical performance of the device can be improved.

[0088] The pre-treatment process 175-1 may include a surface treatment process and a surface cleaning process. The surface treatment process may be a process using a reactive etching substance, which may be generated in-situ in the reaction chamber where the semiconductor device structure 100 is placed, or may be generated upstream of the reaction chamber (such as a remote plasma generator). Then, the reactive substance is filtered so that only radical substances can be used to treat the exposed surface of the semiconductor layer stack 104. The reaction chamber may be a plasma-based process chamber, such as a decoupled plasma process chamber, a remote plasma process chamber, or a combination thereof. The plasma may be generated by driving a capacitively coupled plasma source (CCP) or an inductively coupled plasma source (ICP) with a radio frequency power generator. In some embodiments, the pre-treatment process 175-1 is a radical surface treatment (RST) using neutral radical substances (i.e., a plasma-free process). In some embodiments, the pre-treatment process 175-1 is a plasma surface treatment using plasma substances. Exemplary reactive substances may include a hydrogen plasma or a neutral radical substance of hydrogen, such as a hydrogen radical (or a hydrogen atom radical); a nitrogen plasma or a neutral radical substance of nitrogen, such as a nitrogen radical (or a nitrogen atom radical), or a combination thereof. The hydrogen plasma or the neutral radical substance of hydrogen may be generated from any suitable hydrogen-containing gas, such as hydrogen gas (H2). The nitrogen plasma or the neutral radical substance of nitrogen is generated from any suitable nitrogen-containing gas, such as nitrogen gas (N2), ammonia gas (NH3), nitrous oxide (N2O), or the like.

[0089] In some embodiments, the pre-treatment process 175-1 uses neutral radical species generated from a remote plasma generator, and the neutral radical species (e.g., hydrogen radicals (H*) and nitrogen radicals (N*)) are introduced into the downstream of the reaction chamber at a ratio of about 6:1 to about 25:1 (N*:H*). For example, the ratio (N*:H*) can be about 16:1. In the case where the by-product contains carbon (e.g., SiOC generated from the gate spacer 138), the hydrogen radicals and nitrogen radicals of the pre-treatment process 175-1 can react with SiOC to form silicon oxynitride (SiON), silicon hydroxide (SiOH), methane (CH4), and hydrogen cyanide (HCN), where CH4 and HCN can be simply removed from the reaction chamber. In some embodiments, the carbon content of the exposed surface of the semiconductor layer stack 104 is reduced after the surface treatment process. Thereafter, a surface cleaning process using hydrofluoric acid (HF) and / or diluted hydrofluoric acid is performed to convert SiON and SiOH into silicon tetrafluoride (SiF4), water (H2O), and ammonia (NH3), which can be simply removed from the reaction chamber. In this way, the residues generated during the etching process of a part of the fin structure 112 can be removed.

[0090] Although hydrofluoric acid is discussed above, the surface cleaning process can be any suitable wet cleaning process. For example, the surface cleaning process can use NH4OH, hydrofluoric acid or diluted hydrofluoric acid, deionized water, TMAH, other suitable solutions, or a combination thereof. In some embodiments, the surface cleaning process includes using standard cleaning solution-2 (SC2) and then using standard cleaning solution-1 (SC1), where SC2 is a mixture of deionized water, hydrochloric acid (HCl), and hydrogen peroxide (H2O2), and SC1 is a mixture of deionized water, NH4OH, and H2O2. In some embodiments, isopropyl alcohol (IPA) can be used after SC1. Other suitable wet cleaning processes can be used, such as the APM process (including at least water (H2O), ammonium hydroxide (NH4OH), and hydrogen peroxide (H2O2)), the HPM process (including at least water, H2O2, and hydrochloric acid), the SPM process (also known as piranha cleaning, including at least water, H2O2, and sulfuric acid), or a combination thereof.

[0091] In the case of using an ICP source, the pre-treatment process 175-1 can be performed in a remote plasma generator. In such a situation, the plasma source power can be generated using a continuous wave radio frequency power generator or a pulsed radio frequency power generator operating at a predetermined duty cycle. The source power ionizes the nitrogen-containing gas supplied to the remote plasma generator. Before supplying the generated nitrogen ions to the reaction chamber where the semiconductor device structure 100 is placed, the generated nitrogen ions can be filtered to produce neutral radical species (such as hydrogen and nitrogen radicals). In an exemplary embodiment, the decoupled plasma process can be operated by driving the ICP source with a radio frequency power generator, which can use an adjustable frequency from about 2 MHz to about 13.56 MHz, and the chamber is operated at a pressure of about 0.5 Torr to about 8 Torr, a temperature of about 300 degrees Celsius to about 600 degrees Celsius, and a process time of about 3 seconds to about 50 seconds. The flow rates of the process gases (such as hydrogen-containing gas and nitrogen-containing gas) can be provided at about 200 sccm to 5000 sccm respectively. The radio frequency power generator can be operated to provide a power between about 50 watts and about 1000, and the output of the radio frequency power generator can be controlled by a pulsed signal having a duty cycle of about 20% to about 80%.

[0092] In Figures 8A to 8D it, the edge portion of the second semiconductor layer 108 of the semiconductor layer stack 104 is horizontally removed along the X direction. Removing the edge portion of the second semiconductor layer 108 forms a void 131. In some embodiments, a portion of the second semiconductor layer 108 is removed by a selective etching process, such as isotropic dry etching. Since the pre-treatment process 175-1 removes residues and / or by-products from the exposed surface of the semiconductor layer stack 104, the etching rate load of the second semiconductor layer 108 from top to bottom is substantially the same, resulting in a uniform critical dimension (CD) of the second semiconductor layer 108 at different heights. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, a fluorine-containing etchant, such as fluorine gas (F2), nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), difluoromethane (CH2F2), trifluoromethane (CHF3), and / or hexafluoroethane (C2F6) and hydrogen fluoride (HF), can be used to etch the second semiconductor layer 108 isotropically and selectively. Alternatively, a selective wet etching process can be used to remove the second semiconductor layer 108. In this situation, a wet etchant, such as ammonia water (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution, can be used.

[0093] As Figure 8DAs shown, since the pre-treatment process 175-1 removes surface impurities (such as O / C / N signals), the sidewalls 108S of the second semiconductor layer 108 have improved surface roughness. In some embodiments that can be combined with other embodiments of the present disclosure, the second semiconductor layer 108 has smooth and substantially flat sidewalls 108S along the Y direction or the Z direction. If the pre-treatment process 175-1 pre-removes residues (such as carbon and / or GeO x ), an improvement in the line width variation (sometimes expressed as line width roughness, LWR) along the sidewalls 108S can be observed. In some embodiments, after performing the pre-treatment process 175-1, the LWR on the sidewalls 108S is less than about 5 nanometers, for example about 3 nanometers or less. The improved LWR can result in a uniform CD of the metal gate and lead to better device performance. In addition, the footings "A", "B", "C", "D" in the corner regions of the second semiconductor layer 108 (such as the intersection of the second semiconductor layer 108, the gate spacer 138, and the sacrificial gate dielectric layer 132) are removed to form nearly vertical sharp corners, which will be described in more detail in Figure 9 .

[0094] According to some embodiments, Figure 8E shows a top view of a cross-section E-E of the semiconductor device structure 100 along Figure 6 . In some embodiments that can be combined with other embodiments of the present disclosure, after removing the edge portion of the second semiconductor layer 108, free radical species 165 may remain on the processed surfaces of the semiconductor layer stack 104 (such as the first semiconductor layer 106) and the gate spacer 138, as shown in Figure 8D and Figure 8E . The gate spacer 138 can have a first concentration of free radical species, and the first semiconductor layer 106 has a second concentration of free radical species. In some embodiments, the first concentration and the second concentration of the free radical species can be substantially the same. In some embodiments, the first concentration of the free radical species can be greater than the second concentration of the free radical species.

[0095] In some embodiments, the exposed surface of the first semiconductor layer 106 may be roughened because a portion of the first semiconductor layer 106 may be removed simultaneously during the pre-treatment process 175-1. Since some exposed surfaces of the first semiconductor layer 106 are not covered by the residue 168, the first semiconductor layer 106 not covered by the residue 168 is removed at a faster rate compared to the first semiconductor layer 106 covered by the residue 168. In this way, the exposed surface of the first semiconductor layer 106 can be formed to have surface roughness, and the exposed surface of the gate spacer 138 and / or the first semiconductor layer 106 can have free radical species buried thereon, as shown inFigure 8E As shown. Although not depicted, in a subsequent stage, for example, after replacement gate formation (e.g., Figure 18A ), the first semiconductor layer 106 may have such a rough or irregular surface profile and a traceable amount of free radical species.

[0096] According to some embodiments, Figure 9 shown Figure 8A a part of the semiconductor device structure in. The second semiconductor layer 108a between the first semiconductor layers 106a and 106b has a uniform critical dimension (CD), where the upper portion 108a1 has a first CD, the middle portion 108a2 has a second CD substantially equal to the first CD, and the lower portion 108a3 has a third CD substantially equal to the second CD. In some embodiments that may be combined with other embodiments of the present disclosure, the first CD, the second CD, and the third CD are slightly different from each other. For example, the first CD and the third CD may be substantially the same and greater than the second CD. In one example, the difference between the first CD, the second CD, and the third CD is less than 3 nanometers.

[0097] Similarly, the second semiconductor layer 108b between the first semiconductor layers 106b and 106c has a uniform critical dimension (CD), where the upper portion 108b1 has a fourth CD, the middle portion 108b2 has a fifth CD substantially equal to the fourth CD, and the lower portion 108b3 has a sixth CD substantially equal to the fifth CD. In some embodiments that may be combined with other embodiments of the present disclosure, the fourth CD, the fifth CD, and the sixth CD are slightly different from each other. For example, the fourth CD and the sixth CD may be substantially the same and greater than the fifth CD. In one example, the difference between the fourth CD, the fifth CD, and the sixth CD is less than 3 nanometers.

[0098] Similarly, the second semiconductor layer 108c between the first semiconductor layer 106c and the well portion 116 of the substrate 101 has a uniform critical dimension (CD), where the upper portion 108c1 has a seventh CD, the middle portion 108c2 has an eighth CD substantially equal to the seventh CD, and the lower portion 108c3 has a ninth CD substantially equal to the eighth CD. In some embodiments that may be combined with other embodiments of the present disclosure, the seventh CD, the eighth CD, and the ninth CD are slightly different from each other. For example, the seventh CD and the ninth CD may be substantially the same and greater than the eighth CD. In one example, the difference between the seventh CD, the eighth CD, and the ninth CD is less than 3 nanometers.

[0099] In some embodiments that may be combined with other embodiments of the present disclosure, the first, second, and third first semiconductor layers 106a, 106b, 106c have a thickness T1 between about 3 nanometers and about 6 nanometers.

[0100] In some embodiments, the first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth CDs in the first device region have a first size feature, and the first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth CDs in the second device region have a second size feature different from the first size feature.

[0101] In some embodiments that may be in other embodiments of the present disclosure, each of the first, second, and third CDs has a first width, each of the fourth, fifth, and sixth CDs has a second width equal to the first width, and each of the seventh, eighth, and ninth CDs has a third width equal to the second width. In some examples, the first width, the second width, and the third width are in the range of about 12 nanometers to about 18 nanometers.

[0102] In some embodiments that may be in other embodiments of the present disclosure, each of the first, second, and third CDs has a first width, each of the fourth, fifth, and sixth CDs has a second width equal to the first width, and each of the seventh, eighth, and ninth CDs has a third width greater than the second width.

[0103] In some embodiments that may be in other embodiments of the present disclosure, each of the first, second, and third CDs has a first width, each of the fourth, fifth, and sixth CDs has a second width greater than the first width, and each of the seventh, eighth, and ninth CDs has a third width greater than the second width, partly due to the high aspect ratio of the device.

[0104] In some embodiments, the first width, the second width, and the third width in the first device region have a first size feature, and the first width, the second width, and the third width in the second device region have a second size feature different from the first size feature.

[0105] According to some embodiments, Figure 10 illustrates a portion of the semiconductor device structure 100 after removing the edge portions of each of the second semiconductor layers 108 of the semiconductor layer stack 104 Figure 8D in which. Although not shown, the exposed surface of the gate spacer 138 may have a radical species 165 generated by the pretreatment process 175-1, such as Figure 8DAs shown. In one embodiment, the second semiconductor layer 108 has a first sidewall 108-1, a second sidewall 108-2, a third sidewall 108-3, and a fourth sidewall 108-4. The first sidewall 108-1 abuts against the sacrificial gate dielectric layer 132 on the first side of the sacrificial gate structure 130. The second sidewall 108-2 is on the opposite side of the first sidewall 108-1 and abuts against the sacrificial gate dielectric layer 132 on the second side of the sacrificial gate structure 130. The third sidewall 108-3 connects the first sidewall 108-1 and the second sidewall 108-2. The fourth sidewall 108-4 is on the opposite side of the third sidewall 108-3 and connects the first sidewall 108-1 and the second sidewall 108-2.

[0106] In some embodiments, the first sidewall 108-1 and the third sidewall 108-3 form an angle θ1 in the range of about 45 degrees to about 90 degrees. The first sidewall 108-1 and the fourth sidewall 108-4 form an angle θ2 in the range of about 45 degrees to about 90 degrees. The second sidewall 108-2 and the third sidewall 108-3 form an angle θ3 in the range of about 45 degrees to about 90 degrees. The second sidewall 108-2 and the fourth sidewall 108-4 form an angle θ4 in the range of about 45 degrees to about 90 degrees.

[0107] In some embodiments that may be combined with other embodiments of the present disclosure, the angle θ1, the angle θ2, the angle θ3, and the angle θ4 are substantially the same. In one example, the angle θ1, the angle θ2, the angle θ3, and the angle θ4 are about 50 degrees to about 70 degrees, such as about 60 degrees.

[0108] In some embodiments that may be combined with other embodiments of the present disclosure, the angle θ1 and the angle θ2 are substantially the same, and the angle θ3 and the angle θ4 are substantially the same, where the angle θ1 is different from the angle θ3. For example, the angle θ1 is greater than the angle θ3. Alternatively, the angle θ1 is less than the angle θ3.

[0109] In some embodiments that may be combined with other embodiments of the present disclosure, the angle θ1 and the angle θ3 are substantially the same, and the angle θ2 and the angle θ4 are substantially the same, where the angle θ1 is different from the angle θ2. For example, the angle θ1 is greater than the angle θ2. Alternatively, the angle θ1 is less than the angle θ2.

[0110] In any of the embodiments shown in Figure 10 the second semiconductor layer 108 has a flat or smooth roughness along the Y direction (e.g., longitudinally) and has a uniform critical dimension (CD) on the third sidewall 108-3 and the fourth sidewall 108-4.

[0111] In Figure 11A Figures 11A to 11DIn , a dielectric layer 144a is deposited on the exposed surface of the semiconductor device structure 100. The dielectric layer 144a also fills the void 131( Figure 8A ), which is formed by removing the edge portion of the second semiconductor layer 108. The dielectric layer 144a contacts the processed surface of the second semiconductor layer 108 exposed to the void 131. Suitable materials for the dielectric layer 144a include, but are not limited to, SiO2, Si3N4, SiC, SiCP, SiON, SiOC, SiCN, SiOCN, and / or other suitable materials. Other materials may also be used, such as low-k dielectric materials having a dielectric constant below 3.5. The dielectric layer 144a can be formed by a conformal deposition process, such as ALD. In some embodiments, the dielectric layer 144a is a single-layer structure. In some embodiments, the dielectric layer 144a is a multi-layer structure comprising one or more of the materials discussed herein.

[0112] In Figures 12A to 12D a etch process is performed such that only a portion of the dielectric layer 144a remains in the void 131( Figure 8A ), and a dielectric spacer 144 is formed. The removal process can be any suitable process, such as dry etching, wet etching, or a combination thereof. The etch process can be a selective etch process that uses an etchant that selectively removes the dielectric layer 144a while substantially not removing the sacrificial gate structure 130 and the first semiconductor layer 106. A portion of the dielectric layer 144a can be removed by performing an anisotropic etch. During the anisotropic etch, the dielectric layer 144a within the void 131 is protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 is capped between the dielectric spacers 144 along the X direction.

[0113] In Figures 13A to 13DIn [the figure], an epitaxial source / drain (S / D) feature 146 is formed in a source / drain (S / D) region. The epitaxial S / D feature 146 can grow laterally from the first semiconductor layer 106. The epitaxial S / D feature 146 can include one or more layers of silicon, SiP, SiC, and SiCP for use as an N-type FET or one or more layers of silicon, SiGe, and germanium for use as a P-type FET. The epitaxial S / D feature 146 can be formed by an epitaxial growth process using selective epitaxial growth (SEG), CVD, ALD, or MBE. The second semiconductor layer 108 under the sacrificial gate structure 130 and the epitaxial S / D feature 146 are separated by a dielectric spacer 144. The epitaxial S / D feature 146 can grow both vertically and horizontally simultaneously to form a facet, which can correspond to a crystal plane of the material for the first semiconductor layer 106. In some cases, the epitaxial S / D features 146 of the fin structure can grow and combine with adjacent epitaxial S / D features 146, as Figure 13C shown in the embodiment.

[0114] The epitaxial S / D feature 146 can be an S / D region. For example, one of a pair of epitaxial S / D features 146 is located on one side of the sacrificial gate structure 130 and can be a source region, and the other of the pair of epitaxial S / D features 146 is located on the other side of the sacrificial gate structure 130 and can be a drain region. A pair of epitaxial S / D features 146 can include a source epitaxial feature and a drain epitaxial feature connected by a channel (such as the first semiconductor layer 106). The source / drain region can represent the source or the drain depending on the context, or collectively represent the source and the drain. In this disclosure, the source and the drain can be used interchangeably, and the epitaxial features formed in these regions are substantially the same.

[0115] In Figures 14A to 14DIn , a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the top surfaces of the sacrificial gate structure 130, the insulating material 118, the epitaxial S / D features 146, and the exposed surface of the semiconductor layer stack 104. The CESL 162 may comprise an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, or the like, and may be formed by CVD, PECVD, ALD, or any suitable deposition process. Next, a first interlayer dielectric (ILD) layer 164 is formed on the CESL 162 on the semiconductor device structure 100. The material of the first ILD layer 164 may comprise a compound containing silicon, oxygen, carbon, and / or hydrogen, such as silicon oxide, TEOS oxide, SiCOH, and SiOC. An organic material, such as a polymer, may also be used to form the first ILD layer 164. The first ILD layer 164 may be deposited by a PECVD process or other suitable deposition process. In some embodiments, after the first ILD layer 164 is formed, a thermal process may be performed on the semiconductor device structure 100 to anneal the first ILD layer 164.

[0116] In Figures 15A to 15D , after the first ILD layer 164 is formed, a planarization operation, such as CMP, is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed.

[0117] In Figures 16A to 16D , the sacrificial gate structure 130 and the second semiconductor layer 108 are removed in sequence. Removing the sacrificial gate structure 130 and the second semiconductor layer 108 forms an opening 166 between the gate spacers 138 and between adjacent first semiconductor layers 106. During the removal process, the first ILD layer 164 protects the epitaxial S / D features 146. The sacrificial gate structure 130 may be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 may first be removed by any suitable process, such as dry etching, wet etching, or a combination thereof, and then the sacrificial gate dielectric layer 132 may be removed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant, such as a tetramethylammonium hydroxide (TMAH) solution, may be used to selectively remove the sacrificial gate electrode layer 134 without removing the gate spacers 138, the first ILD layer 164, and the CESL 162.

[0118] Removing the sacrificial gate structure 130 exposes the first semiconductor layer 106 and the second semiconductor layer 108. Then, an etching process is performed to remove the second semiconductor layer 108. The etching process can be any suitable process, such as dry etching, wet etching, or a combination thereof. The etching process can be a selective etching process to remove the second semiconductor layer 108 without removing the gate spacer 138, the first ILD layer 164, the CESL 162, and the first semiconductor layer 106. In the case where the second semiconductor layer 108 is made of SiGe or germanium and the first semiconductor layer 106 is made of silicon, the chemicals used in the selective wet etching process remove the SiGe without substantially affecting the silicon, the gate spacer 138, the dielectric spacer 144, the dielectric material of the first ILD layer 164, and the CESL 162. In one embodiment, a wet etchant, a dry etchant, or any suitable isotropic etchant can be used to remove the second semiconductor layer 108. The wet etchant can be, for example, but not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), phosphoric acid (H3PO4). The dry etchant can be, for example, a fluorine-based (such as fluorine gas) or chlorine-based (such as chlorine gas) gas, or any suitable isotropic etchant. Once the etching process is completed, the portion of the first semiconductor layer 106 not covered by the dielectric spacer 144 is exposed in the opening 166.

[0119] In Figures 17A to 17DIn this case, an alternative gate structure 190 is formed. Each of the alternative gate structures 190 may include a gate dielectric layer 180 and a gate electrode layer 182. In some embodiments, an interfacial layer (IL) (not shown) may be formed between the gate dielectric layer 180 and the first semiconductor layer 106. The IL may also be formed on the exposed surface of the substrate 101. The IL may include or be made of: an oxide (such as silicon oxide) formed by thermally oxidizing or chemically oxidizing the first semiconductor layer 106, a nitride (such as silicon nitride, silicon oxynitride, oxynitride, etc.) and / or a dielectric layer (such as hafnium silicate). Then, a gate dielectric layer 180 is formed on the exposed surface of the semiconductor device structure 100 (such as on the IL (if present), the sidewalls of the gate spacers 138, the top surfaces of the first ILD layer 164 and the CESL 162). The gate dielectric layer 180 may be made of a material that is chemically different from the material of the sacrificial gate dielectric layer 132. The gate dielectric layer 180 may include or be made of a high-k dielectric material, such as hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), lanthanum oxide (LaO), aluminum oxide (AlO), aluminum silicon oxide (AlSiO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum pentoxide (Ta2O5), yttrium oxide (Y2O3), silicon oxynitride (SiON) or other suitable high-k materials. The gate dielectric layer 180 may be a conformal layer formed by a conformal process, which may be, for example, an ALD process, a PECVD process, a molecular-beam deposition (MBD) process, the like, and / or a combination thereof.

[0120] After forming the IL (if present) and the gate dielectric layer 180, a gate electrode layer 182 is formed on the gate dielectric layer 180. The gate electrode layer 182 fills the opening 166 ( Figure 16A ) and surrounds a portion of each of the first semiconductor layers 106. Since the pre-treatment process 175-1 is performed before forming the dielectric spacers 144, the critical dimension (CD) variation and surface roughness of the SiGe layer are reduced. In this way, the CD of the gate electrode layer 182 can be controlled to be uniform. As Figure 17D shown, the gate electrode layer 182 has a uniform CD along the Y direction.

[0121] The gate electrode layer 182 comprises one or more conductive material layers, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 182 can be formed by PVD, CVD, ALD, electroplating, or other suitable methods. In some embodiments, one or more optional conformal layers (not shown) can be deposited conformally (and, if there are more than one layer, sequentially) between the gate dielectric layer 180 and the gate electrode layer 182. The one or more optional conformal layers can include one or more barrier and / or capping layers and one or more work function adjustment layers. The one or more barrier and / or capping layers can include or be nitrides of tantalum and / or titanium, silicon nitride, carbon nitride, and / or aluminum nitride; nitrides, carbonitrides, and / or tungsten carbide, the like, or combinations thereof. The one or more work function adjustment layers can include or be nitrides of tantalum and / or titanium, silicon nitride, carbon nitride, aluminum nitride, aluminum oxide, and / or aluminum carbide; nitrides, carbonitrides, and / or tungsten carbide; cobalt, platinum, the like, or combinations thereof.

[0122] The portions of the gate electrode layer 182, the one or more optional conformal layers (if present), and the gate dielectric layer 180 that are above the top surface of the first ILD layer 164, the CESL 162, and the gate spacers 138 can be removed by a planarization process, such as a CMP process. After the CMP process, the top surfaces of the first ILD layer 164, the CESL 162, the gate spacers 138, and the gate electrode layer 182 are substantially coplanar.

[0123] In Figures 18A to 18D a contact opening is formed through the first ILD layer 164 and the CESL 162 to expose the epitaxial S / D feature 146. Then a silicide layer 184 is formed on the epitaxial S / D feature 146, and a source / drain (S / D) contact 186 is formed in the contact opening over the silicide layer 184. The S / D contact 186 comprises a conductive material, such as ruthenium, molybdenum, cobalt, nickel, tungsten, titanium, tantalum, copper, aluminum, TiN, or TaN. Although not shown, a barrier layer (such as TiN, TaN, or the like) can be formed on the sidewalls of the contact opening before forming the S / D contact 186.

[0124] After forming the contact opening, a silicide layer 184 is formed on the epitaxial S / D feature 146. The silicide layer 184 electrically couples the epitaxial S / D feature 146 to the S / D contact 186 subsequently formed in the contact opening. The silicide layer 184 can be formed by depositing a metal source layer on the epitaxial S / D feature 146 and performing a rapid thermal annealing process. During the rapid thermal annealing process, a portion of the metal source layer on the epitaxial S / D feature 146 reacts with silicon in the epitaxial S / D feature 146 to form the silicide layer 184. The unreacted portion of the metal source layer is then removed. The silicide layer 184 can include a silicide of a metal or a metal alloy, and the metal includes a noble metal, a refractory metal, a rare earth metal, an alloy thereof, or a combination thereof. Next, a conductor material is formed in the contact opening to form the S / D contact 186. The conductor material can be made of a material including one or more of the following: ruthenium, molybdenum, cobalt, nickel, tungsten, titanium, tantalum, copper, aluminum, TiN, and TaN. Although not shown, a barrier layer (such as TiN, TaN, or the like) can be formed on the sidewalls of the contact opening before forming the S / D contact 186. Next, a planarization process, such as CMP, is performed to remove the excess deposited portion of the contact material and expose the top surface of the gate electrode layer 182.

[0125] It should be understood that the semiconductor device structure 100 can be further subjected to complementary metal oxide semiconductor (CMOS) processes and / or back-end-of-line (BEOL) processes to form more features, such as transistors, contact / via elements, interconnect metal layers, dielectric layers, passivation layers, etc. The semiconductor device structure 100 can also include a backside contact (not shown) on the backside of the substrate 101, so that the source or drain in the epitaxial S / D feature 146 is connected to a backside rail (such as a positive voltage VDD or a negative voltage VSS) through the backside contact.

[0126] The various embodiments and examples described herein have advantages over the prior art. According to some embodiments of the present disclosure, a pretreatment process using neutral radicals (such as N* and H*) is performed before forming the dielectric spacer 144 to remove residues from the exposed surface of the second semiconductor layer 108 (which is a SiGe layer), where the second semiconductor layer 108 is stacked alternately with the first semiconductor layer 106 (which is a nanostructured channel layer). The pretreatment process improves the etch loading of the second semiconductor layer 108 (which is a SiGe layer) from top to bottom when subsequently removing the second semiconductor layer 108 (which is a SiGe layer), thus reducing the CD variation and surface roughness of the second semiconductor layer 108 (which is a SiGe layer), and facilitating a uniform inner spacer deposition process. In this way, the sacrificial gate dielectric layer and the inner spacer are prevented from being damaged, thereby maintaining CD control of the metal gate and the integrity of the epitaxial source / drain during subsequent gate replacement processes.

[0127] One embodiment is a method of manufacturing a semiconductor device structure. The method includes forming a sacrificial gate structure on a portion of a fin structure, the fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately. The method also includes removing a portion of the fin structure not covered by the sacrificial gate structure, exposing the plurality of exposed surfaces of each of the first semiconductor layer and the second semiconductor layer to an environment of at least one radical species, removing an edge portion of the second semiconductor layer to form a void between two adjacent first semiconductor layers, and forming a dielectric spacer in the void.

[0128] In some embodiments, the at least one radical species is formed from a nitrogen-containing gas and a hydrogen-containing gas.

[0129] In some embodiments, each of the first semiconductor layer and the second semiconductor layer is exposed to an environment of a plurality of neutral radical species of nitrogen and hydrogen.

[0130] In some embodiments, the at least one radical species is generated from a remote plasma generator placed upstream of the reaction chamber.

[0131] In some embodiments, the at least one radical species is directed to remove a plurality of by-products generated during the removal of the portion of the fin structure.

[0132] In some embodiments, the by-products include a plurality of native oxide layers on the exposed surfaces of each of the first semiconductor layer and the second semiconductor layer and the gate spacer of the sacrificial gate structure.

[0133] In some embodiments, the method further includes, after exposing the exposed surfaces of each of the first semiconductor layer and the second semiconductor layer to an environment of at least one radical species, exposing the exposed surfaces of each of the first semiconductor layer and the second semiconductor layer to a surface cleaning process using hydrofluoric acid and / or dilute hydrofluoric acid.

[0134] A method of fabricating a semiconductor device structure includes removing a portion of a plurality of first semiconductor layers and a plurality of second semiconductor layers that are stacked alternately, wherein at least two surfaces of each of the second semiconductor layers are respectively disposed between gate spacers and a sacrificial gate electrode layer, treating the exposed surfaces of each of the first semiconductor layer and the second semiconductor layer with a plurality of first radical species and a plurality of second radical species, selectively removing edge portions of each of the second semiconductor layers such that each of the second semiconductor layers has a substantially flat surface along the longitudinal direction of each of the second semiconductor layers, depositing dielectric spacers between two adjacent first semiconductor layers, wherein the dielectric spacers contact one of the second semiconductor layers, and forming a plurality of epitaxial source / drain features such that a portion of the epitaxial source / drain features contacts the first semiconductor layer and the dielectric spacers.

[0135] In some embodiments, the first radical species and the second radical species are directed to remove a plurality of by-products generated during the removal of the gate spacers.

[0136] In some embodiments, the by-products include silicon oxycarbide.

[0137] In some embodiments, the exposed sidewalls created by removing the edge portions of each of the second semiconductor layers have a substantially uniform critical dimension along the longitudinal direction of each of the second semiconductor layers.

[0138] In some embodiments, the critical dimension is about 3 nanometers or less.

[0139] In some embodiments, the first radical species includes nitrogen atom radicals, and the second radical species includes hydrogen atom radicals.

[0140] In some embodiments, each of the first semiconductor layer and the second semiconductor layer is exposed to an environment of the first radical species and the second radical species, and the ratio of the first radical species to the second radical species is from about 6:1 to about 25:1.

[0141] In some embodiments, the method further includes performing a pre-cleaning process using hydrofluoric acid or dilute hydrofluoric acid on the treated exposed surfaces of each of the first semiconductor layer and the second semiconductor layer before selectively removing the edge portions of each of the second semiconductor layers.

[0142] In some embodiments, the method further includes removing the sacrificial gate electrode layer and the second semiconductor layer after forming the epitaxial source / drain features.

[0143] A method of manufacturing a semiconductor device structure includes providing a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately, forming a sacrificial gate structure and a gate spacer on a portion of the fin structure, removing, by an etching process, a portion of the fin structure not covered by the sacrificial gate structure, wherein a plurality of exposed surfaces of each of the first semiconductor layer and the second semiconductor layer are covered with a plurality of etch residues from at least the gate spacer, removing the etch residues by reacting a plurality of first radical species and a plurality of second radical species with the etch residues, and selectively removing a portion of the second semiconductor layer.

[0144] In some embodiments, after removing the etch residues, the first semiconductor layer has a first concentration of the first radical species and the second radical species, and after selectively removing the portion of the second semiconductor layer, the first semiconductor layer has a second concentration of the first radical species and the second radical species, and wherein the first concentration of the first radical species and the second radical species is greater than the second concentration of the first radical species and the second radical species.

[0145] In some embodiments, the first radical species includes nitrogen atom radicals, and the second radical species includes hydrogen atom radicals.

[0146] In some embodiments, the exposed surface of the first semiconductor layer has a roughened surface profile.

[0147] The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A manufacturing method of a semiconductor device structure, characterized in that, Comprising: Forming a sacrificial gate structure on a part of a fin structure, the fin structure comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately; Removing a part of the fin structure not covered by the sacrificial gate structure; Exposing a plurality of exposed surfaces of each of the plurality of first semiconductor layers and the plurality of second semiconductor layers to an environment of at least one radical species; Removing an edge portion of the plurality of second semiconductor layers to form a gap between two adjacent ones of the plurality of first semiconductor layers; And Forming a dielectric spacer between the gaps.

2. The method according to claim 1, characterized in that, Wherein the at least one radical species is formed from a nitrogen-containing gas and a hydrogen-containing gas.

3. The method according to claim 1, characterized in that, Wherein the at least one radical species is directed to remove a plurality of by-products generated during the removal of the part of the fin structure.

4. The method according to claim 1, wherein Further comprising: After exposing the plurality of exposed surfaces of each of the plurality of first semiconductor layers and the plurality of second semiconductor layers to the environment of the at least one radical species, exposing the plurality of exposed surfaces of each of the plurality of first semiconductor layers and the plurality of second semiconductor layers to a surface cleaning process using hydrofluoric acid and / or dilute hydrofluoric acid.

5. A manufacturing method of a semiconductor device structure, characterized in that, Comprising: Removing a part of a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately, wherein at least two surfaces of each of the plurality of second semiconductor layers are respectively disposed between a gate spacer and a sacrificial gate electrode layer; Treating a plurality of exposed surfaces of each of the plurality of first semiconductor layers and the plurality of second semiconductor layers with a plurality of first radical species and a plurality of second radical species; Selectively removing an edge portion of each of the plurality of second semiconductor layers such that each of the plurality of second semiconductor layers has a substantially flat surface along a longitudinal direction of each of the plurality of second semiconductor layers; Depositing a dielectric spacer between two adjacent ones of the plurality of first semiconductor layers, wherein the dielectric spacer contacts one of the plurality of second semiconductor layers; And Forming a plurality of epitaxial source / drain features such that a part of the plurality of epitaxial source / drain features contacts the plurality of first semiconductor layers and the dielectric spacer.

6. The method according to claim 5, wherein Wherein the plurality of first radical species and the plurality of second radical species are directed to remove a plurality of by-products generated during the removal of the gate spacer.

7. The method according to claim 6, wherein Wherein the plurality of by-products comprise silicon oxycarbide.

8. A manufacturing method of a semiconductor device structure, characterized in that, Comprising: Providing a fin structure, the fin structure comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately; Forming a sacrificial gate structure and a gate spacer on a part of the fin structure; By an etching process, removing a part of the fin structure not covered by the sacrificial gate structure, wherein a plurality of exposed surfaces of each of the plurality of first semiconductor layers and the plurality of second semiconductor layers are covered by a plurality of etching residues at least from the gate spacer; Removing the plurality of etching residues by reacting a plurality of first radical species and a plurality of second radical species with the plurality of etching residues; And Selectively removing a part of the plurality of second semiconductor layers.

9. The method according to claim 8, wherein After removing the plurality of etching residues, the plurality of first semiconductor layers have a first concentration of the plurality of first radical species and the plurality of second radical species, and after selectively removing the portion of the plurality of second semiconductor layers, the plurality of first semiconductor layers have a second concentration of the plurality of first radical species and the plurality of second radical species, and wherein the first concentration of the plurality of first radical species and the plurality of second radical species is greater than the second concentration of the plurality of first radical species and the plurality of second radical species.

10. The method according to claim 8, wherein Wherein the plurality of exposed surfaces of the plurality of first semiconductor layers have a roughened surface profile.

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