Preparation method of sapphire-based enhanced HEMT epitaxial wafer
By preparing the nitride epitaxial structure on a sapphire substrate and applying a compressive and tensile stress dielectric layer, the problem of low threshold voltage of the enhanced HEMT epitaxial sheet is solved, and the safety and performance improvement of the device is achieved.
Patent Information
- Application Number
- CN202510733349.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-04
- Publication Date
- 2025-07-18
AI Technical Summary
The existing enhanced HEMT epitaxial chip has a low threshold voltage, which poses a risk of incorrect opening, affecting circuit safety.
Nitride epitaxial structure was prepared on a sapphire substrate, and a P-type nitride gate layer was formed by etching, and the pressure-stress and tensile stress dielectric layer was deposited, depleted areas were defined, source and drain metals were prepared to form a sapphire-based reinforced HEMT epitaxial sheet.
Effectively reduce the gate leakage of the device, improve the switching current ratio, reduce power consumption, reduce polarized charge surface density of heterojunction interfaces, and increase threshold voltage.
Abstract
Description
Technical Field
[0001] The present invention relates to a method for preparing a sapphire-based enhanced HEMT epitaxial wafer. Background Art
[0002] As a representative of the third-generation semiconductor materials, gallium nitride (GaN) has many excellent characteristics, such as a high critical breakdown electric field, a high electron mobility, a high two-dimensional electron gas concentration, and good high-temperature working ability, etc. Third-generation semiconductor structures based on gallium nitride, such as high electron mobility field effect transistors (HEMTs), heterostructure field effect transistors (HFETs), etc. have been applied, especially having obvious advantages in fields such as radio frequency and microwave that require high power and high frequency.
[0003] GaN HEMTs are mainly applied in the communication industry and the power electronics industry, but they also have unique advantages in the fields of high-speed digital circuits and mixed signals. GaN HEMTs have excellent high-temperature stability, which can greatly reduce the cost of the circuit in terms of heat source and temperature field control. The wide bandgap characteristic of GaN enables it to have both a high electron saturation velocity and a high breakdown voltage, enabling the device to operate at a higher voltage, which can improve the driving ability of the circuit. Therefore, compared with traditional silicon technologies, digital circuits using GaN HEMT bases can meet the ability to work with large current voltage swings and in harsh environments, making it have potential huge applications in corresponding fields.
[0004] The existing enhanced HEMT epitaxial wafers have a relatively low threshold voltage, and there is a risk of mis-turn-on in actual circuit applications, which affects the circuit safety. Summary of the Invention
[0005] The purpose of the present invention is to provide a method for preparing a sapphire-based enhanced HEMT epitaxial wafer to solve the problems raised in the above background art.
[0006] To solve the above technical problems, the technical solution provided by the present invention is: a method for preparing a sapphire-based enhanced HEMT epitaxial wafer, specifically including the following steps:
[0007] 1) Prepare a nitride epitaxial structure on a sapphire substrate, etch the P-type nitride layer of the nitride epitaxial structure to form a first-level P-type nitride gate layer and a second-level P-type nitride gate layer; prepare a first-level gate metal on the first-level P-type nitride gate layer and a first-level gate metal on the second-level P-type nitride gate layer; the first-level P-type nitride gate layer and its surrounding area are defined as a first-level depletion region, and the second-level P-type nitride gate layer and its surrounding area are defined as a second-level depletion region;
[0008] 2) Deposit a compressive stress dielectric layer on the surface of the nitride epitaxial structure, and the compressive stress dielectric layer covers the depletion regions and the depletion regions;
[0009] 3) Remove the compressive stress dielectric layer and the tensile stress dielectric layer covering the depletion region;
[0010] 4) Deposit a tensile stress dielectric layer on the surface of the nitride epitaxial structure. The tensile stress dielectric layer covers the compressive stress dielectric layer, the first-level depletion region, and the second-level depletion region; Remove the tensile stress dielectric layer covering the compressive stress dielectric layer;
[0011] 5) Prepare the first-level source metal and the first-level drain metal in the depletion region to form a sapphire-based enhancement-mode HEMT epitaxial wafer.
[0012] As a preferred solution, the thickness of the compressive stress dielectric layer is 35 nm to 900 nm, and the stress value is 270 MPa to 2.6 GPa.
[0013] As a preferred solution, the thickness of the tensile stress dielectric layer is 35 nm to 900 nm, and the stress value is 270 MPa to 2.6 GPa.
[0014] As a preferred solution, the nitride epitaxial structure includes a buffer layer, a channel layer, a barrier layer, and a P-type nitride layer.
[0015] The advantages of the present invention are as follows: It is convenient to manufacture. The finished product can effectively reduce the gate leakage current of the device, improve the switching current ratio of the device, reduce power consumption, weaken the polarization electric field intensity of the barrier layer, reduce the polarization charge surface density at the heterojunction interface, and further increase the threshold voltage of the enhancement-mode semiconductor device. Detailed implementation manners
[0016] The following uses specific embodiments to illustrate the present invention, which is not a limitation to the present invention.
[0017] Embodiment 1
[0018] A method for preparing a sapphire-based enhancement-mode HEMT epitaxial wafer specifically includes the following steps:
[0019] 1) Prepare a nitride epitaxial structure on a sapphire substrate, etch the P-type nitride layer of the nitride epitaxial structure to form a first-level P-type nitride gate layer and a second-level P-type nitride gate layer; Prepare a first-level gate metal on the first-level P-type nitride gate layer, and prepare a first-level gate metal on the second-level P-type nitride gate layer; The first-level P-type nitride gate layer and its surrounding area are defined as the first-level depletion region, and the second-level P-type nitride gate layer and its surrounding area are defined as the second-level depletion region;
[0020] 2) Deposit a compressive stress dielectric layer on the surface of the nitride epitaxial structure. The compressive stress dielectric layer covers the depletion region and the depletion region;
[0021] 3) Remove the compressive stress dielectric layer and the tensile stress dielectric layer covering the depletion region;
[0022] 4) Deposit a tensile stress dielectric layer on the surface of the nitride epitaxial structure. The tensile stress dielectric layer covers the compressive stress dielectric layer, the first depletion region, and the second depletion region; remove the tensile stress dielectric layer covering the compressive stress dielectric layer.
[0023] 5) Fabricate a first source metal and a first drain metal in the depletion region to form a sapphire-based enhancement-mode HEMT epitaxial wafer.
[0024] As a preferred solution of this embodiment, the thickness of the compressive stress dielectric layer is 35 nm and the stress value is 270 MPa.
[0025] As a preferred solution of this embodiment, the thickness of the tensile stress dielectric layer is 35 nm and the stress value is 270 MPa.
[0026] As a preferred solution of this embodiment, the nitride epitaxial structure includes a buffer layer, a channel layer, a barrier layer, and a P-type nitride layer.
[0027] Embodiment 2
[0028] A method for fabricating a sapphire-based enhancement-mode HEMT epitaxial wafer specifically includes the following steps:
[0029] 1) Fabricate a nitride epitaxial structure on a sapphire substrate, etch the P-type nitride layer of the nitride epitaxial structure to form a first P-type nitride gate layer and a second P-type nitride gate layer; fabricate a first gate metal on the first P-type nitride gate layer and a first gate metal on the second P-type nitride gate layer; the first P-type nitride gate layer and its peripheral region are defined as the first depletion region, and the second P-type nitride gate layer and its peripheral region are defined as the second depletion region.
[0030] 2) Deposit a compressive stress dielectric layer on the surface of the nitride epitaxial structure. The compressive stress dielectric layer covers the depletion regions.
[0031] 3) Remove the compressive stress dielectric layer and the tensile stress dielectric layer covering the depletion region.
[0032] 4) Deposit a tensile stress dielectric layer on the surface of the nitride epitaxial structure. The tensile stress dielectric layer covers the compressive stress dielectric layer, the first depletion region, and the second depletion region; remove the tensile stress dielectric layer covering the compressive stress dielectric layer.
[0033] 5) Fabricate a first source metal and a first drain metal in the depletion region to form a sapphire-based enhancement-mode HEMT epitaxial wafer.
[0034] As a preferred solution of this embodiment, the thickness of the compressive stress dielectric layer is 900 nm and the stress value is 2.6 GPa.
[0035] As a preferred solution of this embodiment, the thickness of the tensile stress dielectric layer is 900 nm, and the stress value is 2.6 GPa.
[0036] As a preferred solution of this embodiment, the nitride epitaxial structure includes a buffer layer, a channel layer, a barrier layer, and a P-type nitride layer.
[0037] Embodiment 3
[0038] A method for preparing a sapphire-based enhanced HEMT epitaxial wafer specifically includes the following steps:
[0039] 1) Prepare a nitride epitaxial structure on a sapphire substrate, etch the P-type nitride layer of the nitride epitaxial structure to form a first-level P-type nitride gate layer and a second-level P-type nitride gate layer; prepare a first-level gate metal on the first-level P-type nitride gate layer, and prepare a first-level gate metal on the second-level P-type nitride gate layer; the first-level P-type nitride gate layer and its surrounding area are defined as a first-level depletion region, and the second-level P-type nitride gate layer and its surrounding area are defined as a second-level depletion region;
[0040] 2) Deposit a compressive stress dielectric layer on the surface of the nitride epitaxial structure, and the compressive stress dielectric layer covers the depletion region and the depletion region;
[0041] 3) Remove the compressive stress dielectric layer and the tensile stress dielectric layer covering the depletion region;
[0042] 4) Deposit a tensile stress dielectric layer on the surface of the nitride epitaxial structure, and the tensile stress dielectric layer covers the compressive stress dielectric layer, the first-level depletion region, and the second-level depletion region; remove the tensile stress dielectric layer covering the compressive stress dielectric layer;
[0043] 5) Prepare a first-level source metal and a first-level drain metal in the depletion region to form a sapphire-based enhanced HEMT epitaxial wafer.
[0044] As a preferred solution of this embodiment, the thickness of the compressive stress dielectric layer is 450 nm, and the stress value is 1.2 GPa.
[0045] As a preferred solution of this embodiment, the thickness of the tensile stress dielectric layer is 450 nm, and the stress value is 1.2 GPa.
[0046] As a preferred solution of this embodiment, the nitride epitaxial structure includes a buffer layer, a channel layer, a barrier layer, and a P-type nitride layer.
[0047] Embodiment 4
[0048] A method for preparing a sapphire-based enhanced HEMT epitaxial wafer specifically includes the following steps:
[0049] 1) Prepare a nitride epitaxial structure on a sapphire substrate, etch the P-type nitride layer of the nitride epitaxial structure to form a first-level P-type nitride gate layer and a second-level P-type nitride gate layer; prepare a first-level gate metal on the first-level P-type nitride gate layer and a first-level gate metal on the second-level P-type nitride gate layer; define the first-level P-type nitride gate layer and its surrounding area as a first-level depletion region, and define the second-level P-type nitride gate layer and its surrounding area as a second-level depletion region;
[0050] 2) Deposit a compressive stress dielectric layer on the surface of the nitride epitaxial structure, and the compressive stress dielectric layer covers the depletion regions;
[0051] 3) Remove the compressive stress dielectric layer and the tensile stress dielectric layer covering the depletion regions;
[0052] 4) Deposit a tensile stress dielectric layer on the surface of the nitride epitaxial structure, and the tensile stress dielectric layer covers the compressive stress dielectric layer, the first-level depletion region, and the second-level depletion region; remove the tensile stress dielectric layer covering the compressive stress dielectric layer;
[0053] 5) Prepare a first-level source metal and a first-level drain metal in the depletion regions to form a sapphire-based enhancement-mode HEMT epitaxial wafer.
[0054] As a preferred solution of this embodiment, the thickness of the compressive stress dielectric layer is 35 nm, and the stress value is 270 MPa.
[0055] As a preferred solution of this embodiment, the thickness of the tensile stress dielectric layer is 900 nm, and the stress value is 2.6 GPa.
[0056] As a preferred solution of this embodiment, the nitride epitaxial structure includes a buffer layer, a channel layer, a barrier layer, and a P-type nitride layer.
[0057] Example 5
[0058] A method for preparing a sapphire-based enhancement-mode HEMT epitaxial wafer specifically includes the following steps:
[0059] 1) Prepare a nitride epitaxial structure on a sapphire substrate, etch the P-type nitride layer of the nitride epitaxial structure to form a first-level P-type nitride gate layer and a second-level P-type nitride gate layer; prepare a first-level gate metal on the first-level P-type nitride gate layer and a first-level gate metal on the second-level P-type nitride gate layer; define the first-level P-type nitride gate layer and its surrounding area as a first-level depletion region, and define the second-level P-type nitride gate layer and its surrounding area as a second-level depletion region;
[0060] 2) Deposit a compressive stress dielectric layer on the surface of the nitride epitaxial structure, and the compressive stress dielectric layer covers the depletion regions;
[0061] 3) Remove the compressive stress dielectric layer and tensile stress dielectric layer covering the depletion region;
[0062] 4) Deposit a tensile stress dielectric layer on the surface of the nitride epitaxial structure. The tensile stress dielectric layer covers the compressive stress dielectric layer, the first-level depletion region, and the second-level depletion region; remove the tensile stress dielectric layer covering the compressive stress dielectric layer;
[0063] 5) Prepare the first-level source metal and the first-level drain metal in the depletion region to form a sapphire-based enhancement-mode HEMT epitaxial wafer.
[0064] As a preferred solution of this embodiment, the thickness of the compressive stress dielectric layer is 900 nm, and the stress value is 2.6 GPa.
[0065] As a preferred solution of this embodiment, the thickness of the tensile stress dielectric layer is 35 nm, and the stress value is 270 MPa.
[0066] As a preferred solution of this embodiment, the nitride epitaxial structure includes a buffer layer, a channel layer, a barrier layer, and a P-type nitride layer.
[0067] Example 6
[0068] A method for preparing a sapphire-based enhancement-mode HEMT epitaxial wafer specifically includes the following steps:
[0069] 1) Prepare a nitride epitaxial structure on a sapphire substrate, etch the P-type nitride layer of the nitride epitaxial structure to form a first-level P-type nitride gate layer and a second-level P-type nitride gate layer; prepare a first-level gate metal on the first-level P-type nitride gate layer, and prepare a first-level gate metal on the second-level P-type nitride gate layer; the first-level P-type nitride gate layer and its surrounding area are defined as the first-level depletion region, and the second-level P-type nitride gate layer and its surrounding area are defined as the second-level depletion region;
[0070] 2) Deposit a compressive stress dielectric layer on the surface of the nitride epitaxial structure. The compressive stress dielectric layer covers the depletion region and the depletion region;
[0071] 3) Remove the compressive stress dielectric layer and the tensile stress dielectric layer covering the depletion region;
[0072] 4) Deposit a tensile stress dielectric layer on the surface of the nitride epitaxial structure. The tensile stress dielectric layer covers the compressive stress dielectric layer, the first-level depletion region, and the second-level depletion region; remove the tensile stress dielectric layer covering the compressive stress dielectric layer;
[0073] 5) Prepare the first-level source metal and the first-level drain metal in the depletion region to form a sapphire-based enhancement-mode HEMT epitaxial wafer.
[0074] As a preferred solution of this embodiment, the thickness of the compressive stress dielectric layer is 35 nm, and the stress value is 270 MPa.
[0075] As a preferred solution of this embodiment, the thickness of the tensile stress dielectric layer is 450 nm and the stress value is 1.2 GPa.
[0076] As a preferred solution of this embodiment, the nitride epitaxial structure includes a buffer layer, a channel layer, a barrier layer, and a P-type nitride layer.
[0077] Example 7
[0078] A method for preparing a sapphire-based enhanced HEMT epitaxial wafer specifically includes the following steps:
[0079] 1) Prepare a nitride epitaxial structure on a sapphire substrate, etch the P-type nitride layer of the nitride epitaxial structure to form a first-level P-type nitride gate layer and a second-level P-type nitride gate layer; prepare a first-level gate metal on the first-level P-type nitride gate layer and a first-level gate metal on the second-level P-type nitride gate layer; the first-level P-type nitride gate layer and its surrounding area are defined as a first-level depletion region, and the second-level P-type nitride gate layer and its surrounding area are defined as a second-level depletion region;
[0080] 2) Deposit a compressive stress dielectric layer on the surface of the nitride epitaxial structure, and the compressive stress dielectric layer covers the depletion regions;
[0081] 3) Remove the compressive stress dielectric layer and the tensile stress dielectric layer covering the depletion regions;
[0082] 4) Deposit a tensile stress dielectric layer on the surface of the nitride epitaxial structure, and the tensile stress dielectric layer covers the compressive stress dielectric layer, the first-level depletion region, and the second-level depletion region; remove the tensile stress dielectric layer covering the compressive stress dielectric layer;
[0083] 5) Prepare a first-level source metal and a first-level drain metal in the depletion regions to form a sapphire-based enhanced HEMT epitaxial wafer.
[0084] As a preferred solution of this embodiment, the thickness of the compressive stress dielectric layer is 900 nm and the stress value is 2.6 GPa.
[0085] As a preferred solution of this embodiment, the thickness of the tensile stress dielectric layer is 450 nm and the stress value is 1.2 GPa.
[0086] As a preferred solution of this embodiment, the nitride epitaxial structure includes a buffer layer, a channel layer, a barrier layer, and a P-type nitride layer.
[0087] Example 8
[0088] A method for preparing a sapphire-based enhanced HEMT epitaxial wafer specifically includes the following steps:
[0089] 1) Prepare a nitride epitaxial structure on a sapphire substrate, etch the P-type nitride layer of the nitride epitaxial structure to form a first-level P-type nitride gate layer and a second-level P-type nitride gate layer; prepare a first-level gate metal on the first-level P-type nitride gate layer and a first-level gate metal on the second-level P-type nitride gate layer; define the first-level P-type nitride gate layer and its surrounding area as a first-level depletion region, and define the second-level P-type nitride gate layer and its surrounding area as a second-level depletion region;
[0090] 2) Deposit a compressive stress dielectric layer on the surface of the nitride epitaxial structure, and the compressive stress dielectric layer covers the depletion regions;
[0091] 3) Remove the compressive stress dielectric layer and the tensile stress dielectric layer covering the depletion regions;
[0092] 4) Deposit a tensile stress dielectric layer on the surface of the nitride epitaxial structure, and the tensile stress dielectric layer covers the compressive stress dielectric layer, the first-level depletion region, and the second-level depletion region; remove the tensile stress dielectric layer covering the compressive stress dielectric layer;
[0093] 5) Prepare a first-level source metal and a first-level drain metal in the depletion regions to form a sapphire-based enhancement-mode HEMT epitaxial wafer.
[0094] As a preferred solution of this embodiment, the thickness of the compressive stress dielectric layer is 40 nm, and the stress value is 260 MPa.
[0095] As a preferred solution of this embodiment, the thickness of the tensile stress dielectric layer is 40 nm, and the stress value is 260 MPa.
[0096] As a preferred solution of this embodiment, the nitride epitaxial structure includes a buffer layer, a channel layer, a barrier layer, and a P-type nitride layer.
[0097] Example 9
[0098] A method for preparing a sapphire-based enhancement-mode HEMT epitaxial wafer specifically includes the following steps:
[0099] 1) Prepare a nitride epitaxial structure on a sapphire substrate, etch the P-type nitride layer of the nitride epitaxial structure to form a first-level P-type nitride gate layer and a second-level P-type nitride gate layer; prepare a first-level gate metal on the first-level P-type nitride gate layer and a first-level gate metal on the second-level P-type nitride gate layer; define the first-level P-type nitride gate layer and its surrounding area as a first-level depletion region, and define the second-level P-type nitride gate layer and its surrounding area as a second-level depletion region;
[0100] 2) Deposit a compressive stress dielectric layer on the surface of the nitride epitaxial structure, and the compressive stress dielectric layer covers the depletion regions;
[0101] 3) Remove the compressive stress dielectric layer and tensile stress dielectric layer covering the depletion region;
[0102] 4) Deposit a tensile stress dielectric layer on the surface of the nitride epitaxial structure, where the tensile stress dielectric layer covers the compressive stress dielectric layer, the first-level depletion region, and the second-level depletion region; remove the tensile stress dielectric layer covering the compressive stress dielectric layer;
[0103] 5) Prepare the first-level source metal and the first-level drain metal in the depletion region to form a sapphire-based enhancement-mode HEMT epitaxial wafer.
[0104] As a preferred solution of this embodiment, the thickness of the compressive stress dielectric layer is 800 nm, and the stress value is 2.5 GPa.
[0105] As a preferred solution of this embodiment, the thickness of the tensile stress dielectric layer is 800 nm, and the stress value is 2.5 GPa.
[0106] As a preferred solution of this embodiment, the nitride epitaxial structure includes a buffer layer, a channel layer, a barrier layer, and a P-type nitride layer.
[0107] Example 10
[0108] A method for preparing a sapphire-based enhancement-mode HEMT epitaxial wafer specifically includes the following steps:
[0109] 1) Prepare a nitride epitaxial structure on a sapphire substrate, etch the P-type nitride layer of the nitride epitaxial structure to form a first-level P-type nitride gate layer and a second-level P-type nitride gate layer; prepare a first-level gate metal on the first-level P-type nitride gate layer, and prepare a first-level gate metal on the second-level P-type nitride gate layer; the first-level P-type nitride gate layer and its surrounding area are defined as the first-level depletion region, and the second-level P-type nitride gate layer and its surrounding area are defined as the second-level depletion region;
[0110] 2) Deposit a compressive stress dielectric layer on the surface of the nitride epitaxial structure, where the compressive stress dielectric layer covers the depletion regions;
[0111] 3) Remove the compressive stress dielectric layer and the tensile stress dielectric layer covering the depletion region;
[0112] 4) Deposit a tensile stress dielectric layer on the surface of the nitride epitaxial structure, where the tensile stress dielectric layer covers the compressive stress dielectric layer, the first-level depletion region, and the second-level depletion region; remove the tensile stress dielectric layer covering the compressive stress dielectric layer;
[0113] 5) Prepare the first-level source metal and the first-level drain metal in the depletion region to form a sapphire-based enhancement-mode HEMT epitaxial wafer.
[0114] As a preferred solution of this embodiment, the thickness of the compressive stress dielectric layer is 400 nm, and the stress value is 1.3 GPa.
[0115] As a preferred solution of this embodiment, the thickness of the tensile stress dielectric layer is 400 nm, and the stress value is 1.3 GPa.
[0116] As a preferred solution of this embodiment, the nitride epitaxial structure includes a buffer layer, a channel layer, a barrier layer, and a P-type nitride layer.
[0117] Example 11
[0118] A method for preparing a sapphire-based enhanced HEMT epitaxial wafer specifically includes the following steps:
[0119] 1) Prepare a nitride epitaxial structure on a sapphire substrate, etch the P-type nitride layer of the nitride epitaxial structure to form a first-level P-type nitride gate layer and a second-level P-type nitride gate layer; prepare a first-level gate metal on the first-level P-type nitride gate layer, and prepare a first-level gate metal on the second-level P-type nitride gate layer; the first-level P-type nitride gate layer and its surrounding area are defined as a first-level depletion region, and the second-level P-type nitride gate layer and its surrounding area are defined as a second-level depletion region;
[0120] 2) Deposit a compressive stress dielectric layer on the surface of the nitride epitaxial structure, and the compressive stress dielectric layer covers the depletion regions;
[0121] 3) Remove the compressive stress dielectric layer and the tensile stress dielectric layer covering the depletion regions;
[0122] 4) Deposit a tensile stress dielectric layer on the surface of the nitride epitaxial structure, and the tensile stress dielectric layer covers the compressive stress dielectric layer, the first-level depletion region, and the second-level depletion region; remove the tensile stress dielectric layer covering the compressive stress dielectric layer;
[0123] 5) Prepare a first-level source metal and a first-level drain metal in the depletion regions to form a sapphire-based enhanced HEMT epitaxial wafer.
[0124] As a preferred solution of this embodiment, the thickness of the compressive stress dielectric layer is 40 nm, and the stress value is 280 MPa.
[0125] As a preferred solution of this embodiment, the thickness of the tensile stress dielectric layer is 800 nm, and the stress value is 2.5 GPa.
[0126] As a preferred solution of this embodiment, the nitride epitaxial structure includes a buffer layer, a channel layer, a barrier layer, and a P-type nitride layer.
[0127] Example 12
[0128] A method for preparing a sapphire-based enhanced HEMT epitaxial wafer specifically includes the following steps:
[0129] 1) Prepare a nitride epitaxial structure on a sapphire substrate, etch the P-type nitride layer of the nitride epitaxial structure to form a first-level P-type nitride gate layer and a second-level P-type nitride gate layer; prepare a first-level gate metal on the first-level P-type nitride gate layer and a first-level gate metal on the second-level P-type nitride gate layer; the first-level P-type nitride gate layer and its surrounding area are defined as a first-level depletion region, and the second-level P-type nitride gate layer and its surrounding area are defined as a second-level depletion region;
[0130] 2) Deposit a compressive stress dielectric layer on the surface of the nitride epitaxial structure, and the compressive stress dielectric layer covers the depletion regions;
[0131] 3) Remove the compressive stress dielectric layer and the tensile stress dielectric layer covering the depletion regions;
[0132] 4) Deposit a tensile stress dielectric layer on the surface of the nitride epitaxial structure, and the tensile stress dielectric layer covers the compressive stress dielectric layer, the first-level depletion region, and the second-level depletion region; remove the tensile stress dielectric layer covering the compressive stress dielectric layer;
[0133] 5) Prepare a first-level source metal and a first-level drain metal in the depletion regions to form a sapphire-based enhancement-mode HEMT epitaxial wafer.
[0134] As a preferred solution of this embodiment, the thickness of the compressive stress dielectric layer is 800 nm and the stress value is 2.5 GPa.
[0135] As a preferred solution of this embodiment, the thickness of the tensile stress dielectric layer is 40 nm and the stress value is 280 MPa.
[0136] As a preferred solution of this embodiment, the nitride epitaxial structure includes a buffer layer, a channel layer, a barrier layer, and a P-type nitride layer.
[0137] Example 13
[0138] A method for preparing a sapphire-based enhancement-mode HEMT epitaxial wafer specifically includes the following steps:
[0139] 1) Prepare a nitride epitaxial structure on a sapphire substrate, etch the P-type nitride layer of the nitride epitaxial structure to form a first-level P-type nitride gate layer and a second-level P-type nitride gate layer; prepare a first-level gate metal on the first-level P-type nitride gate layer and a first-level gate metal on the second-level P-type nitride gate layer; the first-level P-type nitride gate layer and its surrounding area are defined as a first-level depletion region, and the second-level P-type nitride gate layer and its surrounding area are defined as a second-level depletion region;
[0140] 2) Deposit a compressive stress dielectric layer on the surface of the nitride epitaxial structure, and the compressive stress dielectric layer covers the depletion regions;
[0141] 3) Remove the compressive stress dielectric layer and the tensile stress dielectric layer covering the depletion region;
[0142] 4) Deposit a tensile stress dielectric layer on the surface of the nitride epitaxial structure. The tensile stress dielectric layer covers the compressive stress dielectric layer, the first-level depletion region, and the second-level depletion region; remove the tensile stress dielectric layer covering the compressive stress dielectric layer;
[0143] 5) Prepare the first-level source metal and the first-level drain metal in the depletion region to form a sapphire-based enhanced HEMT epitaxial wafer.
[0144] As a preferred solution of this embodiment, the thickness of the compressive stress dielectric layer is 40 nm, and the stress value is 280 MPa.
[0145] As a preferred solution of this embodiment, the thickness of the tensile stress dielectric layer is 400 nm, and the stress value is 1.3 GPa.
[0146] As a preferred solution of this embodiment, the nitride epitaxial structure includes a buffer layer, a channel layer, a barrier layer, and a P-type nitride layer.
[0147] Example 14
[0148] A method for preparing a sapphire-based enhanced HEMT epitaxial wafer, specifically including the following steps:
[0149] 1) Prepare a nitride epitaxial structure on a sapphire substrate, etch the P-type nitride layer of the nitride epitaxial structure to form a first-level P-type nitride gate layer and a second-level P-type nitride gate layer; prepare a first-level gate metal on the first-level P-type nitride gate layer, and prepare a first-level gate metal on the second-level P-type nitride gate layer; the first-level P-type nitride gate layer and its surrounding area are defined as the first-level depletion region, and the second-level P-type nitride gate layer and its surrounding area are defined as the second-level depletion region;
[0150] 2) Deposit a compressive stress dielectric layer on the surface of the nitride epitaxial structure. The compressive stress dielectric layer covers the depletion regions;
[0151] 3) Remove the compressive stress dielectric layer and the tensile stress dielectric layer covering the depletion region;
[0152] 4) Deposit a tensile stress dielectric layer on the surface of the nitride epitaxial structure. The tensile stress dielectric layer covers the compressive stress dielectric layer, the first-level depletion region, and the second-level depletion region; remove the tensile stress dielectric layer covering the compressive stress dielectric layer;
[0153] 5) Prepare the first-level source metal and the first-level drain metal in the depletion region to form a sapphire-based enhanced HEMT epitaxial wafer.
[0154] As a preferred solution of this embodiment, the thickness of the compressive stress dielectric layer is 800 nm, and the stress value is 2.4 GPa.
[0155] As a preferred solution of this embodiment, the thickness of the tensile stress medium layer is 420 nm, and the stress value is 1.3 GPa.
[0156] As a preferred solution of this embodiment, the nitride epitaxial structure includes a buffer layer, a channel layer, a barrier layer, and a P-type nitride layer.
[0157] As described above, the above are only the preferred specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, according to the technical solution and inventive concept of the present invention, makes equivalent substitutions or changes, and should be covered within the protection scope of the present invention.
Claims
1. A method for preparing a sapphire-based enhanced HEMT epitaxial wafer, characterized in that, Specifically, it includes the following steps: 1) Prepare a nitride epitaxial structure on a sapphire substrate, etch the P-type nitride layer of the nitride epitaxial structure to form a first-level P-type nitride gate layer and a second-level P-type nitride gate layer; prepare a first-level gate metal on the first-level P-type nitride gate layer and a first-level gate metal on the second-level P-type nitride gate layer; the first-level P-type nitride gate layer and its surrounding area are defined as a first-level depletion region, and the second-level P-type nitride gate layer and its surrounding area are defined as a second-level depletion region; 2) Deposit a compressive stress dielectric layer on the surface of the nitride epitaxial structure, and the compressive stress dielectric layer covers the depletion region and the depletion region; 3) Remove the compressive stress dielectric layer and the tensile stress dielectric layer covering the depletion region; 4) Deposit a tensile stress dielectric layer on the surface of the nitride epitaxial structure, and the tensile stress dielectric layer covers the compressive stress dielectric layer, the first-level depletion region, and the second-level depletion region; Remove the tensile stress dielectric layer covering the compressive stress dielectric layer; 5) Prepare a first-level source metal and a first-level drain metal in the depletion region to form a sapphire-based enhancement-mode HEMT epitaxial wafer.
2. The preparation method of the sapphire-based enhanced HEMT epitaxial wafer according to claim 1, wherein: The thickness of the compressive stress dielectric layer is 35 nm to 900 nm, and the stress value is -270 MPa to 2.6 GPa.
3. The preparation method of the sapphire-based enhanced HEMT epitaxial wafer according to claim 1, characterized in that: The thickness of the tensile stress dielectric layer is 35 nm to 900 nm, and the stress value is 270 MPa to 2.6 GPa.
4. The preparation method of the sapphire-based enhanced HEMT epitaxial wafer according to claim 1, characterized in that: The nitride epitaxial structure includes a buffer layer, a channel layer, a barrier layer, and a P-type nitride layer.