Transistor structure and manufacturing method thereof

Abstract

The invention provides a transistor structure and a manufacturing method thereof. The transistor structure comprises a substrate, and a heterojunction film layer, a semiconductor gate layer, an etching stop layer, an alloy layer and a metal gate layer which are arranged on the substrate, the alloy layer is located between the semiconductor gate layer and the metal gate layer; the orthographic projection of the semiconductor gate layer on the substrate is at least partially overlapped with the orthographic projection of the metal gate layer on the substrate. Therefore, the etching stop layer not only can protect the surface of the semiconductor gate layer in the manufacturing process of the transistor structure, but also can directly react with the metal layer to be converted into the alloy layer without being removed, so that the problem that the etching depth is difficult to control is effectively solved, the technological process is simplified, and the production efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a transistor structure and a method for manufacturing the same. Background Art

[0002] High Electron Mobility Transistor (HEMT) is a field effect transistor based on a heterojunction structure, which is widely used in high-frequency and high-power electronic devices. Traditional HEMT is usually depletion mode (D-Mode), that is, there is a two-dimensional electron gas (2DEG) in the channel at zero gate voltage, and the device is in the on state. However, in many application scenarios, the enhancement mode (E-Mode) HEMT is more ideal because it is in the off state at zero gate voltage, which can improve the safety and energy efficiency of the circuit.

[0003] In order to realize E-Mode HEMT, it is usually necessary to introduce a P-type gallium nitride (P-GaN) layer in the gate region. P-GaN forms a space charge region with the GaN (Gallium Nitride) below, depleting the 2DEG formed by spontaneous polarization and piezoelectric polarization at the interface of GaN and AlGaN (Aluminum Gallium Nitride), so that the device is in the off state at zero gate voltage. However, the existing process faces the following technical problems in the preparation of E-Mode HEMT:

[0004] Limitations of dry etching: Although dry etching (such as reactive ion etching) can achieve a higher etching rate, its etching accuracy is low and it is easy to cause excessive etching of the P-GaN layer (P-GaN loss), affecting device performance.

[0005] Disadvantages of wet etching: Although wet etching has high selectivity for materials, the etching speed is difficult to control accurately, which can easily lead to uneven etching areas and affect the reliability and consistency of the device.

[0006] Therefore, how to improve etching accuracy and reduce P-GaN loss has become a technical problem that needs to be solved urgently in the preparation of E-Mode HEMT. Summary of the invention

[0007] The purpose of the present application is to provide a transistor structure and a method for manufacturing the same, so as to improve etching accuracy and reduce P-GaN loss in the preparation of E-Mode HEMT.

[0008] To achieve the above object, the present application provides the following technical solutions:

[0009] In a first aspect, the present application provides a transistor structure, and the transistor structure includes:

[0010] a substrate, and a hetero-conjunctive film layer, a semiconductor gate layer, an etch stop layer, an alloy layer, and a metal gate layer disposed on the substrate;

[0011] The alloy layer is located between the semiconductor gate layer and the metal gate layer;

[0012] The orthographic projection of the semiconductor gate layer on the substrate at least partially overlaps with the orthographic projection of the metal gate layer on the substrate.

[0013] Optionally, the etch stop layer includes: aluminum nitride, and the alloy layer includes titanium-aluminum alloy.

[0014] Optionally, during the fabrication process of the transistor structure, the alloy layer is formed by the reaction of a partial etch stop layer and a metal layer located on the side of the partial etch stop layer away from the substrate, and the etch stop layer is used to protect the semiconductor gate layer during the fabrication process of the transistor structure.

[0015] Optionally, if both the metal layer and the partial etch stop layer do not completely react, the alloy layer is located between the partial etch stop layer and the metal layer; the orthographic projection of the etch stop layer on the substrate at least partially overlaps with the orthographic projection of the semiconductor gate layer on the substrate; the orthographic projection of the metal layer on the substrate at least partially overlaps with the orthographic projection of the semiconductor gate layer on the substrate;

[0016] If both the metal layer and the partial etch stop layer completely react, the alloy layer is located between the semiconductor gate layer and the metal gate layer, and the orthographic projection of the etch stop layer on the substrate does not overlap with the orthographic projection of the semiconductor gate layer on the substrate at all;

[0017] If the metal layer completely reacts and the partial etch stop layer does not completely react, the alloy layer is located between the partial etch stop layer and the metal gate layer; the orthographic projection of the etch stop layer on the substrate at least partially overlaps with the orthographic projection of the semiconductor gate layer on the substrate;

[0018] If the metal layer does not react completely and the partial etch stop layer reacts completely, the alloy layer is located between the semiconductor gate layer and the metal layer; the orthographic projection of the etch stop layer on the substrate does not overlap with the orthographic projection of the semiconductor gate layer on the substrate at all; the orthographic projection of the metal layer on the substrate overlaps with the orthographic projection of the semiconductor gate layer on the substrate at least partially.

[0019] Optionally, the material of the metal layer includes titanium metal.

[0020] Optionally, the semiconductor gate layer includes a P-type group III nitride layer.

[0021] In a second aspect, the present invention provides a method for manufacturing a transistor structure, and the manufacturing method includes:

[0022] Providing a substrate;

[0023] Fabricating a heteroepitaxial film layer on the substrate;

[0024] Forming a semiconductor gate layer pattern on the heteroepitaxial film layer;

[0025] Fabricating an etch stop layer on the semiconductor gate layer pattern; the orthographic projection of the semiconductor gate layer pattern on the substrate is located within the orthographic projection area of the etch stop layer on the substrate;

[0026] Forming a metal layer pattern on a part of the etch stop layer; the part of the etch stop layer reacts with the metal layer pattern to form an alloy layer pattern;

[0027] The orthographic projection of the metal layer pattern on the substrate is located within the orthographic projection area of the semiconductor gate layer pattern on the substrate; the orthographic projection of the metal layer pattern on the substrate overlaps with the orthographic projection of the metal gate layer pattern on the substrate at least partially;

[0028] The etch stop layer is used to protect the semiconductor gate layer pattern during the manufacturing process of the transistor structure; the orthographic projection of the semiconductor gate layer pattern on the substrate overlaps with the orthographic projection of the metal gate layer pattern on the substrate at least partially.

[0029] Optionally, the reaction of the part of the etch stop layer and the metal layer pattern to form an alloy layer includes: the part of the etch stop layer and the metal layer pattern react under preset conditions to generate the alloy layer, and the alloy layer is used to reduce the contact resistance between the metal gate layer pattern and the semiconductor gate layer pattern;

[0030] Among them, the preset conditions are: high-temperature conditions and inert gas conditions, and the reaction is a thermal annealing reaction.

[0031] Optionally, the temperature of the thermal annealing reaction is 875 °C to 900 °C.

[0032] Optionally, the material of the metal layer pattern is titanium metal, the material of the etch stop layer is aluminum nitride, and the material of the alloy layer is: titanium-aluminum alloy.

[0033] Thirdly, the present invention provides a manufacturing method of a transistor structure, and the method includes:

[0034] Providing a substrate;

[0035] Epitaxially growing a hetero-junction film layer and a semiconductor gate layer on the substrate in sequence;

[0036] Removing part of the semiconductor gate layer through a dry or wet etching process;

[0037] Depositing an etch stop layer on the surface of the etched semiconductor gate layer;

[0038] Depositing a passivation layer on the etch stop layer;

[0039] Etching the passivation layer to expose the etch stop layer below the passivation layer;

[0040] Depositing a metal layer and a metal gate layer in sequence on the passivation layer and the exposed etch stop layer;

[0041] Under high-temperature conditions and inert gas conditions, performing a thermal annealing treatment, wherein the thermal annealing treatment is: the metal layer and the exposed etch stop layer react to generate an alloy layer;

[0042] Depositing a passivation layer again on the annealed transistor structure;

[0043] Determining a source region and a drain region, opening holes and depositing ohmic metal in the source region and the drain region through a lithography process, and etching the ohmic metal to determine the metal shapes of the source and the drain;

[0044] Depositing a passivation layer on the current transistor structure and leading out electrodes through a punching process.

[0045] Thus, the etch stop layer can not only protect the surface of the semiconductor gate layer during the manufacturing process of the transistor structure, but also directly react with the metal layer to be transformed into an alloy layer without removal, thereby effectively solving the problem of difficult control of etch depth while simplifying the process flow and improving production efficiency. Description of the Drawings

[0046] When combined with the attachedFigure 1 When reading the following detailed description, various aspects of the present application can be easily understood based on the following detailed description. It is considered that various features may not be drawn to scale. In fact, for the sake of clarity in discussion, the sizes of various features can be arbitrarily increased or decreased.

[0047] Figure 1 is a schematic diagram of a transistor structure provided according to an embodiment of the present application;

[0048] Figure 2 is a schematic diagram of a transistor structure provided according to an embodiment of the present application;

[0049] Figure 3 is a schematic diagram of a transistor structure provided according to an embodiment of the present application;

[0050] Figure 4 is a schematic diagram of a transistor structure provided according to an embodiment of the present application;

[0051] Figure 5 is a flowchart of a method for manufacturing a transistor structure provided according to an embodiment of the present application;

[0052] Figure 6 is a schematic diagram of a hierarchical structure during the manufacturing process of a transistor structure provided according to an embodiment of the present application;

[0053] Throughout the drawings and the detailed description, common reference numerals are used to indicate the same or similar components. The present application will become more apparent from the following detailed description in conjunction with the drawings. Detailed Description of the Embodiment

[0054] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are only examples and are not intended to be restrictive. In the present application, a reference to forming or disposing a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed or disposed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, the present application may repeat reference numerals and / or letters in various instances. This repetition is for the purpose of simplicity and clarity and is not used to limit the relationship between the various embodiments and / or configurations discussed.

[0055] Figure 1 shows a transistor structure, as Figure 1 and Figure 6 shown, the transistor structure includes:

[0056] A substrate 1, and a heterojunction film layer 2, a semiconductor gate layer 3, an etch stop layer 4, an alloy layer 5, and a metal gate layer 6 disposed on the substrate 1;

[0057] The alloy layer 5 is located between the semiconductor gate layer 3 and the metal gate layer 6; the orthographic projection of the semiconductor gate layer 3 on the substrate 1 and the orthographic projection of the metal gate layer 6 on the substrate 1 at least partially overlap.

[0058] Among them, the substrate 1 is the basic part of the transistor structure, and the manufacturing material of the substrate 1 may include but is not limited to silicon (Si), doped Si, silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs), or other semiconductor materials. The substrate 1 may include but is not limited to sapphire, silicon on insulator (SOI), or other suitable materials. The substrate 1 is the foundation of the semiconductor device, which provides a stable platform for constructing other parts of the device.

[0059] The heterojunction film layer 2 is disposed on the substrate 1 along the direction away from the substrate 1. There is a heterojunction in the heterojunction film layer 2. A heterojunction refers to a junction formed by the contact of two different semiconductor materials, which has different bandgap widths. This structure is very important for regulating current flow and electronic properties.

[0060] Furthermore, the heterojunction film layer 2 may include: a first nitride semiconductor layer and a second nitride semiconductor layer. The first nitride semiconductor layer may include a III-V group layer. The first nitride semiconductor layer may include but is not limited to group III nitrides, such as the compound In a Al b Ga 1-a-b N, where a + b ≦ 1. The group III nitride further includes but is not limited to, for example, the compound Al a Ga (1-a)N, where a ≦ 1. The first nitride semiconductor layer may include a gallium nitride (GaN) layer. The bandgap of GaN is about 3.4 eV. The second nitride semiconductor layer may be disposed on the first nitride semiconductor layer, and its bandgap is greater than that of the first nitride semiconductor layer. The second nitride semiconductor layer may include a group III-V layer. The second nitride semiconductor layer may include, but is not limited to, group III nitrides, such as the compound InaAlbGa1-a-bN, where a + b ≦ 1. The group III nitride may further include, but is not limited to, for example, the compound AlaGa(1-a)N, where a ≦ 1. The bandgap of the second nitride semiconductor layer may be greater than that of the first nitride semiconductor layer. The second nitride semiconductor layer may include an aluminum gallium nitride (AlGaN) layer. The bandgap of AlGaN is about 4.0 eV. A heterojunction may be formed between the second nitride semiconductor layer and the first nitride semiconductor layer, and the polarization of the heterojunction forms a two-dimensional electron gas region in the first nitride semiconductor layer.

[0061] The semiconductor gate layer 3 is located above the heterojunction film layer 2 and is a key functional layer of the gate region. The material of the semiconductor gate layer 3 is usually a p-type group III nitride layer, such as P-GaN or P-AlGaN, etc. The semiconductor gate layer 3 forms a space charge region with the first nitride semiconductor layer (such as GaN) in the underlying heterojunction film layer 2, depleting the 2DEG and realizing the characteristics of E-Mode, that is, when the gate voltage is zero, the device is in the off state; when the positive gate voltage is applied, the 2DEG is restored and the device conducts.

[0062] The etch stop layer 4 is used to protect the semiconductor gate layer 3 during the fabrication process of the transistor structure.

[0063] It should be noted that the etch stop layer 4 is located above the semiconductor gate layer 3 and directly covers the semiconductor gate layer 3. It is a key protective layer for the semiconductor gate layer 3. The etch stop layer 4 is used to protect the underlying semiconductor gate layer 3 during the fabrication process of the transistor structure (especially during the etching process) to avoid over-etching and causing loss of the semiconductor gate layer 3. The material of the etch stop layer 4 is usually AlN (aluminum nitride).

[0064] Specifically, when selecting the material of the etch stop layer 4, its selectivity to the etching process and its compatibility with the underlying material are usually considered. During the etching process, the etch stop layer 4 is used to protect the underlying semiconductor gate layer 3 and other important structures from being damaged by the etching liquid or gas. By selecting the appropriate material and thickness, the etch stop layer 4 can effectively control the etching depth, ensure that the material is not over-removed during the manufacturing process, and the etch stop layer 4 can provide a stable interface, which is helpful for the deposition and processing of subsequent layers.

[0065] The etch stop layer 4 is typically deposited on the semiconductor gate layer 3 by methods such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). Moreover, the thickness of the etch stop layer 4 needs to be precisely controlled to ensure its effective protection during the etching process.

[0066] During the fabrication of the transistor structure, the alloy layer 5 is formed by the reaction of a part of the etch stop layer 4 and the metal layer 11 (as Figure 6 shown) located on one side of the part of the etch stop layer 4 away from the substrate 1.

[0067] The alloy layer 5 is located between the semiconductor gate layer 3 and the metal gate layer 6. During the fabrication of the transistor structure, the alloy layer 5 is formed by the reaction of a part of the etch stop layer 4 and the metal layer 11 located on one side of the part of the etch stop layer 4 away from the substrate 1.

[0068] Among them, the alloy layer 5 is formed by the reaction of a part of the etch stop layer 4 and the metal layer 11 located on one side of the part of the etch stop layer 4 away from the substrate 1. The common material of the metal layer 11 is Ti (titanium) metal. Metals such as Ta (tantalum), Ni (nickel), and Co (cobalt) with high reactivity, easy diffusibility, and capable of reacting with the etch stop layer 4 can also be selected. Additionally, the metal layer 11 and its reaction product, that is, the alloy layer 5, need to have low resistance to reduce the contact resistance and provide good interface characteristics.

[0069] If the material of the metal layer 11 is Ti and the material of the etch stop layer 4 is AlN, during the high-temperature annealing process, the metal layer 11 reacts with the etch stop layer 4 to form a Ti-Al alloy, that is, the alloy layer 5. The alloy layer 5 can reduce the contact resistance between the metal gate layer 6 and the semiconductor gate layer 3 and improve the electrical performance of the device.

[0070] It should be noted that if both the metal layer 11 and a part of the etch stop layer 4 do not fully react, the alloy layer 5 is located between a part of the etch stop layer 4 and the metal layer 11; the orthographic projection of the etch stop layer 4 on the substrate 1 and the orthographic projection of the semiconductor gate layer 3 on the substrate 1 at least partially overlap; the orthographic projection of the metal layer 11 on the substrate 1 and the orthographic projection of the semiconductor gate layer 3 on the substrate 1 at least partially overlap, as Figure 2 and Figure 6 shown.

[0071] If both the metal layer 11 and a part of the etch stop layer 4 fully react, the alloy layer 5 is located between the semiconductor gate layer 3 and the metal gate layer 6, and the orthographic projection of the etch stop layer 4 on the substrate 1 and the orthographic projection of the semiconductor gate layer 3 on the substrate 1 do not overlap at all, as Figure 1 and Figure 6 shown.

[0072] If the metal layer 11 has completely reacted and part of the etch stop layer 4 has not completely reacted, the alloy layer 5 is located between the part of the etch stop layer 4 and the metal gate layer 6; the orthographic projection of the etch stop layer 4 on the substrate 1 and the orthographic projection of the semiconductor gate layer 3 on the substrate 1 at least partially overlap, as Figure 3 and Figure 6 shown.

[0073] If the metal layer 11 has not completely reacted and part of the etch stop layer 4 has completely reacted, the alloy layer 5 is located between the semiconductor gate layer 3 and the metal layer 11; the orthographic projection of the etch stop layer 4 on the substrate 1 and the orthographic projection of the semiconductor gate layer 3 on the substrate 1 do not overlap at all; the orthographic projection of the metal layer 11 on the substrate 1 and the orthographic projection of the semiconductor gate layer 3 on the substrate 1 at least partially overlap, as Figure 4 and Figure 6 shown.

[0074] That is to say, there are the above four situations, as shown in Figure 1 , 2 , 3, and 4 respectively. The reaction degree of the metal layer 11 and the etch stop layer 4 determines the position of the alloy layer 5 and the projection overlapping relationship.

[0075] The metal gate layer 6, as a gate electrode, is used to apply a voltage to control the 2DEG concentration in the channel, thereby controlling the switching state of the device. The material of the metal gate layer 6 can be pure metal or TiN (titanium nitride). TiN has good electrical conductivity and thermal stability and is suitable as a gate metal. And the orthographic projection of the metal gate layer 6 and the semiconductor gate layer 3 on the substrate 1 at least partially overlap to ensure that the gate electric field can effectively control the 2DEG concentration.

[0076] In a possible implementation, the material of the etch stop layer 4 is an insulating material (such as aluminum nitride), and the metal ions constituting the insulating material have easy diffusibility. The material of the metal layer 11 is a metal material (such as titanium metal), and the metal material has easy diffusibility.

[0077] It should be noted that the etch stop layer 4 is composed of an insulating material (such as aluminum nitride). This material not only has high etch selectivity and can effectively protect the underlying semiconductor gate layer 3 from over-etching, but also because its metal ions (such as aluminum ions) have easy diffusibility and can react with the upper metal layer 11 (such as titanium metal, Ti) during the high-temperature annealing process. The metal layer 11 is made of a metal material with easy diffusibility (such as titanium). This metal can rapidly diffuse at high temperatures and combine with the metal ions in the etch stop layer 4 to form a stable metal alloy (such as Ti-Al alloy). This alloy layer 5 not only optimizes the contact characteristics between the metal gate layer 6 and the semiconductor gate layer 3, reduces the contact resistance, but also improves the thermal stability and electrical performance of the device. Through this design, the synergistic effect of the etch stop layer 4 and the metal layer 11 ensures efficient control of the gate region and a significant improvement in device performance. Moreover, aluminum nitride and titanium metal are only for illustrative purposes. During the actual fabrication process of the transistor structure, an insulating material can be selected, and the metal ions of this insulating material have easy diffusibility to fabricate the etch stop layer 4, and a metal material with easy diffusibility can be selected to fabricate the metal layer 11.

[0078] In summary, the etch stop layer 4 can not only protect the surface of the semiconductor gate layer 3 during the fabrication process of the transistor structure, but also directly react with the metal layer 11 to be transformed into the alloy layer 5 without removal, thus effectively solving the problem of difficult control of etch depth while simplifying the process flow and improving production efficiency.

[0079] In a possible implementation, the transistor structure further includes: a first epitaxial passivation layer 7 and a second epitaxial passivation layer 8. The first epitaxial passivation layer 7 is disposed on the side of the etch stop layer 4 away from the substrate 1 and covers the etch stop layer 4. The second epitaxial passivation layer 8 is disposed on the side of the first epitaxial passivation layer 7 away from the substrate 1 and covers the first epitaxial passivation layer 7. The metal gate layer 6 is connected to the alloy layer 5 through vias in the first epitaxial passivation layer 7 and the second epitaxial passivation layer 8.

[0080] It should be noted that the material of the first epitaxial passivation layer 7 is usually an oxide layer (such as SiO2 or Al2O3). It is disposed on the side of the etch stop layer 4 away from the substrate 1 and covers the etch stop layer 4. It can protect the etch stop layer 4 from being damaged in subsequent processes, and can also serve as an insulating layer to isolate the etch stop layer 4 from the upper metal gate layer 6 to avoid short circuits.

[0081] Alternatively, the material of the first epitaxial passivation layer 7 can be TEOS (Tetraethyl Orthosilicate), which is a liquid silicon source precursor widely used in chemical vapor deposition (CVD) processes. By thermal decomposition, it generates silicon dioxide (SiO2) and can be used to deposit high-quality insulating layers (such as gate dielectrics, interlayer dielectrics, or passivation layers).

[0082] The material of the second epitaxial passivation layer 8 is usually an oxide layer (such as SiO2 or Si3N4). It is disposed on the side of the first epitaxial passivation layer 7 away from the substrate 1, covering the first epitaxial passivation layer 7, for further protecting the underlying etch stop layer 4 and the first epitaxial passivation layer 7, preventing physical or chemical damage during the process, and as an insulating layer, it can also isolate the metal gate layer 6 from other device regions to avoid electrical interference. Additionally, it can provide a flat surface for subsequent processes (such as lithography and etching), improving process accuracy.

[0083] It should be noted that vias can be opened in the first epitaxial passivation layer 7 and the second epitaxial passivation layer 8. The vias enable the metal gate layer 6 to penetrate through the first epitaxial passivation layer 7 and the second epitaxial passivation layer 8 and connect to the underlying alloy layer 5 (such as a Ti-Al alloy layer) to ensure that the gate voltage can be effectively transmitted to the metal layer 5, thereby controlling the 2DEG concentration in the channel.

[0084] In a possible implementation, as Figures 1 to 4 、 Figure 6 shown, a field plate 9, a source electrode 10, and a drain electrode 10 are also provided. Among them, the field plate 9 is a key electrode for controlling the current flow between the source electrode 10 and the drain electrode 10. By applying a voltage to the field plate 9, an electric field can be formed in the semiconductor material, thereby regulating the formation of the conductive channel. The source electrode 10 is the input end of the current, providing carriers (electrons or holes) for the drain electrode 10 to use. The drain electrode 10 is the output end of the current, receiving the carriers flowing out from the source electrode 10.

[0085] Thus, the etch stop layer 4 can not only protect the surface of the semiconductor gate layer 3 during the fabrication of the transistor structure but also directly react with the metal layer 11 to be transformed into the alloy layer 5 without the need for removal. Thereby, while effectively solving the problem of difficult control of the etch depth, the process flow is simplified and the production efficiency is improved.

[0086] The embodiment of the present application also provides a method for manufacturing a transistor structure, as Figure 5 shown, for manufacturing the transistor structure as Figures 1 to 4 shown. The manufacturing method includes:

[0087] Step S101: Provide a substrate.

[0088] Step S102: Fabricate a hetero-conjunctive film layer on the substrate

[0089] Step S103: Form a semiconductor gate layer pattern on the hetero-conjunctive film layer

[0090] Step S104: Fabricate an etch stop layer on the semiconductor gate layer pattern

[0091] Wherein, the orthographic projection of the semiconductor gate layer pattern on the substrate is located within the orthographic projection area of the etch stop layer on the substrate

[0092] Step S105: Form a metal layer pattern (as shown in 11 in Figure 6 ) on a part of the etch stop layer

[0093] Wherein, a part of the etch stop layer reacts with the metal layer pattern to form an alloy layer pattern; the orthographic projection of the metal layer pattern on the substrate is located within the orthographic projection area of the semiconductor gate layer pattern on the substrate; the orthographic projection of the metal layer pattern on the substrate overlaps at least partially with the orthographic projection of the metal gate layer pattern on the substrate; the etch stop layer is used to protect the semiconductor gate layer pattern during the fabrication process of the transistor structure; the orthographic projection of the semiconductor gate layer pattern on the substrate overlaps at least partially with the orthographic projection of the metal gate layer pattern on the substrate

[0094] It should be noted that during the manufacturing process, first, a substrate is provided as a basis, and then a hetero-conjunctive film layer is fabricated thereon to achieve the required electrical characteristics. Next, a pattern of the semiconductor gate layer is formed on the hetero-conjunctive film layer. To protect the semiconductor gate layer, an etch stop layer is then fabricated thereon to ensure that the semiconductor gate layer will not be damaged during the subsequent etching process. At this time, the orthographic projection of the semiconductor gate layer pattern on the substrate is completely located within the orthographic projection area of the etch stop layer, thus achieving effective protection. Specifically, during the process of opening the gate, etching and opening holes need to be performed on the first passivation layer and the second passivation layer. Without the etch stop layer, it is very easy to damage the semiconductor gate layer during the etching process, while the setting of the etch stop layer can avoid the loss of the semiconductor gate layer

[0095] On this basis, a pattern of the metal layer is further formed on a part of the etch stop layer. The reaction between this metal layer and the etch stop layer forms an alloy layer pattern, ensuring the reliability of the electrical connection. At the same time, the orthographic projection of the metal layer pattern on the substrate overlaps with the orthographic projection of the semiconductor gate layer pattern, ensuring effective contact between them. In addition, the orthographic projection of the metal layer also overlaps at least partially with the orthographic projection of the metal gate layer pattern, further enhancing the stability of the electrical connection. Through this series of steps, the integrity and performance of the transistor structure are ensured, and ultimately the efficient manufacturing of semiconductor devices is achieved

[0096] In a possible implementation, the reaction between a partial etch stop layer and a metal layer pattern to form an alloy layer includes: the partial etch stop layer and the metal layer pattern react under preset conditions to generate an alloy layer, and the alloy layer is used to reduce the contact resistance between the metal gate layer pattern and the semiconductor gate layer pattern; wherein, the preset conditions are: high temperature conditions and inert gas (such as nitrogen) conditions, and the reaction is a thermal annealing reaction. It should be noted that the high temperature condition is 875°C to 900°C.

[0097] In a possible implementation, the material of the etch stop layer is an insulating material, and the metal ions constituting the insulating material have easy diffusibility. The material of the metal layer pattern is a metal material, and the metal material has easy diffusibility. The material of the metal layer pattern is titanium metal, the material of the etch stop layer is aluminum nitride, and the material of the alloy layer is: titanium-aluminum alloy.

[0098] In summary, the etch stop layer can not only protect the surface of the semiconductor gate layer during the manufacturing process of the transistor structure, but also directly react with the metal layer to be converted into an alloy layer without removal, thereby effectively solving the problem of difficult control of the etch depth while simplifying the process flow and improving production efficiency.

[0099] This application also provides a method for manufacturing a transistor structure, and the method includes:

[0100] Providing a substrate;

[0101] Epitaxially growing a heteroepitaxial film layer and a semiconductor gate layer on the substrate in sequence;

[0102] Removing a part of the semiconductor gate layer through a dry or wet etching process;

[0103] Depositing an etch stop layer on the surface of the etched semiconductor gate layer;

[0104] Depositing a passivation layer on the etch stop layer;

[0105] Etching the passivation layer to expose the etch stop layer below the passivation layer;

[0106] Sequentially depositing a metal layer and a metal gate layer on the passivation layer and the exposed etch stop layer;

[0107] Performing a thermal annealing treatment under high temperature conditions and inert gas conditions, wherein the thermal annealing treatment is: the metal layer and the exposed etch stop layer react to generate an alloy layer;

[0108] Depositing a passivation layer again on the annealed transistor structure;

[0109] Determine the source region and the drain region, open holes in the source region and the drain region through a photolithography process and deposit ohmic metal, and etch the ohmic metal to determine the metal shapes of the source and the drain;

[0110] Deposit a passivation layer again on the current transistor structure, and lead out electrodes through a drilling process.

[0111] In an exemplary application scenario, the manufacturing method of the semiconductor gate layer can be generally summarized into the following steps:

[0112] 1. Grow an epitaxial layer, that is, grow a hetero-conjunctive film layer and a semiconductor gate layer on the substrate in sequence;

[0113] 2. Etch the semiconductor gate layer, that is, remove part of the semiconductor gate layer (P-GaN layer) through dry or wet etching to define the gate region;

[0114] 3. Deposit an etch stop layer (AlN layer). AlN has high etch selectivity, can protect the P-GaN layer in the subsequent etching process, and as an interface layer for the high-temperature annealing reaction, can help form an alloy layer;

[0115] 4. Deposit a passivation layer, deposit a passivation layer (such as SiO2 or Al2O3) above the AlN layer for protection and isolation;

[0116] 5. Gate opening (leaving the etch stop layer), remove the passivation layer through etching to expose the underlying AlN layer, but retain the AlN layer as an etch stop layer. The AlN layer protects the P-GaN layer from being over-etched and reduces the loss of P-GaN. In the existing solutions, directly etching to the P-GaN layer easily causes the loss of P-GaN, while the solution in this application improves the etching accuracy through the AlN layer, which avoids the loss of P-GaN;

[0117] 6. Deposit a diffusion metal Ti (metal layer), and then deposit a TiN metal (metal gate layer). The metal layer reacts with the etch stop layer during the subsequent high-temperature annealing to form a good ohmic contact, and the TiN layer, as the metal gate layer, can provide stable electrical properties. It should be noted that in the existing solutions, TiN is directly deposited without a metal layer, and the solution in this application optimizes the interface characteristics through the metal layer.

[0118] 7. Anneal at 875 °C to 900 °C under an N2 atmosphere by RTP, so that Ti reacts with AlN (Ti and AlN react at high temperature to form an alloy layer); Ti reacts with AlN to generate a Ti-Al alloy, improving the contact characteristics between the metal gate layer and the semiconductor gate layer. In addition, the high-temperature annealing can also repair the defects introduced during the etching process;

[0119] 8. Deposit a passivation layer, deposit a further passivation layer for protection and isolation;

[0120] 9. Lithography, opening holes, depositing ohmic metal, opening holes in the source and drain regions, and depositing ohmic contact metal;

[0121] 10. Etching the ohmic metal to define the metal shapes of the source and drain through an etching process;

[0122] 11. Depositing a passivation layer and then punching holes to lead out electrodes, depositing a passivation layer (such as Si3N4) on the device surface and leading out electrodes through punching holes.

[0123] In summary, the etch stop layer can not only protect the surface of the semiconductor gate layer during the fabrication process of the transistor structure, but also directly react with the metal layer to be transformed into an alloy layer without removal, thus effectively solving the problem of difficult control of the etching depth while simplifying the process flow and improving the production efficiency.

[0124] The embodiments of the present application have been discussed in detail above. However, it should be understood that the present application provides many applicable concepts that can be embodied in a variety of specific environments. The specific embodiments discussed are illustrative only and do not limit the scope of the present application.

[0125] Unless otherwise specified, spatial descriptions such as "on", "under", "upward", "left", "right", "downward", "top", "bottom", "vertical", "horizontal", "side", "above", "below", "upper", "above...", "below..." are with respect to the orientation indication shown in the drawings. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and the actual implementation of the structures described herein can be spatially arranged in any orientation or manner, provided that the advantages of the embodiments of the present application are not deviated by such arrangements.

[0126] As used herein, the term "vertical" is used to refer to the upward and downward directions, and the term "horizontal" refers to the direction transverse to the vertical direction.

[0127] As used herein, the terms "about," "substantially," "substantially," and "approximately" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the term can refer to instances where the event or circumstance occurs precisely as well as instances where it occurs very nearly. For example, when used in conjunction with a numerical value, the term can refer to a range of variation of less than or equal to ±10% of the stated value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first numerical value is within a range of variation of less than or equal to ±10% of a second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first numerical value can be considered "substantially" the same as or equal to the second numerical value. For example, "substantially" vertical can refer to an angular range of variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1%, or less than or equal to ±0.05°.

[0128] If the displacement between two surfaces does not exceed 5 μm, does not exceed 2 μm, does not exceed 1 μm, or does not exceed 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface does not exceed 5 μm, does not exceed 2 μm, does not exceed 1 μm, or does not exceed 0.5 μm, then the surface can be considered substantially flat.

[0129] As used herein, unless the context clearly dictates otherwise, the singular terms "a / an" and "the" can include plural referents.

[0130] As used herein, the terms "conductive," "electrically conductive," and "conductivity" refer to the ability to conduct an electric current. Conductive materials generally denote those materials that exhibit little or no opposition to the flow of an electric current. A measure of conductivity is Siemens per meter (S / m). Generally, a conductive material is a material having a conductivity greater than about 104 S / m (such as at least 105 S / m or at least 106 S / m). The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0131] In addition, quantities, ratios, and other numerical values are sometimes presented in a range format in this document. It should be understood that such range formats are used for convenience and brevity and should be interpreted flexibly, including not only the explicitly specified values as the limits of the range, but also all individual values or sub-ranges subsumed within that range as if each value and sub-range were explicitly specified.

[0132] Although the present application has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not restrictive. Those skilled in the art will understand that various changes and substitutions of equivalents can be made without departing from the true spirit and scope of the present application as defined by the appended claims. The drawings may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the process reproductions and the actual equipment in the present application. There may be other embodiments of the present application that are not specifically described. The present specification and the drawings should be regarded as illustrative rather than restrictive. Modifications can be made to adapt a particular situation, material, composition of matter, method, or process to the objectives, spirit, and scope of the present application. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations can be combined, subdivided, or reordered without departing from the teachings of the present application to form equivalent methods. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present application.

Claims

1. A transistor structure, characterized in that, The transistor structure includes: a substrate, and a heteroepitaxial film layer, a semiconductor gate layer, an etch stop layer, an alloy layer, and a metal gate layer disposed on the substrate; the alloy layer is located between the semiconductor gate layer and the metal gate layer; the orthographic projection of the semiconductor gate layer on the substrate at least partially overlaps with the orthographic projection of the metal gate layer on the substrate.

2. The transistor structure according to claim 1, wherein The etch stop layer includes aluminum nitride, and the alloy layer includes a titanium-aluminum alloy.

3. The transistor structure according to claim 1, characterized in that, During the fabrication process of the transistor structure, the alloy layer is formed by the reaction of a partial etch stop layer and a metal layer located on the side of the partial etch stop layer away from the substrate, and the etch stop layer is used to protect the semiconductor gate layer during the fabrication process of the transistor structure.

4. The transistor structure according to claim 3, wherein if both the metal layer and the partial etch stop layer do not completely react, the alloy layer is located between the partial etch stop layer and the metal layer; the orthographic projection of the etch stop layer on the substrate at least partially overlaps with the orthographic projection of the semiconductor gate layer on the substrate; the orthographic projection of the metal layer on the substrate at least partially overlaps with the orthographic projection of the semiconductor gate layer on the substrate; if both the metal layer and the partial etch stop layer completely react, the alloy layer is located between the semiconductor gate layer and the metal gate layer, and the orthographic projection of the etch stop layer on the substrate does not overlap with the orthographic projection of the semiconductor gate layer on the substrate at all; if the metal layer completely reacts and the partial etch stop layer does not completely react, the alloy layer is located between the partial etch stop layer and the metal gate layer; the orthographic projection of the etch stop layer on the substrate at least partially overlaps with the orthographic projection of the semiconductor gate layer on the substrate; if the metal layer does not completely react and the partial etch stop layer completely reacts, the alloy layer is located between the semiconductor gate layer and the metal layer; the orthographic projection of the etch stop layer on the substrate does not overlap with the orthographic projection of the semiconductor gate layer on the substrate at all; the orthographic projection of the metal layer on the substrate at least partially overlaps with the orthographic projection of the semiconductor gate layer on the substrate.

5. The transistor structure according to claim 3, wherein The material of the metal layer includes titanium metal.

6. The transistor structure according to claim 1, wherein, The semiconductor gate layer includes a P-type group III nitride layer.

7. A manufacturing method of a transistor structure, characterized in that, The manufacturing method includes: providing a substrate; fabricating a heteroepitaxial film layer on the substrate; forming a semiconductor gate layer pattern on the heteroepitaxial film layer; fabricating an etch stop layer on the semiconductor gate layer pattern; the orthographic projection of the semiconductor gate layer pattern on the substrate is located within the orthographic projection area of the etch stop layer on the substrate; forming a metal layer pattern on a part of the etch stop layer; the part of the etch stop layer reacts with the metal layer pattern to form an alloy layer pattern; The orthographic projection of the metal layer pattern on the substrate is located within the orthographic projection area of the semiconductor gate layer pattern on the substrate; the orthographic projection of the metal layer pattern on the substrate overlaps at least partially with the orthographic projection of the metal gate layer pattern on the substrate; The etch stop layer is used to protect the semiconductor gate layer pattern during the fabrication of the transistor structure; the orthographic projection of the semiconductor gate layer pattern on the substrate overlaps at least partially with the orthographic projection of the metal gate layer pattern on the substrate.

8. The manufacturing method according to claim 7, wherein, The reaction of the partial etch stop layer and the metal layer pattern to form an alloy layer includes: the partial etch stop layer and the metal layer pattern react under preset conditions to generate the alloy layer, and the alloy layer is used to reduce the contact resistance between the metal gate layer pattern and the semiconductor gate layer pattern; Wherein, the preset conditions are: high temperature conditions and inert gas conditions, and the reaction is a thermal annealing reaction.

9. The method according to claim 8, wherein The temperature of the thermal annealing reaction is 875 °C to 900 °C.

10. The method according to any one of claims 7 to 9, wherein, The material of the metal layer pattern is titanium metal, the material of the etch stop layer is aluminum nitride, and the material of the alloy layer is: titanium-aluminum alloy.

11. A manufacturing method of a transistor structure, characterized in that, The method includes: Providing a substrate; Epitaxially growing a heteroepitaxial film layer and a semiconductor gate layer on the substrate in sequence; Removing a part of the semiconductor gate layer by a dry or wet etching process; Depositing an etch stop layer on the surface of the etched semiconductor gate layer; Depositing a passivation layer on the etch stop layer; Etching the passivation layer to expose the etch stop layer below the passivation layer; Sequentially depositing a metal layer and a metal gate layer on the passivation layer and the exposed etch stop layer; Performing a thermal annealing treatment under high temperature conditions and inert gas conditions, wherein the thermal annealing treatment is: the metal layer and the exposed etch stop layer react to generate an alloy layer; Depositing a passivation layer again on the annealed transistor structure; Determining the source region and the drain region, opening holes and depositing ohmic metal in the source region and the drain region by a photolithography process, and etching the ohmic metal to determine the metal shapes of the source and the drain; Depositing a passivation layer again on the current transistor structure, and leading out electrodes by a punching process.

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