Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes: a substrate; a wall structure on the substrate, extending in a first direction, and including a first side surface and a second side surface; a first lower active pattern on the first side surface and including a first lower bridge pattern spaced apart from the substrate; a first upper active pattern on the first side surface and including a first upper bridge pattern spaced farther from the substrate than the first lower active pattern; a first gate structure on the first side surface and intersecting the first lower active pattern and the first upper active pattern; a second lower active pattern on the second side surface and including a second lower bridge pattern spaced apart from the substrate; a second upper active pattern on the second side surface and including a second upper bridge pattern spaced farther from the substrate than the second lower active pattern; and a second gate structure on the second side surface and intersecting the second lower active pattern and the second upper active pattern, a width of the wall structure in the second direction increasing as extending away from the substrate.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0006265, filed with the Korean Intellectual Property Office on January 15, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device. More particularly, the present disclosure relates to a semiconductor device including stacked multi-gate transistors and a method of manufacturing a semiconductor device. Background Art

[0003] One of the scaling schemes for increasing the integration density of integrated circuit devices includes multi-gate transistors, in which a fin-shaped or nanowire-shaped silicon body is formed on a substrate and a gate is formed on the surface of the silicon body.

[0004] Since such multi-gate transistors use a three-dimensional channel, they are easily scaled. In addition, the current control ability of the multi-gate transistors can be improved without increasing the gate length of the multi-gate transistors. Further, the multi-gate transistors can effectively suppress the short-channel effect (SCE) in which the potential of the channel region is affected by the drain voltage. Summary of the Invention

[0005] One advantage that can be achieved through the embodiments described in the present disclosure is that the semiconductor device can have improved performance.

[0006] Another advantage that can be achieved through the embodiments described in the present disclosure is improved performance in a method of manufacturing a semiconductor device.

[0007] The advantages according to the present disclosure are not limited to the above advantages. Other objects and advantages according to the present disclosure not mentioned can be understood based on the following description and can be more clearly understood based on the embodiments according to the present disclosure. Further, it will be readily understood that the objects and advantages according to the present disclosure can be achieved by using the devices shown in the claims and their combinations.

[0008] According to one aspect of the present disclosure, a semiconductor device includes: a substrate; a wall structure disposed on the substrate and extending in a first direction, wherein the wall structure includes a first side surface and a second side surface opposite the first side surface in a second direction intersecting the first direction; a first lower active pattern disposed on the first side surface and including at least one first lower bridge pattern spaced apart from the substrate; a first upper active pattern disposed on the first side surface and including at least one first upper bridge pattern spaced farther from the substrate than the first lower active pattern; a first gate structure disposed on the first side surface and intersecting the first lower active pattern and the first upper active pattern; a second lower active pattern disposed on the second side surface and including at least one second lower bridge pattern spaced apart from the substrate; a second upper active pattern disposed on the second side surface and including at least one second upper bridge pattern spaced farther from the substrate than the second lower active pattern; and a second gate structure disposed on the second side surface and intersecting the second lower active pattern and the second upper active pattern, wherein a width of the wall structure in the second direction increases as the wall structure extends away from the substrate.

[0009] According to one aspect of the present disclosure, a semiconductor device includes: a substrate; a wall structure disposed on the substrate and extending in a first direction, wherein the wall structure includes a first side surface and a second side surface opposite the first side surface in a second direction intersecting the first direction; a first lower active pattern disposed on the first side surface and including at least one first lower bridge pattern spaced apart from the substrate; a first upper active pattern disposed on the first side surface and including at least one first upper bridge pattern spaced farther from the substrate than the first lower active pattern; a first gate structure disposed on the first side surface and intersecting the first lower active pattern and the first upper active pattern; a second lower active pattern disposed on the second side surface and including at least one second lower bridge pattern spaced apart from the substrate; a second upper active pattern disposed on the second side surface and including at least one second upper bridge pattern spaced farther from the substrate than the second lower active pattern; and a second gate structure disposed on the second side surface and intersecting the second lower active pattern and the second upper active pattern, wherein a width of each of the at least one first upper bridge patterns in the second direction is less than a width of each of the at least one first lower bridge patterns in the second direction, wherein a third direction intersects the first direction and the second direction, and wherein a thickness of each of the at least one first upper bridge patterns in the third direction is greater than a thickness of each of the at least one first lower bridge patterns in the third direction.

[0010] According to one aspect of the present disclosure, a semiconductor device includes: a substrate; a wall structure disposed on the substrate and extending in a first direction, wherein the wall structure includes a first side surface and a second side surface opposite the first side surface in a second direction intersecting the first direction; a first lower active pattern disposed on the first side surface and including at least one first lower sheet-like pattern spaced apart from the substrate; a first upper active pattern disposed on the first side surface and including at least one first upper sheet-like pattern spaced farther from the substrate than the first lower active pattern; a first gate structure disposed on the first side surface and intersecting the first lower active pattern and the first upper active pattern; a second lower active pattern disposed on the second side surface and including at least one second lower sheet-like pattern spaced apart from the substrate; a second upper active pattern disposed on the second side surface and including at least one second upper sheet-like pattern spaced farther from the substrate than the second lower active pattern; and a second gate structure disposed on the second side surface and intersecting the second lower active pattern and the second upper active pattern, wherein a width of each sheet-like pattern in the at least one first upper sheet-like pattern in the second direction is less than a width of each sheet-like pattern in the at least one first lower sheet-like pattern in the second direction, and wherein a number of sheet-like patterns in the at least one first upper sheet-like pattern is greater than a number of sheet-like patterns in the at least one first lower sheet-like pattern.

[0011] According to one aspect of the present disclosure, a method of manufacturing a semiconductor device includes: providing a substrate including a first region and a second region, forming a first lower active pattern including at least one first lower bridge-like pattern spaced apart from the substrate on the first region, forming a first upper active pattern including at least one first upper bridge-like pattern spaced farther from the substrate than the first lower active pattern on the first region, forming a second lower active pattern including at least one second lower bridge-like pattern spaced apart from the substrate on the second region, forming a second upper active pattern including at least one second upper bridge-like pattern spaced farther from the substrate than the second lower active pattern on the second region, forming a wall structure between the first region and the second region to extend in a first direction to isolate the first lower active pattern and the second lower active pattern from each other and to isolate the first upper active pattern and the second upper active pattern from each other, forming a first gate structure on the first region to intersect the first lower active pattern and the first upper active pattern, and forming a second gate structure on the second region to intersect the second lower active pattern and the second upper active pattern, wherein a second direction intersects the first direction, and wherein a width of the wall structure in the second direction increases as the wall structure extends away from the substrate.

[0012] It should be noted that the effects of the present disclosure are not limited to the above, and other effects of the present disclosure will become clear from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects and features of the present disclosure will become more apparent by describing illustrative embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0014] Figure 1 is a layout diagram for describing a semiconductor device according to some embodiments.

[0015] Figure 2 is a cross-sectional view taken along line A-A of Figure 1 the

[0016] Figure 3 and Figure 4 are various enlarged views for describing region R1 of Figure 2 the

[0017] Figure 5 is a cross-sectional view taken along line B-B of Figure 1 the

[0018] Figure 6 is a cross-sectional view taken along line C-C of Figure 1 the

[0019] Figure 7 is a cross-sectional view for describing a semiconductor device according to some embodiments.

[0020] Figure 8 is a cross-sectional view for describing a semiconductor device according to some embodiments.

[0021] Figure 9 is for describing Figure 8 region R2 of the

[0022] Figure 10 is a cross-sectional view for describing a semiconductor device according to some embodiments.

[0023] Figure 11 is for describing Figure 10 region R3 of the

[0024] Figures 12 to 15 are various cross-sectional views for describing a semiconductor device according to some embodiments.

[0025] Figures 16 to 41 is a view of an intermediate structure corresponding to an intermediate step of a method for manufacturing a semiconductor device according to some embodiments.

[0026] Figure 42 is a view of an intermediate structure corresponding to an intermediate step of a method for manufacturing a semiconductor device according to some embodiments.

[0027] Figure 43It is a view of an intermediate structure corresponding to an intermediate step of a method for manufacturing a semiconductor device according to some embodiments. Detailed Description

[0028] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms associated with an item or step are not intended to exclude the presence of additional items or steps. It will also be understood that when the terms "comprises" and "comprising" are used in this specification, they specify the presence of the recited features, integers, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, operations, elements, components, and / or portions thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. When referring to "C to D", unless otherwise stated, this means including C and C to D including D.

[0029] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer, or portion described below may be referred to as the second element, component, region, layer, or portion in a later specification or claim.

[0030] In addition, terms such as "same", "equal", "planar", "coplanar", "parallel", and "perpendicular" as used herein encompass equivalency or approximate equivalency including variations that may occur, for example, due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning.

[0031] Hereinafter, with reference to Figures 1 to 15 , a semiconductor device according to some embodiments is described.

[0032] Figure 1 is a layout diagram for describing a semiconductor device according to some embodiments. Figure 2 is Figure 1 a cross-sectional view taken along line A-A. Figure 3 and Figure 4 are various enlarged views for describing Figure 2 the R1 region of Figure 5 is Figure 1 a cross-sectional view taken along line B-B. Figure 6 is Figure 1 a cross-sectional view taken along line C-C.

[0033] Referring to Figures 1 to 6 Figures 1 to 6 , a semiconductor device according to some embodiments may include a substrate 100, a first lower active pattern AP11, a first upper active pattern AP12, a second lower active pattern AP21, a second upper active pattern AP22, a wall structure 102, a first base insulating film 104, a second base insulating film 204, a first intermediate insulating film 105, a second intermediate insulating film 205, a field insulating film 106, a first gate structure GS1, a second gate structure GS2, a first gate spacer 140, a second gate spacer 240, a first lower source / drain pattern 160A, a first upper source / drain pattern 160B, a second lower source / drain pattern 260A, a second upper source / drain pattern 260B, an interlayer insulating film 180, a first gate contact CB1, and a second gate contact CB2.

[0034] The substrate 100 may be made of bulk silicon or silicon on insulator (SOI). Optionally, the substrate 100 may be embodied as a silicon substrate, or may be made of a material other than silicon (such as, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide), but is not limited thereto. Optionally, the substrate 100 may be composed of a base substrate and an epitaxial layer formed on the base substrate. For ease of description, an example in which the substrate 100 is embodied as a silicon substrate is described below.

[0035] The substrate 100 may include a first region I and a second region II. The first region I and the second region II may be isolated from each other by a wall structure 102 disposed therebetween. For example, the wall structure 102 may extend longitudinally in a first direction X parallel to the upper surface of the substrate 100. An item, layer, or a part of an item or layer described as extending "longitudinally" in a specific direction has a length in the specific direction and a width perpendicular to the specific direction, where the length is greater than the width. In addition, the wall structure 102 may include a first side surface 102a and a second side surface 102b that face each other in a second direction Y parallel to the upper surface of the substrate 100 and intersecting the first direction X. The first region I may be a region of the substrate 100 defined on the first side surface 102a of the wall structure 102. The second region II may be a region of the substrate 100 defined on the second side surface 102b of the wall structure 102. When viewed from the first direction X, the wall structure 102 may be, for example, a wall having two opposite side surfaces (such as, the first side surface 102a and the second side surface 102b), a top surface, and a bottom surface.

[0036] In some embodiments, transistors of different conductive types may be formed in the first region I and the second region II, respectively. In one example, the first region I may be an N-channel metal-oxide-semiconductor field-effect transistor (NFET) region, and the second region II may be a P-channel metal-oxide-semiconductor field-effect transistor (PFET) region. In another example, the first region I may be a PFET region while the second region II may be an NFET region. However, the technical concept of the present disclosure is not limited thereto, and transistors of the same conductive type may be formed in the first region I and the second region II.

[0037] A first lower active pattern AP11 may be formed on the first region I of the substrate 100. The first lower active pattern AP11 may extend in the first direction X. For example, it may be longer in the first direction X than in the second direction Y. The first lower active pattern AP11 may include at least one first lower bridge-like pattern (e.g., in one embodiment, bridge-like patterns 111 to 114) spaced apart from the substrate 100. For example, the at least one first lower bridge-like pattern (e.g., bridge-like patterns 111 to 114) may include a first lower sheet-like pattern 111, a second lower sheet-like pattern 112, a third lower sheet-like pattern 113, and a fourth lower sheet-like pattern 114 sequentially stacked on the upper surface of the substrate 100. The first lower sheet-like pattern 111, the second lower sheet-like pattern 112, the third lower sheet-like pattern 113, and the fourth lower sheet-like pattern 114 may be spaced apart from each other and may extend in the first direction X. The first lower active pattern AP11 may be configured as a channel region of a multi-bridge-channel multi-bridge-channel field-effect transistor (MBCFET). The number of sheet-like patterns included in the first lower active pattern AP11 is merely illustrative and is not limited to the number shown.

[0038] A first upper active pattern AP12 may be formed on the first lower active pattern AP11. The first upper active pattern AP12 may extend in the first direction X. The first upper active pattern AP12 may include at least one first upper bridge-like pattern (e.g., in one embodiment, bridge-like patterns 115 to 118), and may be spaced farther from the substrate than the first lower active pattern AP11. For example, the at least one first upper bridge-like pattern (e.g., bridge-like patterns 115 to 118) may include a first upper sheet-like pattern 115, a second upper sheet-like pattern 116, a third upper sheet-like pattern 117, and a fourth upper sheet-like pattern 118 sequentially stacked on the upper surface of the first lower active pattern AP11. The first upper sheet-like pattern 115, the second upper sheet-like pattern 116, the third upper sheet-like pattern 117, and the fourth upper sheet-like pattern 118 may be spaced apart from each other and may extend in the first direction X. The first upper active pattern AP12 may be configured as a channel region of a multi-bridge-channel MBCFET.

[0039] In some embodiments, the first fin pattern 110 may be formed between the substrate 100 and the first lower active pattern AP11. The first fin pattern 110 may protrude from the upper surface of the first region I of the substrate 100 and extend longitudinally in the first direction X. The first fin pattern 110 may be formed by etching a portion of the substrate 100 or may be an epitaxial layer grown from the substrate 100. Thus, the first fin pattern 110 may be a part of the substrate or may be attached to the substrate and may be provided together with the substrate in either case. The first lower active pattern AP11 and the first upper active pattern AP12 may be sequentially stacked on the first fin pattern 110 in a vertical direction (e.g., a third direction Z intersecting the first direction X and the second direction Y) intersecting the upper surface of the substrate 100.

[0040] The second lower active pattern AP21 may be formed on the second region II of the substrate 100. The second lower active pattern AP21 may extend in the first direction X. The second lower active pattern AP21 may include at least one second lower bridge pattern (e.g., bridge patterns 211 to 214) spaced apart from the substrate 100. For example, the at least one second lower bridge pattern (bridge patterns 211 to 214) may include a fifth lower sheet pattern 211, a sixth lower sheet pattern 212, a seventh lower sheet pattern 213, and an eighth lower sheet pattern 214 sequentially stacked on the upper surface of the substrate 100. The fifth lower sheet pattern 211, the sixth lower sheet pattern 212, the seventh lower sheet pattern 213, and the eighth lower sheet pattern 214 may be spaced apart from each other and may extend in the first direction X. The second lower active pattern AP21 may be configured as a channel region of an MBCFET including a multi-bridge channel. The number of sheet patterns included in the second lower active pattern AP21 is merely illustrative and is not limited to the number shown.

[0041] The second upper active pattern AP22 may be formed on the second lower active pattern AP21. The second upper active pattern AP22 may extend in the first direction X. The second upper active pattern AP22 may include at least one second upper bridge pattern (e.g., bridge patterns 215 to 218) and may be spaced farther from the substrate than the second lower active pattern. For example, the at least one second upper bridge pattern (bridge patterns 215 to 218) may include a fifth upper sheet pattern 215, a sixth upper sheet pattern 216, a seventh upper sheet pattern 217, and an eighth upper sheet pattern 218 sequentially stacked on the upper surface of the second lower active pattern AP21. The fifth upper sheet pattern 215, the sixth upper sheet pattern 216, the seventh upper sheet pattern 217, and the eighth upper sheet pattern 218 may be spaced apart from each other and extend in the first direction X. The second upper active pattern AP22 may be configured as a channel region of an MBCFET including a multi-bridge channel.

[0042] In some embodiments, the second fin pattern 210 may be formed between the substrate 100 and the second lower active pattern AP21. The second fin pattern 210 may be provided together with the substrate 100. The second fin pattern 210 may protrude from the upper surface of the second region II of the substrate 100 and extend longitudinally in the first direction X. The second fin pattern 210 may be formed by etching a portion of the substrate 100 or may be an epitaxial layer grown from the substrate 100. The second lower active pattern AP21 and the second upper active pattern AP22 may be sequentially disposed on the second fin pattern 210 in the third direction Z.

[0043] Each of the active patterns AP11, AP12, AP21, and AP22 may include silicon (Si) or germanium (Ge) as an elemental semiconductor material. Alternatively, each of the active patterns AP11, AP12, AP21, and AP22 may include a compound semiconductor, e.g., a group-IV-IV compound semiconductor or a group-III-V compound semiconductor. The group-IV-IV compound semiconductor may include, for example, a binary compound including two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), a ternary compound including three of them, or a compound obtained by doping a group-IV element into them. The group-III-V compound semiconductor may include, for example, one of binary compounds, ternary compounds, and quaternary compounds formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as a group-III element and at least one of phosphorus (P), arsenic (As), and antimony (Sb) as a group-V element. For ease of description, in the following description, the active patterns AP11, AP12, AP21, and AP22 will each be described as silicon (Si) patterns. Throughout the specification, unless the context clearly and / or explicitly describes otherwise, when a component is described as "including" a specific element or group of elements, it will be understood that the component is formed only of the element or group of elements, or the element or group of elements may be combined with additional elements to form the component. On the other hand, the term "consisting of" indicates that the component is formed only of the listed elements.

[0044] In some embodiments, the first lower active pattern AP11 and the second lower active pattern AP21 may be disposed at the same height. The first upper active pattern AP12 and the second upper active pattern AP22 may be disposed at the same height. In this regard, "disposed at the same height" means disposed at the same vertical height based on a common reference plane such as the upper surface of the substrate 100 (e.g., at the same height or distance above the top surface of the substrate 100). For example, as shown, the first lower bridge patterns 111 to 114 and the second lower bridge patterns 211 to 214 may be disposed at the same vertical height. The first upper bridge patterns 115 to 118 and the second upper bridge patterns 215 to 218 may be disposed at the same vertical height.

[0045] In some embodiments, the first lower active pattern AP11 and the second lower active pattern AP21 may be formed at the same height. The first upper active pattern AP12 and the second upper active pattern AP22 may be formed at the same height. In some embodiments, the items "formed at the same height" refer to items formed in the same manufacturing process. The first lower active pattern AP11 and the second lower active pattern AP21 may be made of the same material and / or the same material composition. The first upper active pattern AP12 and the second upper active pattern AP22 may be made of the same material and / or the same material composition.

[0046] The first base insulating film 104 may be disposed between the substrate 100 and the first lower active pattern AP11. The first base insulating film 104 may electrically insulate the substrate 100 and the first lower active pattern AP11 from each other. For example, the first base insulating film 104 may be disposed between the first fin pattern 110 and the first lower sheet pattern 111. In some embodiments, the first base insulating film 104 may conformally extend along the upper surface of the substrate 100 and the upper surface and one side surface of the first fin pattern 110.

[0047] The second base insulating film 204 may be disposed between the substrate 100 and the second lower active pattern AP21. The second base insulating film 204 may electrically insulate the substrate 100 and the second lower active pattern AP21 from each other. For example, the second base insulating film 204 may be disposed between the second fin pattern 210 and the fifth lower sheet pattern 211. In some embodiments, the second base insulating film 204 may conformally extend along the upper surface of the substrate 100, the upper surface and one side surface of the second fin pattern 210.

[0048] Each of the first base insulating film 104 and the second base insulating film 204 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. However, embodiments of the present disclosure are not limited thereto. In one example, each of the first base insulating film 104 and the second base insulating film 204 may be a silicon nitride film.

[0049] In some embodiments, the first base insulating film 104 and the second base insulating film 204 may be disposed at the same height. In some embodiments, the first base insulating film 104 and the second base insulating film 204 may be formed at the same height. For example, portions of the first base insulating film 104 and the second base insulating film that are at the same horizontal distance from the wall structure 102 may be at the same height.

[0050] The first intermediate insulating film 105 may be disposed between the first lower active pattern AP11 and the first upper active pattern AP12. The first intermediate insulating film 105 may electrically insulate the first lower active pattern AP11 and the first upper active pattern AP12 from each other. For example, the first intermediate insulating film 105 may be disposed between the fourth lower sheet pattern 114 and the first upper sheet pattern 115.

[0051] The second intermediate insulating film 205 may be disposed between the second lower active pattern AP21 and the second upper active pattern AP22. The second intermediate insulating film 205 may electrically insulate the second lower active pattern AP21 and the second upper active pattern AP22 from each other. For example, the second intermediate insulating film 205 may be disposed between the eighth lower sheet pattern 214 and the fifth upper sheet pattern 215.

[0052] Each of the first intermediate insulating film 105 and the second intermediate insulating film 205 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. However, embodiments of the present disclosure are not limited thereto. In one example, each of the first intermediate insulating film 105 and the second intermediate insulating film 205 may be a silicon nitride film.

[0053] In some embodiments, the first intermediate insulating film 105 and the second intermediate insulating film 205 may be disposed at the same height. In some embodiments, the first intermediate insulating film 105 and the second intermediate insulating film 205 may be formed at the same height.

[0054] The field insulating film 106 may be formed on the substrate 100. For example, the field insulating film 106 may be formed on the first base insulating film 104 and the second base insulating film 204. The field insulating film 106 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. However, embodiments of the present disclosure are not limited thereto. In one example, the field insulating film 106 may be a silicon oxide film.

[0055] In some embodiments, the field insulating film 106 may fill at least a portion of the regions on the side surfaces of the first fin pattern 110 and at least a portion of the regions on the side surfaces of the second fin pattern 210. In Figure 2 the figure, the upper surface of the field insulating film 106 is shown to be coplanar with the upper surfaces of the first base insulating film 104 and the second base insulating film 204. However, this is merely an example. In another example, the vertical height of the upper surface of the field insulating film 106 may be lower than the vertical height of each of the upper surfaces of the first base insulating film 104 and the second base insulating film 204, or may be higher than the vertical height of each of the upper surfaces of the first base insulating film 104 and the second base insulating film 204. When referring to orientation, layout, position, shape, size, composition, quantity, or other metrics, terms such as "same", "equal", "planar", or "coplanar" used herein do not necessarily mean exactly identical orientation, layout, position, shape, size, composition, quantity, or other metrics, but are intended to cover approximately identical orientation, layout, position, shape, size, composition, quantity, or other metrics within acceptable variations that may occur, for example, due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning. For example, an item described as "substantially the same", "substantially equal", or "substantially planar" may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.

[0056] The wall structure 102 may longitudinally extend in a first direction X at a position between the first region I and the second region II. The wall structure 102 may isolate the first lower active pattern AP11 and the second lower active pattern AP21 from each other, and isolate the first upper active pattern AP12 and the second upper active pattern AP22 from each other. For example, the first lower active pattern AP11 and the first upper active pattern AP12 may contact a first side surface 102a of the wall structure 102. The second lower active pattern AP21 and the second upper active pattern AP22 may contact a second side surface 102b of the wall structure 102. Each of the active patterns AP11, AP12, AP21, and AP22 may be provided as a channel region of a forksheet field effect transistor (forksheet FET).

[0057] The wall structure 102 may include an insulating material (such as at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof). However, embodiments of the present disclosure are not limited thereto. In one example, the wall structure 102 may be a silicon nitride film. The wall structure 102 may be provided as a dielectric wall of a Dielectric Wall Scheme (DWS) forksheet field effect transistor (forksheet FET) structure.

[0058] The wall structure 102 may have a tapered shape. Specifically, the width of the wall structure 102 in the second direction Y may increase as the wall structure 102 extends away from the substrate 100. This may be due to the characteristics of the etching process (or patterning process) used to form the wall structure 102. However, embodiments of the present disclosure are not limited thereto.

[0059] The lower surface of the wall structure 102 is shown to be coplanar with the upper surface of the substrate 100. This is merely an example. In another example, the lower surface of the wall structure 102 may be formed at a vertical height lower than the vertical height of the upper surface of the substrate 100, or may be formed at a vertical height higher than the vertical height of the upper surface of the substrate 100.

[0060] In some embodiments, the wall structure 102 may isolate the first base insulating film 104 and the second base insulating film 204 from each other. The lower surface of the wall structure 102 may be formed at a vertical height lower than the vertical height of each of the lower surfaces of the first base insulating film 104 and the second base insulating film 204. In addition, the wall structure 102 may isolate the first intermediate insulating film 105 and the second intermediate insulating film 205 from each other.

[0061] Since the wall structure 102 has a tapered shape, the width of each of the active patterns AP11, AP12, AP21, and AP22 may decrease as each of the active patterns AP11, AP12, AP21, and AP22 extends away from the substrate 100. In addition, the width of the first upper active pattern AP12 may be smaller than the width of the first lower active pattern AP11. The width of the second upper active pattern AP22 may be smaller than the width of the second lower active pattern AP21. In this regard, the width refers to the width in the second direction Y. For example, as Figure 3 shown, the width W12 of the fourth lower sheet pattern 114 may be smaller than the width W11 of the first lower sheet pattern 111. The width W22 of the fourth upper sheet pattern 118 may be smaller than the width W21 of the first upper sheet pattern 115. In addition, the width W21 of the first upper sheet pattern 115 may be smaller than the width W12 of the fourth lower sheet pattern 114. When the width of each sheet pattern can decrease in the direction away from the substrate 100, the above various sheet pattern widths may represent the maximum width of the pattern in the second direction Y.

[0062] In addition, when the wall structure 102 has a tapered shape, each side surface of the active patterns AP11, AP12, AP21, and AP22 facing the wall structure 102 may have an inclination angle with respect to the upper surface of the substrate 100. For example, as Figure 3 shown, one side surface of the first lower sheet pattern 111 facing the wall structure 102 may define a first acute angle θ1 with respect to the lower surface of the first lower sheet pattern 111.

[0063] In some embodiments, the thickness of each of the first upper bridge-shaped patterns 115 to 118 may be greater than the thickness of each of the first lower bridge-shaped patterns 111 to 114. In this regard, the thickness represents the thickness in the third direction Z. For example, as Figure 3 shown, the thickness T2 of the first upper sheet-shaped pattern 115 may be greater than the thickness T1 of the first lower sheet-shaped pattern 111.

[0064] In some embodiments, each of the plurality of first lower bridge-shaped patterns 111 to 114 may have the same thickness (e.g., T1). In some embodiments, each of the plurality of first upper bridge-shaped patterns 115 to 118 may have the same thickness (e.g., T2).

[0065] In some embodiments, the number of the first upper bridge-shaped patterns 115 to 118 may be equal to the number of the first lower bridge-shaped patterns 111 to 114. For example, as shown, each of the total number of the first lower bridge-shaped patterns 111 to 114 and the total number of the first upper bridge-shaped patterns 115 to 118 may be 4.

[0066] In some embodiments, the cross-sectional area size of the first upper active pattern AP12 may be equal to the cross-sectional area size of the first lower active pattern AP11. In this regard, the cross-sectional area size represents the area size of the cross-section intersecting the first direction X. For example, the thickness (e.g., T2) of each of the first upper bridge-shaped patterns 115 to 118 may be controlled such that the combined cross-sectional area size of the first upper bridge-shaped patterns 115 to 118 is equal to the combined cross-sectional area size of the first lower bridge-shaped patterns 111 to 114.

[0067] In some embodiments, the interval between adjacent first upper bridge-shaped patterns among the plurality of first upper bridge-shaped patterns 115 to 118 may be less than the interval between adjacent first lower bridge-shaped patterns among the plurality of first lower bridge-shaped patterns 111 to 114. For example, as Figure 3 shown, the interval D2 between the first upper sheet-shaped pattern 115 and the second upper sheet-shaped pattern 116 may be less than the interval D1 between the first lower sheet-shaped pattern 111 and the second lower sheet-shaped pattern 112.

[0068] In some embodiments, each of the side surfaces of the active patterns AP11, AP12, AP21, and AP22 opposite to the wall structure 102 may also have an inclination angle with respect to the upper surface of the substrate 100. For example, as Figure 3As shown in [reference], the other surface of the first lower sheet-like pattern 111 opposite to the wall structure 102 may have a second acute angle θ2 with respect to the lower surface of the first lower sheet-like pattern 111. This may be due to the characteristics of the etching process (or patterning process) for forming the active patterns AP11, AP12, AP21, and AP22. However, embodiments of the present disclosure are not limited thereto.

[0069] In some embodiments, as Figure 3 shown in [reference], the second acute angle θ2 may be equal to the first acute angle θ1.

[0070] In some embodiments, as Figure 4 shown in [reference], the second acute angle θ2 may be different from the first acute angle θ1. In some embodiments, the first acute angle θ1 may be less than the second acute angle θ2.

[0071] The first gate structure GS1 may be formed on the first region I of the substrate 100. The first gate structure GS1 may intersect the first lower active pattern AP11 and the first upper active pattern AP12. For example, the first gate structure GS1 may extend in the second direction Y while being disposed on the first side surface 102a of the wall structure 102. The first lower bridge-like patterns 111 to 114 and the first upper bridge-like patterns 115 to 118 may extend in the first direction X and extend through the first gate structure GS1. Accordingly, the first gate structure GS1 may surround the peripheries of each of the first lower bridge-like patterns 111 to 114 and the peripheries of each of the first upper bridge-like patterns 115 to 118.

[0072] The second gate structure GS2 may be formed on the second region II of the substrate 100. The second gate structure GS2 may intersect the second lower active pattern AP21 and the second upper active pattern AP22. For example, the second gate structure GS2 may extend in the second direction Y while being disposed on the second side surface 102b of the wall structure 102. The second lower bridge-like patterns 211 to 214 and the second upper bridge-like patterns 215 to 218 may extend in the first direction X and extend through the second gate structure GS2. Accordingly, the second gate structure GS2 may surround the peripheries of each of the second lower bridge-like patterns 211 to 214 and the peripheries of each of the second upper bridge-like patterns 215 to 218.

[0073] The first gate structure GS1 may include a first gate dielectric film 120 and a first gate electrode 130. The second gate structure GS2 may include a second gate dielectric film 220 and a second gate electrode 230.

[0074] The first gate dielectric film 120 may be disposed on the first lower active pattern AP11 and the first upper active pattern AP12. The first gate dielectric film 120 may conformally extend along the surfaces of the first lower bridge-like patterns 111 to 114, the first upper bridge-like patterns 115 to 118, and the wall structure 102. The first gate dielectric film 120 may be disposed between the first lower active pattern AP11 and the first gate electrode 130 and between the first upper active pattern AP12 and the first gate electrode 130. The first gate dielectric film 120 may also extend along the upper surface of the first base insulating film 104 and / or the upper surface of the field insulating film 106. In addition, the first gate dielectric film 120 may extend along the side surface of the first intermediate insulating film 105.

[0075] In some embodiments, a portion of the first gate dielectric film 120 may be disposed between the wall structure 102 and the first gate electrode 130. For example, the first gate dielectric film 120 may extend along the first side surface 102a of the wall structure 102.

[0076] The second gate dielectric film 220 may be disposed on the second lower active pattern AP21 and the second upper active pattern AP22. The second gate dielectric film 220 may conformally extend along the surfaces of the second lower bridge-like patterns 211 to 214, the second upper bridge-like patterns 215 to 218, and the wall structure 102. The second gate dielectric film 220 may be disposed between the second lower active pattern AP21 and the second gate electrode 230 and between the second upper active pattern AP22 and the second gate electrode 230. The second gate dielectric film 220 may also extend along the upper surface of the second base insulating film 204 and / or the upper surface of the field insulating film 106. In addition, the second gate dielectric film 220 may extend along the side surface of the second intermediate insulating film 205.

[0077] In some embodiments, a portion of the second gate dielectric film 220 may be disposed between the wall structure 102 and the second gate electrode 230. For example, the second gate dielectric film 220 may extend along the second side surface 102b of the wall structure 102.

[0078] Each of the first gate dielectric film 120 and the second gate dielectric film 220 may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a dielectric constant higher than that of silicon oxide. The high-k material may include, for example, hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), strontium titanate (SrTiO3), lanthanum aluminate (LaAlO3), yttrium oxide (Y2O3), hafnium oxynitride (HfO x N y ), zirconium oxynitride (ZrO x N y), lanthanum oxynitride (La2O x N y ), aluminum oxynitride (Al2O x N y ), titanium oxynitride (TiO x N y ), strontium titanate oxynitride (SrTiO x N y ), lanthanum aluminate oxynitride (LaAlO x N y ), yttrium oxynitride (Y2O x N y ), and at least one of combinations thereof. However, embodiments of the present disclosure are not limited thereto.

[0079] A semiconductor device according to some embodiments may include a negative capacitance (NC) FET using a negative capacitor. For example, the first gate dielectric film 120 and / or the second gate dielectric film 220 may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0080] The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, when two or more capacitors are connected in series with each other and the capacitance of each capacitor has a positive value, the total capacitance is less than the capacitance of each individual capacitor. In contrast, when at least one of the capacitances of two or more capacitors connected in series with each other has a negative value, the total capacitance may have a positive value and be greater than the absolute value of each individual capacitance.

[0081] When a ferroelectric material film having a negative capacitance and a paraelectric material film having a positive capacitance are connected in series with each other, the total capacitance value of the ferroelectric material film and the paraelectric material film connected in series with each other can be increased. Using the increase in the total capacitance value, a transistor including the ferroelectric material film can have a subthreshold swing (SS) lower than about 60 mV / decade at room temperature.

[0082] The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanate oxide, barium titanate oxide, and lead zirconium titanate oxide. In this regard, in one example, hafnium zirconium oxide may represent a material obtained by doping hafnium oxide with zirconium (Zr). In another example, hafnium zirconium oxide may represent a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0083] The ferroelectric material film may also include a dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the ferroelectric material film may vary according to the type of ferroelectric material included in the ferroelectric material film.

[0084] When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include at least one of, for example, gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0085] When the dopant is aluminum (Al), the ferroelectric material film may include from about 3 at% to about 8 at% (atomic percent) of aluminum. In this regard, the content of the dopant may be the content of aluminum based on the sum of hafnium and aluminum.

[0086] When the dopant is silicon (Si), the ferroelectric material film may include from about 2 at% to about 10 at% of silicon. When the dopant is yttrium (Y), the ferroelectric material film may include from about 2 at% to about 10 at% of yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may include from about 1 at% to about 7 at% of gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may include from about 50 at% to about 80 at% of zirconium.

[0087] The paraelectric material film may have paraelectric properties. The paraelectric material film may include at least one of, for example, silicon oxide and metal oxides having a high dielectric constant. Although the metal oxides included in the paraelectric material film may include at least one of, for example, hafnium oxide, zirconium oxide, and aluminum oxide. However, the present disclosure is not limited thereto.

[0088] The ferroelectric material film and the paraelectric material film may include the same materials or material components, or may be formed of the same materials or material components. The ferroelectric material film may have ferroelectric properties, but the paraelectric material film may not have ferroelectric properties. For example, when each of the ferroelectric material film and the paraelectric material film includes hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material film is different from the crystal structure of the hafnium oxide included in the paraelectric material film.

[0089] The ferroelectric material film may have a thickness with dimensions set to exhibit ferroelectric properties. Although the thickness of the ferroelectric material film may be, for example, in the range of about 0.5 nm to about 10 nm, the present disclosure is not limited thereto. Since the critical thickness for exhibiting ferroelectric properties may vary based on the type of ferroelectric material, the thickness of the ferroelectric material film may vary according to the type of ferroelectric material.

[0090] In one example, the first gate dielectric film 120 and / or the second gate dielectric film 220 may include a ferroelectric material film. In another example, the first gate dielectric film 120 and / or the second gate dielectric film 220 may include a plurality of ferroelectric material films spaced apart from each other. The first gate dielectric film 120 and / or the second gate dielectric film 220 may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked on top of each other.

[0091] The first gate electrode 130 may be disposed on the first gate dielectric film 120. In some embodiments, the first gate electrode 130 may be formed by stacking a plurality of conductive films. For example, the first gate electrode 130 may include a first work function adjusting film 132 that controls the work function, and a first filling conductive film 134 that fills the space defined by the first work function adjusting film 132.

[0092] The second gate electrode 230 may be disposed on the second gate dielectric film 220. In some embodiments, the second gate electrode 230 may be formed by stacking a plurality of conductive films. For example, the second gate electrode 230 may include a second work function adjusting film 232 that controls the work function, and a second filling conductive film 234 that fills the space defined by the second work function adjusting film 232.

[0093] The first work function adjusting film 132 and the second work function adjusting film 232 are shown to have the same thickness. However, this is only an example. In another example, the first work function adjusting film 132 and the second work function adjusting film 232 have different thicknesses.

[0094] Each of the first work function adjusting film 132 and the second work function adjusting film 232 may include at least one of, for example, TiN, TaN, TiC, TaC, TiAlC, and combinations thereof. However, the embodiments of the present disclosure are not limited thereto. Each of the first filling conductive film 134 and the second filling conductive film 234 may include, for example, W or Al. However, the embodiments of the present disclosure are not limited thereto.

[0095] In some embodiments, the wall structure 102 may extend in the first direction X so as to isolate the first gate structure GS1 and the second gate structure GS2 from each other. For example, the upper surface of the wall structure 102 may be formed at a vertical height higher than the vertical height of each of the upper surfaces of the first gate structure GS1 and the second gate structure GS2.

[0096] The first gate spacer 140 may extend along the side surface of the first gate structure GS1. In some embodiments, a portion of the first gate dielectric film 120 may be disposed between the first gate electrode 130 and the first gate spacer 140. For example, as Figure 5As shown in [reference], the first gate dielectric film 120 may also extend along at least a part of the inner surface of the first gate spacer 140. The first gate dielectric film 120 may be formed in a replacement process. However, embodiments of the present disclosure are not limited thereto.

[0097] The second gate spacer 240 may extend along the side surface of the second gate structure GS2. In some embodiments, a part of the second gate dielectric film 220 may be disposed between the second gate electrode 230 and the second gate spacer 240. For example, as Figure 6 shown in [reference], the second gate dielectric film 220 may also extend along at least a part of the inner surface of the second gate spacer 240. The second gate dielectric film 220 may be formed in a replacement process. However, embodiments of the present disclosure are not limited thereto.

[0098] Each of the first gate spacer 140 and the second gate spacer 240 may include at least one of, for example, silicon nitride, silicon oxynitride, silicon carbonitride, boron nitride silicon, boron carbon nitride silicon, silicon carbon oxynitride, and combinations thereof. However, embodiments of the present disclosure are not limited thereto. In one example, each of the first gate spacer 140 and the second gate spacer 240 is a silicon nitride film.

[0099] The first lower source / drain pattern 160A and the first upper source / drain pattern 160B may be formed on at least one side surface of the first gate structure GS1. For example, the first lower source / drain pattern 160A may be formed on two opposite sides of the first gate structure GS1 to form a first source / drain region and a second source / drain region, and the first upper source / drain pattern 160B may be formed on two opposite sides of the first gate structure GS1 to form a first source / drain region and a second source / drain region. The first lower source / drain pattern 160A may be in contact with the first lower active pattern AP11 in the first direction X. The first upper source / drain pattern 160B may be in contact with the first upper active pattern AP12 in the first direction X. For example, the first lower bridge patterns 111 to 114 may extend in the first direction X through the first gate structure GS1 and the first gate spacer 140 to contact the first lower source / drain pattern 160A. In addition, the first upper bridge patterns 115 to 118 may extend in the first direction X through the first gate structure GS1 and the first gate spacer 140 to contact the first upper source / drain pattern 160B. The first lower source / drain pattern 160A and the first upper source / drain pattern 160B may be electrically insulated from the first gate electrode 130 via the first gate spacer 140 and / or the first gate dielectric film 120.

[0100] In some embodiments, each of the first lower source / drain pattern 160A and the first upper source / drain pattern 160B may be an epitaxial layer. For example, the first lower source / drain pattern 160A may be formed by epitaxial growth from the first lower active pattern AP11. The first upper source / drain pattern 160B may be formed by epitaxial growth from the first upper active pattern AP12.

[0101] When the first region I is an NFET region, each of the first lower source / drain pattern 160A and the first upper source / drain pattern 160B may contain an n-type impurity (e.g., phosphorus (P), antimony (Sb), or arsenic (As)) or an impurity that prevents the diffusion of the n-type impurity. When the first region I is an NFET region, each of the first lower source / drain pattern 160A and the first upper source / drain pattern 160B may further contain a tensile stress material. In one example, when each of the first lower active pattern AP11 and the first upper active pattern AP12 is embodied as a silicon (Si) pattern, each of the first lower source / drain pattern 160A and the first upper source / drain pattern 160B may include a material having a lattice constant smaller than that of silicon (Si) (e.g., silicon carbide (SiC)).

[0102] In some embodiments, the first lower source / drain pattern 160A and the first upper source / drain pattern 160B may be electrically insulated from each other. For example, as shown in FIG. 5, the first isolation insulating film 108 may be formed between the first lower source / drain pattern 160A and the first upper source / drain pattern 160B. The thickness of the first isolation insulating film 108 is shown to be equal to the thickness of the first intermediate insulating film 105. However, this is only an example. In another example, the thickness of the first isolation insulating film 108 may be different from the thickness of the first intermediate insulating film 105.

[0103] The second lower source / drain pattern 260A and the second upper source / drain pattern 260B may be formed on at least one side surface of the second gate structure GS2. For example, the second lower source / drain pattern 260A may be formed on two opposite sides of the second gate structure GS2 to form a first source / drain region and a second source / drain region, and the second upper source / drain pattern 260B may be formed on two opposite sides of the second gate structure GS2 to form a first source / drain region and a second source / drain region. The second lower source / drain pattern 260A may be in contact with the second lower active pattern AP21 in the first direction X. The second upper source / drain pattern 260B may be in contact with the second upper active pattern AP22 in the first direction X. For example, the second lower bridge patterns 211 to 214 may extend in the first direction X through the second gate structure GS2 and the second gate spacer 240 to be in contact with the second lower source / drain pattern 260A. In addition, the second upper bridge patterns 215 to 218 may extend in the first direction X through the second gate structure GS2 and the second gate spacer 240 to be in contact with the second upper source / drain pattern 260B. The second lower source / drain pattern 260A and the second upper source / drain pattern 260B may be electrically insulated from the second gate electrode 230 via the second gate spacer 240 and / or the second gate dielectric film 220.

[0104] In some embodiments, each of the second lower source / drain pattern 260A and the second upper source / drain pattern 260B may include or may be an epitaxial layer. For example, the second lower source / drain pattern 260A may be formed by epitaxial growth from the second lower active pattern AP21. The second upper source / drain pattern 260B may be formed by epitaxial growth from the second upper active pattern AP22.

[0105] When the second region II is a PFET region, each of the second lower source / drain pattern 260A and the second upper source / drain pattern 260B may include a p-type impurity (e.g., boron (B), indium (In), gallium (Ga), or aluminum (Al)) or an impurity that prevents the diffusion of the p-type impurity. When the second region II is a PFET region, each of the second lower source / drain pattern 260A and the second upper source / drain pattern 260B may further include a compressive stress material. In one example, when each of the second lower active pattern AP21 and the second upper active pattern AP22 is embodied as a silicon (Si) pattern, each of the second lower source / drain pattern 260A and the second upper source / drain pattern 260B may include a material having a lattice constant larger than that of silicon (Si) (e.g., silicon germanium (SiGe)). In some embodiments, each of the first lower source / drain pattern 160A and the second lower source / drain pattern 260A may include an n-type impurity (e.g., phosphorus (P), antimony (Sb), or arsenic (As)) or an impurity that prevents the diffusion of the n-type impurity, and each of the first upper source / drain pattern 160B and the second upper source / drain pattern 260B may include a p-type impurity (e.g., boron (B), indium (In), gallium (Ga), or aluminum (Al)), or an impurity that prevents the diffusion of the p-type impurity.

[0106] In some embodiments, the second lower source / drain pattern 260A and the second upper source / drain pattern 260B may be electrically insulated from each other. For example, as Figure 6 shown, the second isolation insulating film 208 may be formed between the second lower source / drain pattern 260A and the second upper source / drain pattern 260B. The thickness of the second isolation insulating film 208 is shown to be equal to the thickness of the second intermediate insulating film 205. However, this is only an example. In another example, the thickness of the second isolation insulating film 208 may be different from the thickness of the second intermediate insulating film 205.

[0107] The interlayer insulating film 180 may be formed on the wall structure 102, the gate structures GS1 and GS2, and the source / drain patterns 160A, 160B, 260A, and 260B. The interlayer insulating film 180 may cover the wall structure 102, the gate structures GS1 and GS2, and the source / drain patterns 160A, 160B, 260A, and 260B.

[0108] The interlayer insulating film 180 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, boron silicon nitride, boron carbon nitride, silicon carbon oxynitride, and a low dielectric constant material having a dielectric constant smaller than that of silicon oxide. However, embodiments of the present disclosure are not limited thereto. The low dielectric constant material may include, for example, flowable oxide (FOX), tolylene silylene (TOSZ), undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluoride silicate glass (FSG), carbon-doped silicon oxide (CDO), xerogel, aerogel, amorphous fluorocarbon, organosilicate glass (OSG), parylene, bisbenzocyclobutene (BCB), SiLK, polyimide, porous polymer materials, and combinations thereof. However, embodiments of the present disclosure are not limited thereto.

[0109] The first gate contact CB1 may be electrically connected to the first gate structure GS1. For example, the first gate contact CB1 may extend in the third direction Z through the interlayer insulating film 180 and may contact the upper surface of the first gate electrode 130.

[0110] The second gate contact CB2 may be electrically connected to the second gate structure GS2. For example, the second gate contact CB2 may extend in the third direction Z through the interlayer insulating film 180 and may contact the upper surface of the second gate electrode 230.

[0111] Each of the first gate contact CB1 and the second gate contact CB2 may include a conductive material (such as a metal (such as cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), or cobalt tungsten phosphorus (CoWP), etc.)). However, embodiments of the present disclosure are not limited thereto.

[0112] As semiconductor devices become more highly integrated, semiconductor devices using stacked multi-gate transistors are being studied to implement a larger number of semiconductor devices in the same area. Such a semiconductor device may include a lower multi-gate transistor on a substrate and an upper multi-gate transistor stacked on the lower multi-gate transistor.

[0113] In one example, in a dielectric wall scheme (DWS) fin field effect transistor (fin FET) structure including stacked multi-gate transistors, the wall structure 102 serving as a dielectric wall may have a tapered shape in which its width decreases as the wall structure extends downward. In this case, the channel width of the upper multi-gate transistor may be smaller than the channel width of the lower multi-gate transistor, and a difference may occur between the characteristics of the lower multi-gate transistor and the characteristics of the upper multi-gate transistor.

[0114] A semiconductor device according to some embodiments may minimize the difference between the characteristics of a lower multi-gate transistor and the characteristics of an upper multi-gate transistor by controlling the channel area size of the lower multi-gate transistor and / or the channel area size of the upper multi-gate transistor. For example, as described above, the thickness (e.g., T2) of each of the first upper bridge-shaped patterns 115 to 118 may be greater than the thickness (e.g., T1) of each of the first lower bridge-shaped patterns 111 to 114. In addition, in some embodiments, the thickness (e.g., T2) of each of the first upper bridge-shaped patterns 115 to 118 may be controlled such that the cross-sectional area size of the combined first upper bridge-shaped patterns 115 to 118 is equal to the cross-sectional area size of the combined first lower bridge-shaped patterns 111 to 114. For example, a specific group of bridge-shaped patterns (e.g., sheet patterns) may together form a channel region between the source region and the drain region of a transistor. The group of bridge-shaped patterns may include all the bridge-shaped patterns for the corresponding transistor and may be described as a multi-sheet channel pattern. In some embodiments, when viewed in the direction (e.g., the first direction X) longitudinally extending from the wall structure 102, even though the lengths of the sheet patterns in the direction (e.g., the second direction Y) perpendicular to the direction longitudinally extending from the wall structure 102 may be different, the multi-sheet channel pattern (e.g., the first upper bridge-shaped patterns 115 to 118) of the upper transistor may have the same cross-sectional area as the multi-sheet channel pattern (e.g., the first lower bridge-shaped patterns 111 to 114) of the lower transistor. In some embodiments, the cross-sectional area of the first lower active pattern AP11 and the cross-sectional area of the first upper active pattern AP12 are within a specific percentage difference (e.g., a difference from 0% to 5%). Similar differences may occur between other corresponding upper and lower active patterns. Therefore, the difference between the characteristics of the lower multi-gate transistor and the characteristics of the upper multi-gate transistor may be minimized, thereby providing a semiconductor device with improved performance.

[0115] Figure 7 is a cross-sectional view for describing a semiconductor device according to some embodiments. For ease of description, descriptions that are repetitive with those described above with reference to Figures 1 to 6 are briefly elaborated or omitted.

[0116] Referring to Figure 7 , in a semiconductor device according to some embodiments, the first gate electrode 130 may include a first lower work function adjusting film 132a and a first upper work function adjusting film 132b. The second gate electrode 230 may include a second lower work function adjusting film 232a and a second upper work function adjusting film 232b.

[0117] The first lower work function adjustment film 132a may intersect with the first lower active pattern AP11. The first upper work function adjustment film 132b may intersect with the first upper active pattern AP12. The second lower work function adjustment film 232a may intersect with the second lower active pattern AP21. The second upper work function adjustment film 232b may intersect with the second upper active pattern AP22.

[0118] Each of the first lower work function adjustment film 132a, the first upper work function adjustment film 132b, the second lower work function adjustment film 232a, and the second upper work function adjustment film 232b may include at least one of, for example, TiN, TaN, TiC, TaC, TiAlC, and combinations thereof. However, embodiments of the present disclosure are not limited thereto.

[0119] In some embodiments, the first lower work function adjustment film 132a and the first upper work function adjustment film 132b may be work function adjustment films of different conduction types. The second lower work function adjustment film 232a and the second upper work function adjustment film 232b may be work function adjustment films of different conduction types. In one example, each of the first lower work function adjustment film 132a and the second lower work function adjustment film 232a may be a work function adjustment film for an NFET, and each of the first upper work function adjustment film 132b and the second upper work function adjustment film 232b may be a work function adjustment film for a PFET. In another example, each of the first lower work function adjustment film 132a and the second lower work function adjustment film 232a may be a work function adjustment film for a PFET, while each of the first upper work function adjustment film 132b and the second upper work function adjustment film 232b may be a work function adjustment film for an NFET. In another example, each of the first lower work function adjustment film 132a and the second upper work function adjustment film 232b may be a work function adjustment film for an NFET, while each of the first upper work function adjustment film 132b and the second lower work function adjustment film 232a may be a work function adjustment film for a PFET.

[0120] Figure 8 is a cross-sectional view for describing a semiconductor device according to some embodiments. Figure 9 is for describing Figure 8 An enlarged view of the R2 region of. For ease of description, descriptions that are repetitive with those described above with reference to Figures 1 to 6 are briefly described or omitted.

[0121] Referring to Figure 8 and Figure 9, in a semiconductor device according to some embodiments, the number of at least one first upper bridge-shaped pattern (e.g., bridge-shaped patterns 115 to 119) may be greater than the number of at least one first lower bridge-shaped pattern (e.g., bridge-shaped patterns 111 to 114). For example, the first upper bridge-shaped patterns 115 to 119 may further include a fifth upper sheet-shaped pattern 119. Thus, the number of the first lower bridge-shaped patterns 111 to 114 may be 4, while the number of the first upper bridge-shaped patterns 115 to 119 may be 5.

[0122] In some embodiments, the thickness of each of the first upper bridge-shaped patterns 115 to 119 may be equal to the thickness of each of the first lower bridge-shaped patterns 111 to 114. For example, as Figure 9 shown, the thickness T2 of the first upper sheet-shaped pattern 115 may be equal to the thickness T1 of the first lower sheet-shaped pattern 111.

[0123] In some embodiments, the plurality of first lower bridge-shaped patterns 111 to 114 may have the same thickness (e.g., T1). In some embodiments, the plurality of first upper bridge-shaped patterns 115 to 119 may have the same thickness (e.g., T2).

[0124] In some embodiments, the cross-sectional area size of the first upper active pattern AP12 may be equal to the cross-sectional area size of the first lower active pattern AP11. For example, the number of at least one first upper bridge-shaped pattern (e.g., 115 to 119) may be controlled such that the cross-sectional area size of the first upper bridge-shaped patterns 115 to 119 is equal to the cross-sectional area size of the first lower bridge-shaped patterns 111 to 114. Thus, the difference between the characteristics of the lower multi-gate transistor and the characteristics of the upper multi-gate transistor can be minimized, thereby providing a semiconductor device with improved performance.

[0125] In some embodiments, the interval between adjacent first upper bridge-shaped patterns among the plurality of first upper bridge-shaped patterns 115 to 119 may be less than the interval between adjacent first lower bridge-shaped patterns among the plurality of first lower bridge-shaped patterns 111 to 114. For example, as Figure 9 shown, the interval D2 between the first upper sheet-shaped pattern 115 and the second upper sheet-shaped pattern 116 may be less than the interval D1 between the first lower sheet-shaped pattern 111 and the second lower sheet-shaped pattern 112.

[0126] Figure 10 is a cross-sectional view for describing a semiconductor device according to some embodiments. Figure 11 is for describing Figure 10 an enlarged view of the R3 region of. For ease of description, descriptions that are repetitive with the descriptions set forth above with reference to Figures 1 to 6 are briefly elaborated or omitted.

[0127] Referring to Figure 10 andFigure 11 In a semiconductor device according to some embodiments, each of some of the plurality of first upper bridge-shaped patterns 115 to 118 may have a thickness different from that of each of the others of the plurality of first upper bridge-shaped patterns 115 to 118.

[0128] For example, the thickness T21 of each of the first upper sheet-shaped pattern 115, the second upper sheet-shaped pattern 116, and the third upper sheet-shaped pattern 117 may be equal to the thickness of each of the bridge-shaped patterns of the first lower bridge-shaped patterns 111 to 114 (e.g., T1). The thickness T22 of the fourth upper sheet-shaped pattern 118 may be greater than the thickness of each of the first lower bridge-shaped patterns 111 to 114 (e.g., T1).

[0129] In some embodiments, the cross-sectional area size of the first upper active pattern AP12 may be equal to the cross-sectional area size of the first lower active pattern AP11. For example, the thickness T22 of the fourth upper sheet-shaped pattern 118 may be controlled such that the cross-sectional area size of the first upper bridge-shaped patterns 115 to 118 is equal to the cross-sectional area size of the first lower bridge-shaped patterns 111 to 114.

[0130] In some embodiments, the interval between adjacent first upper bridge-shaped patterns among the plurality of first upper bridge-shaped patterns 115 to 118 may be smaller than the interval between adjacent first lower bridge-shaped patterns among the plurality of first lower bridge-shaped patterns 111 to 114. For example, as Figure 11 shown, the interval D21 between the first upper sheet-shaped pattern 115 and the second upper sheet-shaped pattern 116 and / or the interval D22 between the third upper sheet-shaped pattern 117 and the fourth upper sheet-shaped pattern 118 may be smaller than the interval D1 between the first lower sheet-shaped pattern 111 and the second lower sheet-shaped pattern 112.

[0131] Figures 12 to 15 are cross-sectional views for describing a semiconductor device according to some embodiments. For ease of description, descriptions that are repetitive with those described above with reference to Figures 1 to 6 are briefly elaborated or omitted.

[0132] Referring to Figures 12 to 15 , a semiconductor device according to some embodiments further includes a third upper active pattern AP13, a fourth upper active pattern AP23, a third intermediate insulating film 305, and a fourth intermediate insulating film 405.

[0133] The third upper active pattern AP13 may be formed on the first upper active pattern AP12. The third upper active pattern AP13 may be spaced farther from the substrate 100 than the first upper active pattern AP12. The first gate structure GS1 may intersect the third upper active pattern AP13.

[0134] The fourth upper active pattern AP23 may be formed on the second upper active pattern AP22. The fourth upper active pattern AP23 may be spaced further from the substrate by 100 than the second upper active pattern AP22. The second gate structure GS2 may intersect the fourth upper active pattern AP23.

[0135] The third intermediate insulating film 305 may be disposed between the first upper active pattern AP12 and the third upper active pattern AP13. The third intermediate insulating film 305 may electrically insulate the first upper active pattern AP12 and the third upper active pattern AP13 from each other.

[0136] The fourth intermediate insulating film 405 may be disposed between the second upper active pattern AP22 and the fourth upper active pattern AP23. The fourth intermediate insulating film 405 may electrically insulate the second upper active pattern AP22 and the fourth upper active pattern AP23 from each other.

[0137] Referring Figure 12 and Figure 13 FIGS. 13 and 14, in a semiconductor device according to some embodiments, the third upper active pattern AP13 may include at least one third upper bridge-like pattern (e.g., bridge-like patterns 311 to 314). The fourth upper active pattern AP23 may include at least one fourth upper bridge-like pattern (e.g., bridge-like patterns 411 to 414).

[0138] Referring Figure 12 FIGS. 15 and 16, in a semiconductor device according to some embodiments, the thickness of each of the first upper bridge-like patterns 115 to 118 may be greater than the thickness of each of the first lower bridge-like patterns 111 to 114. In addition, the thickness of each of the third upper bridge-like patterns 311 to 314 may be greater than the thickness of each of the first upper bridge-like patterns 115 to 118. In some embodiments, the cross-sectional area size of the third upper active pattern AP13 may be equal to the cross-sectional area size of the first upper active pattern AP12.

[0139] Referring Figure 13, in a semiconductor device according to some embodiments, the number of the first upper bridge-shaped patterns 115 to 119 may be greater than the number of the first lower bridge-shaped patterns 111 to 114. In addition, the thickness of each of the third upper bridge-shaped patterns 311 to 314 may be greater than the thickness of each of the first lower bridge-shaped patterns 111 to 114 and / or the thickness of each of the first upper bridge-shaped patterns 115 to 119. In some embodiments, the cross-sectional area size of the third upper active pattern AP13 may be equal to the cross-sectional area size of the first upper active pattern AP12. In a semiconductor device according to some embodiments, the number of the second upper bridge-shaped patterns 215 to 219 may be greater than the number of the second lower bridge-shaped patterns 211 to 214. In addition, the thickness of each of the fourth upper bridge-shaped patterns 411 to 414 may be greater than the thickness of each of the second lower bridge-shaped patterns 211 to 214 and / or the thickness of each of the second upper bridge-shaped patterns 215 to 219. In some embodiments, the cross-sectional area size of the fourth upper active pattern AP23 may be equal to the cross-sectional area size of the second upper active pattern AP22.

[0140] Referring to Figure 14 and Figure 15 , in a semiconductor device according to some embodiments, the third upper active pattern AP13 may include at least one of the third upper bridge-shaped patterns 311 to 316. The fourth upper active pattern AP23 may include at least one of the fourth upper bridge-shaped patterns 411 to 416.

[0141] Referring to Figure 14 , in a semiconductor device according to some embodiments, the thickness of each of at least one of the first upper bridge-shaped patterns 115 to 118 may be greater than the thickness of each of at least one of the first lower bridge-shaped patterns 111 to 114. In addition, the number of the bridge-shaped patterns of at least one of the third upper bridge-shaped patterns 311 to 316 may be greater than the number of the bridge-shaped patterns of at least one of the first upper bridge-shaped patterns 115 to 118. In some embodiments, the cross-sectional area size of the third upper active pattern AP13 may be equal to the cross-sectional area size of the first upper active pattern AP12.

[0142] Referring to Figure 15 , in a semiconductor device according to some embodiments, the number of the bridge-shaped patterns of at least one of the first upper bridge-shaped patterns 115 to 119 may be greater than the number of the bridge-shaped patterns of at least one of the first lower bridge-shaped patterns 111 to 114. In addition, the number of the bridge-shaped patterns of at least one of the third upper bridge-shaped patterns 311 to 316 may be greater than the number of the bridge-shaped patterns of at least one of the first upper bridge-shaped patterns 115 to 119. In some embodiments, the cross-sectional area size of the third upper active pattern AP13 may be equal to the cross-sectional area size of the first upper active pattern AP12.

[0143] Hereinafter, referring to Figures 1 to 43, describes a method for manufacturing a semiconductor device according to some embodiments.

[0144] Figures 16 to 41 is a view of an intermediate structure corresponding to an intermediate step of a method for manufacturing a semiconductor device according to some embodiments. For ease of description, descriptions that are repetitive with those described above with reference to Figures 1 to 15 are briefly elaborated or omitted.

[0145] Referring to Figure 16 and Figure 17 , a base sacrificial film 504, a first active film pAP1, a first sacrificial film 530A, an intermediate sacrificial film 505, a second active film pAP2, a second sacrificial film 530B, and at least one protective film 592 and 594 are formed on a substrate 100. As a reference, Figure 17 is a cross-sectional view taken along line A-A of Figure 16 .

[0146] The base sacrificial film 504 may be formed on the substrate 100. The first active film pAP1 and the first sacrificial film 530A may be alternately stacked on top of each other while being disposed on the base sacrificial film 504. For example, the first active film pAP1 may include at least one lower active film (e.g., active films 511 to 514) sequentially stacked on the base sacrificial film 504. The first sacrificial film 530A may be disposed between adjacent lower active films among the lower active films 511 to 514 and may space adjacent lower active films among the lower active films 511 to 514 apart from each other in a vertical direction (e.g., the third direction Z).

[0147] The intermediate sacrificial film 505 may be formed on the first active film pAP1 and the first sacrificial film 530A. The second active film pAP2 and the second sacrificial film 530B may be alternately stacked on top of each other while being disposed on the intermediate sacrificial film 505. For example, the second active film pAP2 may include upper active films 515 to 518 sequentially stacked on the intermediate sacrificial film 505. The second sacrificial film 530B may be disposed between adjacent upper active films among the upper active films 515 to 518 and may space adjacent upper active films among the upper active films 515 to 518 apart from each other in a vertical direction (e.g., the third direction Z).

[0148] In some embodiments, the thickness of each active film among at least one of the upper active films 515 to 518 may be greater than the thickness of each active film among at least one of the lower active films 511 to 514.

[0149] The first sacrificial film 530A and the second sacrificial film 530B may have an etching selectivity with respect to the first active film pAP1 and the second active film pAP2, respectively. In one example, each of the first active film pAP1 and the second active film pAP2 may include a silicon (Si) film, while each of the first sacrificial film 530A and the second sacrificial film 530B may include a silicon germanium (SiGe) film.

[0150] Each of the base sacrificial film 504 and the intermediate sacrificial film 505 may have an etching selectivity with respect to the substrate 100, the first active film pAP1, the first sacrificial film 530A, the second active film pAP2, and the second sacrificial film 530B. In one example, each of the first sacrificial film 530A and the second sacrificial film 530B may include a silicon germanium (SiGe) film containing a first concentration of germanium (Ge). Each of the base sacrificial film 504 and the intermediate sacrificial film 505 may include a silicon germanium (SiGe) film containing a second concentration of germanium (Ge) that is greater than the first concentration.

[0151] At least one protective film 592 and 594 may be formed on the second active film pAP2 and the second sacrificial film 530B. At least one protective film 592 and 594 may include a variety of materials to protect the first active film pAP1, the first sacrificial film 530A, the second active film pAP2, and / or the second sacrificial film 530B in subsequent processes. In one example, a first protective film 592 including silicon oxide (SiO) and a second protective film 594 including amorphous silicon (a-Si) may be sequentially stacked on the second active film pAP2 and the second sacrificial film 530B.

[0152] Referring Figure 18 and Figure 19 , a first base sacrificial pattern 104S, a second base sacrificial pattern 204S, a first lower active pattern AP11, a first lower sacrificial pattern 531A, a second lower active pattern AP21, a second lower sacrificial pattern 532A, a first intermediate sacrificial pattern 105S, a second intermediate sacrificial pattern 205S, a first upper active pattern AP12, a first upper sacrificial pattern 531B, a second upper active pattern AP22, and a second upper sacrificial pattern 532B are formed on the substrate 100. As a reference, Figure 19 is a cross-sectional view taken along Figure 18 line A-A.

[0153] Each of the first base sacrificial pattern 104S, the second base sacrificial pattern 204S, the first lower active pattern AP11, the first lower sacrificial pattern 531A, the second lower active pattern AP21, the second lower sacrificial pattern 532A, the first intermediate sacrificial pattern 105S, the second intermediate sacrificial pattern 205S, the first upper active pattern AP12, the first upper sacrificial pattern 531B, the second upper active pattern AP22, and the second upper sacrificial pattern 532B may extend in the first direction X. For example, a patterning process may be performed to Figure 16 and Figure 17 pattern the base sacrificial film 504, the first active film pAP1, the first sacrificial film 530A, the intermediate sacrificial film 505, the second active film pAP2, the second sacrificial film 530B, and at least one protective film 592 and 594 of

[0154] In some embodiments, in the process of etching the base sacrificial film 504, a portion of the substrate 100 may be etched to form a first fin pattern 110 on the first region I and a second fin pattern 210 on the second region II.

[0155] Referring to Figure 20 , a first filling insulating film 602 is formed.

[0156] The first filling insulating film 602 may fill the region between the first lower active pattern AP11 and the second lower active pattern AP21 and the region between the first upper active pattern AP12 and the second upper active pattern AP22. For example, the first filling insulating film 602 may cover Figure 19 the resulting structure. The first filling insulating film 602 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. However, embodiments of the present disclosure are not limited thereto. In one example, the first filling insulating film 602 may include a silicon nitride film.

[0157] Referring to Figure 21 , the first base sacrificial pattern 104S, the second base sacrificial pattern 204S, the first intermediate sacrificial pattern 105S, and the second intermediate sacrificial pattern 205S are exposed.

[0158] For example, a portion of the first filling insulating film 602 may be removed, so that the side surfaces of the first base sacrificial pattern 104S, the second base sacrificial pattern 204S, the first intermediate sacrificial pattern 105S, and the second intermediate sacrificial pattern 205S may be exposed. In some embodiments, the portions of the first filling insulating film 602 that fill the regions between the first lower active pattern AP11 and the second lower active pattern AP21 and between the first upper active pattern AP12 and the second upper active pattern AP22 may not be removed.

[0159] Referring toFigure 22 , the first base sacrificial pattern 104S, the second base sacrificial pattern 204S, the first intermediate sacrificial pattern 105S, and the second intermediate sacrificial pattern 205S are removed.

[0160] Each of the first base sacrificial pattern 104S, the second base sacrificial pattern 204S, the first intermediate sacrificial pattern 105S, and the second intermediate sacrificial pattern 205S may have an etching selectivity with respect to the substrate 100, the active patterns AP11, AP12, AP21, and AP22, and the sacrificial patterns 531A, 532A, 531B, and 532B, and thus may be selectively removed.

[0161] Referring to Figure 23 , a second filling insulating film 604 is formed.

[0162] The second filling insulating film 604 may fill the area obtained by removing the first base sacrificial pattern 104S, the second base sacrificial pattern 204S, the first intermediate sacrificial pattern 105S, and the second intermediate sacrificial pattern 205S. For example, the second filling insulating film 604 may cover Figure 22 the resulting structure. The second filling insulating film 604 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. However, embodiments of the present disclosure are not limited thereto. In one example, the second filling insulating film 604 may include a silicon nitride film.

[0163] Referring to Figure 24 , a wall structure 102, a first base insulating film 104, a second base insulating film 204, a first intermediate insulating film 105, and a second intermediate insulating film 205 are formed.

[0164] For example, a field insulating film 106 may be formed on the second filling insulating film 604. The field insulating film 106 may not cover the active patterns AP11, AP12, AP21, and AP22, and the sacrificial patterns 531A, 532A, 531B, and 532B to expose them. For example, the upper surface of the field insulating film 106 may be formed at a vertical height lower than the vertical height of the lower surface of the first lower sheet pattern 111.

[0165] Subsequently, a recess process may be performed on the second filling insulating film 604. Accordingly, the first base insulating film 104 may be formed between the substrate 100 and the first lower active pattern AP11, and the second base insulating film 204 may be formed between the substrate 100 and the second lower active pattern AP21.

[0166] Subsequently, the first fill insulating film 602 provided on at least one of the protective films 592 and 594 can be removed. Subsequently, at least one of the protective films 592 and 594 can be removed. Accordingly, the wall structure 102 that isolates the first lower active pattern AP11 and the second lower active pattern AP21 from each other and isolates the first upper active pattern AP12 and the second upper active pattern AP22 from each other can be formed.

[0167] Referring to Figure 25 and Figure 26 , a first mask pattern MP1 is formed on the second region II of the substrate 100. As a reference, Figure 26 is a cross-sectional view taken along line A-A of Figure 25 .

[0168] The first mask pattern MP1 may cover the second region II of the substrate 100. For example, the first mask pattern MP1 may cover the second lower active pattern AP21, the second lower sacrificial pattern 532A, the second upper active pattern AP22, and the second upper sacrificial pattern 532B. The first mask pattern MP1 may cover at least a portion of the wall structure 102. However, embodiments of the present disclosure are not limited thereto.

[0169] Referring to Figures 27 to 29 , a dummy gate structure DG1 and a first gate spacer 140 are formed on the first region I of the substrate 100. As a reference, Figure 28 is a cross-sectional view taken along line A-A of Figure 27 , and Figure 29 is a cross-sectional view taken along line B-B of Figure 27 .

[0170] The dummy gate structure DG1 may intersect the first lower active pattern AP11, the first lower sacrificial pattern 531A, the first upper active pattern AP12, and the first upper sacrificial pattern 531B. For example, the dummy gate structure DG1 may extend in the second direction Y while being disposed on the first side surface 102a of the wall structure 102.

[0171] In some embodiments, the dummy gate structure DG1 may include a dummy gate dielectric film 520 and a dummy gate electrode 530. For example, a dielectric film and an electrode film may be sequentially stacked on the first region I of the substrate 100. Subsequently, a gate mask 550 extending in the second direction Y may be formed on the electrode film on the first region I. Subsequently, a patterning process may be performed to pattern the dielectric film and the electrode film using the gate mask 550 as an etching mask. The patterned dielectric film may form the dummy gate dielectric film 520. The patterned electrode film may form the dummy gate electrode 530.

[0172] The dummy gate structure DG1 may have an etching selectivity with respect to the first lower active pattern AP11, the first lower sacrificial pattern 531A, the first upper active pattern AP12, and the first upper sacrificial pattern 531B. In one example, the dummy gate electrode 530 may include a polysilicon (poly Si) film.

[0173] Subsequently, a first gate spacer 140 may be formed on the side surface of the dummy gate structure DG1. The first gate spacer 140 may extend along the side surface of the dummy gate structure DG1. The first gate spacer 140 may include at least one of, for example, silicon nitride, silicon oxynitride, silicon carbonitride, boron nitride, boron carbonitride, silicon carbon oxynitride, and combinations thereof. However, embodiments of the present disclosure are not limited thereto.

[0174] Referring to Figure 30 , an etching process is performed on the first lower active pattern AP11, the first lower sacrificial pattern 531A, the first upper active pattern AP12, and the first upper sacrificial pattern 531B.

[0175] For example, the etching process may use the dummy gate structure DG1 and the first gate spacer 140 as etching masks. When the etching process is performed, a first recess 110r may be formed on the outer side surface of the dummy gate structure DG1. In some embodiments, the first recess 110r may be defined on the upper surface of the first base insulating film 104.

[0176] Referring to Figure 31 , a first lower source / drain pattern 160A, a first upper source / drain pattern 160B, and an interlayer insulating film 180 are formed.

[0177] The first lower source / drain pattern 160A may fill the lower part of the first recess 110r. For example, an epitaxial growth process may be performed using the first lower active pattern AP11 as a seed layer. Thus, the first lower source / drain pattern 160A in contact with the first lower active pattern AP11 may be formed.

[0178] The first upper source / drain pattern 160B may fill the upper part of the first recess 110r. For example, a first isolation insulating film 108 may be formed to cover the first lower source / drain pattern 160A and not cover the first upper active pattern AP12 to expose it. Subsequently, an epitaxial growth process using the first upper active pattern AP12 as a seed layer may be performed. Thus, the first upper source / drain pattern 160B in contact with the first upper active pattern AP12 may be formed.

[0179] Subsequently, an interlayer insulating film 180 may be formed to cover the first upper source / drain pattern 160B. The interlayer insulating film 180 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, boron nitride, boron carbonitride, silicon carbon oxynitride, and a low-k dielectric material having a dielectric constant lower than that of silicon oxide. However, embodiments of the present disclosure are not limited thereto.

[0180] Referring to Figure 32 , the dummy gate structure DG1 is removed.

[0181] The dummy gate structure DG1 may have an etching selectivity with respect to the first lower active pattern AP11, the first lower sacrificial pattern 531A, the first upper active pattern AP12, and the first upper sacrificial pattern 531B, and thus may be selectively removed. When the dummy gate structure DG1 is removed, the first lower active pattern AP11, the first lower sacrificial pattern 531A, the first upper active pattern AP12, and the first upper sacrificial pattern 531B may be exposed.

[0182] Referring to Figure 33 , the first lower sacrificial pattern 531A and the first upper sacrificial pattern 531B are removed.

[0183] Each of the first lower sacrificial pattern 531A and the first upper sacrificial pattern 531B may have an etching selectivity with respect to the first lower active pattern AP11 and the first upper active pattern AP12, and thus may be selectively removed.

[0184] Referring to Figures 34 to 36 , a first gate structure GS1 is formed. For reference, Figure 35 is a cross-sectional view taken along line A-A of Figure 34 , and Figure 36 is a cross-sectional view taken along line B-B of Figure 34 .

[0185] For example, a first gate dielectric film 120 and a first gate electrode 130 may be sequentially stacked on the first lower active pattern AP11 and the first upper active pattern AP12. Subsequently, a patterning process may be performed on the first gate dielectric film 120 and the first gate electrode 130. Accordingly, the first gate structure GS1 may be formed to surround the perimeters of at least one first lower bridge-like pattern 111 to 114 and at least one first upper bridge-like pattern 115 to 118.

[0186] Referring to Figure 37 and Figure 38 , a second mask pattern MP2 is formed on the first region I of the substrate 100. For reference, Figure 38 is a cross-sectional view taken along line A-A of Figure 37 .

[0187] The second mask pattern MP2 may cover a first region I of the substrate 100. For example, the second mask pattern MP2 may cover the first lower active pattern AP11, the first upper active pattern AP12, the first lower source / drain pattern 160A and the first upper source / drain pattern 160B, and the first gate structure GS1. The second mask pattern MP2 may cover at least a portion of the wall structure 102. However, embodiments of the present disclosure are not limited thereto.

[0188] Referring to Figures 39 to 41 , a second lower source / drain pattern 260A, a second upper source / drain pattern 260B, and a second gate structure GS2 are formed on a second region II of the substrate 100. As a reference, Figure 40 is a cross-sectional view taken along line A-A of Figure 39 , and Figure 41 is a cross-sectional view taken along line C-C of Figure 39 . Except for forming the second lower source / drain pattern 260A, the second upper source / drain pattern 260B, and the second gate structure GS2 on the second region II of the substrate 100, the second lower source / drain pattern 260A, the second upper source / drain pattern 260B, and the second gate structure GS2 may be formed in a manner similar to the above-described manner of forming the first lower source / drain pattern 160A, the first upper source / drain pattern 160B, and the first gate structure GS1. Therefore, the detailed description thereof is omitted below.

[0189] Next, referring to Figures 1 to 6 , a first gate contact CB1 contacting the first gate structure GS1 and a second gate contact CB2 contacting the second gate structure GS2 are formed. Thus, the semiconductor device described above with reference to Figures 1 to 6 can be manufactured.

[0190] Figure 42 is a view of an intermediate structure corresponding to an intermediate step of a method for manufacturing a semiconductor device according to some embodiments. For ease of description, descriptions that are repetitive of those described above with reference to Figures 1 to 41 are briefly elaborated or omitted.

[0191] Referring to Figure 42 , the second active film pAP2 may include at least one upper active film (e.g., upper active films 515 to 519) sequentially stacked on the intermediate sacrificial film 505. As a reference, Figure 42 is another cross-sectional view taken along line A-A of Figure 16 .

[0192] In some embodiments, the number of upper active films 515 to 519 may be greater than the number of lower active films 511 to 514.

[0193] Subsequently, the above-described operations may be performed with reference toFigures 18 to 41 The steps described above. Thus, a semiconductor device as described above with reference to Figure 8 and Figure 9 can be manufactured.

[0194] Figure 43 is a diagram of an intermediate structure corresponding to an intermediate step of a method for manufacturing a semiconductor device according to some embodiments. For ease of description, descriptions that are repetitive with those described above with reference to Figures 1 to 41 are briefly elaborated or omitted.

[0195] Referring to Figure 43 , the second active film pAP2 may include at least one upper active film (e.g., upper active films 515 to 518) sequentially stacked on the intermediate sacrificial film 505. As a reference, Figure 43 is another cross-sectional view taken along line A-A of Figure 16 .

[0196] In some embodiments, each of some of the upper active films 515 to 518 among the plurality of upper active films may have a thickness different from the thickness of each of the other upper active films among the plurality of upper active films 515 to 518.

[0197] Subsequently, the steps described above with reference to Figures 18 to 41 can be performed. Thus, a semiconductor device as described above with reference to Figure 10 and Figure 11 can be manufactured.

[0198] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the present disclosure. Therefore, the disclosed preferred embodiments of the present disclosure are for general and descriptive purposes only and not for the purpose of limitation.

[0199] Terms such as "same", "equal", "plane", "coplanar", "parallel", and "perpendicular" as used herein encompass equivalency or approximate equivalency including variations that may occur (e.g., due to manufacturing processes). Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize such meaning.

Claims

1. A semiconductor device, comprising: A substrate; A wall structure disposed on the substrate and extending in a first direction, wherein the wall structure includes a first side surface and a second side surface opposite to the first side surface in a second direction intersecting the first direction; A first lower active pattern disposed on the first side surface and including at least one first lower bridge-like pattern spaced apart from the substrate; A first upper active pattern disposed on the first side surface and including at least one first upper bridge-like pattern spaced farther from the substrate than the first lower active pattern; A first gate structure disposed on the first side surface and intersecting the first lower active pattern and the first upper active pattern; A second lower active pattern disposed on the second side surface and including at least one second lower bridge-like pattern spaced apart from the substrate; A second upper active pattern disposed on the second side surface and including at least one second upper bridge-like pattern spaced farther from the substrate than the second lower active pattern; and A second gate structure disposed on the second side surface and intersecting the second lower active pattern and the second upper active pattern, wherein the width of the wall structure in the second direction increases as the wall structure extends away from the substrate.

2. The semiconductor device according to claim 1, wherein, The at least one first lower bridge-like pattern is a plurality of lower sheet-like patterns, and the at least one first upper bridge-like pattern is a plurality of upper sheet-like patterns, and The width in the second direction of each sheet-like pattern among the plurality of upper sheet-like patterns is smaller than the width in the second direction of each sheet-like pattern among the plurality of lower sheet-like patterns.

3. The semiconductor device according to claim 1, wherein, A third direction intersects the first direction and the second direction, wherein the thickness in the third direction of each bridge-like pattern among the at least one first upper bridge-like patterns is greater than the thickness in the third direction of each bridge-like pattern among the at least one first lower bridge-like patterns.

4. The semiconductor device according to claim 1, wherein, The number of bridge-like patterns of the at least one first upper bridge-like pattern is greater than the number of bridge-like patterns of the at least one first lower bridge-like pattern.

5. The semiconductor device according to claim 1, further comprising: A base insulating film disposed between the substrate and the first lower active pattern to electrically insulate the substrate and the first lower active pattern from each other.

6. The semiconductor device according to claim 1, further comprising: An intermediate insulating film disposed between the first lower active pattern and the first upper active pattern to electrically insulate the first lower active pattern and the first upper active pattern from each other.

7. The semiconductor device according to claim 1, wherein, The first gate structure includes a gate dielectric film and a gate electrode sequentially stacked on the first lower active pattern and the first upper active pattern, wherein a part of the gate dielectric film is disposed between the wall structure and the gate electrode.

8. The semiconductor device according to claim 1, further comprising: A first lower source / drain pattern disposed on a side surface of the first gate structure and contacting the first lower active pattern in the first direction; A first upper source / drain pattern disposed on a side surface of the first gate structure and contacting the first upper active pattern in the first direction; A second lower source / drain pattern disposed on a side surface of the second gate structure and contacting the second lower active pattern in the first direction; And A second upper source / drain pattern disposed on a side surface of the second gate structure and contacting the second upper active pattern in the first direction.

9. The semiconductor device according to claim 8, wherein, Each of the first lower source / drain pattern and the first upper source / drain pattern includes impurities of a first conductivity type. Wherein, each of the second lower source / drain pattern and the second upper source / drain pattern includes impurities of a second conductivity type different from the first conductivity type.

10. The semiconductor device according to claim 8, wherein, Each of the first lower source / drain pattern and the second lower source / drain pattern includes impurities of a first conductivity type. Wherein, each of the first upper source / drain pattern and the second upper source / drain pattern includes impurities of a second conductivity type different from the first conductivity type.

11. A semiconductor device, comprising: A substrate; A wall structure disposed on the substrate and extending in a first direction, wherein the wall structure includes a first side surface and a second side surface opposite to the first side surface in a second direction intersecting the first direction; A first lower active pattern disposed on the first side surface and including at least one first lower bridge-like pattern spaced apart from the substrate; A first upper active pattern disposed on the first side surface and including at least one first upper bridge-like pattern spaced further from the substrate than the first lower active pattern; A first gate structure disposed on the first side surface and intersecting the first lower active pattern and the first upper active pattern; A second lower active pattern disposed on the second side surface and including at least one second lower bridge-like pattern spaced apart from the substrate; A second upper active pattern disposed on the second side surface and including at least one second upper bridge-like pattern spaced further from the substrate than the second lower active pattern; and A second gate structure disposed on the second side surface and intersecting the second lower active pattern and the second upper active pattern, Wherein, the width in the second direction of each of the at least one first upper bridge-like patterns is less than the width in the second direction of each of the at least one first lower bridge-like patterns, Wherein, a third direction intersects the first direction and the second direction, and the thickness in the third direction of each of the at least one first upper bridge-like patterns is greater than the thickness in the third direction of each of the at least one first lower bridge-like patterns.

12. The semiconductor device according to claim 11, wherein, The width of the wall structure in the second direction increases as the wall structure extends away from the substrate.

13. The semiconductor device according to claim 11, wherein, The thickness in the third direction of each of the at least one second upper bridge-like patterns is greater than the thickness in the third direction of each of the at least one second lower bridge-like patterns.

14. The semiconductor device according to claim 11, wherein, The at least one first lower bridge-like pattern includes a first lower sheet-like pattern and an adjacent second lower sheet-like pattern stacked in sequence on the substrate and spaced apart from each other, Wherein, the at least one first upper bridge-like pattern includes a first upper sheet-like pattern and an adjacent second upper sheet-like pattern stacked in sequence on the first lower active pattern and spaced apart from each other, Wherein, the interval in the third direction between the first upper sheet-like pattern and the second upper sheet-like pattern is less than the interval in the third direction between the first lower sheet-like pattern and the second lower sheet-like pattern.

15. The semiconductor device according to claim 11, wherein, The area size of the cross-section of the first upper active pattern intersecting the first direction is equal to the area size of the cross-section of the first lower active pattern intersecting the first direction.

16. A semiconductor device, comprising: A substrate; A wall structure is provided on a substrate and extends in a first direction. The wall structure includes a first side surface and a second side surface opposite the first side surface in a second direction intersecting the first direction; A first lower active pattern is provided on the first side surface and includes at least one first lower sheet-like pattern spaced apart from the substrate; A first upper active pattern is provided on the first side surface and includes at least one first upper sheet-like pattern spaced further from the substrate than the first lower active pattern; A first gate structure is provided on the first side surface and intersects the first lower active pattern and the first upper active pattern; A second lower active pattern is provided on the second side surface and includes at least one second lower sheet-like pattern spaced apart from the substrate; A second upper active pattern is provided on the second side surface and includes at least one second upper sheet-like pattern spaced further from the substrate than the second lower active pattern; and A second gate structure is provided on the second side surface and intersects the second lower active pattern and the second upper active pattern, wherein the width in the second direction of each sheet-like pattern in the at least one first upper sheet-like pattern is less than the width in the second direction of each sheet-like pattern in the at least one first lower sheet-like pattern, wherein the number of sheet-like patterns in the at least one first upper sheet-like pattern is greater than the number of sheet-like patterns in the at least one first lower sheet-like pattern.

17. The semiconductor device according to claim 16, wherein, The width of the wall structure in the second direction increases as the wall structure extends away from the substrate.

18. The semiconductor device according to claim 16, wherein, The number of sheet-like patterns in the at least one second upper sheet-like pattern is greater than the number of sheet-like patterns in the at least one second lower sheet-like pattern.

19. The semiconductor device according to claim 16, wherein, The at least one first lower sheet-like pattern includes a lower sheet-like pattern and an adjacent lower sheet-like pattern that are sequentially stacked on the substrate and spaced apart from each other, wherein the at least one first upper sheet-like pattern includes an upper sheet-like pattern and an adjacent upper sheet-like pattern that are sequentially stacked on the first lower active pattern and spaced apart from each other, wherein the spacing in a third direction perpendicular to the first direction and the second direction between the upper sheet-like pattern and the adjacent upper sheet-like pattern is less than the spacing in the third direction between the lower sheet-like pattern and the adjacent lower sheet-like pattern.

20. The semiconductor device according to claim 16, wherein, The area size of the cross-section of the first upper active pattern intersecting the first direction is equal to the area size of the cross-section of the first lower active pattern intersecting the first direction.

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