Double-groove power device and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductor devices, and relates to a double-trench power device and a preparation method thereof, comprising an epitaxial wafer, a source trench, a gate trench, a first metal contact hole, an isolation oxide layer and a metal layer. The epitaxial wafer is provided with a plurality of first grooves which are separately arranged, and a second groove is arranged between every two adjacent first grooves; wherein an MESA region is arranged between the adjacent first groove and second groove. The source trench is disposed in the first trench, and the upper surface of the source trench is lower than the upper surface of the MESA region. A gate trench is disposed within the second trench. The first metal contact hole is arranged on the upper surface of the source trench in the first trench, the bottom of the first metal contact hole extends to the source polysilicon layer in the source trench, and the side wall of the first metal contact hole is contacted with the source region in the MESA region on the side wall of the first trench. And the isolation oxide layer is arranged on the MESA region and the upper surface of the gate trench. The metal layer is arranged on the upper surfaces of the isolation oxide layer and the first metal contact hole. The double-groove power device provided by the scheme has good switching characteristics, conduction performance and integration level.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a double-trench power device and a manufacturing method thereof. Background Art

[0002] The double-trench power device (Double-Trench Device) is a common structure in semiconductor devices, that is, two trench structures, namely, a gate trench and a source trench, are designed on an epitaxial wafer. This double-trench design can avoid the concentration of the electric field near a single trench, thereby improving the breakdown voltage performance and reliability of the device.

[0003] The existing double-trench power device includes an epitaxial wafer, a source trench, a gate trench, a body region, a source region, an isolation oxide layer, a metal contact hole, and a metal layer; wherein, multiple trenches are provided on the epitaxial wafer, and there is a MESA region between two adjacent trenches. A source trench is provided at the middle position in each trench. The source trench includes a source functional layer composed of a source polysilicon layer and a source oxide layer. Gate trenches are provided on both sides of the source trench in each trench. The gate trench includes a gate functional layer composed of a gate polysilicon layer and a gate oxide layer. The source region and the body region are provided in the MESA region. The isolation oxide layer is provided on the top of the MESA region, the source trench, and the gate trench. The metal contact hole penetrates through the isolation oxide layer and extends to the source region and the body region in the MESA region. The metal layer is provided on the top of the isolation oxide layer and the metal contact hole. When a voltage is applied to the gate functional layer to turn on the device, an external current will flow into the source region and the body region through the metal contact hole, and flow to the drain through a conductive channel. The source trench is used to protect the oxide layer at the bottom of the gate trench and reduce the gate electric field distribution, thereby improving the breakdown voltage performance of the device.

[0004] In the existing double-trench power device, the close arrangement of the source trench and the gate trench will increase the mutual interference between the source electric field and the gate electric field, increase the capacitive coupling effect of the device, resulting in an increase in the parasitic capacitance of the device. At the same time, since the metal contact hole is provided in the source region and the body region in the MESA region, the equivalent contact area with the trench is small, resulting in a large contact resistance of the device. Therefore, the large parasitic capacitance and contact resistance make the switching performance and conduction performance of the device poor; in addition, when reducing the feature size of the cell to improve the integration of the device, the metal contact hole will inevitably be close to the trench. At this time, the conductivity of the metal will cause charges to accumulate near the metal contact hole, and an electric field enhancement phenomenon will occur at the edge of the trench. This uneven electric field distribution phenomenon will make the device more likely to be broken down in the region with too high an electric field strength, thereby resulting in a decrease in the breakdown voltage ability and reliability of the device.

[0005] In summary, the existing double-groove power device structure has poor switching performance and conduction performance, and when reducing the cell feature size, it will cause the breakdown voltage performance and reliability of the device to decline, thus limiting the improvement of device integration. Summary of the Invention

[0006] For this reason, the technical problem to be solved by the present invention is to overcome the problem that the existing double-groove power device structure has poor switching performance and conduction performance, and when reducing the cell feature size, it will cause the breakdown voltage performance and reliability of the device to decline, thus limiting the improvement of device integration.

[0007] To solve the above technical problem, the present invention provides a double-groove power device, including: An epitaxial wafer, on which there are a plurality of discretely arranged first grooves, and a second groove is arranged between two adjacent first grooves; wherein, there is a MESA region between an adjacent first groove and the second groove; A source trench, arranged in the first groove, and its upper surface is lower than the upper surface of the MESA region; A gate trench, arranged in the second groove; A first metal contact hole, arranged on the upper surface of the source trench in the first groove, its bottom extends to the source polysilicon layer in the source trench, and its sidewall is in contact with the source region in the MESA region on the sidewall of the first groove; An isolation oxide layer, arranged on the upper surfaces of the MESA region and the gate trench; A metal layer, arranged on the upper surfaces of the isolation oxide layer and the first metal contact hole.

[0008] Preferably, the depth of the first groove is greater than the depth of the second groove.

[0009] Preferably, it further includes: A second metal contact hole, penetrating through the isolation oxide layer on the upper surface of the gate trench and extending to the gate polysilicon layer in the gate trench.

[0010] Preferably, the width of the first groove is 1.0 μm to 4.0 μm, and the depth of the first groove is 5.0 μm to 10.0 μm; and / or, The width of the second groove is 0.18 μm to 1.0 μm, and the depth of the second groove is 1.0 μm to 3.0 μm; and / or, The distance between the upper surface of the source trench and the upper surface of the MESA region is 0.3 μm to 0.5 μm; and / or, The depth of the first metal contact hole extending into the source polysilicon layer is 0.25 μm to 0.4 μm.

[0011] Preferably, the thickness of the source oxide layer in the source trench is 2000 Å to 10000 Å; and / or, The thickness of the first gate oxide layer located at the bottom of the second trench in the gate trench is 200 Å to 500 Å; and / or, The thickness of the second gate oxide layer located on the sidewall of the second trench in the gate trench is 400 Å to 800 Å; and / or, The distance between the upper surface of the gate polysilicon layer in the gate trench and the upper surface of the MESA region is 500 Å to 1000 Å.

[0012] The present invention also provides a method for manufacturing a double-trench power device, which is used to manufacture the above-mentioned double-trench power device, and includes: Form a plurality of first trenches on the epitaxial wafer, and form a second trench between two adjacent first trenches; wherein, there is a MESA region between the adjacent first trench and the second trench; Form a source trench in the first trench, form a gate trench in the second trench, and form an isolation oxide layer on the upper surface of the MESA region and the gate trench; wherein, the upper surface of the source trench is lower than the upper surface of the MESA region; Form a first metal contact hole on the upper surface of the source trench in the first trench, and form a metal layer on the upper surface of the isolation oxide layer and the first metal contact hole; wherein, the bottom of the first metal contact hole extends to the source polysilicon layer in the source trench, and the sidewall of the first metal contact hole is in contact with the source region in the MESA region on the sidewall of the first trench.

[0013] Preferably, forming a source trench in the first trench, forming a gate trench in the second trench, and forming an isolation oxide layer on the upper surface of the MESA region and the gate trench includes: Deposit a source oxide layer on the sidewall, bottom of the first trench and in the second trench; wherein, the source oxide layer in the first trench has a third trench; Deposit a source polysilicon layer in the third trench; wherein, the upper surface of the source polysilicon layer is flush with the upper surface of the MESA region; Perform ion implantation and push-anneal activation on the MESA region to form a source region and a body region, form an isolation oxide layer on the surfaces of the MESA region, the source oxide layer, the source polysilicon layer and the gate trench, and etch and remove the isolation oxide layer on the surfaces of the source oxide layer and the source polysilicon layer; Etch the source oxide layer and the source polysilicon layer until the upper surfaces of the source oxide layer and the source polysilicon layer are lower than the upper surface of the MESA region, to obtain a source trench.

[0014] Preferably, forming a gate trench in the second trench includes: Etch a part of the source oxide layer in the second trench, and use the source oxide layer located at the bottom of the second trench as the first gate oxide layer; form a second gate oxide layer on the sidewall of the second trench, and the first gate oxide layer and the second gate oxide layer have a fourth trench; A gate polysilicon layer is formed in the fourth trench, and a third gate oxide layer is formed on top of the gate polysilicon layer. The gate trench is obtained based on the first gate oxide layer, the second gate oxide layer, the gate polysilicon layer, and the third gate oxide layer in the second trench.

[0015] Preferably, a first metal contact hole is formed on the upper surface of the source trench in the first trench. Forming a metal layer on the isolation oxide layer and the upper surface of the first metal contact hole includes: Etch the source polysilicon layer in the source trench to form a first contact hole, and perform ion implantation, annealing, and activation on the bottom of the first contact hole; Fill a tungsten plug in the first contact hole and on the upper surface of the source trench to form a first metal contact hole; deposit a metal layer on the isolation oxide layer and the surface of the first metal contact hole.

[0016] Preferably, it further includes: Etch the isolation oxide layer on the upper surface of the gate trench and the gate polysilicon layer in the gate trench to form a second contact hole, and perform ion implantation, annealing, and activation on the bottom of the second contact hole; Fill a tungsten plug in the second contact hole to form a second metal contact hole.

[0017] The dual-trench power device provided by the present invention has the following beneficial effects: 1. Multiple discrete first trenches are provided on the epitaxial wafer in this application. A second trench is provided between two adjacent first trenches. The epitaxial wafer between the adjacent first trenches and the second trench is used as the MESA region. The source trench is arranged in the first trench, and the gate trench is arranged in the second trench, so that there is a certain physical distance between the source trench and the gate trench, effectively isolating the source electric field and the gate electric field, reducing the mutual influence between the gate and the source, thereby reducing the capacitive coupling effect and the parasitic capacitance of the device. On this basis, by restricting the upper surface of the source trench to be lower than the upper surface of the MESA region and directly arranging the first metal contact hole on the upper surface of the source trench, the bottom of the first metal contact hole extends to the source polysilicon layer, and its sidewall is in contact with the source region of the MESA region. The source polysilicon layer is used as the current contact platform. When the gate voltage is controlled to turn on the device, part of the external current flows into the source trench through the metal contact hole and then diffuses to the source region and the body region, and another part of the external current directly flows to the source region through the metal contact hole and finally flows to the drain through the conductive channel. This design increases the contact area between the metal contact hole and the source trench, reduces the contact resistance between the two, and enables the external current to enter the device more smoothly; therefore, the double-trench power device designed in this application reduces the parasitic capacitance and the contact resistance of the device at the same time, thereby improving the switching performance and the on-state performance of the device; in addition, since the first metal contact hole is arranged above the source trench and extends to the source polysilicon layer, the carriers in the source polysilicon layer can neutralize the charges near the metal contact hole, reducing the degree of charge aggregation. At the same time, the conductivity of the source polysilicon layer can also transfer the charges aggregated around the metal contact hole to other regions. Even when the cell feature size is reduced, the source polysilicon layer connected to the metal contact hole can be used to improve the electric field distribution characteristics, making the electric field distribution more uniform, thereby ensuring the breakdown voltage performance and reliability of the device while improving the device integration.

[0018] 2. When the depth of the first trench is greater than the depth of the second trench, the arrangement of the deep and shallow trenches enables the deeper source trench to provide a good current path for the device. At the same time, the relative area between the shallower gate trench and the deeper source trench is reduced, so that the gate electrode and the source electrode do not interfere with each other, effectively reducing the capacitive coupling effect between the gate electrode and the source electrode, thereby further reducing the parasitic capacitance of the device, improving the switching speed of the device, and optimizing the switching characteristics of the device.

[0019] 3. Arranging a second metal contact hole in the gate trench can make the gate polysilicon layer periodically short-circuited with the source polysilicon layer, thereby reducing the input capacitance, Miller capacitance and gate charge of the device, and thus reducing the FOM figure of merit of the device, that is, reducing the energy loss of the device during the on-state and switching processes, and further improving the performance of the device. Description of the Drawings

[0020] To make the content of the present invention easier to be clearly understood, the following further details the present invention according to specific embodiments of the present invention and in conjunction with the accompanying drawings, where: Figure 1 Schematic structural diagram of the first double-groove power device provided by this application; Figure 2 Three-dimensional structural diagram of the first double-groove power device provided by this application; Figure 3 Schematic structural diagram of the second double-groove power device provided by this application; Figure 4 Flow chart of the preparation method of the double-groove power device provided by this application; Figure 5 Flow chart of the trench etching process provided by this application; where, Figure 5 (a) in is a schematic diagram of forming a first trench etching photoresist on an epitaxial wafer, Figure 5 (b) in is in Figure 5 (a) in is a schematic diagram of etching to obtain a first trench, Figure 5 (c) in is in Figure 5 (b) in is a schematic diagram of etching to obtain a second trench; Figure 6 Flow chart of the preparation process of the source function layer provided by this application; where, Figure 6 (a) in is a schematic diagram of preparing a source oxide layer, Figure 6 (b) in is in Figure 6 (a) in is a schematic diagram of preparing a source polysilicon layer; Figure 7 Flow chart of the preparation process of the gate function layer provided by this application; where, Figure 7 (a) in is a schematic diagram of preparing a first gate oxide layer, Figure 7 (b) in is in Figure 7 (a) in is a schematic diagram of forming a second gate oxide layer, Figure 7 (c) in is in Figure 7 (b) in is a schematic diagram of forming a gate polysilicon layer and a third gate oxide layer; Figure 8 Flow chart of the preparation process of the isolation oxide layer provided by this application; where, Figure 8 (a) in is a schematic diagram of depositing an isolation oxide layer, Figure 8 (b) in is a schematic diagram of etching the isolation oxide layer on the upper surface of the source trench and the source trench; Figure 9 Flow chart of the preparation process of the first metal contact hole and the metal layer provided by this application; where, Figure 9 (a) in is a schematic diagram of forming a first metal contact hole, Figure 9In (b) is a schematic diagram of forming a metal layer on (a) in Figure 9 ; Description of the reference numerals in the accompanying drawings: 1, epitaxial wafer; 11, first trench; 12, second trench; 13, MESA region; 131, source region; 132, body region; 14, photoresist; 2, source trench; 21, source oxide layer; 211, third trench; 22, source polysilicon layer; 221, first contact hole; 3, gate trench; 31, first gate oxide layer; 32, second gate oxide layer; 33, gate polysilicon layer; 34, third gate oxide layer; 35, fourth trench; 4, first metal contact hole; 41, tungsten plug; 5, isolation oxide layer; 6, metal layer; 7, second metal contact hole. Detailed implementation manners

[0021] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, so that those skilled in the art can better understand the present invention and be able to implement it, but the specific embodiments cited are not intended to limit the present invention.

[0022] Please refer to Figure 1 , Figure 1 which shows a schematic structural diagram of a double-trench power device provided by the present application, Figure 2 and which shows a three-dimensional structural diagram of the double-trench power device. The double-trench power device includes an epitaxial wafer 1, a source trench 2, a gate trench 3, a first metal contact hole 4, an isolation oxide layer 5 and a metal layer 6.

[0023] The epitaxial wafer 1 has a plurality of discretely arranged first trenches 11, and a second trench 12 is arranged between two adjacent first trenches 11; wherein, a MESA region 13 is provided between an adjacent first trench 11 and the second trench 12.

[0024] The source trench 2 is arranged in the first trench 11, and its upper surface is lower than the upper surface of the MESA region 13.

[0025] The gate trench 3 is arranged in the second trench 12.

[0026] The first metal contact hole 4 is arranged on the upper surface of the source trench 2 in the first trench 11, its bottom extends to the source polysilicon layer 22 in the source trench 2, and its side wall is in contact with the source region 131 in the MESA region 13 on the side wall of the first trench 11.

[0027] The isolation oxide layer 5 is arranged on the upper surfaces of the MESA region 13 and the gate trench 3.

[0028] The metal layer 6 is arranged on the upper surfaces of the isolation oxide layer 5 and the first metal contact hole 4.

[0029] In this application, by separately arranging the gate trench and the source trench, a certain physical distance is created between the source trench and the gate trench, effectively isolating the source electric field and the gate electric field, reducing the mutual influence between the gate and the source, thereby reducing the capacitance coupling effect and the parasitic capacitance of the device. On this basis, by restricting the upper surface of the source trench to be lower than the upper surface of the MESA region and directly arranging the first metal contact hole on the upper surface of the source trench, the bottom of the first metal contact hole extends to the source polysilicon layer, and its sidewall is in contact with the source region of the MESA region. Using the source polysilicon layer as a current contact platform directly increases the contact area between the metal contact hole and the source trench and reduces the contact resistance. Therefore, by simultaneously reducing the parasitic capacitance and the contact resistance of the device, the switching performance and the conduction performance of the device are improved. In addition, since the first metal contact hole is arranged above the source trench and extends to the source polysilicon layer, the source polysilicon layer, the body region, and the source region are at the same potential. The carriers in the source polysilicon layer can neutralize the charges near the metal contact hole, reducing the degree of charge accumulation. At the same time, the conductivity of the source polysilicon layer can also transfer the charges accumulated around the metal contact hole to other regions. Even when reducing the cell feature size, the source polysilicon layer connected to the metal contact hole can be used to improve the electric field distribution characteristics, making the electric field distribution more uniform, thereby ensuring the breakdown voltage performance and reliability of the device while improving the device integration degree.

[0030] Preferably, the depth of the first trench 11 is greater than the depth of the second trench 12. Through the setting of such deep and shallow trenches, the deeper source trench 2 can provide a good current path for the device. At the same time, the relative area between the shallower gate trench 3 and the deeper source trench 2 is reduced, so that the gate electrode and the source electrode do not interfere with each other, effectively reducing the capacitance coupling effect between the gate electrode and the source electrode, thereby further reducing the parasitic capacitance of the device, improving the switching speed of the device, and optimizing the switching characteristics of the device.

[0031] Further, the width of the first trench 11 is 1.0 μm to 4.0 μm, and the depth of the first trench 11 is 5.0 μm to 10.0 μm. For example, the width of the first trench 11 can be 1.0 μm, 1.5 μm, 2.0 μm, 2.5 μm, 3.0 μm, 3.5 μm, 4.0 μm; the depth of the first trench 11 can be 5.0 μm, 5.5 μm, 6.0 μm, 6.5 μm, 7.0 μm, 7.5 μm, 8.0 μm, 8.5 μm, 9.0 μm, 9.5 μm, 10.0 μm.

[0032] Further, the width of the second trench 12 is 0.18 μm to 1.0 μm, and the depth of the second trench 12 is 1.0 μm to 3.0 μm. For example, the width of the second trench 12 can be 0.18 μm, 0.3 μm, 0.42 μm, 0.54 μm, 0.66 μm, 0.78 μm, 0.9 μm, 1.0 μm; the depth of the second trench 12 can be 1.0 μm, 1.5 μm, 2.0 μm, 2.5 μm, 3.0 μm.

[0033] Further, as Figure 3 shown in the structural schematic diagram of another double-trench power device provided by the present application, the double-trench power device further includes a second metal contact hole 7.

[0034] The second metal contact hole 7 penetrates through the isolation oxide layer 5 on the upper surface of the gate trench 3 and extends to the gate polysilicon layer 33 in the gate trench 3.

[0035] Optionally, in some embodiments of the present application, the second metal contact hole 7 can be provided on some of the gate trenches 3, or can be provided on all of the gate trenches 3.

[0036] By providing the second metal contact hole on the gate trench, the gate polysilicon layer can be periodically short-circuited with the source polysilicon layer. Since the input capacitance of the device is composed of the parallel connection of the gate-source capacitance and the gate-drain capacitance, when the gate polysilicon layer and the source polysilicon layer are short-circuited, part of the capacitance originally existing between the gate and the source is short-circuited, thereby reducing the input capacitance of the device; and, after the gate polysilicon layer and the source polysilicon layer are short-circuited, it is equivalent to adding a low-impedance path between the gate and the drain, enabling the gate potential to change more quickly with the drain voltage, thereby reducing the Miller capacitance; further, the reduction of the input capacitance and the Miller capacitance means that the gate charge is reduced during the device switching process, thereby reducing the FOM figure of merit of the device and improving the switching performance and conduction performance of the device.

[0037] Specifically, as Figure 1 shown in, the source trench 2 includes a source oxide layer 21 located at the bottom and side walls of the first trench 11, and a source polysilicon layer 22 covered by the source oxide layer 21.

[0038] Further, the distance between the upper surface of the source trench 2 and the upper surface of the MESA region 13 is 0.3 μm to 0.5 μm. For example, the distance between the upper surface of the source trench 2 and the upper surface of the MESA region 13 can be 0.3 μm, 0.32 μm, 0.34 μm, 0.36 μm, 0.38 μm, 0.40 μm, 0.42 μm, 0.44 μm, 0.46 μm, 0.48 μm, 0.50 μm.

[0039] Further, the depth to which the first metal contact hole 4 extends into the source polysilicon layer 22 is 0.25 μm to 0.4 μm. For example, the depth to which the first metal contact hole 4 extends into the source polysilicon layer 22 can be 0.25 μm, 0.28 μm, 0.31 μm, 0.34 μm, 0.37 μm, or 0.40 μm.

[0040] Further, the thickness of the source oxide layer 21 in the source trench 2 is 2000 Å to 10000 Å. For example, the thickness of the source oxide layer 21 can be 2000 Å, 3000 Å, 4000 Å, 5000 Å, 6000 Å, 7000 Å, 8000 Å, 9000 Å, or 10000 Å.

[0041] Specifically, as Figure 1 shown, the gate trench 3 includes a first gate oxide layer 31 at the bottom of the second trench 12, a second gate oxide layer 32 on the sidewall of the second trench 12, a gate polysilicon layer 33 coated by the first gate oxide layer 31 and the second gate oxide layer 32, and a third gate oxide layer 34 on the top of the gate polysilicon layer 33.

[0042] Further, the thickness of the first gate oxide layer 31 at the bottom of the second trench 12 in the gate trench 3 is 200 Å to 500 Å. For example, the thickness of the first gate oxide layer 31 can be 200 Å, 250 Å, 300 Å, 350 Å, 400 Å, 450 Å, or 500 Å.

[0043] The provision of the relatively thick first gate oxide layer 31 at the bottom of the gate trench 3 can provide the ability of the bottom of the gate trench 3 to withstand high electric field impact, thereby improving the breakdown voltage performance and reliability of the device.

[0044] Further, the thickness of the second gate oxide layer 32 on the sidewall of the second trench 12 in the gate trench 3 is 400 Å to 800 Å. For example, the thickness of the second gate oxide layer 32 can be 400 Å, 450 Å, 500 Å, 550 Å, 600 Å, 650 Å, 700 Å, 750 Å, or 800 Å.

[0045] Further, the distance between the upper surface of the gate polysilicon layer 33 in the gate trench 3 and the upper surface of the MESA region 13 is 500 Å to 1000 Å. For example, the distance between the upper surface of the gate polysilicon layer 33 and the upper surface of the MESA region 13 can be 500 Å, 550 Å, 600 Å, 650 Å, 700 Å, 750 Å, 800 Å, 850 Å, 900 Å, 950 Å, or 1000 Å.

[0046] The embodiment of the present application also provides a preparation method for the above double-trench power device. As Figure 4 shown is the flow chart of the preparation method for the double-trench power device. The method specifically includes: S10: Form a plurality of first trenches on the epitaxial wafer, and form second trenches between two adjacent first trenches; wherein, there is a MESA region between the adjacent first trenches and second trenches.

[0047] S20: Form source trenches in the first trenches, form gate trenches in the second trenches, and form an isolation oxide layer on the MESA region and the upper surface of the gate trenches; wherein, the upper surface of the source trenches is lower than the upper surface of the MESA region.

[0048] S30: Form first metal contact holes on the upper surface of the source trenches in the first trenches, and form a metal layer on the upper surface of the isolation oxide layer and the first metal contact holes; wherein, the bottom of the first metal contact holes extends to the source polysilicon layer in the source trenches, and the side walls of the first metal contact holes are in contact with the source regions in the MESA regions on the side walls of the first trenches.

[0049] The present application also provides another preparation method of a double trench power device to further explain the above preparation method of the double trench power device, as Figures 5 to 9 shown, wherein, Figure 5 is a process flow chart of trench etching, Figure 6 is a process flow chart of preparing the source functional layer, Figure 7 is a process flow chart of preparing the gate functional layer, Figure 8 is a process flow chart of preparing the isolation oxide layer, Figure 9 is a process flow chart of preparing the first metal contact holes and the metal layer, and this preparation method specifically includes: S100: Provide a medium-doped silicon substrate wafer, and form an epitaxial layer on the silicon substrate wafer to obtain epitaxial wafer 1.

[0050] S101: Form a photoresist 14 for etching the first trenches 11 on the surface of the epitaxial wafer 1, as shown in Figure 5 (a) therein.

[0051] S102: Etch the epitaxial wafer 1 based on the photoresist 14 to form a plurality of first trenches 11, as shown in Figure 5 (b) therein.

[0052] Furthermore, the width of the first trenches 11 is 1.0 μm to 4.0 μm, and the depth of the first trenches 11 is 5.0 μm to 10.0 μm.

[0053] S103: Form a photoresist 14 for etching the second trenches 12 on the surface of the epitaxial wafer 1 between the adjacent first trenches 11, and etch the epitaxial wafer 1 based on the photoresist 14 to form second trenches 12 between the adjacent first trenches 11, and form a MESA region 13 between the adjacent first trenches 11 and second trenches 12, as shown in Figure 5 (c) therein.

[0054] Further, the width of the second trench 12 is 0.18 μm to 1.0 μm, and the depth of the second trench 12 is 1.0 μm to 3.0 μm.

[0055] S104: Deposit a source oxide layer 21 on the sidewalls, bottom of the first trench 11, and inside the second trench 12; wherein, the source oxide layer 21 inside the first trench 11 has a third trench 211, as Figure 6 shown in (a) of.

[0056] S105: Deposit a source polysilicon layer 22 in the third trench 211; wherein, the upper surface of the source polysilicon layer 22 is flush with the upper surface of the MESA region 13, as Figure 6 shown in (b) of.

[0057] S106: Etch a part of the source oxide layer 21 inside the second trench 12, and use the source oxide layer 21 located at the bottom of the second trench 12 as a first gate oxide layer 31, as Figure 7 shown in (a) of; form a second gate oxide layer 32 on the sidewalls of the second trench 12, and the first gate oxide layer 31 and the second gate oxide layer 32 have a fourth trench 35, as Figure 7 shown in (b) of.

[0058] S107: Form a gate polysilicon layer 33 in the fourth trench 35, form a third gate oxide layer 34 on the top of the gate polysilicon layer 33, and obtain a gate trench 3 based on the first gate oxide layer 31, the second gate oxide layer 32, the gate polysilicon layer 33, and the third gate oxide layer 34 inside the second trench 12, as Figure 7 shown in (c) of.

[0059] Further, the thickness of the first gate oxide layer 31 is 200 Å to 500 Å, and / or the thickness of the second gate oxide layer 32 is 400 Å to 800 Å, and / or the distance between the upper surface of the gate polysilicon layer 33 and the upper surface of the MESA region 13 is 500 Å to 1000 Å.

[0060] S108: Perform ion implantation and annealing activation on the MESA region 13 to form a source region 131 and a body region 132.

[0061] S109: Form an isolation oxide layer 5 on the surfaces of the MESA region 13, the source oxide layer 21, the source polysilicon layer 22, and the gate trench 3, as Figure 8 shown in (a) of, and etch and remove the isolation oxide layer 5 on the surfaces of the source oxide layer 21 and the source polysilicon layer 22, as Figure 8 shown in (b) of.

[0062] S110: Etch the source oxide layer 21 and the source polysilicon layer 22 until the upper surfaces of the source oxide layer 21 and the source polysilicon layer 22 are lower than the upper surface of the MESA region 12, obtaining the source trench 2.

[0063] Further, the distance between the upper surface of the source trench 2 and the upper surface of the MESA region 13 is 0.3 μm to 0.5 μm.

[0064] Further, the thickness of the source oxide layer 21 in the source trench 2 is 2000 Å to 10000 Å.

[0065] S111: Etch the source polysilicon layer 22 in the source trench 2 to form the first contact hole 221, and perform ion implantation, annealing, and activation on the bottom of the first contact hole 221.

[0066] S112: Fill the tungsten plug 41 in the first contact hole 211 and on the upper surface of the source trench 2 to form the first metal contact hole 4, as shown in (a) of Figure 9 ; Deposit the metal layer 6 on the surface of the isolation oxide layer 5 and the first metal contact hole 4, as shown in (b) of Figure 9 .

[0067] Optionally, in some embodiments, after forming the first metal contact hole 4 and the metal layer 6, it further includes: S113: Etch the isolation oxide layer 5 on the upper surface of the gate trench 3 and the gate polysilicon layer 33 in the gate trench 3 to form the second contact hole, and perform ion implantation, annealing, and activation on the bottom of the second contact hole.

[0068] S114: Fill the tungsten plug in the second contact hole to form the second metal contact hole 7, obtaining the double trench power device as shown in Figure 3 .

[0069] The technical solutions of the present application will be described in more detail below in conjunction with multiple embodiments. However, it should be understood that the following embodiments are only for explaining and illustrating the technical solutions and do not limit the scope of the present application. Embodiment 1

[0070] This embodiment provides a double trench power device, specifically including: an epitaxial wafer, a source trench, a gate trench, a first metal contact hole, an isolation oxide layer, and a metal layer.

[0071] There are multiple discrete first trenches with a depth of 1.0 μm and a width of 5.0 μm on the epitaxial wafer. A second trench with a depth of 0.18 μm and a width of 1.0 μm is provided between adjacent two first trenches. There is a MESA region between the adjacent first trench and the second trench.

[0072] The source trench is disposed within the first trench, and its upper surface is lower than the upper surface of the MESA region, and the distance from the upper surface of the MESA region is 0.3 μm. Among them, the thickness of the source oxide layer is 2000 Å.

[0073] The gate trench is disposed within the second trench. Among them, the thickness of the first gate oxide layer located at the bottom of the second trench is 200 Å, the thickness of the second gate oxide layer located on the sidewall of the second trench is 400 Å, and the distance from the upper surface of the gate polysilicon layer to the upper surface of the MESA region is 500 Å.

[0074] The first metal contact hole is disposed on the upper surface of the source trench within the first trench, and its bottom extends to the source polysilicon layer within the source trench, with an extension depth of 0.25 μm, and its sidewall is in contact with the source region within the MESA region on the sidewall of the first trench.

[0075] The isolation oxide layer is disposed on the upper surfaces of the MESA region and the gate trench.

[0076] The metal layer is disposed on the upper surfaces of the isolation oxide layer and the first metal contact hole. Embodiment 2

[0077] This embodiment provides a double-trench power device, specifically including: an epitaxial wafer, a source trench, a gate trench, a first metal contact hole, an isolation oxide layer, and a metal layer.

[0078] The epitaxial wafer has a plurality of discrete first trenches with a depth of 2.5 μm and a width of 7.5 μm. A second trench with a depth of 0.59 μm and a width of 2.0 μm is provided between adjacent two first trenches, and a MESA region is provided between the adjacent first trench and the second trench.

[0079] The source trench is disposed within the first trench, and its upper surface is lower than the upper surface of the MESA region, and the distance from the upper surface of the MESA region is 0.4 μm. Among them, the thickness of the source oxide layer is 6000 Å.

[0080] The gate trench is disposed within the second trench. Among them, the thickness of the first gate oxide layer located at the bottom of the second trench is 350 Å, the thickness of the second gate oxide layer located on the sidewall of the second trench is 600 Å, and the distance from the upper surface of the gate polysilicon layer to the upper surface of the MESA region is 750 Å.

[0081] The first metal contact hole is disposed on the upper surface of the source trench within the first trench, and its bottom extends to the source polysilicon layer within the source trench, with an extension depth of 0.3 μm, and its sidewall is in contact with the source region within the MESA region on the sidewall of the first trench.

[0082] The isolation oxide layer is disposed on the upper surfaces of the MESA region and the gate trench.

[0083] The metal layer is disposed on the isolation oxide layer and the upper surface of the first metal contact hole. Embodiment 3

[0084] This embodiment provides a double-groove power device, which specifically includes: an epitaxial wafer, a source trench, a gate trench, a first metal contact hole, an isolation oxide layer, and a metal layer.

[0085] The epitaxial wafer has a plurality of first trenches that are separately arranged with a depth of 4.0 μm and a width of 10.0 μm. A second trench with a depth of 1.0 μm and a width of 3.0 μm is arranged between two adjacent first trenches. There is a MESA region between the adjacent first trench and the second trench.

[0086] The source trench is disposed in the first trench, and its upper surface is lower than the upper surface of the MESA region, and the distance from the upper surface of the MESA region is 0.5 μm. Among them, the thickness of the source oxide layer is 10000 Å.

[0087] The gate trench is disposed in the second trench. Among them, the thickness of the first gate oxide layer located at the bottom of the second trench is 500 Å, the thickness of the second gate oxide layer located on the sidewall of the second trench is 800 Å, and the distance between the upper surface of the gate polysilicon layer and the upper surface of the MESA region is 1000 Å.

[0088] The first metal contact hole is disposed on the upper surface of the source trench in the first trench, and its bottom extends to the source polysilicon layer in the source trench, with an extension depth of 0.4 μm, and its sidewall is in contact with the source region in the MESA region of the sidewall of the first trench.

[0089] The isolation oxide layer is disposed on the upper surfaces of the MESA region and the gate trench.

[0090] The metal layer is disposed on the isolation oxide layer and the upper surface of the first metal contact hole.

[0091] The performance of the double-groove power device provided in the above embodiment is tested, and the performance test results shown in Table 1 below are obtained: Table 1 On-resistance Rdson (mΩ) Gate charge Qg (nC) Figure of merit FOM (nC·mR) Example 1 6.8 21 142.8 Example 2 7.4 26 192.4 Example 3 8.9 38 338.2 It can be seen from the table that the double-groove power device provided in this application has a low on-resistance, gate charge, and FOM figure of merit; moreover, by comparing Embodiment 1 to Embodiment 3, it can be found that although the structural parameters are different, the on-resistance, gate charge, and FOM figure of merit are generally not very different, indicating that the double-groove power device provided by this solution has good on-state performance and switching performance.

[0092] Obviously, the above embodiments are merely examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all implementation manners here. And the obvious changes or modifications derived therefrom still fall within the protection scope of the present invention.

Claims

1. A double-groove power device, characterized in that, Including: An epitaxial wafer, on which there are a plurality of discretely arranged first trenches, and a second trench is arranged between two adjacent first trenches; wherein, there is a MESA region between an adjacent first trench and the second trench; A source trench, arranged in the first trench, and its upper surface is lower than the upper surface of the MESA region; A gate trench, arranged in the second trench; A first metal contact hole, arranged on the upper surface of the source trench in the first trench, its bottom extends to the source polysilicon layer in the source trench, and its sidewall is in contact with the source region in the MESA region of the sidewall of the first trench; An isolation oxide layer, arranged on the upper surfaces of the MESA region and the gate trench; A metal layer, arranged on the upper surfaces of the isolation oxide layer and the first metal contact hole.

2. The double-groove power device according to claim 1, wherein The depth of the first trench is greater than the depth of the second trench.

3. The double-groove power device according to claim 1, wherein It further includes: A second metal contact hole, penetrating through the isolation oxide layer on the upper surface of the gate trench and extending to the gate polysilicon layer in the gate trench.

4. The double-trench power device according to claim 1, wherein The width of the first trench is 1.0 μm to 4.0 μm, and the depth of the first trench is 5.0 μm to 10.0 μm; and / or, The width of the second trench is 0.18 μm to 1.0 μm, and the depth of the second trench is 1.0 μm to 3.0 μm; and / or, The distance between the upper surface of the source trench and the upper surface of the MESA region is 0.3 μm to 0.5 μm; and / or, The depth that the first metal contact hole extends into the source polysilicon layer is 0.25 μm to 0.4 μm.

5. The double-trench power device according to claim 1, wherein The thickness of the source oxide layer in the source trench is 2000 Å to 10000 Å; and / or, The thickness of the first gate oxide layer at the bottom of the second trench in the gate trench is 200 Å to 500 Å; and / or, The thickness of the second gate oxide layer on the sidewall of the second trench in the gate trench is 400 Å to 800 Å; and / or, The distance between the upper surface of the gate polysilicon layer in the gate trench and the upper surface of the MESA region is 500 Å to 1000 Å.

6. A manufacturing method of a double-groove power device, characterized in that, The preparation method is used to prepare the double-trench power device according to any one of claims 1 to 5, including: Forming a plurality of first trenches on the epitaxial wafer, and forming a second trench between two adjacent first trenches; wherein, there is a MESA region between an adjacent first trench and the second trench; Forming a source trench in the first trench, forming a gate trench in the second trench, and forming an isolation oxide layer on the upper surfaces of the MESA region and the gate trench; wherein, the upper surface of the source trench is lower than the upper surface of the MESA region; Forming a first metal contact hole on the upper surface of the source trench in the first trench, and forming a metal layer on the upper surfaces of the isolation oxide layer and the first metal contact hole; wherein, the bottom of the first metal contact hole extends to the source polysilicon layer in the source trench, and the sidewall of the first metal contact hole is in contact with the source region in the MESA region of the sidewall of the first trench.

7. The manufacturing method of the double-groove power device according to claim 6, wherein Forming a source trench in the first trench, forming a gate trench in the second trench, and forming an isolation oxide layer on the upper surfaces of the MESA region and the gate trench includes: Deposit a source oxide layer on the sidewalls, bottom of the first trench, and within the second trench; wherein, the source oxide layer within the first trench has a third trench; Deposit a source polysilicon layer within the third trench; wherein, the upper surface of the source polysilicon layer is flush with the upper surface of the MESA region; Perform ion implantation and drive-in activation on the MESA region to form a source region and a body region, form an isolation oxide layer on the surfaces of the MESA region, the source oxide layer, the source polysilicon layer, and the gate trench, and etch away the isolation oxide layer on the surfaces of the source oxide layer and the source polysilicon layer; Etch the source oxide layer and the source polysilicon layer until the upper surfaces of the source oxide layer and the source polysilicon layer are lower than the upper surface of the MESA region, obtaining a source trench.

8. The manufacturing method of the double-groove power device according to claim 7, characterized in that Forming a gate trench within the second trench includes: Etch a portion of the source oxide layer within the second trench, and use the source oxide layer located at the bottom of the second trench as a first gate oxide layer; form a second gate oxide layer on the sidewalls of the second trench, and the first gate oxide layer and the second gate oxide layer have a fourth trench; Form a gate polysilicon layer within the fourth trench, form a third gate oxide layer on the top of the gate polysilicon layer, and obtain a gate trench based on the first gate oxide layer, the second gate oxide layer, the gate polysilicon layer, and the third gate oxide layer within the second trench.

9. The manufacturing method of the double-groove power device according to claim 6, characterized in that, Form a first metal contact hole on the upper surface of the source trench within the first trench, and forming a metal layer on the upper surfaces of the isolation oxide layer and the first metal contact hole includes: Etch the source polysilicon layer within the source trench to form a first contact hole, and perform ion implantation, annealing, and activation on the bottom of the first contact hole; Fill the first contact hole and the upper surface of the source trench with a tungsten plug to form a first metal contact hole; deposit a metal layer on the surfaces of the isolation oxide layer and the first metal contact hole.

10. The manufacturing method of the double-groove power device according to claim 6, wherein, Also includes: Etch the isolation oxide layer on the upper surface of the gate trench and the gate polysilicon layer within the gate trench to form a second contact hole, and perform ion implantation, annealing, and activation on the bottom of the second contact hole; Fill the second contact hole with a tungsten plug to form a second metal contact hole.

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