Ga2O3 vertical power transistor based on heterogeneous P-type barrier layer and preparation method thereof
By introducing a heterogeneous P-type barrier layer and an N-type semiconductor channel layer into the gallium oxide vertical power transistor, the problems of high production difficulty and poor withstand voltage characteristics in the prior art are solved, and a smaller off-state leakage current and higher withstand voltage are achieved, which simplifies the preparation process.
Patent Information
- Application Number
- CN202510468374.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-15
- Publication Date
- 2025-07-18
AI Technical Summary
The existing gallium oxide vertical field effect transistor devices have problems such as difficult preparation, poor gate control characteristics, and difficult to balance off off-state leakage and on-resistance. The high-resistance current barrier layer structure formed by N or Mg doped gallium oxide cannot effectively suppress the device's voltage resistance characteristics.
A heterogeneous P-type barrier layer and an N-type gallium oxide drift layer are used to form a heterogeneous PN junction, and an N-type semiconductor channel layer is installed thereon. The heterogeneous PN junction is used to block the leakage current, and the high voltage is borne by the depletion of the drift layer, and the preparation process is simplified in combination with a variety of deposition processes.
It achieves a smaller off-state leakage current and higher voltage withstand characteristics, simplifies the preparation process and improves the performance of gallium oxide power transistors.
Smart Images
Figure CN120343955A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to semiconductor technology, and particularly to a Ga2O3 vertical power transistor based on a heterogenous P-type blocking layer and a preparation method thereof. Background Art
[0002] Gallium oxide (Ga2O3) has an ultra-large bandgap of 4.8 eV and a critical breakdown field strength of 8 MV / cm. Moreover, a gallium oxide single crystal substrate can be prepared by a low-cost melting growth method, which is an optimal material for future high-voltage-resistant and low-loss power devices and can meet the application requirements of a power system with high power density, high conversion efficiency, small size, light weight, and low cost. However, due to the difficulty in realizing p-type doping of gallium oxide, the development and application of gallium oxide power transistor devices are greatly restricted. There are two implementation schemes for existing gallium oxide vertical field effect transistors. One is to use a fin channel and rely on a metal-oxide-semiconductor (MOS) gate structure to control the on and off of the channel (see the literature Z. Hu, et al., Enhancement-mode Ga2O3 Vertical Transistors with Breakdown Voltage > 1 kV, IEEE Electron Device Letters 39(6), 869-872, 2018). The problem with this device structure is the high preparation difficulty, poor gate control characteristics, and the difficulty in achieving the balance between off-state leakage current and on-resistance. The other scheme is to form a high-resistance current blocking layer structure by using N or Mg-doped gallium oxide to suppress the off-state leakage current of the device (see the literature M. H. Wong, et al., Current aperture vertical b-Ga2O3 MOSFETs fabricated by N-and si-ion implantation doping, IEEE Electron Device Lett. 40(3), 431–434, 2019). The main problem with this device structure is that the off-state leakage current cannot be effectively suppressed and the voltage withstand characteristics of the device are poor. Summary of the Invention
[0003] The purpose of the present invention is to provide a Ga2O3 vertical power transistor based on a heterogenous P-type blocking layer and a preparation method thereof to solve the problems existing in the above-mentioned prior art.
[0004] The Ga2O3 vertical power transistor based on a heterogenous P-type blocking layer in the present invention includes an N-type gallium oxide drift layer, an N-type gallium oxide substrate, and a drain electrode, which are sequentially stacked.
[0005] An N-type gallium oxide drift layer is provided with a heterojunction P-type blocking layer thereon. The heterojunction P-type blocking layer and the N-type gallium oxide drift layer form a heterojunction PN junction. The heterojunction P-type blocking layer is provided with a current aperture. An N-type semiconductor channel layer is provided on the heterojunction P-type blocking layer. The N-type semiconductor channel layer is in electrical contact with the N-type gallium oxide drift layer through the current aperture. A gate dielectric layer is provided on the N-type semiconductor channel layer. A gate electrode is provided on the gate dielectric layer. A source electrode is provided at the end of the gate dielectric layer. The source electrode forms an ohmic contact with the N-type semiconductor channel layer through a contact layer.
[0006] The contact layer is a metal ohmic contact layer. The end of the N-type semiconductor channel layer covers the inner side of the heterojunction P-type blocking layer. The gate dielectric layer is provided with a contact hole to expose the N-type semiconductor channel layer and the heterojunction P-type blocking layer. The metal ohmic contact layer is in electrical contact with the exposed portions of the N-type semiconductor channel layer and the heterojunction P-type blocking layer through the contact hole.
[0007] The heterojunction P-type blocking layer is one of nickel oxide, cuprous oxide, and stannous oxide.
[0008] The thickness of the heterojunction P-type blocking layer is 200 nm to 800 nm.
[0009] The material of the N-type semiconductor channel layer is one of gallium oxide, indium oxide, zinc oxide, and indium gallium zinc oxide.
[0010] The thickness of the N-type semiconductor channel layer is 50 nm to 500 nm.
[0011] The contact layer is a highly doped N-type semiconductor contact layer. The N-type semiconductor channel layer completely covers the heterojunction P-type blocking layer. A contact hole is provided on the outer side of the gate dielectric layer to expose the N-type semiconductor channel layer. The highly doped N-type semiconductor contact layer covers the exposed portion of the N-type semiconductor channel layer. The source electrode is provided above the highly doped N-type semiconductor contact layer.
[0012] The preparation method of the Ga2O3 vertical power transistor based on the heterojunction P-type blocking layer in the present invention includes the following steps:
[0013] S1. Homoepitaxially grow an N-type gallium oxide drift layer on an N-type gallium oxide substrate.
[0014] S2. Deposit a metal on the back of the N-type gallium oxide substrate to form a drain electrode with ohmic contact.
[0015] S3. Deposit a heterojunction P-type semiconductor material on the N-type gallium oxide drift layer and perform patterning to form a heterojunction P-type blocking layer provided with a current aperture.
[0016] S4. Deposit an N-type semiconductor material on the heterogeneous P-type blocking layer and perform patterning to form an N-type semiconductor channel layer;
[0017] S5. Deposit a dielectric material on the N-type semiconductor channel layer and perform patterning to form a gate dielectric layer provided with contact holes;
[0018] S6. Deposit a contact layer on the gate dielectric layer, and deposit a metal on the contact layer to form a source electrode;
[0019] S7. Deposit a metal on the gate dielectric layer to form a gate electrode.
[0020] When the contact layer is a metal, make the contact layer in ohmic contact with the N-type semiconductor channel layer; when the contact layer is a highly doped N-type semiconductor, make the contact layer in ohmic contact with the source electrode.
[0021] The deposition methods include magnetron sputtering, chemical vapor deposition, atomic layer deposition, and pulsed laser deposition.
[0022] In the Ga2O3 vertical power transistor based on the heterogeneous P-type blocking layer and its manufacturing method in the present invention, the advantages are as follows: by introducing a heterogeneous P-type blocking layer and an N-type semiconductor channel layer above it, the problem of p-type doping of gallium oxide materials is cleverly avoided; the heterogeneous PN junction is used to block leakage current, and the depletion of the drift layer is used to bear high voltage, so the off-state leakage of the device is smaller and the breakdown voltage is higher than that of the traditional device using a high-resistance current blocking layer; the heterogeneous P-type blocking layer and the N-type semiconductor channel layer can be prepared by various methods, and the manufacturing process is simple. Description of the Drawings
[0023] Figure 1 It is a schematic structural diagram of the first embodiment of the Ga2O3 vertical power transistor in the present invention.
[0024] Figure 2 It is a schematic flow chart of the manufacturing method in the present invention.
[0025] Figure 3 It is a simulation curve graph of the output characteristics of the Ga2O3 vertical power transistor in the present invention.
[0026] Figure 4 It is a simulation curve graph of the transfer characteristics of the Ga2O3 vertical power transistor in the present invention.
[0027] Figure 5 It is a schematic structural diagram of the second embodiment of the Ga2O3 vertical power transistor in the present invention.
[0028] Reference Signs:
[0029] 101 - N-type gallium oxide substrate, 102 - N-type gallium oxide drift layer, 103 - hetero P-type blocking layer, 104 - N-type semiconductor channel layer, 105 - gate dielectric layer, 106 - highly doped N-type semiconductor contact layer;
[0030] 210 - drain, 221 - metal ohmic contact layer, 222 - source, 230 - gate. Detailed implementation manners
[0031] Example 1
[0032] As Figure 1 , the Ga2O3 vertical power transistor based on the hetero P-type blocking layer in the present invention includes an N-type gallium oxide drift layer 102, an N-type gallium oxide substrate 101, and a drain 210 that are sequentially stacked.
[0033] A hetero P-type blocking layer 103 is disposed above the N-type gallium oxide drift layer 102, and the hetero P-type blocking layer 103 and the N-type gallium oxide drift layer 102 form a hetero PN junction. The hetero P-type blocking layer 103 is provided with a current aperture. An N-type semiconductor channel layer 104 is provided on the hetero P-type blocking layer 103. The N-type semiconductor channel layer 104 is in electrical contact with the N-type gallium oxide drift layer 102 through the current aperture. A gate dielectric layer 105 is provided on the N-type semiconductor channel layer 104. A gate 230 is provided on the gate dielectric layer 105. A source 222 is provided at the end of the gate dielectric layer 105. The source 222 forms an ohmic contact with the N-type semiconductor channel layer 104 through a contact layer.
[0034] In this embodiment, the contact layer is a metal ohmic contact layer 221. The end of the N-type semiconductor channel layer 104 covers the inner side of the hetero P-type blocking layer 103. The gate dielectric layer 105 is provided with a contact hole to expose the N-type semiconductor channel layer 104 and the hetero P-type blocking layer 103. The metal ohmic contact layer 221 is in electrical contact with the exposed portions of the N-type semiconductor channel layer 104 and the hetero P-type blocking layer 103 through the contact hole.
[0035] The hetero P-type blocking layer 103 can be any P-type doped oxide semiconductor, for example, nickel oxide, cuprous oxide, stannous oxide, etc. are selected. The thickness of the hetero P-type blocking layer 103 is 200 nm to 800 nm.
[0036] The N-type semiconductor channel layer 104 can be any N-type doped oxide semiconductor, for example, gallium oxide, indium oxide, zinc oxide, indium gallium zinc oxide, etc. are selected. The thickness of the N-type semiconductor channel layer 104 is 50 nm to 500 nm.
[0037] The specific process of the preparation method is as Figure 2 shown, and includes the following steps:
[0038] S1. Homoepitaxially grow an N-type gallium oxide drift layer 102 on an N-type gallium oxide substrate 101;
[0039] S2. Deposit metal on the back of the N-type gallium oxide substrate 101 to form a drain 210 with ohmic contact;
[0040] S3. Deposit a heterojunction P-type semiconductor material on the N-type gallium oxide drift layer 102 and perform patterning to form a heterojunction P-type blocking layer 103 with a current aperture;
[0041] S4. Deposit an N-type semiconductor material on the heterojunction P-type blocking layer 103 and perform patterning to form an N-type semiconductor channel layer 104;
[0042] S5. Deposit a dielectric material on the N-type semiconductor channel layer 104 and perform patterning to form a gate dielectric layer 105 with a contact hole;
[0043] S6. Deposit a contact layer on the gate dielectric layer 105 and deposit metal on the contact layer to form a source 222;
[0044] S7. Deposit metal on the gate dielectric layer 105 to form a gate 230.
[0045] In this embodiment, the contact layer is made of metal, and during deposition, the contact layer is in ohmic contact with the N-type semiconductor channel layer 104. The deposition methods include but are not limited to conventional processes such as magnetron sputtering, chemical vapor deposition, atomic layer deposition, and pulsed laser deposition.
[0046] The device in this embodiment is an enhancement-mode MOSFET. By applying a voltage to the gate 230 to apply a vertical electric field under the gate, the electron concentration in the N-type semiconductor channel layer 104 is increased, enabling the device to turn on. Figure 3 and Figure 4 The output characteristic curve and transfer characteristic curve obtained by simulation are given. The heterojunction PN junction is used to block leakage current, and the depletion of the drift layer is used to bear high voltage. Compared with traditional devices using a high-resistance current blocking layer, the off-state leakage current of this device is smaller and the breakdown voltage is higher.
[0047] Embodiment 2
[0048] As Figure 5As shown, the structural difference from the first embodiment is that the contact layer is a highly doped N-type semiconductor contact layer 106. The N-type semiconductor channel layer 104 completely covers the heterogenous P-type blocking layer 103. A contact hole is provided outside the gate dielectric layer 105 to expose the N-type semiconductor channel layer 104. The highly doped N-type semiconductor contact layer 106 covers the exposed portion of the N-type semiconductor channel layer 104. The source electrode 222 is disposed above the highly doped N-type semiconductor contact layer 106. During fabrication, a highly doped N-type semiconductor is selected for the contact layer, so that an ohmic contact is formed between the contact layer and the source electrode 222 during deposition.
[0049] The term "highly doped" means that the doping concentration of the contact layer is greater than that of the N-type semiconductor channel layer 104.
[0050] This embodiment can improve the ohmic contact, further reduce the contact resistance, and further lower the on-state resistance of the device.
[0051] For those skilled in the art, various corresponding changes and deformations can be made according to the technical solutions and concepts described above, and all such changes and deformations should fall within the protection scope of the claims of the present invention.
Claims
1. A Ga2O3 vertical power transistor based on a heterogenous P-type blocking layer, comprising an N-type gallium oxide drift layer (102), an N-type gallium oxide substrate (101), and a drain (210) stacked in sequence; Characterized in that, A heterogenous P-type blocking layer (103) is disposed above the N-type gallium oxide drift layer (102), and the heterogenous P-type blocking layer (103) and the N-type gallium oxide drift layer (102) form a heterogenous PN junction; the heterogenous P-type blocking layer (103) is provided with a current aperture; an N-type semiconductor channel layer (104) is provided on the heterogenous P-type blocking layer (103); the N-type semiconductor channel layer (104) is in electrical contact with the N-type gallium oxide drift layer (102) through the current aperture; a gate dielectric layer (105) is provided on the N-type semiconductor channel layer (104); a gate (230) is provided on the gate dielectric layer (105); a source (222) is provided at the end of the gate dielectric layer (105); the source (222) forms an ohmic contact with the N-type semiconductor channel layer (104) through a contact layer.
2. The Ga2O3 vertical power transistor based on a heterogeneous P-type blocking layer according to claim 1, wherein The contact layer is a metal ohmic contact layer (221); the end of the N-type semiconductor channel layer (104) covers the inner side of the heterogenous P-type blocking layer (103); the gate dielectric layer (105) is provided with a contact hole to expose the N-type semiconductor channel layer (104) and the heterogenous P-type blocking layer (103); the metal ohmic contact layer (221) is in electrical contact with the exposed portions of the N-type semiconductor channel layer (104) and the heterogenous P-type blocking layer (103) through the contact hole.
3. The Ga2O3 vertical power transistor based on a heterogeneous P-type blocking layer according to claim 1, characterized in that, The heterogenous P-type blocking layer (103) is one of nickel oxide, cuprous oxide, and stannous oxide.
4. The Ga2O3 vertical power transistor based on a heterogeneous P-type blocking layer according to claim 1, characterized in that, The thickness of the heterogenous P-type blocking layer (103) is 200 nm to 800 nm.
5. The Ga2O3 vertical power transistor based on a heterogeneous P-type blocking layer according to claim 1, characterized in that, The material of the N-type semiconductor channel layer (104) is one of gallium oxide, indium oxide, zinc oxide, and indium gallium zinc oxide.
6. The Ga2O3 vertical power transistor based on a heterogeneous P-type blocking layer according to claim 1, wherein, The thickness of the N-type semiconductor channel layer (104) is 50 nm to 500 nm.
7. The Ga2O3 vertical power transistor based on a heterogeneous P-type blocking layer according to claim 1, wherein The contact layer is a highly doped N-type semiconductor contact layer (106); the N-type semiconductor channel layer (104) completely covers the heterogenous P-type blocking layer (103); a contact hole is provided on the outer side of the gate dielectric layer (105) to expose the N-type semiconductor channel layer (104); the highly doped N-type semiconductor contact layer (106) covers the exposed portion of the N-type semiconductor channel layer (104); the source (222) is provided above the highly doped N-type semiconductor contact layer (106).
8. A method for fabricating a Ga2O3 vertical power transistor based on a heterogeneous P-type blocking layer, characterized in that, Comprising the following steps: S1. Homoepitaxially grow an N-type gallium oxide drift layer (102) on an N-type gallium oxide substrate (101); S2. Deposit metal on the back of the N-type gallium oxide substrate (101) to form an ohmic contact drain (210); S3. Deposit a heterogenous P-type semiconductor material on the N-type gallium oxide drift layer (102) and perform patterning to form a heterogenous P-type blocking layer (103) provided with a current aperture; S4. Deposit an N-type semiconductor material on the heterogenous P-type blocking layer (103) and perform patterning to form an N-type semiconductor channel layer (104); S5. Deposit a dielectric material on the N-type semiconductor channel layer (104) and perform patterning to form a gate dielectric layer (105) provided with contact holes; S6. Deposit a contact layer on the gate dielectric layer (105), and deposit a metal on the contact layer to form a source electrode (222); S7. Deposit a metal on the gate dielectric layer (105) to form a gate electrode (230).
9. The preparation method according to claim 8, wherein When the contact layer is a metal, make the contact layer have an ohmic contact with the N-type semiconductor channel layer (104); when the contact layer is a highly doped N-type semiconductor, make the contact layer have an ohmic contact with the source electrode (222).
10. The preparation method according to claim 8, wherein, The deposition methods include magnetron sputtering, chemical vapor deposition, atomic layer deposition, and pulsed laser deposition.