Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a lower electrode, a channel on the lower electrode and including an oxide semiconductor, an upper electrode on the channel and including tungsten or molybdenum, a first intermediate layer between the lower electrode and the channel, and a second intermediate layer between the channel and the upper electrode, wherein the channel has a vertical channel structure extending from the lower electrode to the upper electrode in the vertical direction, and the first intermediate layer and the second intermediate layer include different materials.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device having a reduced contact resistance and a method of manufacturing the same. Background Art

[0002] A transistor is a semiconductor device used as an electrical switch and is used in various integrated circuit (IC) devices including memories, driver ICs, logic devices, etc. To increase the integration degree of IC devices, the space occupied by transistors has rapidly decreased, and research has been conducted to maintain the performance of IC devices while reducing the size of transistors.

[0003] As semiconductor processes become more refined, the size of transistors decreases, and the area where the gate electrode and the channel face each other also decreases. Therefore, problems are caused by the short-channel effect. For example, phenomena such as threshold voltage variation, carrier velocity saturation, and subthreshold characteristic degradation occur. Therefore, methods for overcoming the short-channel effect and effectively reducing the channel length have been sought.

[0004] In the case of a silicon (Si) channel, as the channel length decreases, problems such as reduced mobility, increased difficulty in controlling the threshold voltage V th , increased leakage current, and increased contact resistance occur, which limits the scaling of silicon channels. Therefore, research on semiconductor devices applying an oxide semiconductor to the channel has been actively conducted. Summary of the Invention

[0005] A semiconductor device configured to reduce contact resistance is provided.

[0006] A method of manufacturing a semiconductor device configured to reduce contact resistance is provided.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the present disclosure.

[0008] According to an aspect of the present disclosure, a semiconductor device includes a lower electrode, a channel on the lower electrode and including an oxide semiconductor, an upper electrode on the channel and including tungsten or molybdenum, a first intermediate layer between the lower electrode and the channel, and a second intermediate layer between the channel and the upper electrode, wherein the channel has a vertical channel structure extending from the lower electrode to the upper electrode in a vertical direction, the first intermediate layer and the second intermediate layer include different materials, the first intermediate layer includes indium oxide or indium nitride, and the second intermediate layer includes a material having an oxide formation energy greater than that of the upper electrode, and the oxide formation energy of the second intermediate layer is in the range of about -2.5 eV / atom to about 0.5 eV / atom.

[0009] The second intermediate layer may include a material having a work function in the range of about 4.6 eV to about 6.0 eV.

[0010] The difference between the oxide formation energy of the second intermediate layer and the oxide formation energy of the upper electrode may be in the range of about 0.5 eV / atom to about 3.58 eV / atom.

[0011] The second intermediate layer may include at least one of Ni, Co, Rh, Pd, Pt, Re, Ru, and Cu.

[0012] The channel may be an oxide including at least one of In, Zn, Ga, Sn, Hf, and Ti.

[0013] The lower electrode may include at least one selected from the group consisting of W (tungsten), Co (cobalt), Ni (nickel), Fe (iron), Ti (titanium), Mo (molybdenum), Cr (chromium), Zr (zirconium), Hf (hafnium), Nb (niobium), Ta (tantalum), Ag (silver), Au (gold), Al (aluminum), Cu (copper), Sb (tin), V (vanadium), Ru (ruthenium), Pt (platinum), Zn (zinc), and Mg (magnesium), or may include nitrides of these materials.

[0014] The semiconductor device may further include a bonding layer including TiN between the second intermediate layer and the upper electrode.

[0015] The second intermediate layer may extend from the bonding surface between the channel and the upper electrode to the side surface of the upper electrode.

[0016] The first intermediate layer may have a thickness in the range of about 1 nm to about 5 nm.

[0017] The second intermediate layer may have a thickness in the range of about 1 nm to about 3 nm.

[0018] The thickness of the second intermediate layer may be less than the thickness of the first intermediate layer.

[0019] The semiconductor device may further include a metal oxide layer between the lower electrode and the first intermediate layer.

[0020] The gate electrode may have a gate-all-around structure to surround the channel.

[0021] The channel, the gate insulating layer, and the gate electrode may be arranged such that their longitudinal directions are in the vertical direction of the semiconductor device and may be arranged in the horizontal direction of the semiconductor device.

[0022] The channel may have a U-shaped cross-section.

[0023] The channel may include a first channel having an L-shaped cross-section and a second channel symmetrically arranged with respect to the first channel about the vertical direction of the semiconductor device.

[0024] According to another aspect of the present disclosure, a method of manufacturing a semiconductor device includes: depositing a lower electrode on a substrate, depositing a first intermediate layer on the lower electrode, depositing a channel including an oxide semiconductor on the first intermediate layer, depositing a gate insulating layer on the channel, depositing a gate electrode on the gate insulating layer, depositing a second intermediate layer on an upper surface of the channel, and depositing an upper electrode on the second intermediate layer, wherein the first intermediate layer and the second intermediate layer include different materials from each other, the first intermediate layer includes indium oxide or indium nitride, and the second intermediate layer includes a material having an oxide formation energy greater than that of the upper electrode, and the oxide formation energy of the second intermediate layer is in the range of about -2.5 eV / atom to about 0.5 eV / atom.

[0025] The first intermediate layer, the channel, and the second intermediate layer may be formed by an atomic layer deposition (ALD) method. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0027] Figure 1 A semiconductor device according to an embodiment is schematically illustrated;

[0028] Figure 2 A current change according to voltage with respect to semiconductor devices according to an embodiment and a comparative example is shown;

[0029] Figure 3 A material distribution of work function and oxide formation energy is shown;

[0030] Figure 4 A mobility change according to annealing temperature during a thin film process in a plasma enhanced atomic layer deposition (PEALD) process and a sputtering process is shown;

[0031] Figure 5 Shows a change Figure 1 Examples of the second intermediate layer in the semiconductor device shown in

[0032] Figure 6 Shows in Figure 1 Examples of further providing other layers in the semiconductor device shown in

[0033] Figure 7 A semiconductor device according to an embodiment is shown;

[0034] Figure 8 is a cross-sectional view of a semiconductor device according to an embodiment;

[0035] Figure 9 is a cross-sectional view of a semiconductor device according to an embodiment;

[0036] Figure 10 is a cross-sectional view of a semiconductor device according to an embodiment;

[0037] Figure 11 is a cross-sectional view of a semiconductor device according to an embodiment;

[0038] Figure 12 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment;

[0039] Figure 13 is a diagram showing an ALD method used in a method of manufacturing a semiconductor device according to an embodiment;

[0040] Figures 14 to 29 is a diagram showing a method of manufacturing a semiconductor device according to an embodiment;

[0041] Figure 30 shows a memory device including a semiconductor device according to an embodiment;

[0042] Figure 31 is a schematic block diagram of a display driver integrated circuit (IC) (DDI) including a semiconductor device according to an embodiment and a display device including the DDI;

[0043] Figure 32 is a circuit diagram of a CMOS inverter including a semiconductor device according to an embodiment;

[0044] Figure 33 is a circuit diagram of a CMOS SRAM device including a semiconductor device according to an embodiment;

[0045] Figure 34 is a circuit diagram of a CMOS NAND circuit including a semiconductor device according to an embodiment;

[0046] Figure 35 is a block diagram of an electronic system including a semiconductor device according to an embodiment; and

[0047] Figure 36 is a block diagram of an electronic system including a semiconductor device according to an embodiment. Detailed Description

[0048] Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Accordingly, the embodiments are described below only by referring to the accompanying drawings to explain the aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of..." modify the entire list of elements when following the list of elements and do not modify individual elements of the list.

[0049] Hereinafter, a semiconductor device and a method of manufacturing the same according to various embodiments will be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals in the drawings denote like elements, and for clarity and convenience of explanation, the dimensions of components in the drawings may be exaggerated. Although terms such as "first", "second", etc. may be used to describe various components, these components do not necessarily have to be limited to the above terms. The above terms are only used to distinguish one component from another.

[0050] Expressions used in the singular encompass the plural expressions unless they have a clearly different meaning in the context. When a part "comprises" an element, another element may be further comprised unless otherwise described, rather than excluding the existence of another element. For convenience of explanation, the dimensions or thicknesses of components in the drawings may be arbitrarily exaggerated. In addition, when a certain material layer is described as being provided on a substrate or another layer, the material layer may be in contact with the other layer, or a third layer may exist between the material layer and the other layer. In the following embodiments, the materials constituting each layer are provided only as examples, and other materials may also be used.

[0051] Figure 1 A semiconductor device 100 according to an embodiment is schematically shown.

[0052] Referring to Figure 1 , the semiconductor device 100 may include a substrate 110, a lower electrode 120 provided on the substrate 110, a channel 140 provided on the lower electrode 120, and an upper electrode 170 provided on the channel 140. A first intermediate layer 130 may be provided between the lower electrode 120 and the channel 140, and a second intermediate layer 160 may be provided between the channel 140 and the upper electrode 170. A gate electrode 150 may be provided on one side of the channel 140, and a gate insulating layer 155 may be provided between the channel 140 and the gate electrode 150.

[0053] The lower electrode 120, the channel 140, and the upper electrode 170 may be disposed in a direction (z-direction) perpendicular to the substrate 110. The lower electrode 120, the channel 140, and the upper electrode 170 may have the same width. However, the present disclosure is not limited thereto. The lower electrode 120 may be a source electrode and the upper electrode 170 may be a drain electrode, or the lower electrode 120 may be a drain electrode and the upper electrode 170 may be a source electrode.

[0054] The gate electrode 150 may be disposed such that its longitudinal direction (z-direction) is perpendicular to the substrate 110. Here, the longitudinal direction indicates the direction in which the length of the corresponding component is relatively long when viewed from the drawing. The channel 140, the gate insulating layer 155, and the gate electrode 150 may be arranged in a row in a horizontal direction (x-direction) with respect to the substrate 110.

[0055] The molding insulating layer 180 may be provided on the substrate 110 to fill an empty space. The lower electrode 120 may be spaced apart from the substrate 110 by the molding insulating layer 180.

[0056] The substrate 110 may be an insulating substrate, or may be a semiconductor substrate having an insulating layer formed on its surface. Alternatively, the substrate 110 may be a semiconductor substrate. The semiconductor substrate may include, for example, Si, Ge, SiGe, or III-V group semiconductor materials. The substrate 110 may be, for example, a silicon substrate having silicon oxide formed on its surface, but is not limited thereto.

[0057] The lower electrode 120 may be spaced apart from the substrate 110. The lower electrode 120 may include at least one selected from the group consisting of W (tungsten), Co (cobalt), Ni (nickel), Fe (iron), Ti (titanium), Mo (molybdenum), Cr (chromium), Zr (zirconium), Hf (hafnium), Nb (niobium), Ta (tantalum), Ag (silver), Au (gold), Al (aluminum), Cu (copper), Sb (tin), V (vanadium), Ru (ruthenium), Pt (platinum), Zn (zinc), and Mg (magnesium), or may include a nitride containing these materials. For example, the lower electrode 120 may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, or WSiN.

[0058] Figure 1An example is shown in which the lower electrode 120 includes a single layer, but the present disclosure is not limited thereto, and the lower electrode 120 may have a multi-layer structure. For example, the lower electrode 120 may include a first electrode, a second electrode below the first electrode, and a third electrode below the second electrode. The first electrode may include at least one selected from the group consisting of W (tungsten), Co (cobalt), Ni (nickel), Fe (iron), Ti (titanium), Mo (molybdenum), Cr (chromium), Zr (zirconium), Hf (hafnium), Nb (niobium), Ta (tantalum), Ag (silver), Au (gold), Al (aluminum), Cu (copper), Sb (tin), V (vanadium), Ru (ruthenium), Pt (platinum), Zn (zinc), and Mg (magnesium), or may include a nitride containing these materials. The second electrode may include WSi, and the third electrode may include TiN.

[0059] As another example, the lower electrode 120 may include Zn with a content of 10 atomic percent (at%) or less. Zn may have a content of 10 at% or less relative to the total metal elements in the lower electrode 120. Here, the content of Zn may represent the content of Zn relative to the total metal elements other than oxygen included in the lower electrode 120. Alternatively, the lower electrode 120 may include Zn with a content of 5 at% or less.

[0060] The channel 140 may be between the lower electrode 120 and the upper electrode 170 and may extend relatively long in a direction perpendicular to the substrate 110 (z direction). That is, the semiconductor device 100 may have a vertical channel structure in which the channel 140 extends relatively long from the lower electrode 120 toward the upper electrode 170. The channel 140 may include an oxide semiconductor. The channel 140 may be an oxide including at least one of In, Zn, Ga, Sn, Hf, and Ti. The channel 140 may include, for example, InGaZnO, InGaO, InSnO, InZnO, InO, InHfO, InTiO, HfInZnO, or any combination thereof. The channel 140 may have an amorphous state and may thus reduce the off-current.

[0061] The channel 140 may include, for example, In and Zn, and the content of In in the channel 140 may be greater than or equal to the content of Zn in the channel 140. The channel 140 may include (In) a1 (Zn) a2 (M) a3 O. Here, M may be Sn, Ga, Hf, Ti, or any combination thereof, a1 may be a real number satisfying 0 < a1 ≤ 10, a2 may be a real number satisfying 0 < a2 ≤ 10, a3 may be a real number satisfying 0 ≤ a3 ≤ 10, and a1 > a2.

[0062] The upper electrode 170 may include tungsten (W) or molybdenum (Mo).

[0063] The first intermediate layer 130 can be provided between the lower electrode 120 and the channel 140 to reduce the contact resistance of the lower electrode 140. When the channel 140 is formed on the lower electrode 120, the channel 140 can be formed by an atomic layer deposition process. During the atomic layer deposition process, since a strong oxidant such as O3 is used for the oxidation reaction of the precursor, the contact resistance deteriorates due to the reaction with the oxidant. The first intermediate layer 130 can include indium oxide (InO) or indium nitride (InN) to reduce the contact resistance of the lower electrode 120. For example, the first intermediate layer 130 can include at least one of InGaZnO, InGaO, InSnO, InZnO, InO, and InN. For example, when the first intermediate layer 130 includes InGaZnO or InZnO, the content of In can be greater than the content of Zn.

[0064] In the above example, when the first intermediate layer 130 is an oxide including a first indium and the channel 140 is an oxide including a second indium, the content of the first indium in the first intermediate layer 130 can be greater than the content of the second indium in the channel 140. The content of the second indium in the channel 140 can be greater in a region relatively close to the first intermediate layer 130 than in a region relatively far from the first intermediate layer 130. Refer to Figure 1 , the content of the second indium at the D1 position of the channel 140 is greater than the content of the second indium at the D2 position, where D1 and D2 are located at distances D1 and D2 from the boundary surface 131 between the first intermediate layer 130 and the channel 140, respectively, and D1 < D2. Alternatively, the content of the second indium in the channel 140 can have a gradient content distribution that gradually increases toward the first intermediate layer 130.

[0065] For example, the first intermediate layer 130 can include (In) b1 (M 1 ) b2 O, and the channel 140 can include (In) c1 (M 2 ) c2 O. Here, M 1 and M 2 can be Zn, Sn, Ga, Hf, Ti, or any combination thereof, b1 can be a real number satisfying 0 < b1 ≤ 10, b2 can be a real number satisfying 0 < b2 ≤ 10, c1 can be a real number satisfying 0 < c1 ≤ 10, c2 can be a real number satisfying 0 < c2 ≤ 10, and b1 > c1.

[0066] For example, when each of the channel 140 and the first intermediate layer 130 includes In, Ga, Zn, and O, the composition ratios of In, Ga, and Zn in the channel 140 can be 1:1:1, and the composition ratios of In, Ga, and Zn in the first intermediate layer 130 can be 2:1:1.

[0067] The first intermediate layer 130 can be arranged to be in direct contact with the channel 140.

[0068] Figure 2 It is a graph showing the current according to voltage for Embodiment A including an InN intermediate layer between the W bottom electrode and the IGZO channel and Comparative Example B having no intermediate layer between the W bottom electrode and the IGZO channel. The current is relatively higher in graph A than in graph B, which can confirm that the contact resistance is lower in graph A than in graph B.

[0069] The second intermediate layer 160 can include a material having an oxide-forming energy greater than that of the upper electrode 170 to suppress the supply of oxygen to the channel 140. Since the second intermediate layer 160 is formed in an oxygen-free atmosphere, the thickness d2 of the second intermediate layer 160 is less than the thickness d1 of the first intermediate layer 130. The contact resistance can be reduced by making the thickness d2 of the second intermediate layer 160 relatively smaller than the thickness d1 of the first intermediate layer 130. The thickness d1 of the first intermediate layer 130 can be in the range of about 1 nm to about 5 nm. The thickness d2 of the second intermediate layer 160 can be in the range of about 1 nm to about 3 nm.

[0070] Meanwhile, the second intermediate layer 160 can be oxidized in a subsequent heat treatment process to deteriorate the contact resistance. Therefore, the second intermediate layer 160 includes a material having an oxide-forming energy greater than that of the upper electrode 170 to suppress oxygen in the subsequent heat treatment process, thereby preventing an increase in contact resistance. The second intermediate layer 160 can be arranged to be in direct contact with the channel 140.

[0071] Figure 3 It shows the material distribution of work function and oxide-forming energy. The second intermediate layer 160 can include a material having an oxide-forming energy greater than that of the upper electrode 170. The upper electrode 170 can include tungsten (W) or molybdenum (Mo), and the second intermediate layer 160 can include a material having an oxide-forming energy greater than that of tungsten (W) or molybdenum (Mo). The oxide-forming energy Eo of tungsten is higher than that of molybdenum and is about -2.65 eV / atom. The second intermediate layer 160 can include, for example, a material having an oxide-forming energy greater than -2.65 eV / atom. The second intermediate layer 160 can include a material having an oxide-forming energy in the range of about -2.5 eV / atom to about 0.5 eV / atom. The difference between the oxide-forming energy of the second intermediate layer 160 and the oxide-forming energy of the upper electrode 170 can be in the range of about 0.5 eV / atom to about 3.58 eV / atom.

[0072] The second intermediate layer 160 may include at least one of Ni, Co, Rh, Pd, Pt, Re, Ru, and Cu.

[0073] The second intermediate layer 160 may include a material having a work function greater than 4.56 eV. For example, the second intermediate layer 160 may include a material having a work function in the range of about 4.6 eV to about 6.0 eV.

[0074] In the semiconductor device 100 according to an embodiment, the degradation of the contact resistance may be minimized by differently configuring the materials of the first intermediate layer 130 and the second intermediate layer 160. That is, the first intermediate layer 130 may include a material suitable for reducing the contact resistance at the interface between the lower electrode 120 and the channel 140, and the second intermediate layer 160 may include a material suitable for reducing the contact resistance at the interface between the channel 140 and the upper electrode 170. The second intermediate layer 160 does not include the material included in the first intermediate layer 130, and the first intermediate layer 130 does not include the material included in the second intermediate layer 160.

[0075] The materials of the first intermediate layer 130 and the second intermediate layer 160 are described in more detail with different configurations.

[0076] Figure 4 The mobility change according to the annealing temperature is shown. When the semiconductor device is deposited by a plasma enhanced atomic layer deposition (PEALD) process, the mobility decreases as the annealing temperature increases. As the annealing temperature increases, each layer of the semiconductor device crystallizes, and the mobility decreases according to the crystallization, indicating an increase in resistance. That is, the crystallization of each layer of the semiconductor device may be a factor increasing the resistance. Therefore, reducing the crystallization of the semiconductor device is beneficial for reducing the resistance.

[0077] However, when the second intermediate layer 160 includes indium, the crystallization temperature of the channel 140 may decrease as the indium content increases. When the first intermediate layer 130 between the lower electrode 120 and the channel 140 includes indium, since the channel 140 is deposited on the first intermediate layer 130, the first intermediate layer 130 or the lower electrode 120 is less affected by the crystallization of the channel 140. On the other hand, when the second intermediate layer 160 includes indium, since the second intermediate layer 160 is deposited on the channel 140, the contact region acts as a seed crystal according to the crystallization of the channel 140 to increase the crystallinity of the upper electrode 170, thereby increasing the resistance. In addition, since the crystallinity of the contact portion of the upper electrode 170 may vary depending on the temperature or subsequent processes, the uniformity of the memory cell array including the semiconductor device may deteriorate. Therefore, while the first intermediate layer 130 includes indium, the second intermediate layer 130 may be configured not to include indium.

[0078] Next, the reason why it is difficult to apply the material applied to the second intermediate layer 160 to the first intermediate layer 130 is that it is difficult to dry-etch a material having a high oxide-forming energy, which makes it difficult to form an intermediate layer having a high oxide-forming energy on the lower electrode 120.

[0079] As described above, in the semiconductor device 100 according to the embodiment, the first intermediate layer 130 and the second intermediate layer 160 include different materials from each other. Therefore, the contact resistance between the lower electrode 120 and the upper electrode 170 can be reduced.

[0080] Figure 5 An example of changing the second intermediate layer in the semiconductor device shown in Figure 1 is shown. In Figure 5 components having the same reference numerals as those in Figure 1 have the same configuration and effects, and thus, their detailed descriptions are omitted.

[0081] The semiconductor device 100A may include a second intermediate layer 161 between the channel 140 and the upper electrode 170. The second intermediate layer 161 may extend from the bonding surface between the channel 140 and the upper electrode 170 to the side surface of the upper electrode 170. The second intermediate layer 161 may also be provided at the interface between the upper electrode 170 and the molding insulating layer 180 to further reduce the contact resistance of the upper electrode 170.

[0082] Figure 6 An example of further providing some layers in the semiconductor device shown in Figure 1 is shown.

[0083] The semiconductor device 100B may include a metal oxide layer 122 between the lower electrode 120 and the first intermediate layer 130. The semiconductor device 100B may include a bonding layer 165 between the second intermediate layer 160 and the upper electrode 170. The bonding layer 165 may include, for example, TiN.

[0084] The metal oxide layer 122 may be an oxide layer including a metal same as the metal included in the lower electrode 120. For example, the metal oxide layer 122 may be an oxide layer including W (tungsten), Co (cobalt), Ni (nickel), Fe (iron), Ti (titanium), Mo (molybdenum), Cr (chromium), Zr (zirconium), Hf (hafnium), Nb (niobium), Ta (tantalum), Ag (silver), Au (gold), Al (aluminum), Cu (copper), Sb (tin), V (vanadium), Ru (ruthenium), Pt (platinum), Zn (zinc), and Mg (magnesium) or any combination thereof.

[0085] The content of oxygen included in the metal oxide layer 122 may vary from the lower electrode 120 to the channel 140. For example, the content of oxygen included in the metal oxide layer 122 may increase toward the channel 140.

[0086] The metal oxide layer 122 can be formed by reacting a metal source with an oxygen source on the lower electrode 120, or can be formed by oxidizing the metal of the lower electrode 120 through heat treatment in the process of forming the channel 140 or manufacturing the semiconductor device 100B.

[0087] Figure 7 A semiconductor device 200 of another example is shown. In Figure 7 , components with the same reference numerals as those in Figure 1 have substantially the same configurations and effects as those described with reference to Figure 1 , and thus their detailed descriptions are omitted.

[0088] The semiconductor device 200 includes a lower electrode 120, a first intermediate layer 130, a channel 140, a second intermediate layer 160, and an upper electrode 170 arranged in a direction (z direction) perpendicular to the substrate 110. A gate insulating layer 260 can be provided around the channel 140, and a gate electrode 250 can be provided around the gate insulating layer 260. The gate electrode 250 is provided around the channel 140 to increase the area where the gate electrode 250 and the channel 140 face each other and improve the short-channel effect. The semiconductor device 200 can be applied to a so-called gate-all-around structure. Although not shown in Figure 7 , the metal oxide layer 122 and the bonding layer 165 described with reference to Figure 6 can also be applied to Figure 7 .

[0089] Figure 8 A semiconductor device 300 according to another embodiment is shown.

[0090] The semiconductor device 300 can include a lower electrode 320, a first intermediate layer 330 provided on the lower electrode 320, and a channel 340 provided on the first intermediate layer 330.

[0091] The channel 340 can have a U-shaped cross section. The channel 340 can include a bottom portion 340B in contact with the first intermediate layer 330, a first vertically extending portion 340L extending from one end of the bottom portion 340B in a direction (z direction) perpendicular to the lower electrode 320, and a second vertically extending portion 340R extending from the other end of the bottom portion 340B in a direction (z direction) perpendicular to the lower electrode 320.

[0092] The first gate electrode 351 may be spaced apart from the first vertically extending portion 340L, and the second gate electrode 352 may be spaced apart from the second vertically extending portion 340R. The first gate insulating layer 361 may be provided between the first vertically extending portion 340L and the first gate electrode 351, and the second gate insulating layer 362 may be provided between the second vertically extending portion 340R and the second gate electrode 352.

[0093] The first gate electrode 351 and / or the second gate electrode 352 may extend in the second horizontal direction y. The first gate electrode 351 and the second gate electrode 352 may be spaced apart from each other. The first gate electrode 351 and / or the second gate electrode 352 may constitute a word line. The electrical signal input to the first gate electrode 351 may not match the electrical signal input to the second gate electrode 352. The first gate electrode 351 may control the channel of the first vertically extending portion 340L, and the second gate electrode 352 may control the channel of the second vertically extending portion 340R.

[0094] The insulating spacer 391 may be disposed between the first gate electrode 351 and the second gate electrode 352 spaced apart from each other. The insulating spacer 391 may be conformally disposed on the sidewalls facing each other of the first gate electrode 351 and the second gate electrode 352 and / or on the upper surface of the channel 340. The insulating spacer 391 may have an upper surface disposed in the same plane as the first gate electrode 351 and the second gate electrode 352. The insulating spacer 391 may include, for example, silicon nitride. The buried insulating layer 392 may fill the space between the first gate electrode 351 and the second gate electrode 352 spaced apart from each other on the insulating spacer 391. The buried insulating layer 392 may include, for example, silicon oxide. The upper insulating layer 393 may be disposed on the upper surfaces of the first gate electrode 351, the second gate electrode 352, and / or the buried insulating layer 392. The upper surface of the upper insulating layer 393 may be disposed at the same level as the upper surface of the molding insulating layer 380.

[0095] The upper electrode 370 may be disposed on the upper portion of the channel 340. The upper electrode 370 may be used as a landing pad. The upper electrode 370 may include a left upper electrode and a right upper electrode. The left upper electrode may be electrically connected to the first vertically extending portion 340L. The right upper electrode may be electrically connected to the second vertically extending portion 340R. The left upper electrode and the right upper electrode may not be electrically connected to each other. The upper electrode 370 may include a lower portion 370a and an upper portion 370b, and the lower portion 370a and the upper portion 370b have different widths from each other. The upper portion 370b of the upper electrode 370 may be the landing pad of the upper electrode 370 disposed at a level higher than the level of the upper surface of the molded insulating layer 380. The lower portion 370a of the upper electrode 370 may be a buried contact disposed inside the upper electrode recess defined between the molded insulating layer 380 and the upper insulating layer 393. In an embodiment, the lower portion 370a of the upper electrode 370 may have a first width w1 in the first horizontal direction x, and the upper portion 370b of the upper electrode 370 may have a second width w2 greater than the first width w1 in the first horizontal direction x. The lower portion 370a of the upper electrode 370 may have a bottom surface disposed inside the upper electrode recess, and the upper portion 370b of the upper electrode 370 is on the upper surface of the molded insulating layer 380 and the upper surface of the upper insulating layer 393 on the lower portion 370a of the upper electrode 370. Thus, the upper electrode 370 may have a T-shaped vertical cross-section. The second intermediate layer 360 may be provided between the bottom surface of the lower portion 370a of the upper electrode 370 and the first vertically extending portion 340L and between the bottom surface of the lower portion 370a of the upper electrode 370 and the second vertically extending portion 340R.

[0096] The two side walls of the lower portion 370a of the upper electrode 370 may be aligned with the two side walls of the first vertically extending portion 340L and the second vertically extending portion 340R. The bottom surface of the lower portion 370a of the upper electrode 370 may be disposed at a level equal to or higher than the upper surfaces of the first gate electrode 351 and / or the second gate electrode 352, and a part of the side walls of the lower portion 370a of the upper electrode 370 may be covered by the first gate insulating layer 361 and / or the second gate insulating layer 362. The upper electrode insulating layer 394 surrounding the upper electrode 370 may be disposed on the upper surfaces of the molding insulating layer 380 and the upper insulating layer 393. The semiconductor device 300 may have a vertical channel transistor (VCT) structure including a vertical channel region extending in a direction z perpendicular to the lower electrode 320. The first gate electrode 351 and the second gate electrode 352 may have a straight cross-section, the first gate insulating layer 361 may have an L-shaped cross-section, and the second gate insulating layer 362 may have a cross-section symmetric to the first gate insulating layer 361 with respect to the z-axis. Alternatively, the first gate insulating layer 361 and the second gate insulating layer 362 may have a straight cross-section like the first gate electrode 351 and the second gate electrode 352.

[0097] In the semiconductor device 300, a first intermediate layer 330 may be provided between the lower electrode 320 and the bottom portion 340B of the channel 340. A second intermediate layer 360 may be provided between the first vertically extending portion 340L of the channel 340 and the lower portion 370a of the upper electrode 370 and between the second vertically extending portion 340R of the channel 340 and the lower portion 370a of the upper electrode 370.

[0098] Figure 9 An example in which the position of the second intermediate layer is changed as compared with Figure 8 is shown. To avoid redundancy in the description, reference Figure 9 is made only to the second intermediate layer 360. In the semiconductor device 300A, the second intermediate layer 360 may include a lower intermediate layer 360a at the interface between the first vertically extending portion 340L of the channel 340 and the lower portion 370a of the upper electrode 370 and a side intermediate layer 360b provided on the side surface of the upper electrode 370 and a part of the bottom surface of the upper portion 370b of the upper electrode 370. In addition, the second intermediate layer 360 may include a lower intermediate layer 360a at the interface between the second vertically extending portion 340R and the lower portion 370a of another upper electrode 370 and a side intermediate layer 360b provided on the side surface of the another upper electrode 370 and a part of the bottom surface of the upper portion 370b of the another upper electrode 370. The second intermediate layer 360 extends to the side surface of the upper electrode 370, and thus, the contact resistance can be further reduced.

[0099] Figure 10Shows a semiconductor device 300B according to another embodiment.

[0100] In Figure 10 , components with the same reference numerals as in Figure 8 have substantially the same configuration and effects, and thus their detailed descriptions are omitted.

[0101] In Figure 10 compared with Figure 8 , the shape of the channel in the semiconductor device 300B may be different. The channel may include a first channel 341 and a second channel 342. The first channel 341 may have an L-shaped cross-section, and the second channel 342 may have a shape symmetric to the first channel 341 with respect to the z-direction. The first channel 341 and the second channel 342 are separated from each other.

[0102] The first channel 341 and the second channel 342 may be positioned such that their longitudinal directions are arranged in a direction (z-direction) perpendicular to a substrate (not shown).

[0103] Figure 11 Shows an example of changing the first intermediate layer in the semiconductor device shown in Figure 8 .

[0104] Compared with Figure 8 , in Figure 11 , a first intermediate layer 331 may be provided over the entire lower electrode 320 in the semiconductor device 300C. Here, the lower electrode 320 may include bit lines, and the first intermediate layer 331 may be provided along the lower electrode 320. The first intermediate layer 331 may be longer than the bottom portion 340B of the channel 340.

[0105] Next, the effects of the semiconductor devices 100, 200, 300, 300A, 300B, and 300C according to the embodiments are described.

[0106] The semiconductor devices 100, 200, 300, 300A, 300B, and 300C may be applied to transistors including an oxide semiconductor channel 140. Referring to Figure 9 , a first intermediate layer 330 may be provided to increase the content of In between the lower electrode 320 and the channel 340, such that the contact resistance may be reduced. For example, W, which is widely used as an electrode material, has strong oxidation reactivity and is easily oxidized during the oxidation reaction of the ALD precursor, while suppressing the oxidation reaction of In on the electrode surface, thereby reducing the In component of the oxide semiconductor. When the In component decreases in the channel 340, device characteristics may deteriorate, such as a reduction in carriers, an increase in resistance, and a decrease in the on-current I on .

[0107] Therefore, the contact resistance of the lower electrode 320 can be reduced by providing a first intermediate layer 330 including indium between the channel 340 and the lower electrode 320.

[0108] As silicon-based memory or logic devices reach high integration limits and require channel lengths of several tens of nanometers or several nanometers, it is very important to reduce the off-state current. In addition, it is necessary to improve the subthreshold swing (SS) and on / off ratio, which are the characteristics required to distinguish clear on / off states. However, silicon-based semiconductor devices have limitations in improving such characteristics. On the other hand, semiconductor devices employing the oxide semiconductor in the channel are very excellent in terms of required characteristics (low off-state current, low SS, and high on / off ratio). Therefore, by applying an oxide semiconductor device having such advantages to a memory or logic device or by stacking an oxide semiconductor device on a Si-based device via a low-temperature process of 500 °C or lower, the integration degree can be increased.

[0109] In addition, the contact resistance of the upper electrode 370 can be reduced by providing a second intermediate layer 360 including a material having an oxide formation energy greater than that of the upper electrode 370 between the upper surface of the channel 340 and the upper electrode 370.

[0110] Figure 12 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment.

[0111] Deposit a lower electrode on a substrate (S110), and deposit a first intermediate layer on the lower electrode (S120). Deposit a channel including an oxide semiconductor on the first intermediate layer (S130). The first intermediate layer and the channel can be deposited using, for example, an ALD process or a PE-ALD process. Deposit a gate insulating layer on the channel (S140). Then, deposit a gate electrode on the gate insulating layer (S150). Deposit a second intermediate layer on the channel (S160), and deposit an upper electrode on the second intermediate layer (S170).

[0112] Figure 13 is a flowchart showing a process of depositing a first intermediate layer, a channel, and a second intermediate layer. The operations of depositing the first intermediate layer, the channel, and the second intermediate layer may include an ALD process. The ALD process may include an operation S121 of injecting a precursor into a chamber, a purge operation S122, an operation S123 of injecting a reactant into the chamber to react with the precursor, and a purge operation S124. The operations S121, S122, S123, and S124 may be repeated m times (m is a natural number), for example, 1 to 100 times. Alternatively, m may include a range of 1 to 70 times.

[0113] The ALD process can be performed by differentiating according to the initial crystal nucleation rate of a thin film of a chemical substance selectively exposed on the surface of the lower electrode. By applying a precursor highly reactive with the electrode material to the lower electrode, a first intermediate layer with a high indium content can be selectively deposited only on the electrode. When a precursor with low reactivity with the electrode material is used in the lower electrode, the indium content in the first intermediate layer can be increased by increasing the sub-cycles of the initial deposition of the thin film. The type of precursor is a material such as 3-dimethylaminopropyl dimethyl indium (DADI) including In, and this material does not have high surface reactivity with the lower electrode (such as W, Pt, and Au), and thus the indium content tends to rapidly decrease at the interface. Therefore, it is necessary to increase the sub-cycles of the precursor on the lower electrode.

[0114] Next, refer to Figures 14 to 29 to describe a method of manufacturing a semiconductor device according to an embodiment.

[0115] Refer to Figure 14 , and a plurality of molded insulating layers 1080 extending in the second horizontal direction y can be deposited on a lower electrode 1020 extending in the first horizontal direction x. The molded insulating layers 1080 can be stacked to a certain height in the vertical direction z. The plurality of molded insulating layers 1080 and the lower electrode 1020 can form an opening 1085.

[0116] Refer to Figure 15 , and a first intermediate layer 1030 can be deposited on the lower electrode 1020. The first intermediate layer 1030 can include indium oxide or indium nitride. The first intermediate layer 1030 can be deposited using the ALD process. The first intermediate layer 1030 can have a thickness in the range of about 1 nm to about 5 nm.

[0117] Refer to Figure 16 , and a channel 1040 including an oxide semiconductor can be deposited on the first intermediate layer 1030 and the molded insulating layers 1080. The channel 1040 can be deposited by the ALD method. The channel 1040 can have a U-shaped cross-section. Refer to Figure 17 , and a gate insulating layer 1060 can be deposited on the channel 1040. Refer to Figure 18 , and a gate electrode 1050 can be deposited on the gate insulating layer 1060.

[0118] Refer to Figure 19 , for Figure 18The gate electrode 1050 of the structure shown in performs anisotropic etching so that the bottom portion 1043 of the channel 1040 can be exposed. Thus, the gate electrode 1050 can be separated into a first gate electrode 1051 and a second gate electrode 1052, and the gate insulating layer 1060 can be separated into a first gate insulating layer 1061 and a second gate insulating layer 1062. In addition, the gate electrode 1050, the gate insulating layer 1060, and the channel 1040 can be etched on the upper portion of the molding insulating layer 1080 so that the upper surface of the molding insulating layer 1080 can be exposed. The upper surface level of the molding insulating layer 1080, the upper surface levels of the first gate electrode 1051 and the second gate electrode 1052, and the upper surface levels of the first gate insulating layer 1061 and the second gate insulating layer 1062 can coincide with each other.

[0119] Reference Figure 20 , when etching is performed on the first gate electrode 1051 and the second gate electrode 1052 again, the upper surface levels of the first gate electrode 1051 and the second gate electrode 1052 can be lower than the upper surface level of the molding insulating layer 1080.

[0120] Reference Figure 20 , the insulating liner 1091 can be deposited from the surface of the bottom portion 1043 of the channel 1040 to the upper surface level of the first gate electrode 1051 and / or the second gate electrode 1052. The buried insulating layer 1092 can be filled inside the insulating liner 1091. The insulating liner 1091 and the buried insulating layer 1092 may not be distinguished from each other. The upper insulating layer 1093 can be deposited on the upper surface of the first gate electrode 1051 and / or the second gate electrode 1052 and the upper surface of the insulating liner 1091. The surface level of the upper insulating layer 1093 can coincide with the upper surface level of the molding insulating layer 1080, the upper surface level of the channel 1040, and the upper surface levels of the first gate insulating layer 1061 and the second gate insulating layer 1062.

[0121] For convenience, Figure 21 only the portion corresponding to Figure 20 one pixel in is shown. Reference Figure 21 , the upper portions of the first channel 1041 and the second channel 1042 can be partially etched, and the second intermediate layer 1065 can be deposited on the upper portions of the first channel 1041 and the second channel 1042. The second intermediate layer 1065 can use the ALD process. The second intermediate layer 1065 can have a thickness in the range of about 1 nm to about 3 nm. When the upper portions of the first channel 1041 and the second channel 1042 are partially etched, the upper portion of the upper insulating layer 1093 can be partially etched.

[0122] Reference Figure 22 , it can be in Figure 21The upper electrode 1070 is deposited on the structure shown in []. After depositing the upper electrode 1070, the central portion of the upper electrode 1070 and the upper portion of the upper insulating layer 1093 may be partially etched to separate the upper electrode 1070.

[0123] Reference Figure 23 , an upper electrode insulating layer 1094 may be deposited between the upper electrodes 1070 and on a part of the upper portion of the upper insulating layer 1093. The upper surface level of the upper electrode insulating layer 1094 and the surface level of the upper electrode 1070 may coincide with each other.

[0124] Figure 24 is a diagram showing a method of manufacturing Figure 10 the semiconductor device shown in []. Hereinafter, descriptions redundant with those of Figure 19 will be omitted, and the differences will be mainly described.

[0125] Reference Figure 24 , the gate electrode 1050, the gate insulating layer 1060, and the channel 1040 may be etched on the bottom portion of the opening such that the surface of the first intermediate layer 1030 may be partially exposed. Accordingly, the channel 1040 may be separated into a first channel 1041 and a second channel 1042, the gate insulating layer 1060 may be separated into a first gate insulating layer 1061 and a second gate insulating layer 1062, and the gate electrode 1050 may be separated into a first gate electrode 1051 and a second gate electrode 1052.

[0126] Reference Figure 25 , an insulating spacer 1091 may be deposited from the upper surface of the first intermediate layer 1030 to the upper surface level of the first gate electrode 1051 and / or the second gate electrode 1052.

[0127] Reference Figure 26 , similar to Figure 21 , the upper portions of the first channel 1041 and the second channel 1042 may be partially etched, and a first intermediate layer 1065 may be deposited on the upper portions of the first channel 1041 and the second channel 1042. In addition, as shown in Figure 27 in [], the upper electrode 1070 may be deposited on the structure shown in Figure 26 , and the central portion of the upper electrode 1070 and the upper portion of the upper insulating layer 1093 may be partially etched.

[0128] Reference Figure 28 , similar to Figure 23 , an upper electrode insulating layer 1094 may be deposited between the upper electrodes 1070 and on a part of the upper portion of the upper insulating layer 1093. The upper surface level of the upper electrode insulating layer 1094 and the surface level of the upper electrode 1070 may coincide with each other.

[0129] InFigure 29 Among them, compared with Figure 15 , only the first intermediate layer 1031 is changed. The first intermediate layer 1031 can be deposited on the entire surface of the lower electrode 1020. The first intermediate layer 1031 can be formed by selective formation of an In precursor. The lower electrode 1020 can be formed as a bit line, and the first intermediate layer 1031 can be formed and patterned on the lower electrode 1020 of the bit line.

[0130] The semiconductor device according to an embodiment can be applied to, for example, a transistor, a field effect transistor (FET), a semiconductor memory device, a logic device, an image sensor, etc. The logic device is responsible for calculation and control, and the memory device is responsible for storing information. The logic device can be applied to micro components, analog ICs, logic ICs, etc. The analog IC can include a power semiconductor, an image sensor, a touch controller, etc. The logic IC can include a display driver IC (DDI), a T-CON, a media IC, an application processor (AP), a vehicle semiconductor, etc. The memory device can include a DRAM, an SRAM, a NAND memory, etc.

[0131] Figure 30 An example in which the semiconductor device 300 according to an embodiment is applied to a DRAM is shown. The semiconductor device 300 is the same as the semiconductor device described with reference to Figure 8 , and thus, for simplicity of description, its detailed description is omitted.

[0132] Referring to Figure 30 , the memory device 500 can include the semiconductor device 300 and a capacitor 400 connected to the upper electrode 370 of the semiconductor device 300.

[0133] The capacitor 400 may include a first electrode 410, a dielectric layer 430, and a second electrode 450. The dielectric layer 430 may include at least one of, for example, HfO2, ZrO2, CeO2, La2O3, Ta2O3, and TiO2. An interfacial layer 420 may be further provided between the first electrode 410 and the dielectric layer 430. The interfacial layer 420 may include a material represented by MM'ON, M′O, or M'ON, where M may include any one of the following: Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U, and M' may include any one of the following: H, Li, Be, B, N, O, Na, Mg, Al, Si, P, S, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, As, Se, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U. A leakage current reduction layer 440 may be further provided between the dielectric layer 430 and the second electrode 450. The leakage current reduction layer 440 may include, for example, an AlZrO layer. However, the leakage current reduction layer 440 is not limited thereto.

[0134] As described above, when the semiconductor device 300 according to an embodiment is applied to the memory device 500, even if the memory device 500 is miniaturized, the semiconductor device 300 may include a first intermediate layer 330 and a second intermediate layer 360, thereby reducing the contact resistance and improving the electrical characteristics.

[0135] In Figure 30 , the semiconductor devices 100A, 100B, 200, 300A, 300B, and 300C according to the embodiments may be applied instead of the semiconductor device 300.

[0136] The semiconductor device according to an embodiment has an ultra-small size and excellent electrical performance, and thus is suitable for application to an integrated circuit (IC) device with high integration.

[0137] A semiconductor device according to an embodiment can form a transistor, and the transistor forms a digital circuit or an analog circuit. In some configurations, the semiconductor device can be used as a high-voltage transistor or a low-voltage transistor. For example, the semiconductor device in the embodiment can form a high-voltage transistor, and the high-voltage transistor forms a peripheral circuit of a flash memory device and an electrically erasable programmable read-only memory (EEPROM) device, and the flash memory device and the electrically erasable programmable read-only memory (EEPROM) device are non-volatile memory devices that operate at a high voltage. Alternatively, the semiconductor device according to the embodiment can form a transistor included in an IC chip for a liquid crystal display (LCD), an IC chip for an LED display device or a micro-LED display device.

[0138] Figure 31 FIG. 6 is a schematic block diagram of a display driver IC (DDI) 1500 according to an embodiment and a display device 1520 including the DDI 1500.

[0139] Reference Figure 31 , the DDI 1500 can include a controller 1502, a power circuit 1504, a driver block 1506, and a memory block 1508. The controller 1502 receives and decodes a command applied from a main processing unit (MPU) 1522, and controls each block of the DDI 1500 to implement an operation according to the command. The power circuit 1504 generates a driving voltage in response to the control of the controller 1502. The driver block 1506 drives a display panel 1524 by using the driving voltage generated by the power circuit 1504 in response to the control of the controller 1502. The display panel 1524 can be an LCD panel or a micro-LED device. The memory block 1508 is a block that temporarily stores a command input to the controller 1502 or a control signal output from the controller 1502 or stores necessary data, and can include memories such as a RAM and a ROM. The power circuit 1504 and the driver block 1506 can include the semiconductor devices 100, 200, 300, 300A, 300B, and 300C according to the above embodiments.

[0140] Figure 32 FIG. 7 is a circuit diagram of a CMOS inverter 1600 according to an embodiment.

[0141] The CMOS inverter 1600 includes a CMOS transistor 1610. The CMOS transistor 1610 includes a PMOS transistor 1620 and an NMOS transistor 1630 connected to each other between a power supply terminal Vdd and a ground terminal. The CMOS transistor 1610 can include the semiconductor devices 100, 200, 300, 300A, 300B, and 300C according to the above embodiments.

[0142] Figure 33 It is a circuit diagram of a CMOS SRAM device 1700 according to an embodiment.

[0143] The CMOS SRAM device 1700 includes a pair of driving transistors 1710. Each of the pair of driving transistors 1710 includes a PMOS transistor 1720 and an NMOS transistor 1730 that are connected to each other between a power supply terminal Vdd and a ground terminal. The CMOS SRAM device 1700 may further include a pair of transfer transistors 1740. The source of the transfer transistor 1740 is cross-connected to a common node of the PMOS transistor 1720 and the NMOS transistor 1730 that constitute the driving transistor 1710. The power supply terminal Vdd is connected to the source of the PMOS transistor 1720, and the ground terminal is connected to the source of the NMOS transistor 1730. The word line WL may be connected to the gates of the pair of transfer transistors 1740, and the bit line BL and the inverted phase line may be respectively connected to the drains of the pair of transfer transistors 1740.

[0144] At least one of the driving transistor 1710 and the transfer transistor 1740 of the CMOS SRAM device 1700 may include semiconductor devices 100, 200, 300, 300A, 300B, and 300C according to the above embodiments.

[0145] Figure 34 It is a circuit diagram of a CMOS NAND circuit 1800 according to an embodiment.

[0146] The CMOS NAND circuit 1800 includes a pair of CMOS transistors to which different input signals are transmitted. The CMOS NAND circuit 1800 may include semiconductor devices 100, 200, 300, 300A, 300B, and 300C according to the above embodiments.

[0147] Figure 35 It is a block diagram showing an electronic system 1900 according to an embodiment.

[0148] The electronic system 1900 includes a memory 1910 and a memory controller 1920. The memory controller 1920 may control the memory 1910 to read data from and / or write data to the memory 1910 in response to a request from a host 1930. At least one of the memory 1910 and the memory controller 1920 may include semiconductor devices 100, 200, 300, 300A, 300B, and 300C according to the above embodiments.

[0149] Figure 36 It is a block diagram of an electronic system 2000 according to an embodiment.

[0150] The electronic system 2000 can configure a wireless communication device or a device capable of transmitting and / or receiving information in a wireless environment. The electronic system 2000 includes a controller 2010, an input / output device (I / O) 2020, a memory 2030, and a wireless interface 2040, which are interconnected via a bus 2050.

[0151] The controller 2010 can include at least one of a microprocessor, a digital signal processor, and similar processor devices. The I / O device 2020 can include at least one of a keypad, a keyboard, and a display. The memory 2030 can be used to store commands executed by the controller 2010. For example, the memory 2030 can be used to store user data. The electronic system 2000 can use the wireless interface 2040 to send / receive data via a wireless communication network. The wireless interface 2040 can include an antenna and / or a wireless transceiver. The electronic system 2000 can include semiconductor devices 100, 200, 300, 300A, 300B, and 300C according to the above-described embodiments with reference to Figures 1 to 26 .

[0152] According to an embodiment, a semiconductor device can exhibit good electrical performance in a super-small structure, and thus can be applied to IC devices, and miniaturization, low power, and high performance can be achieved.

[0153] According to an embodiment, a semiconductor device can include a first intermediate layer between a lower electrode and a channel and a second intermediate layer between an upper electrode and the channel, thereby reducing contact resistance.

[0154] As the size of a semiconductor device decreases and the contact area between an electrode and a channel decreases, the contact resistance increases. According to an embodiment, a semiconductor device can reduce contact resistance by using a first intermediate layer and a second intermediate layer including different materials.

[0155] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that various changes in form and detail can be made therein without departing from the spirit and scope defined by the appended claims.

[0156] This application is based on and claims priority to Korean Patent Application No. 10-2024-0008289, filed with the Korean Intellectual Property Office on January 18, 2024, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: A lower electrode; A channel on the lower electrode, the channel comprising an oxide semiconductor; An upper electrode on the channel, the upper electrode comprising tungsten or molybdenum; A first intermediate layer between the lower electrode and the channel; and A second intermediate layer between the channel and the upper electrode, Wherein the channel has a vertical channel structure extending from the lower electrode to the upper electrode in a vertical direction, The first intermediate layer and the second intermediate layer contain different materials from each other, The first intermediate layer comprises indium oxide or indium nitride, and The second intermediate layer comprises a material having an oxide formation energy greater than that of the upper electrode, and the oxide formation energy of the second intermediate layer is in the range of -2.5 eV / atom to 0.5 eV / atom.

2. The semiconductor device according to claim 1, wherein the second intermediate layer comprises a material having a work function in the range of 4.6 eV to 6.0 eV.

3. The semiconductor device according to claim 1, wherein the difference between the oxide formation energy of the second intermediate layer and the oxide formation energy of the upper electrode is in the range of 0.5 eV / atom to 3.58 eV / atom.

4. The semiconductor device according to claim 1, wherein the second intermediate layer comprises at least one of Ni, Co, Rh, Pd, Pt, Re, Ru, and Cu.

5. The semiconductor device according to claim 1, wherein the channel is an oxide comprising at least one of In, Zn, Ga, Sn, Hf, and Ti.

6. The semiconductor device according to claim 1, wherein the lower electrode comprises at least one selected from the group consisting of W (tungsten), Co (cobalt), Ni (nickel), Fe (iron), Ti (titanium), Mo (molybdenum), Cr (chromium), Zr (zirconium), Hf (hafnium), Nb (niobium), Ta (tantalum), Ag (silver), Au (gold), Al (aluminum), Cu (copper), Sb (tin), V (vanadium), Ru (ruthenium), Pt (platinum), Zn (zinc), and Mg (magnesium) or comprises a nitride containing these materials.

7. The semiconductor device according to claim 1 further comprises: A bonding layer comprising TiN between the second intermediate layer and the upper electrode.

8. The semiconductor device according to claim 1, wherein the second intermediate layer extends from a bonding surface between the channel and the upper electrode to a side surface of the upper electrode.

9. The semiconductor device according to claim 1, wherein the first intermediate layer has a thickness in the range of 1 nm to 5 nm.

10. The semiconductor device according to claim 1, wherein the second intermediate layer has a thickness in the range of 1 nm to 3 nm.

11. The semiconductor device according to claim 1, wherein the thickness of the second intermediate layer is less than the thickness of the first intermediate layer.

12. The semiconductor device according to claim 1 further comprises: A metal oxide layer between the lower electrode and the first intermediate layer.

13. The semiconductor device according to claim 1, wherein the gate electrode has a gate-all-around structure to surround the channel.

14. The semiconductor device according to claim 1, wherein the channel, the gate insulating layer, and the gate electrode are arranged such that their longitudinal directions are in the vertical direction of the semiconductor device and are arranged in the horizontal direction of the semiconductor device.

15. The semiconductor device according to claim 1, wherein the channel has a U-shaped cross-section.

16. The semiconductor device according to claim 1, wherein the channel includes a first channel having an L-shaped cross-section and a second channel symmetrically arranged with respect to the first channel about the vertical direction of the semiconductor device.

17. A method of manufacturing a semiconductor device, the method comprising: depositing a lower electrode on a substrate; depositing a first intermediate layer on the lower electrode; depositing a channel including an oxide semiconductor on the first intermediate layer; depositing a gate insulating layer on the channel; depositing a gate electrode on the gate insulating layer; depositing a second intermediate layer on the upper surface of the channel; and depositing an upper electrode on the second intermediate layer, wherein the first intermediate layer and the second intermediate layer include different materials from each other, the first intermediate layer includes indium oxide or indium nitride, and the second intermediate layer includes a material having an oxide formation energy greater than that of the upper electrode, and the oxide formation energy of the second intermediate layer is in the range of -2.5 eV / atom to 0.5 eV / atom.

18. The method according to claim 17, wherein the first intermediate layer, the channel, and the second intermediate layer are formed by an atomic layer deposition method.

19. The method according to claim 17, wherein the second intermediate layer includes a material having a work function in the range of 4.6 eV to 6.0 eV.

20. The method according to claim 17, wherein the second intermediate layer includes at least one of Ni, Co, Rh, Pd, Pt, Re, Ru, and Cu.

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