Two-dimensional indium selenide / tungsten selenide ferroelectric heterojunction transistor with low gate voltage regulation and control and preparation method of two-dimensional indium selenide / tungsten selenide ferroelectric heterojunction transistor

Abstract

The invention belongs to the field of heterojunction transistors, discloses a two-dimensional indium selenide / tungsten selenide ferroelectric heterojunction transistor with low gate voltage regulation and control and a preparation method, and particularly provides application of the two-dimensional indium selenide / tungsten selenide ferroelectric heterojunction transistor in showing higher capability of gate voltage regulation and control of ferroelectric polarization inversion under the condition of low gate voltage. According to the two-dimensional indium selenide / tungsten selenide heterojunction ferroelectric transistor, SiO2 / Si serves as a substrate, a source electrode and a drain electrode are arranged on the surface of the substrate at intervals, and an alpha-In2Se3 / WSe2 heterojunction is formed; compared with a single alpha-In2Se3 transistor, the heterojunction ferroelectric transistor shows stronger capability of regulating and controlling ferroelectric polarization inversion by a gate voltage under a gate scanning voltage of-10V to + 10V. The invention finds that a heterojunction transistor device composed of alpha-In2Se3 and WSe2 can realize ferroelectric channel modulation under small gate voltage, and solves the application problem that a single alpha-In2Se3 transistor can only show ferroelectric modulation under large gate voltage.

Description

Technical Field

[0001] The present invention belongs to the field of heterojunction transistors, and more specifically, relates to a two-dimensional indium selenide / tungsten diselenide ferroelectric heterojunction transistor with low gate voltage regulation and a preparation method thereof. Background Art

[0002] The discovery of two-dimensional van der Waals ferroelectric materials effectively solves the problem of compatibility with traditional ferroelectric materials in the integrated CMOS process. The ferroelectric polarization of two-dimensional intrinsic ferroelectric materials mainly originates from the eccentric displacement of specific atoms in the unit cell, breaking the spatial inversion symmetry and forming switchable electric dipoles. In2Se3 is a two-dimensional ferroelectric material that has been intensively studied in recent years, and the obvious property differences among its multiple phases fully reflect its research potential. Numerous theories and experiments indicate that α-In2Se3 is the most stable crystalline phase of the In2Se3 system at room temperature, and has the valuable property of coupling in-plane polarization and out-of-plane polarization. However, a back-gate transistor device with a SiO2 gate dielectric prepared with α-In2Se3 as the channel material can only exhibit suitable ferroelectricity under a large gate voltage of ±50V, which greatly hinders the application process of α-In2Se3 transistors.

[0003] At the same time, monolayer WSe2 material, as a direct-bandgap P-type semiconductor material, is a research hotspot for preparing heterojunctions with other N-type semiconductor materials. Most of the existing WSe2 heterojunction devices focus on reporting their excellent optoelectronic properties and applications, and few people pay attention to their influence on the ferroelectricity of ferroelectric materials.

[0004] Chinese Patent CN114361296A discloses a preparation method of a high-performance photodetector based on a heterojunction structure, which is a two-terminal device of a heterojunction; although it also constructs a WSe2 / α-In2Se3 heterojunction formed by a p-type-WSe2 two-dimensional crystal material and an n-type-α-In2Se3 crystal two-dimensional material, it uses a method of first constructing the heterojunction and then evaporating a metal electrode thereon. This method is relatively cumbersome, and the device cannot be reused, and lattice damage and defects will be introduced into the heterojunction channel when evaporating the electrode. The two-terminal device of the heterojunction reported in the literature does not further explore and utilize the out-of-plane ferroelectricity of α-In2Se3, and lacks an effective means to regulate the ferroelectric polarization inversion of α-In2Se3 by a gate. Summary of the Invention

[0005] In view of the above deficiencies or improvement requirements of the prior art, the purpose of the present invention is to provide a two-dimensional indium selenide / tungsten diselenide ferroelectric heterojunction transistor with low gate voltage regulation and a preparation method thereof. It is found that a heterojunction transistor device composed of α-In2Se3 and WSe2 can achieve ferroelectric channel modulation under a small gate voltage, enabling the device to exhibit ferroelectricity and solving the application problem that a single α-In2Se3 transistor can only exhibit ferroelectric modulation under a large gate voltage.

[0006] To achieve the above object, according to the present invention, there is provided an application of a two-dimensional indium selenide / tungsten diselenide heterojunction ferroelectric transistor in exhibiting a stronger ability of gate voltage-regulated ferroelectric polarization reversal under low gate voltage conditions. The characteristics are that the two-dimensional indium selenide / tungsten diselenide heterojunction ferroelectric transistor uses SiO2 / Si as a substrate, and a source electrode and a drain electrode are arranged at intervals on the surface of the substrate; one of the source electrode and the drain electrode is denoted as the first electrode, and the other is denoted as the second electrode. Then, one end of the two-dimensional WSe2 material peeled off is covered by the first electrode, and one end of the two-dimensional α-In2Se3 thin film peeled off is covered by the second electrode; the two-dimensional WSe2 material is arranged along the surface of the substrate, and the other end of the two-dimensional WSe2 material is located between the first electrode and the second electrode and is spaced from the second electrode; the two-dimensional α-In2Se3 thin film is arranged along the surface of the substrate, and the other end of the two-dimensional α-In2Se3 thin film is also located between the first electrode and the second electrode and partially overlaps with the two-dimensional WSe2 material, covering the upper part of the edge of the two-dimensional WSe2 material;

[0007] The two-dimensional indium selenide / tungsten diselenide heterojunction ferroelectric transistor exhibits a stronger ability of gate voltage-regulated ferroelectric polarization reversal compared with a single α-In2Se3 transistor under a gate scanning voltage of -10V to +10V; wherein, the single α-In2Se3 transistor uses SiO2 / Si as a substrate, a source electrode and a drain electrode are arranged at intervals on the surface of the substrate, and a single α-In2Se3 material is arranged along the surface of the substrate, and both ends of the α-In2Se3 material cover the source electrode and the drain electrode respectively.

[0008] As a further preference of the present invention, in the two-dimensional indium selenide / tungsten diselenide heterojunction ferroelectric transistor and the single α-In2Se3 transistor, the source electrode and the drain electrode both adopt a chromium / gold laminated electrode, wherein the chromium layer is in direct contact with the substrate.

[0009] As a further preference of the present invention, the chromium / gold laminated electrode is formed by evaporation. In the chromium / gold laminated electrode, the thickness of the chromium layer is 5nm, and the thickness of the gold layer is 25nm.

[0010] As a further preference of the present invention, in the two-dimensional indium selenide / tungsten selenide heterojunction ferroelectric transistor and the single α-In2Se3 transistor, the channel width between the source and the drain is 20 μm.

[0011] As a further preference of the present invention, the two-dimensional indium selenide / tungsten selenide heterojunction ferroelectric transistor is prepared by a preparation method including the following steps:

[0012] (1) A first electrode and a second electrode are prepared on the surface of the SiO2 / Si substrate by using a metal hard mask template, and the distance between the first electrode and the second electrode meets a preset requirement, correspondingly forming a channel with a preset width;

[0013] (2) The two-dimensional WSe2 material is transferred onto the substrate obtained in step (1) by using the mechanical exfoliation method, so that the exfoliated two-dimensional WSe2 material is arranged along the substrate surface, and one end of the exfoliated two-dimensional WSe2 material covers the first electrode; the other end of the two-dimensional WSe2 material is located between the first electrode and the second electrode and is spaced from the second electrode;

[0014] (3) The two-dimensional α-In2Se3 material is transferred onto the substrate obtained in step (2) by using the mechanical exfoliation method, so that the exfoliated two-dimensional α-In2Se3 material is arranged along the substrate surface, and one end of the exfoliated two-dimensional α-In2Se3 thin film covers the second electrode; the other end of the two-dimensional α-In2Se3 thin film is also located between the first electrode and the second electrode and partially overlaps with the two-dimensional WSe2 material, covering above the edge of the two-dimensional WSe2 material, thereby forming a two-dimensional indium selenide / tungsten selenide heterojunction.

[0015] As a further preference of the present invention, in step (1), the thickness of SiO2 in the SiO2 / Si substrate is 150 nm.

[0016] As a further preference of the present invention, in step (1), the first electrode and the second electrode are a chromium / gold laminated electrode formed by electron beam evaporation, and the evaporation sequence is chromium first and then gold.

[0017] As a further preference of the present invention, both the two-dimensional α-In2Se3 material and the two-dimensional WSe2 material are obtained by dry transfer on a pure bulk crystal by using the mechanical exfoliation method; preferably, it is obtained by dry transfer by adhering to a thin layer through the adhesion force on the surface of polydimethylsiloxane (PDMS).

[0018] Through the above technical solution conceived by the present invention, compared with the prior art, the present invention obtains a two-dimensional indium selenide / tungsten selenide heterojunction ferroelectric transistor with low gate voltage regulation, which can exhibit ferroelectricity under low gate voltage, overcoming the problem of large gate voltage application of a single α-In2Se3 transistor. The heterojunction in the present invention is composed of vertically stacked two-dimensional indium selenide and two-dimensional tungsten selenide, and the structure of the vertical heterojunction is specifically metal-two-dimensional indium selenide-two-dimensional tungsten selenide-metal. On the basis of the original channel transistor, the present invention adds materials to form a heterojunction structure, effectively improving the ferroelectric channel regulation performance of the device, reducing the required gate voltage, and contributing to the application of ferroelectric semiconductor field effect transistors.

[0019] The preparation method of the device of the present invention is simple and efficient. The heterojunction device can adopt the process sequence of first evaporating source and drain electrodes and then transferring two-dimensional materials, avoiding the lattice damage defects introduced on the surface of the two-dimensional channel material during the metal evaporation process, and obtaining a higher-quality two-dimensional semiconductor-metal interface contact. For example, based on the present invention, a metal chromium hard mask can be used to evaporate and deposit metal electrodes on the surface of a SiO2 / Si substrate (such as a commercially available 150nm SiO2 / Si substrate). Based on the two-dimensional tungsten selenide material peeled from the bulk by mechanical exfoliation, the dry transfer technology and the fixed-point transfer method of the two-dimensional material transfer platform are used to build it between two metal electrodes, and then the two-dimensional α-phase indium selenide is peeled off in the same way and covered between the two-dimensional tungsten selenide material and the metal electrodes to construct a two-dimensional indium selenide / tungsten selenide heterojunction structure (the obtained heterojunction structure can be stored in a dry environment at room temperature). The method of the present invention can stably prepare high-quality metal-two-dimensional indium selenide-two-dimensional tungsten selenide-metal heterojunction transistors, while avoiding the chemical pollution in the lithography process and the damage to the material surface during the electrode evaporation process, weakening the Fermi level pinning caused by interface defects, forming a high-quality two-dimensional indium selenide / tungsten selenide heterojunction interface contact, and promoting the construction of two-dimensional indium selenide / tungsten selenide heterojunction ferroelectric transistors.

[0020] Specifically, the present invention can achieve the following beneficial effects:

[0021] (1) After replacing the single α-In2Se3 channel with the α-In2Se3 / WSe2 heterojunction channel in the present invention, it is found that its ferroelectric performance is significantly improved, and the gate voltage for realizing polarization reversal is also greatly reduced, which helps to promote its application process. The heterojunction transistor device obtained by the present invention has better ferroelectric regulation performance, which helps to the application of ferroelectric semiconductor field effect transistors.

[0022] (2) The preparation method of the device of the present invention has simple process operations and high repeatability. The preparation process of the present invention is carried out under normal temperature and pressure throughout, and the process flow is to deposit electrodes first and then transfer two-dimensional materials. If the material parameters transferred at one time do not meet the requirements, the materials can be removed by cleaning and then transferred again, enabling the device to be reused repeatedly and avoiding the cumbersome traditional processes. At the same time, the interface damage of the two-dimensional material is small, and a higher-quality interface contact can be formed. The process operations of the preparation method of the present invention avoid lithography on the two-dimensional material, avoiding chemical contamination during the lithography process and material damage introduced during the evaporation process.

[0023] The heterojunction transistor device composed of α-In2Se3 and WSe2 can regulate the ferroelectric polarization inversion of the channel material and thus regulate the channel conductance through the gate voltage compared with the two-terminal heterojunction device (such as the two-terminal heterojunction device reported in CN114361296A). Compared with a single α-In2Se3 transistor device, it also reduces the gate voltage required to regulate the ferroelectric polarization inversion, which opens up a relatively wide application prospect for the device (such as being used as a neural synapse device to simulate the regulation of synaptic weights by regulating the channel conductance of the device through the gate voltage). Brief Description of the Drawings

[0024] Figure 1 It is a schematic structural diagram of the α-In2Se3 ferroelectric transistor prepared in Example 1 of the method of the present invention.

[0025] Figure 2 It is an optical microscope picture of the α-In2Se3 ferroelectric transistor prepared in Example 1 of the method of the present invention.

[0026] Figure 3 It is a transfer characteristic curve of the α-In2Se3 ferroelectric transistor prepared in Example 1 of the method of the present invention.

[0027] Figure 4 It is a schematic structural diagram of the α-In2Se3 / WSe2 heterojunction ferroelectric transistor prepared in Example 2 of the method of the present invention.

[0028] Figure 5 It is an optical microscope picture of the α-In2Se3 / WSe2 heterojunction ferroelectric transistor prepared in Example 2 of the method of the present invention.

[0029] Figure 6 It is a transfer characteristic curve of the α-In2Se3 / WSe2 heterojunction ferroelectric transistor prepared in Example 2 of the method of the present invention. Detailed Embodiments

[0030] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0031] The two-dimensional α-In2Se3 and two-dimensional WSe2 bulk materials used in the following examples are all industrial products purchased on the market with a purity greater than 99.99%.

[0032] Example 1:

[0033] In this example, based on the prior art, an α-In2Se3 ferroelectric transistor with a back-gate structure is prepared using a single two-dimensional α-In2Se3 material, which specifically includes the following steps:

[0034] Step 1: First, a single two-dimensional α-In2Se3 ferroelectric transistor was prepared. A 150 nm SiO2 / Si substrate was selected as the substrate and cut into squares with a silicon wafer knife, and then cleaned successively with acetone, ethanol, and deionized water. Then, a photoresist was spin-coated on the substrate using a spin coater. After pre-baking, a metal hard mask was used to lithograph the electrode channels on the substrate, and after post-baking, a developer solution was prepared for development. A 5 nm metal Cr and a 25 nm metal Au were successively evaporated on the lithographed substrate using a syskey electron beam evaporator. Finally, stripping was performed with acetone, and after cleaning with ethanol and deionized water, the substrate with the electrodes and channels etched was obtained.

[0035] Step 2: A small amount of α-In2Se3 bulk material was picked up with a blue film tape and folded in half along the center, and pasted back and forth seven to eight times. A PDMS rubber block of about 5 mm × 5 mm was cut and stuck on a glass slide, and the material on the blue film tape was picked up with the other side. Uniform materials with appropriate size and thickness were observed under a microscope, and then transferred to the electrodes and channels of the substrate at fixed points using a two-dimensional material transfer platform. The schematic structural diagram is as shown in Figure 1 , and the physical photo is as shown in Figure 2 .

[0036] Figure 3 is the transfer curve graph of the prepared two-dimensional α-In2Se3 ferroelectric transistor. It can be clearly seen from the figure that it is very difficult to observe the polarization reversal of the channel material (the storage window is very small) of the α-In2Se3 ferroelectric transistor under a gate voltage of ±10 V (i.e., a gate sweep voltage of -10 V to +10 V). As the gate voltage increases, the storage window shows a positive correlation and an increasing trend, and a large storage window can only be exhibited at a large gate voltage (±50 V, i.e., a gate sweep voltage of -50 V to +50 V), which greatly hinders its application process.

[0037] Example 2:

[0038] This example is based on the inventive concept of the present invention to prepare an α-In2Se3 / WSe2 heterojunction ferroelectric transistor with a back-gate structure. The transfer sequence is to selenize tungsten first and then indium. A part of the transferred two-dimensional indium selenide material can cover the tungsten selenide material. The specific steps are as follows:

[0039] Step 1: Preparation of the α-In2Se3 / WSe2 heterojunction ferroelectric transistor. Similarly, a 150-nm SiO2 / Si substrate is selected as the substrate, which is cut into squares with a silicon wafer knife and cleaned successively with acetone, ethanol, and deionized water. Then, a photoresist is spin-coated on the substrate using a spin coater. After pre-baking, a metal hard mask template is used to lithograph the electrode channels on the substrate, and after post-baking, a developer is prepared for development. A 5-nm metal Cr and a 25-nm metal Au are successively evaporated on the lithographed substrate using a syskey electron beam evaporator. Finally, stripping is performed with acetone, and after cleaning with ethanol and deionized water, the substrate with the electrodes and channels engraved can be obtained.

[0040] Step 2: Take some WSe2 bulk materials with blue film tape and fold them in half along the center, and paste them repeatedly seven to eight times. Cut a PDMS rubber block of about 5 mm×5 mm and stick it on a glass slide, and use the other side to pick up the materials on the blue film tape. Observe the uniform materials with appropriate size and thickness under a microscope, and use a two-dimensional material transfer platform to transfer them to the electrodes and channels of the substrate at a fixed point. It should be noted that the WSe2 material needs to cover one electrode on one side and be in the channel between the two electrodes on the other side, and cannot cover the other electrode (a suitable distance can be left for the subsequent transfer of two-dimensional indium selenide). Transfer the α-In2Se3 material in the same way, and it should be noted that one side of the α-In2Se3 material covers the WSe2 material and the other side covers the other electrode. The structural schematic diagram is as Figure 4 , and the physical photo is as Figure 5 .

[0041] Figure 6 is the transfer characteristic curve of the prepared α-In2Se3 / WSe2 heterojunction ferroelectric transistor. Compared with Figure 3 , it can be seen that the addition of the WSe2 material greatly reduces the gate voltage required for ferroelectric regulation, and can exhibit a strong ability to regulate ferroelectric polarization reversal with a gate voltage of ±10 V (i.e., a gate sweep voltage of -10 V to +10 V). The storage window is significantly larger than that of a single two-dimensional α-In2Se3 ferroelectric transistor under a ±10 V gate voltage, optimizing the ferroelectric performance of the device, and at the same time, the on-off ratio of the transistor is significantly increased. Figure 3

[0042] ​The above embodiments are only examples. For example, in addition to the chromium / gold laminated electrode with the above-mentioned thickness setting for the source and drain, other thickness settings can also be used (such as other settings with a total thickness < 40 nm). Of course, in addition to the chromium / gold laminated electrode, other commonly used electrodes can also be used; for another example, the channel width can also be adjusted according to actual needs.

[0043] Those skilled in the art can easily understand that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention should be included within the protection scope of the present invention.

Claims

1. Application of a two-dimensional indium selenide / tungsten selenide heterojunction ferroelectric transistor in showing a stronger ability to regulate ferroelectric polarization inversion under low gate voltage conditions, characterized in that The two-dimensional indium selenide / tungsten diselenide heterojunction ferroelectric transistor uses SiO2 / Si as a substrate, and a source electrode and a drain electrode are spaced apart on the surface of the substrate; one of the source electrode and the drain electrode is denoted as the first electrode, and the other is denoted as the second electrode. Then, one end of the two-dimensional WSe2 material peeled off is covered by the first electrode, and one end of the two-dimensional α-In2Se3 thin film peeled off is covered by the second electrode; the two-dimensional WSe2 material is arranged along the substrate surface, and the other end of the two-dimensional WSe2 material is located between the first electrode and the second electrode and is spaced from the second electrode; the two-dimensional α-In2Se3 thin film is arranged along the substrate surface, and the other end of the two-dimensional α-In2Se3 thin film is also located between the first electrode and the second electrode and partially overlaps with the two-dimensional WSe2 material, covering the upper part of the edge of the two-dimensional WSe2 material. Under the gate scanning voltage of -10V to +10V, the two-dimensional indium selenide / tungsten diselenide heterojunction ferroelectric transistor exhibits a stronger ability to regulate ferroelectric polarization reversal by the gate voltage compared with a single α-In2Se3 transistor; among them, the single α-In2Se3 transistor uses SiO2 / Si as a substrate, a source electrode and a drain electrode are spaced apart on the surface of the substrate, and a single α-In2Se3 material is arranged along the substrate surface, and both ends of the α-In2Se3 material cover the source electrode and the drain electrode respectively.

2. The application according to claim 1, characterized in that, In the two-dimensional indium selenide / tungsten diselenide heterojunction ferroelectric transistor and the single α-In2Se3 transistor, both the source electrode and the drain electrode are laminated electrodes of chromium / gold, and among them, the chromium layer is in direct contact with the substrate.

3. The application according to claim 2, wherein The laminated electrode of chromium / gold is formed by evaporation. In the laminated electrode of chromium / gold, the thickness of the chromium layer is 5nm, and the thickness of the gold layer is 25nm.

4. The application according to claim 1, wherein In the two-dimensional indium selenide / tungsten diselenide heterojunction ferroelectric transistor and the single α-In2Se3 transistor, the channel width between the source electrode and the drain electrode is 20μm.

5. The application according to claim 1, characterized in that, The two-dimensional indium selenide / tungsten diselenide heterojunction ferroelectric transistor is prepared by a preparation method including the following steps: (1) Use a metal hard mask template to prepare a first electrode and a second electrode spaced apart on the surface of the SiO2 / Si substrate. The distance between the first electrode and the second electrode meets the preset requirements, and a channel with a preset width is correspondingly formed. (2) Use the mechanical exfoliation method to transfer the two-dimensional WSe2 material onto the substrate obtained in step (1), so that the exfoliated two-dimensional WSe2 material is arranged along the substrate surface, and one end of the two-dimensional WSe2 material peeled off is covered by the first electrode; the other end of the two-dimensional WSe2 material is located between the first electrode and the second electrode and is spaced from the second electrode. (3) Transfer the two-dimensional α-In2Se3 material to the substrate obtained in step (2) by mechanical exfoliation method, and arrange the exfoliated two-dimensional α-In2Se3 material along the surface of the substrate. One end of the exfoliated two-dimensional α-In2Se3 thin film covers the second electrode; the other end of the two-dimensional α-In2Se3 thin film is also located between the first electrode and the second electrode, and partially overlaps with the two-dimensional WSe2 material, covering the upper part of the edge of the two-dimensional WSe2 material, thereby forming a two-dimensional indium selenide / tungsten selenide heterojunction.

6. The application according to claim 5, wherein In step (1), the thickness of SiO2 in the SiO2 / Si substrate is 150 nm.

7. The application according to claim 5, characterized in that In step (1), the first electrode and the second electrode are a chromium / gold laminated electrode formed by electron beam evaporation, and the evaporation sequence is chromium first and then gold.

8. The application according to claim 5, characterized in that, Both the two-dimensional α-In2Se3 material and the two-dimensional WSe2 material are obtained by dry transfer on a pure bulk crystal by mechanical exfoliation method.

9. The application according to claim 8, wherein Both the two-dimensional α-In2Se3 material and the two-dimensional WSe2 material are obtained by dry transfer by adhering to a thin layer through the adhesion force on the surface of polydimethylsiloxane (PDMS).

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