Semiconductor device terminal protection structure and manufacturing method

Abstract

The invention provides a semiconductor device terminal protection structure and a manufacturing method. According to the semiconductor device terminal protection structure, in a voltage division protection region, voltage division grooves are formed in a first conduction type epitaxial layer, the columnar voltage division grooves are arranged at intervals to form disconnected annular groove structures, and more than two disconnected annular groove structures are arranged around an active region at intervals; a second conductive type well region is arranged at the top of the first conductive type epitaxial layer; the voltage dividing groove extends below the second conductive type well region from the first main surface; a gate oxide layer is arranged on the inner wall of the voltage dividing groove; field plate polycrystalline silicon is arranged in the partial pressure groove; the series diode structure and the leading-out pole which are integrally constructed stretch across all more than two disconnected annular groove structures; the terminal electric field can be better and uniformly distributed, and the voltage withstanding reliability of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a terminal protection structure and manufacturing method for semiconductor devices. Background Art

[0002] There are roughly several existing terminal protection structures for semiconductor devices: 1. Closed annular trench type terminals (for example, the invention patent 201210332017.8 provides a trench type semiconductor power device with a 4-layer lithography technology); 2. Closed annular implanted well protection terminals or closed annular doped well protection terminals combined with polysilicon / metal field plates; these terminal protection structures have relatively high requirements for designers. The voltage division ability and voltage tolerance of the terminal protection ring are related to many factors such as the distance, width, and epitaxial layer of the ring. They are passive voltage division structures. Due to factors such as the spacing between the voltage withstand wells and the epitaxial depletion rate, the electric potential is unevenly distributed between the wells. In the closed annular trench type terminal, there will be electric field concentration on the inner side of each terminal protection trench, and in the closed annular implanted well protection terminal or the closed annular doped well protection terminal combined with polysilicon / metal field plates, there will be electric field concentration on the outer side of each terminal protection ring, which will reduce its reliability.

[0003] For the existing closed independent voltage division rings, whether they are doped well type or trench type, there are many influencing factors for the voltage division values on each voltage division ring, and it is impossible to achieve average voltage division, and the electric field cannot be evenly distributed; there are problems of premature breakdown and reduced reliability. Summary of the Invention

[0004] To solve at least one technical problem in the prior art, embodiments of the present invention provide a terminal protection structure and manufacturing method for semiconductor devices to improve the reliability of the devices. To achieve the above technical objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, embodiments of the present invention provide a terminal protection structure for semiconductor devices; the semiconductor device includes an active region, a voltage division protection region, and a cut-off protection region; the active region is located in the central region of the device layout, the voltage division protection region is arranged around the active region, and the cut-off protection region is arranged around the voltage division protection region; the semiconductor device includes a first conductive type substrate, and a first conductive type epitaxial layer is provided on the first conductive type substrate; the surface of the first conductive type epitaxial layer facing away from the first conductive type substrate is the first main surface, and the surface of the first conductive type substrate facing away from the first conductive type epitaxial layer is the second main surface; a drain metal is provided on the second main surface; In the active region, there are unit cell trenches in the first-conductivity-type epitaxial layer; the strip-shaped unit cell trenches are arranged in parallel at intervals; on the top of the first-conductivity-type epitaxial layer between adjacent unit cell trenches, a second-conductivity-type well region and a first-conductivity-type implantation layer are provided from bottom to top; the unit cell trenches extend from the first main surface under the second-conductivity-type well region; a gate oxide layer is provided on the inner wall of the unit cell trenches; gate polysilicon is provided in the unit cell trenches, and the gate polysilicon is insulated from the first-conductivity-type implantation layer, the second-conductivity-type well region and the first-conductivity-type epitaxial layer through the gate oxide layer; a second type of insulating dielectric layer is provided above the first main surface, and a source metal and a gate metal are provided on the second type of insulating dielectric layer; the source metal is connected to the first-conductivity-type implantation layer and the second-conductivity-type well region between adjacent unit cell trenches through a source contact hole penetrating the second type of insulating dielectric layer and the first-conductivity-type implantation layer, and is connected to the second-conductivity-type well region between the outermost unit cell trench and the voltage-dividing protection region through a source contact hole penetrating the second type of insulating dielectric layer; the gate metal is connected to the gate polysilicon in the unit cell trenches through a gate contact hole penetrating the second type of insulating dielectric layer; The semiconductor device terminal protection structure includes: In the voltage-dividing protection region, voltage-dividing trenches are provided in the first-conductivity-type epitaxial layer, and the columnar voltage-dividing trenches are arranged at intervals to form a discontinuous annular trench structure, and two or more discontinuous annular trench structures are arranged around the active region at intervals; a second-conductivity-type well region is provided on the top of the first-conductivity-type epitaxial layer; the voltage-dividing trenches extend from the first main surface under the second-conductivity-type well region; a gate oxide layer is provided on the inner wall of the voltage-dividing trenches; field plate polysilicon is provided in the voltage-dividing trenches, and the field plate polysilicon is insulated from the second-conductivity-type well region and the first-conductivity-type epitaxial layer through the gate oxide layer; Above the first main surface, there is a strip-shaped integrated series diode structure and an extraction electrode; below the integrated series diode structure and the extraction electrode, there is a first type of insulating dielectric layer; the integrated series diode structure and the extraction electrode straddle above all two or more discontinuous annular trench structures; the series diode structure includes two or more diodes, the second-conductivity-type electrode at the head end of the first diode faces the active region, and the first-conductivity-type electrodes of each diode are respectively located above each discontinuous annular trench structure; the extraction electrode is a second-conductivity-type electrode and is connected to the first-conductivity-type electrode at the end of the last diode, and the extraction electrode faces the cut-off protection region; above the first main surface and the integrated series diode structure and the extraction electrode, there is a second type of insulating dielectric layer; on the second type of insulating dielectric layer, there is an annular interconnect metal; each annular interconnect metal is correspondingly distributed above each discontinuous annular trench structure, and each annular interconnect metal is connected to the first-conductivity-type electrode of a corresponding diode below it through a second type of interconnect contact hole penetrating the second type of insulating dielectric layer, and is connected to the field plate polysilicon in each voltage-dividing trench in a corresponding discontinuous annular trench structure below it through a third type of interconnect contact hole penetrating the second type of insulating dielectric layer; The source metal is also connected to the second-conductivity-type electrode at the head end of the first diode in the integrated series diode structure and the extraction electrode through a first type of interconnect contact hole penetrating the second type of insulating dielectric layer; In the cut-off protection region, a cut-off ring trench is provided in the first-conductivity-type epitaxial layer, and the annular cut-off ring trenches are continuously arranged to form a closed annular trench structure around the voltage-dividing protection region; a second-conductivity-type well region is provided at the top of the first-conductivity-type epitaxial layer, and a second-conductivity-type well region and a first-conductivity-type implantation layer are provided from bottom to top at the top of the first-conductivity-type epitaxial layer on the side of the cut-off ring trench away from the active region; the cut-off ring trench extends from the first main surface under the second-conductivity-type well region; a gate oxide layer is provided on the inner wall of the cut-off ring trench; a cut-off ring polysilicon is provided in the cut-off ring trench; above the first main surface, there is a second type of insulating dielectric layer, and above the second type of insulating dielectric layer, there is a cut-off ring metal, and the cut-off ring metal is connected to the cut-off ring polysilicon in the cut-off ring trench through a cut-off ring contact hole penetrating the second type of insulating dielectric layer, and is connected to the first-conductivity-type implantation layer and the second-conductivity-type well region on the side of the cut-off ring trench away from the active region through a cut-off ring contact hole penetrating the second type of insulating dielectric layer and the first-conductivity-type implantation layer; The cut-off ring metal is also connected to the extraction electrode in the integrated series diode structure and the extraction electrode through a fourth type of interconnect contact hole penetrating the second type of insulating dielectric layer.

[0005] Furthermore, in the integrated series diode structure and the extraction electrode, the reverse voltage drops of each diode are the same.

[0006] Further, in the integrally - structured series diode structure and the lead - out electrode, the reverse breakdown voltage of each diode is 10V - 20V.

[0007] Further, there are multiple integrally - structured series diode structures and lead - out electrodes.

[0008] Further, the voltage - dividing trench is cylindrical.

[0009] In a second aspect, an embodiment of the present invention provides a manufacturing method of a semiconductor device terminal protection structure for manufacturing the semiconductor device terminal protection structure as described above, including the following steps: Step S1: Provide a first - conductivity - type substrate, and grow a first - conductivity - type epitaxial layer on the first - conductivity - type substrate; the surface of the first - conductivity - type epitaxial layer facing away from the first - conductivity - type substrate is the first main surface, and the surface of the first - conductivity - type substrate facing away from the first - conductivity - type epitaxial layer is the second main surface; Etch to form unit cell trenches, voltage - dividing trenches, and cut - off ring trenches in the first - conductivity - type epitaxial layer; the unit cell trenches are located in the active region of the device. In the active region, each strip - shaped unit cell trench is arranged in parallel at intervals; the voltage - dividing trenches are located in the voltage - dividing protection region of the device. In the voltage - dividing protection region, each column - shaped voltage - dividing trench is arranged at intervals and forms a discontinuous annular trench structure, and two or more discontinuous annular trench structures are arranged at intervals around the active region; the cut - off ring trenches are located in the cut - off protection region of the device. In the cut - off protection region, the annular cut - off ring trenches are continuously arranged to form a closed - type annular trench structure around the voltage - dividing protection region; Step S2: Grow or deposit a gate oxide layer on the first main surface, in the unit cell trenches, voltage - dividing trenches, and cut - off ring trenches; Step S3: Deposit and etch conductive polysilicon on the first main surface to form gate polysilicon in the unit cell trenches, field - plate polysilicon in the voltage - dividing trenches, and cut - off ring polysilicon in the cut - off ring trenches; Step S4: Inject second - conductivity - type impurities into the first main surface and push the well to form a second - conductivity - type well region on the top of the first - conductivity - type epitaxial layer; Step S5: Deposit a first - type insulating dielectric layer on the first main surface, and then deposit an undoped polysilicon or single - crystal silicon layer on the first - type insulating dielectric layer; Step S6: Inject first - conductivity - type impurities into the polysilicon or single - crystal silicon layer, and then selectively etch the polysilicon or single - crystal silicon layer and the first - type insulating dielectric layer to leave strip - shaped semiconductor structures and the first - type insulating dielectric layer under the strip - shaped semiconductor structures; the strip - shaped semiconductor structures straddle over all two or more discontinuous annular trench structures; Step S7, selectively implant impurities of the second conduction type so that the strip semiconductor structure forms an integrated series diode structure and an extraction electrode; the series diode structure includes two or more diodes, the second conduction type electrode at the head of the first diode faces the active region, and the first conduction type electrodes of each diode are respectively located above each discontinuous annular trench structure; the extraction electrode is a second conduction type electrode and is connected to the first conduction type electrode at the end of the last diode, and the extraction electrode faces the cut-off protection region; Step S8, selectively implant impurities of the first conduction type and anneal. In the active region, a first conduction type implantation layer is formed on the top of the first conduction type epitaxial layer between adjacent unit cell trenches; in the cut-off protection region, a first conduction type implantation layer is formed on the top of the first conduction type epitaxial layer on the side of the cut-off ring trench facing away from the active region; Step S9, deposit a second type of insulating dielectric layer on the first main surface; then selectively etch hole structures to form a source contact hole, a first type of interconnection contact hole, a second type of interconnection contact hole, a third type of interconnection contact hole, a fourth type of interconnection contact hole, a cut-off ring contact hole, and a gate contact hole; Step S10, deposit a metal layer on the second type of insulating dielectric layer and selectively etch to form a source metal, an annular interconnection metal, a cut-off ring metal, and a gate metal; The source metal is connected to the first conduction type implantation layer between adjacent unit cell trenches and the second conduction type well region through the source contact hole penetrating the second type of insulating dielectric layer and the first conduction type implantation layer, and is connected to the second conduction type well region between the outermost unit cell trench and the voltage dividing protection region through the source contact hole penetrating the second type of insulating dielectric layer; The source metal is also connected to the second conduction type electrode at the head of the first diode in the integrated series diode structure and the extraction electrode through the first type of interconnection contact hole penetrating the second type of insulating dielectric layer; The gate metal is connected to the gate polysilicon in the unit cell trench through the gate contact hole penetrating the second type of insulating dielectric layer; Each annular interconnection metal is correspondingly distributed above each discontinuous annular trench structure. Each annular interconnection metal is connected to the first conduction type electrode of a corresponding diode below it through the second type of interconnection contact hole penetrating the second type of insulating dielectric layer, and is connected to the field plate polysilicon in each voltage dividing trench in a corresponding discontinuous annular trench structure below it through the third type of interconnection contact hole penetrating the second type of insulating dielectric layer; The cut-off ring metal is connected to the cut-off ring polysilicon in the cut-off ring trench through the cut-off ring contact hole penetrating the second type of insulating dielectric layer, and is connected to the first conduction type implantation layer on the side of the cut-off ring trench facing away from the active region and the second conduction type well region through the cut-off ring contact hole penetrating the second type of insulating dielectric layer and the first conduction type implantation layer; The cutoff ring metal is also connected to the lead electrode in the series diode structure and the lead electrode of the integrated structure through the fourth type of interconnection contact hole penetrating the second type of insulating dielectric layer.

[0010] Step S11, depositing a drain metal on the second main surface.

[0011] The beneficial effects brought by the technical solution provided by the embodiment of the present invention are as follows: By setting the discontinuous annular trench structure, the potential density and electric field strength around the voltage-dividing trench are reduced; by introducing the series diode structure, the voltage values borne by each voltage-resistant structure (i.e., the discontinuous annular trench structure) can be set, and the voltages borne by each voltage-resistant structure can be made consistent, so as to achieve better uniform distribution of the terminal electric field, improve the voltage resistance reliability of the device, and the design and process windows. Description of the Drawings

[0012] Figure 1 It is a schematic layout diagram of the semiconductor device structure in the embodiment of the present invention.

[0013] Figure 2a It is a cross-sectional view taken along line A-A in Figure 1 during the etching of the trench in the embodiment of the present invention.

[0014] Figure 2b It is a cross-sectional view taken along line B-B in Figure 1 during the etching of the trench in the embodiment of the present invention.

[0015] Figure 3a It is a cross-sectional view taken along line A-A in Figure 1 during the deposition of the gate oxide layer in the embodiment of the present invention.

[0016] Figure 3b It is a cross-sectional view taken along line B-B in Figure 1 during the deposition of the gate oxide layer in the embodiment of the present invention.

[0017] Figure 4a It is a cross-sectional view taken along line A-A in Figure 1 during the formation of the deposited conductive polysilicon and etching in the embodiment of the present invention.

[0018] Figure 4b It is a cross-sectional view taken along line B-B in Figure 1 during the formation of the deposited conductive polysilicon and etching in the embodiment of the present invention.

[0019] Figure 5a It is a cross-sectional view taken along line A-A in Figure 1 during the formation of the second conductive type well region in the embodiment of the present invention.

[0020] Figure 5b It is a cross-sectional view taken along line B-B in Figure 1 during the formation of the second conductive type well region in the embodiment of the present invention.

[0021] Figure 6a In the embodiment of the present invention, when depositing the first type of insulating dielectric layer and undoped polysilicon or single crystal silicon layer, the Figure 1 Cross-sectional view taken along line A-A in

[0022] Figure 6b In the embodiment of the present invention, when depositing the first type of insulating dielectric layer and undoped polysilicon or single crystal silicon layer, the Figure 1 Cross-sectional view taken along line B-B in

[0023] Figure 7a In the embodiment of the present invention, when forming a strip-shaped semiconductor structure, the Figure 1 Cross-sectional view taken along line A-A in

[0024] Figure 7b In the embodiment of the present invention, when forming a strip-shaped semiconductor structure, the Figure 1 Cross-sectional view taken along line B-B in

[0025] Figure 8a In the embodiment of the present invention, when forming a series diode structure and an extraction electrode, the Figure 1 Cross-sectional view taken along line A-A in

[0026] Figure 8b In the embodiment of the present invention, when forming a series diode structure and an extraction electrode, the Figure 1 Cross-sectional view taken along line B-B in

[0027] Figure 9a In the embodiment of the present invention, when forming a first conductivity type implantation layer, the Figure 1 Cross-sectional view taken along line A-A in

[0028] Figure 9b In the embodiment of the present invention, when forming a first conductivity type implantation layer, the Figure 1 Cross-sectional view taken along line B-B in

[0029] Figure 10a In the embodiment of the present invention, the semiconductor device structure in the Figure 1 Cross-sectional view taken along line A-A in

[0030] Figure 10b In the embodiment of the present invention, the semiconductor device structure in the Figure 1 Cross-sectional view taken along line B-B in Detailed implementation manners

[0031] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0032] In the description of the embodiments of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation on the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and should not be construed as indicating or implying relative importance.

[0033] In the description of the embodiments of the present invention, it should be noted that unless otherwise clearly specified and defined, the terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0034] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0035] In an embodiment of the present invention, the semiconductor device is a MOSFET power device; In the first embodiment, taking the N-type MOSFET power device as an example, the first conduction type is N-type and the second conduction type is P-type; The first embodiment of the present invention provides a semiconductor device terminal protection structure; the semiconductor device includes an active region C1, a voltage-dividing protection region C2, and a cut-off protection region C3; the active region C1 is located in the central region of the device layout, the voltage-dividing protection region C2 is disposed around the active region C1, and the cut-off protection region C3 is disposed around the voltage-dividing protection region C2; the semiconductor device includes a first-conduction-type substrate 1, and a first-conduction-type epitaxial layer 2 is provided on the first-conduction-type substrate 1; the surface of the first-conduction-type epitaxial layer 2 facing away from the first-conduction-type substrate 1 is the first main surface, and the surface of the first-conduction-type substrate 1 facing away from the first-conduction-type epitaxial layer 2 is the second main surface; a drain metal is provided on the second main surface. In the active region C1, a unit cell trench 3 is provided in the first conductivity type epitaxial layer 2; the strip-shaped unit cell trenches 3 are arranged in parallel at intervals; a second conductivity type well region 8 and a first conductivity type implantation layer 11 are provided on the top of the first conductivity type epitaxial layer 2 between adjacent unit cell trenches 3 from bottom to top; the unit cell trench 3 extends from the first main surface under the second conductivity type well region 8; a gate oxide layer 6 is provided on the inner wall of the unit cell trench 3; a gate polysilicon 701 is provided in the unit cell trench 3, and the gate polysilicon 701 is insulated from the first conductivity type implantation layer 11, the second conductivity type well region 8 and the first conductivity type epitaxial layer 2 through the gate oxide layer 6; a second type of insulating dielectric layer 12 is provided above the first main surface, and a source metal 14 and a gate metal 17 are provided on the second type of insulating dielectric layer 12; the source metal 14 is connected to the first conductivity type implantation layer 11 and the second conductivity type well region 8 between adjacent unit cell trenches 3 through a source contact hole 1301 penetrating through the second type of insulating dielectric layer 12 and the first conductivity type implantation layer 11, and is connected to the second conductivity type well region 8 between the outermost unit cell trench 3 and the voltage division protection region C2 through a source contact hole 1301 penetrating through the second type of insulating dielectric layer 12; the gate metal 17 is connected to the gate polysilicon 701 in the unit cell trench 3 through a gate contact hole penetrating through the second type of insulating dielectric layer 12; The semiconductor device terminal protection structure includes: In the voltage division protection region C2, a voltage division trench 4 is provided in the first conductivity type epitaxial layer 2, and the columnar voltage division trenches 4 are arranged at intervals to form a discontinuous annular trench structure, and two or more discontinuous annular trench structures are arranged at intervals around the active region C1; a second conductivity type well region 8 is provided on the top of the first conductivity type epitaxial layer 2; the voltage division trench 4 extends from the first main surface under the second conductivity type well region 8; a gate oxide layer 6 is provided on the inner wall of the voltage division trench 4; a field plate polysilicon 702 is provided in the voltage division trench 4; the field plate polysilicon 702 is insulated from the second conductivity type well region 8 and the first conductivity type epitaxial layer 2 through the gate oxide layer 6; Above the first main surface, there is a strip-shaped integral structure of a series diode structure 1002 and an extraction electrode 1003; below the integral structure of the series diode structure 1002 and the extraction electrode 1003, there is a first type of insulating dielectric layer 9; the integral structure of the series diode structure 1002 and the extraction electrode 1003 straddle above all two or more discontinuous annular trench structures; the series diode structure 1002 includes two or more diodes, the second conductive type electrode at the head end of the first diode faces the active region C1, and the first conductive type electrodes of each diode are respectively located above each discontinuous annular trench structure; the extraction electrode 1003 is a second conductive type electrode and is connected to the first conductive type electrode at the end of the last diode, and the extraction electrode 1003 faces the cut-off protection region C3; above the first main surface and the integral structure of the series diode structure 1002 and the extraction electrode 1003, there is a second type of insulating dielectric layer 12; on the second type of insulating dielectric layer 12, there is an annular interconnect metal 15; each annular interconnect metal 15 is correspondingly distributed above each discontinuous annular trench structure, and each annular interconnect metal 15 is connected to the first conductive type electrode of a corresponding diode below it through a second type of interconnect contact hole 1303 penetrating the second type of insulating dielectric layer 12, and is connected to the field plate polysilicon 702 in each voltage dividing trench 4 in a corresponding discontinuous annular trench structure below it through a third type of interconnect contact hole 1304 penetrating the second type of insulating dielectric layer 12; The source metal 14 is also connected to the second conductive type electrode at the head end of the first diode in the integral structure of the series diode structure 1002 and the extraction electrode 1003 through a first type of interconnect contact hole 1302 penetrating the second type of insulating dielectric layer 12; In the cut-off protection region C3, a cut-off ring trench 5 is provided in the first conductive type epitaxial layer 2, the annular cut-off ring trench 5 is continuously arranged, and a closed annular trench structure is formed around the voltage dividing protection region C2; a second conductive type well region 8 is provided at the top of the first conductive type epitaxial layer 2, and from bottom to top, a second conductive type well region 8 and a first conductive type implantation layer 11 are provided on the top of the first conductive type epitaxial layer 2 on the side of the cut-off ring trench 5 away from the active region; the cut-off ring trench 5 extends from the first main surface under the second conductive type well region 8; a gate oxide layer 6 is provided on the inner wall of the cut-off ring trench 5; a cut-off ring polysilicon 703 is provided in the cut-off ring trench 6; above the first main surface, there is a second type of insulating dielectric layer 12, and above the second type of insulating dielectric layer 12, there is a cut-off ring metal 16, and the cut-off ring metal 16 is connected to the cut-off ring polysilicon 703 in the cut-off ring trench 6 through a cut-off ring contact hole 1306 penetrating the second type of insulating dielectric layer 12, and is connected to the first conductive type implantation layer 11 and the second conductive type well region 8 on the side of the cut-off ring trench 5 away from the active region through a cut-off ring contact hole 1306 penetrating the second type of insulating dielectric layer 12 and the first conductive type implantation layer 11; The cutoff ring metal 16 is also connected to the lead electrode 1003 in the integrally constructed series diode structure 1002 and the lead electrode 1003 through the fourth type of interconnect contact hole 1305 penetrating the second type of insulating dielectric layer 12; Preferably, in the integrally constructed series diode structure 1002 and the lead electrode 1003, the reverse breakdown voltages of the diodes are the same.

[0036] When the device withstands reverse voltage, the equipotential lines are distributed around each independent columnar voltage-dividing groove 4 in the discontinuous annular groove structure. Therefore, its electric field distribution is a three-dimensional distribution. Compared with the electric field distribution on both sides inside and outside the voltage-dividing groove in the prior art, it becomes a distribution around the groove. Under the condition of withstanding the same breakdown voltage, its potential density decreases and the electric field strength also decreases.

[0037] When the device withstands reverse voltage, the voltage on the cutoff ring metal is almost the same as the drain voltage; the voltage between the drain and the source is applied to the integrally constructed series diode structure 1002 and the lead electrode 1003; the voltages borne by the discontinuous annular groove structures can be configured to be the same (when the reverse breakdown voltages of the diodes are the same), that is, equal to the reverse breakdown voltage of one diode, avoiding the problems of uneven electric field distribution, premature breakdown and reduced reliability caused by the relatively high voltages borne by several voltage-dividing ring grooves on the inner side in the trench-type breakdown voltage structure in the prior art. The present application can actively distribute the terminal potential distribution and the electric field distribution, and the electric field distribution is uniform. In some embodiments, in the integrally constructed series diode structure 1002 and the lead electrode 1003, the reverse breakdown voltages of the diodes can gradually increase from the inside to the outside.

[0038] Specifically, in the integrally constructed series diode structure 1002 and the lead electrode 1003, the reverse breakdown voltages of the diodes are 10V to 20V, such as 10V, 12V, 14V, 16V, 18V, 20V.

[0039] Preferably, a plurality of the integrally constructed series diode structures 1002 and the lead electrode 1003 are provided.

[0040] Preferably, the voltage-dividing groove 4 is cylindrical; the electric field distribution around the voltage-dividing groove 4 is more uniform.

[0041] Embodiment 2, taking an N-type MOSFET power device as an example, the first conductivity type is N-type and the second conductivity type is P-type; Embodiment 2 of the present invention proposes a manufacturing method for a semiconductor device terminal protection structure, including the following steps: Step S1, as shown in FIGS. 2A and 2B, provide a first-conductivity-type substrate 1, and grow a first-conductivity-type epitaxial layer 2 on the first-conductivity-type substrate 1; the surface of the first-conductivity-type epitaxial layer 2 facing away from the first-conductivity-type substrate 1 is the first main surface, and the surface of the first-conductivity-type substrate 1 facing away from the first-conductivity-type epitaxial layer 2 is the second main surface; Etch to form unit cell trenches 3, voltage-dividing trenches 4 and cutoff ring trenches 5 in the first-conductivity-type epitaxial layer 2; the unit cell trenches 3 are located in the active region C1 of the device, and in the active region C1, the strip-shaped unit cell trenches 3 are arranged in parallel at intervals; the voltage-dividing trenches 4 are located in the voltage-dividing protection region C2 of the device, and in the voltage-dividing protection region C2, the columnar voltage-dividing trenches 4 are arranged at intervals to form a discontinuous annular trench structure, and two or more discontinuous annular trench structures are arranged at intervals around the active region C1; the cutoff ring trenches 5 are located in the cutoff protection region C3 of the device, and in the cutoff protection region C3, the annular cutoff ring trenches 5 are continuously arranged to form a closed annular trench structure around the voltage-dividing protection region C2; In Figure 1 In the example shown, there are three discontinuous annular trench structures formed by arranging the columnar voltage-dividing trenches 4 at intervals, and there is one closed annular trench structure formed by continuously arranging the annular cutoff ring trenches 5; more discontinuous annular trench structures can be set according to the breakdown voltage requirement of the device; in one discontinuous annular trench structure, the individual voltage-dividing trenches 4 are independent and arranged at intervals to enclose a ring; When etching to form the unit cell trenches 3, voltage-dividing trenches 4 and cutoff ring trenches 5, first deposit a hard mask layer on the first main surface, apply photoresist on the hard mask layer, form a photoresist trench pattern by photolithography through a photomask, then etch the hard mask layer to form a hard mask for etching trenches, and then etch the first main surface to form the unit cell trenches 3, voltage-dividing trenches 4 and cutoff ring trenches 5; remove the hard mask layer; Step S2, as shown in FIGS. 3A and 3B, grow or deposit a gate oxide layer 6 on the first main surface, in the unit cell trenches 3, voltage-dividing trenches 4 and cutoff ring trenches 5; Step S3, as shown in FIGS. 4A and 4B, deposit and etch conductive polysilicon 7 on the first main surface to form gate polysilicon 701 in the unit cell trenches 3, field plate polysilicon 702 in the voltage-dividing trenches 4, and cutoff ring polysilicon 703 in the cutoff ring trenches 5; Step S4, as shown in FIGS. 5A and 5B, implant second-conductivity-type impurities on the first main surface and push the well to form a second-conductivity-type well region 8 on the top of the first-conductivity-type epitaxial layer 2; Step S5, as shown in FIGS. 6A and 6B, deposit a first type of insulating dielectric layer 9 on the first main surface, and then deposit an undoped polysilicon or single-crystalline silicon layer 10 on the first type of insulating dielectric layer 9; Step S6, as shown in FIGS. 7A and 7B, implant impurities of the first conduction type into the polysilicon or single-crystal silicon layer 10, and then selectively etch the polysilicon or single-crystal silicon layer 10 and the first type of insulating dielectric layer 9, leaving a strip-shaped semiconductor structure 1001 and the first type of insulating dielectric layer 9 below the strip-shaped semiconductor structure 1001; the strip-shaped semiconductor structure 1001 straddles over all of the two or more discontinuous annular trench structures; Step S7, as shown in FIGS. 8A and 8B, selectively implant impurities of the second conduction type, such that the strip-shaped semiconductor structure 1001 forms an integrated series diode structure 1002 and a lead-out electrode 1003; the series diode structure 1002 includes two or more diodes, the second-conduction-type electrode at the head end of the first diode faces the active region C1, and the first-conduction-type electrodes of each diode are respectively located above each discontinuous annular trench structure; the lead-out electrode 1003 is a second-conduction-type electrode and is connected to the first-conduction-type electrode at the end of the last diode, and the lead-out electrode 1003 faces the cut-off protection region C3; In this embodiment, the series diode structure 1002 is three diodes connected in series, that is Figure 1 diodes P1N1, P2N2, and P3N3 are connected in series, the P electrode of the diode P1N1 faces the active region C1, and the N electrodes ( Figure 1 N1, N2, and N3 in Figure 1 this n+1 ) of each diode are respectively located above each discontinuous annular trench structure; the lead-out electrode 1003 is a P electrode ( P in ) and is connected to the N electrode of the diode P3N3; the lead-out electrode 1003 faces the cut-off protection region C3; Step S8, as shown in FIGS. 9A and 9B, selectively implant impurities of the first conduction type and anneal, in the active region C1, form a first-conduction-type implantation layer 11 on the top of the first-conduction-type epitaxial layer 2 between adjacent unit cell trenches 3; in the cut-off protection region C3, form a first-conduction-type implantation layer 11 on the top of the first-conduction-type epitaxial layer 2 on the side of the cut-off ring trench 5 away from the active region; Step S9, as shown in FIGS. 10A and 10B, deposit a second type of insulating dielectric layer 12 on the first main surface; then selectively etch the hole structure to form a source contact hole 1301, a first type of interconnection contact hole 1302, a second type of interconnection contact hole 1303, a third type of interconnection contact hole 1304, a fourth type of interconnection contact hole 1305, a cut-off ring contact hole 1306, and a gate contact hole; The gate contact hole is not shown in the figure; Step S10, as shown in FIGS. 10A and 10B, deposit a metal layer on the second type of insulating dielectric layer 12 and selectively etch to form a source metal 14, an annular interconnection metal 15, a cut-off ring metal 16, and a gate metal 17; The source metal 14 is connected to the first-conductivity-type implanted layer 11 and the second-conductivity-type well region 8 between adjacent unit cell trenches 3 through a source contact hole 1301 that penetrates the second-type insulating dielectric layer 12 and the first-conductivity-type implanted layer 11, and is connected to the second-conductivity-type well region 8 between the outermost unit cell trench 3 and the voltage-dividing protection region C2 through a source contact hole 1301 that penetrates the second-type insulating dielectric layer 12; The source metal 14 is also connected to the second-conductivity-type electrode at the first diode anode of the integrally-formed series diode structure 1002 and the lead-out electrode 1003 through a first-type interconnection contact hole 1302 that penetrates the second-type insulating dielectric layer 12; The gate metal 17 is connected to the gate polysilicon 701 in the unit cell trench 3 through a gate contact hole that penetrates the second-type insulating dielectric layer 12; Each annular interconnection metal 15 is correspondingly distributed above each discontinuous annular trench structure. Each annular interconnection metal 15 is connected to the first-conductivity-type electrode of a corresponding diode below it through a second-type interconnection contact hole 1303 that penetrates the second-type insulating dielectric layer 12, and is connected to the field plate polysilicon 702 in each voltage-dividing trench 4 in a corresponding discontinuous annular trench structure below it through a third-type interconnection contact hole 1304 that penetrates the second-type insulating dielectric layer 12; The cutoff ring metal 16 is connected to the cutoff ring polysilicon 703 in the cutoff ring trench 5 through a cutoff ring contact hole 1306 that penetrates the second-type insulating dielectric layer 12, and is connected to the first-conductivity-type implanted layer 11 and the second-conductivity-type well region 8 on the side of the cutoff ring trench 5 away from the active region through a cutoff ring contact hole 1306 that penetrates the second-type insulating dielectric layer 12 and the first-conductivity-type implanted layer 11; The cutoff ring metal 16 is also connected to the lead-out electrode 1003 in the integrally-formed series diode structure 1002 and the lead-out electrode 1003 through a fourth-type interconnection contact hole 1305 that penetrates the second-type insulating dielectric layer 12; The connection method between the gate metal 17 and the gate polysilicon 701 is relatively mature. For example, a gate lead-out trench is provided around the unit cell trench 3, and gate polysilicon is also provided in the gate lead-out trench. The gate polysilicon in the gate lead-out trench is connected to the gate polysilicon in the unit cell trench, and the gate metal 17 is connected to the gate polysilicon in the gate lead-out trench through a gate contact hole that penetrates the second-type insulating dielectric layer 12, thereby connecting the gate polysilicon in the unit cell trench 3; Step S11, depositing a drain metal on the second main surface.

[0042] The drain metal is not drawn in the figure, hereby noted.

[0043] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention rather than to limit them. Although the present invention has been described in detail with reference to the embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and all of them should be covered by the scope of the claims of the present invention.

Claims

1. A semiconductor device terminal protection structure; the semiconductor device includes an active region (C1), a voltage-dividing protection region (C2), and a cut-off protection region (C3); the active region (C1) is located in the central region of the device layout, the voltage-dividing protection region (C2) is arranged around the active region (C1), and the cut-off protection region (C3) is arranged around the voltage-dividing protection region (C2); the semiconductor device includes a first-conductivity-type substrate (1), and a first-conductivity-type epitaxial layer (2) is provided on the first-conductivity-type substrate (1); the surface of the first-conductivity-type epitaxial layer (2) facing away from the first-conductivity-type substrate (1) is the first main surface, and the surface of the first-conductivity-type substrate (1) facing away from the first-conductivity-type epitaxial layer (2) is the second main surface; a drain metal is provided on the second main surface. In the active region (C1), a unit cell trench (3) is provided in the first-conductivity-type epitaxial layer (2); each strip-shaped unit cell trench (3) is arranged at intervals in parallel; a second-conductivity-type well region (8) and a first-conductivity-type implantation layer (11) are provided on the top of the first-conductivity-type epitaxial layer (2) between adjacent unit cell trenches (3) from bottom to top; the unit cell trench (3) extends from the first main surface under the second-conductivity-type well region (8); a gate oxide layer (6) is provided on the inner wall of the unit cell trench (3); a gate polysilicon (701) is provided in the unit cell trench (3), and the gate polysilicon (701) is insulated from the first-conductivity-type implantation layer (11), the second-conductivity-type well region (8), and the first-conductivity-type epitaxial layer (2) through the gate oxide layer (6); a second-type insulating dielectric layer (12) is provided above the first main surface, and a source metal (14) and a gate metal (17) are provided on the second-type insulating dielectric layer (12); the source metal (14) is connected to the first-conductivity-type implantation layer (11) and the second-conductivity-type well region (8) between adjacent unit cell trenches (3) through a source contact hole (1301) penetrating through the second-type insulating dielectric layer (12) and the first-conductivity-type implantation layer (11), and is connected to the second-conductivity-type well region (8) between the outermost unit cell trench (3) and the voltage-dividing protection region (C2) through a source contact hole (1301) penetrating through the second-type insulating dielectric layer (12); the gate metal (17) is connected to the gate polysilicon (701) in the unit cell trench (3) through a gate contact hole penetrating through the second-type insulating dielectric layer (12); characterized in that The semiconductor device terminal protection structure includes: In the voltage-dividing protection region (C2), voltage-dividing trenches (4) are provided in the first-conductivity-type epitaxial layer (2). Each columnar voltage-dividing trench (4) is arranged at intervals to form a discontinuous annular trench structure, and two or more discontinuous annular trench structures are arranged at intervals around the active region (C1); a second-conductivity-type well region (8) is provided on the top of the first-conductivity-type epitaxial layer (2); the voltage-dividing trenches (4) extend from the first main surface under the second-conductivity-type well region (8); a gate oxide layer (6) is provided on the inner wall of the voltage-dividing trenches (4); field plate polysilicon (702) is provided in the voltage-dividing trenches (4); the field plate polysilicon (702) is insulated from the second-conductivity-type well region (8) and the first-conductivity-type epitaxial layer (2) through the gate oxide layer (6); Above the first main surface, a strip-shaped integral series diode structure (1002) and an extraction electrode (1003) are provided; a first type of insulating dielectric layer (9) is provided below the integral series diode structure (1002) and the extraction electrode (1003); the integral series diode structure (1002) and the extraction electrode (1003) straddle above all two or more discontinuous annular trench structures; the series diode structure (1002) includes two or more diodes. The second-conductivity-type electrode at the head of the first diode faces the active region (C1), and the first-conductivity-type electrodes of each diode are respectively located above each discontinuous annular trench structure; the extraction electrode (1003) is a second-conductivity-type electrode and is connected to the first-conductivity-type electrode at the end of the last diode, and the extraction electrode (1003) faces the cut-off protection region (C3); a second type of insulating dielectric layer (12) is provided above the first main surface and the integral series diode structure (1002) and the extraction electrode (1003); an annular interconnect metal (15) is provided on the second type of insulating dielectric layer (12); each annular interconnect metal (15) is correspondingly distributed above each discontinuous annular trench structure. Each annular interconnect metal (15) is connected to the first-conductivity-type electrode of a corresponding diode below through a second type of interconnect contact hole (1303) penetrating the second type of insulating dielectric layer (12), and is connected to the field plate polysilicon (702) in each voltage-dividing trench (4) in a corresponding discontinuous annular trench structure below through a third type of interconnect contact hole (1304) penetrating the second type of insulating dielectric layer (12); The source metal (14) is also connected to the second-conductivity-type electrode at the head of the first diode in the integral series diode structure (1002) and the extraction electrode (1003) through a first type of interconnect contact hole (1302) penetrating the second type of insulating dielectric layer (12); In the cut-off protection region (C3), a cut-off ring trench (5) is provided in the first conductivity type epitaxial layer (2). The annular cut-off ring trench (5) is continuously arranged to form a closed annular trench structure surrounding the voltage-dividing protection region (C2). On the top of the first conductivity type epitaxial layer (2), a second conductivity type well region (8) is provided. On the top of the first conductivity type epitaxial layer (2) on the side of the cut-off ring trench (5) away from the active region, a second conductivity type well region (8) and a first conductivity type implantation layer (11) are provided from bottom to top. The cut-off ring trench (5) extends from the first main surface under the second conductivity type well region (8). A gate oxide layer (6) is provided on the inner wall of the cut-off ring trench (5). A cut-off ring polysilicon (703) is provided in the cut-off ring trench (5). Above the first main surface, a second type of insulating dielectric layer (12) is provided. Above the second type of insulating dielectric layer (12), a cut-off ring metal (16) is provided. The cut-off ring metal (16) is connected to the cut-off ring polysilicon (703) in the cut-off ring trench (5) through a cut-off ring contact hole (1306) penetrating the second type of insulating dielectric layer (12), and is connected to the first conductivity type implantation layer (11) and the second conductivity type well region (8) on the side of the cut-off ring trench (5) away from the active region through a cut-off ring contact hole (1306) penetrating the second type of insulating dielectric layer (12) and the first conductivity type implantation layer (11). The cut-off ring metal (16) is further connected to the lead-out electrode (1003) in the integrally constructed series diode structure (1002) and the lead-out electrode (1003) through a fourth type of interconnection contact hole (1305) penetrating the second type of insulating dielectric layer (12).

2. The semiconductor device terminal protection structure according to claim 1, wherein in the integrally constructed series diode structure (1002) and the lead-out electrode (1003), the reverse breakdown voltages of the diodes are the same.

3. The semiconductor device terminal protection structure according to claim 2, wherein in the integrally constructed series diode structure (1002) and the lead-out electrode (1003), the reverse breakdown voltage of each diode is 10V to 20V.

4. The semiconductor device terminal protection structure according to claim 1 or 2, wherein a plurality of the integrally constructed series diode structures (1002) and lead-out electrodes (1003) are provided.

5. The semiconductor device terminal protection structure according to claim 1 or 2, wherein the voltage-dividing trench (4) is cylindrical.

6. A manufacturing method of a semiconductor device terminal protection structure for manufacturing the semiconductor device terminal protection structure according to any one of claims 1 to 5, characterized in that, Comprising the following steps: Step S1, providing a first conductivity type substrate (1), and growing a first conductivity type epitaxial layer (2) on the first conductivity type substrate (1); the surface of the first conductivity type epitaxial layer (2) facing away from the first conductivity type substrate (1) is the first main surface, and the surface of the first conductivity type substrate (1) facing away from the first conductivity type epitaxial layer (2) is the second main surface; Etch single cell trenches (3), voltage dividing trenches (4) and cutoff ring trenches (5) in the epitaxial layer (2) of the first conductivity type; the single cell trenches (3) are located in the active region (C1) of the device, and in the active region (C1), the strip-shaped single cell trenches (3) are arranged in parallel at intervals; the voltage dividing trenches (4) are located in the voltage dividing protection region (C2) of the device, and in the voltage dividing protection region (C2), the columnar voltage dividing trenches (4) are arranged at intervals to form a discontinuous annular trench structure, and two or more discontinuous annular trench structures are arranged at intervals around the active region (C1); the cutoff ring trenches (5) are located in the cutoff protection region (C3) of the device, and in the cutoff protection region (C3), the annular cutoff ring trenches (5) are continuously arranged to form a closed annular trench structure around the voltage dividing protection region (C2); Step S2, grow or deposit a gate oxide layer (6) on the first main surface, in the single cell trenches (3), the voltage dividing trenches (4) and the cutoff ring trenches (5); Step S3, deposit and etch conductive polysilicon 7 on the first main surface to form gate polysilicon (701) in the single cell trenches (3), field plate polysilicon (702) in the voltage dividing trenches (4), and cutoff ring polysilicon (703) in the cutoff ring trenches (5); Step S4, implant impurities of the second conductivity type on the first main surface and push the well to form a well region (8) of the second conductivity type on the top of the epitaxial layer (2) of the first conductivity type; Step S5, deposit a first type of insulating dielectric layer (9) on the first main surface, and then deposit an undoped polysilicon or single crystal silicon layer (10) on the first type of insulating dielectric layer (9); Step S6, implant impurities of the first conductivity type on the polysilicon or single crystal silicon layer (10), and then selectively etch the polysilicon or single crystal silicon layer (10) and the first type of insulating dielectric layer (9) to leave a strip-shaped semiconductor structure (1001) and the first type of insulating dielectric layer (9) below the strip-shaped semiconductor structure (1001); the strip-shaped semiconductor structure (1001) straddles over all two or more discontinuous annular trench structures; Step S7, selectively implant impurities of the second conductivity type so that the strip-shaped semiconductor structure (1001) forms an integral series diode structure (1002) and a lead-out electrode (1003); the series diode structure (1002) includes two or more diodes, the second conductivity type electrode at the head of the first diode faces the active region (C1), and the first conductivity type electrodes of each diode are respectively located above each discontinuous annular trench structure; the lead-out electrode (1003) is a second conductivity type electrode and is connected to the first conductivity type electrode at the end of the last diode, and the lead-out electrode (1003) faces the cutoff protection region (C3); Step S8, selectively implant impurities of the first conductivity type and anneal to form a first conductivity type implantation layer (11) on the top of the epitaxial layer (2) of the first conductivity type between adjacent single cell trenches (3) in the active region (C1); in the cutoff protection region (C3), form a first conductivity type implantation layer (11) on the top of the epitaxial layer (2) of the first conductivity type on the side of the cutoff ring trench (5) away from the active region; Step S9, deposit a second type of insulating dielectric layer (12) on the first main surface; Then, selectively etch the hole structure to form a source contact hole (1301), a first type of interconnect contact hole (1302), a second type of interconnect contact hole (1303), a third type of interconnect contact hole (1304), a fourth type of interconnect contact hole (1305), a cutoff ring contact hole (1306), and a gate contact hole; Step S10, deposit a metal layer on the second type of insulating dielectric layer (12) and selectively etch it to form a source metal (14), an annular interconnect metal (15), a cutoff ring metal (16), and a gate metal (17); The source metal (14) is connected to the first conductive type implanted layer (11) and the second conductive type well region (8) between adjacent unit cell trenches (3) through the source contact hole (1301) that penetrates the second type of insulating dielectric layer (12) and the first conductive type implanted layer (11), and is connected to the second conductive type well region (8) between the outermost unit cell trench (3) and the voltage dividing protection region (C2) through the source contact hole (1301) that penetrates the second type of insulating dielectric layer (12); The source metal (14) is also connected to the second conductive type electrode at the first end of the first diode in the integrally structured series diode structure (1002) and the lead-out electrode (1003) through the first type of interconnect contact hole (1302) that penetrates the second type of insulating dielectric layer (12); The gate metal (17) is connected to the gate polysilicon (701) in the unit cell trench (3) through the gate contact hole that penetrates the second type of insulating dielectric layer (12); Each annular interconnect metal (15) is correspondingly distributed above each discontinuous annular trench structure. Each annular interconnect metal (15) is connected to the first conductive type electrode of a corresponding diode below it through the second type of interconnect contact hole (1303) that penetrates the second type of insulating dielectric layer (12), and is connected to the field plate polysilicon (702) in each voltage dividing trench (4) in a corresponding discontinuous annular trench structure below it through the third type of interconnect contact hole (1304) that penetrates the second type of insulating dielectric layer (12); The cutoff ring metal (16) is connected to the cutoff ring polysilicon (703) in the cutoff ring trench (5) through the cutoff ring contact hole (1306) that penetrates the second type of insulating dielectric layer (12), and is connected to the first conductive type implanted layer (11) and the second conductive type well region (8) on the side of the cutoff ring trench (5) away from the active region through the cutoff ring contact hole (1306) that penetrates the second type of insulating dielectric layer (12) and the first conductive type implanted layer (11); The cutoff ring metal (16) is also connected to the lead-out electrode (1003) in the integrally structured series diode structure (1002) and the lead-out electrode (1003) through the fourth type of interconnect contact hole (1305) that penetrates the second type of insulating dielectric layer (12); Step S11, deposit a drain metal on the second main surface.

7. The manufacturing method of the semiconductor device terminal protection structure according to claim 6, wherein In the integrally-constructed series diode structure (1002) and the lead-out electrode (1003), the reverse breakdown voltages of the respective diodes are the same.

8. The manufacturing method of the semiconductor device terminal protection structure according to claim 7, characterized in that In the integrally-constructed series diode structure (1002) and the lead-out electrode (1003), the reverse breakdown voltage of each diode is 10V to 20V.

9. The manufacturing method of the semiconductor device terminal protection structure according to claim 6 or 7, characterized in that A plurality of the integrally-constructed series diode structures (1002) and lead-out electrodes (1003) are provided.

10. The manufacturing method of the semiconductor device terminal protection structure according to claim 6 or 7, characterized in that The voltage-dividing trench (4) is cylindrical.

Images