Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention suppresses variations in depth and concentration of bonding between a base layer and a carrier accumulation layer of a semiconductor device. This semiconductor device is provided with: a source layer (13) of a first conductivity type, which is located in a surface layer section of a semiconductor layer and is defined by a concentration distribution of a first impurity; a second conductivity-type base layer (15) located below the source layer (13) and defined by the concentration distribution of a second impurity; a carrier storage layer (2) of the first conductivity type, which is located below the base layer (15) and is defined by the concentration distribution of the third impurity; a drift layer (1) of a first conductivity type located below the carrier storage layer (2); and a second conductivity-type CSC layer (50) defined by the concentration distribution of the fourth impurity. The fourth impurity-containing region of the CSC layer (50) includes a region in which the second impurity-containing region of the base layer (15) overlaps the third impurity-containing region of the carrier storage layer (2).

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] For example, Patent Document 1 below discloses a technique of designing a p-type base layer and an n-type carrier accumulation layer of an IGBT to have peak impurity concentrations in order to reduce the deviation of the threshold voltage (Vth) of the IGBT.

[0003] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2008-205015

[0004] In the IGBT of Patent Document 1, since the peak impurity concentrations of the p-type base layer and the n-type carrier accumulation layer are stable, the deviation of the stable threshold voltage becomes small. However, deviations in depth and concentration occur at the junction between the n + type source layer and the p-type base layer, and at the junction between the p-type base layer and the n-type carrier accumulation layer. In this case, in the transition state of switching, current cannot be cut off at a portion where the impurity concentration is low, resulting in a reduction in breakdown voltage tolerance, or current concentration due to deviation of the local carrier distribution and a reduction in breakdown voltage tolerance. As a result, the reverse bias safe operating area (RBSOA) of the semiconductor device is reduced. Summary of the Invention

[0005] The present invention has been made to solve the above problems, and an object thereof is to suppress deviations in depth and concentration at the junction between the base layer and the carrier accumulation layer of a semiconductor device.

[0006] The semiconductor device of the present invention includes: a source layer of a first conductivity type, which is located in the surface layer portion of the semiconductor layer and is defined by the concentration distribution of a first impurity; a base layer of a second conductivity type, which is located below the source layer and is defined by the concentration distribution of a second impurity; the carrier accumulation layer of the first conductivity type, which is located below the base layer and is defined by the concentration distribution of a third impurity; the drift layer of the first conductivity type, which is located below the carrier accumulation layer; and the CSC layer of the second conductivity type, which is defined by the concentration distribution of a fourth impurity and is located at a position where the region containing the fourth impurity includes a region where the region containing the second impurity of the base layer overlaps with the region containing the third impurity of the carrier accumulation layer.

[0007] According to the present invention, by providing a CSC layer in the semiconductor device, it is possible to suppress deviations in depth and concentration at the junction between the base layer and the carrier accumulation layer of the semiconductor device. Brief Description of the Drawings

[0008] Figure 1 It is a diagram showing the structure of the semiconductor device of Embodiment 1.

[0009] Figure 2 It is the n- + type source layer, p-type base layer, n-type carrier accumulation layer, n- 一 type drift layer, and a graph of the impurity concentration distribution of the p-type CSC layer.

[0010] Figure 3 It is a flowchart for explaining the manufacturing method of the semiconductor device of Embodiment 1.

[0011] Figure 4 It is the n- of the semiconductor device of Embodiment 2 + type source layer, p-type base layer, n-type carrier accumulation layer, n- 一 type drift layer, and a graph of the impurity concentration distribution of the p-type CSC layer.

[0012] Figure 5 It is the n- of the semiconductor device of Embodiment 3 + type source layer, p-type base layer, n-type carrier accumulation layer, n- 一 type drift layer, and a graph of the impurity concentration distribution of the p-type CSC layer.

[0013] Figure 6 It is the n- of the semiconductor device of Embodiment 4 + type source layer, p-type base layer, n-type carrier accumulation layer, n- 一 type drift layer, and a graph of the impurity concentration distribution of the p-type CSC layer.

[0014] Figure 7 It is the n- of the semiconductor device of Embodiment 5 + type source layer, p-type base layer, n-type carrier accumulation layer, n- 一 type drift layer, and a graph of the impurity concentration distribution of the p-type CSC layer.

[0015] Figure 8 It is the n- of the semiconductor device of Embodiment 6 + type source layer, p-type base layer, n-type carrier accumulation layer, n- 一 type drift layer, and a graph of the impurity concentration distribution of the p-type CSC layer.

[0016] Figure 9 It is a diagram showing the structure of the semiconductor device of Embodiment 7.

[0017] Figure 10 It is a diagram showing the structure of the semiconductor device of Embodiment 8.

[0018] Figure 11 It is a diagram showing the structure of the semiconductor device of Embodiment 9.

[0019] Explanation of reference numerals: 1…n 一 n-type drift layer; 2…n-type carrier accumulation layer; 3…n-type buffer layer; 4…interlayer insulating film; 5…barrier metal; 6…emitter electrode; 7…collector; 10…IGBT region; 11…active trench gate; 11a…gate trench electrode; 11b…gate trench insulating film; 12…dummy trench gate; 12a…dummy trench electrode; 12b…dummy trench insulating film; 13…n + -type source layer; 14…p + -type contact layer; 15…p-type base layer; 16…p-type collector layer; 16a…p-type terminal collector layer; 20…diode region; 21…diode trench gate; 21a…diode trench electrode; 21b…diode trench insulating film; 24…p + -type contact layer; 25…p-type anode layer; 26…n + -type cathode layer; 50…p-type CSC layer; 60…Schottky region; 61…Schottky adjustment layer. Detailed implementation mode

[0020] In the following description, n and p represent the conductivity types of semiconductors. In the present invention, the first conductivity type is set as the n-type and the second conductivity type is set as the p-type for description. However, conversely, the first conductivity type can also be set as the p-type and the second conductivity type can be set as the n-type. In addition, n 一 means that the impurity concentration is lower than the concentration of n, and n + means that the impurity concentration is higher than the concentration of n. Similarly, p 一 means that the impurity concentration is lower than the concentration of p, and p + means that the impurity concentration is higher than the concentration of p.

[0021] In addition, the height of the impurity concentration in each region is defined by the peak concentration. That is, a region with a high (or low) impurity concentration means a region with a high (or low) peak concentration of impurities.

[0022] <Embodiment 1>

[0023] Hereinafter, the structure of the semiconductor device according to Embodiment 1 will be described. The semiconductor element included in the semiconductor device is assumed to be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), an RC-IGBT (Reverse Conducting IGBT), an SBD (Schottky Barrier Diode), a PN diode, etc. Here, the semiconductor element is assumed to be an RC-IGBT for explanation.

[0024] The material of the semiconductor element can be silicon (Si) or a wide bandgap semiconductor such as silicon carbide (SiC). A semiconductor device formed using a wide bandgap semiconductor has excellent operation at high voltage, high current, and high temperature compared to a semiconductor device using silicon. As the wide bandgap semiconductor, in addition to silicon carbide, there are gallium nitride (GaN)-based materials, diamond, etc.

[0025] Figure 1 It is a diagram showing the structure of the semiconductor device according to Embodiment 1, and is a cross-sectional view of the IGBT region 10 that functions as an IGBT in the RC-IGBT. In addition, the diode region that functions as a diode in the RC-IGBT will be described in the embodiments shown later.

[0026] As Figure 1 shown, an active trench gate 11 and a dummy trench gate 12 are provided in the IGBT region 10. The active trench gate 11 is configured such that a gate trench electrode 11a is provided in a trench formed in a semiconductor substrate (semiconductor layer) with a gate trench insulating film 11b interposed therebetween. The dummy trench gate 12 is configured such that a dummy trench electrode 12a is provided in a trench formed in the semiconductor substrate with a dummy trench insulating film 12b interposed therebetween. The gate trench electrode 11a of the active trench gate 11 is electrically connected to a gate pad (not shown). The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to the emitter electrode 6.

[0027] On both sides in the width direction of the active trench gate 11, an n + -type source layer 13 is provided in contact with the gate trench insulating film 11b. The n + -type source layer 13 is, for example, a semiconductor layer having arsenic (As) or phosphorus (P) etc. as an n-type impurity. That is, the n + -type source layer 13 is located in the surface layer portion of the semiconductor layer and is defined by the concentration distribution of the n-type first impurity. The n +The concentration of the n-type impurity in the source layer 13 is, for example, 1.0E+17 / cm 3 ~1.0E+20 / cm 3 .

[0028] A p + type contact layer 14. In addition, n + The source layer 13 can also be connected to the p + The type contact layers 14 are alternately arranged along the extension direction of the active trench gate 11. + The p-type contact layer 14 is a semiconductor layer containing boron (B) or aluminum (Al) as a p-type impurity. + The concentration of the p-type impurity in the p-type contact layer 14 is, for example, 1.0E+15 / cm 3 ~1.0E+20 / cm 3 .

[0029] exist Figure 1 In the example, three active trench gates 11 in a group and three dummy trench gates 12 in a group are alternately arranged in parallel. However, there is no limit to the number of active trench gates 11 included in one group of active trench gates 11 and the number of dummy trench gates 12 included in one group of dummy trench gates 12. The number of dummy trench gates 12 may be 0. That is, all trenches provided in the IGBT region 10 may be used as active trench gates 11.

[0030] The semiconductor device has a semiconductor substrate. 一 Type drift layer 1. n 一 The n-type drift layer 1 is a semiconductor layer containing arsenic, phosphorus, or the like as an n-type impurity. 一 The concentration of n-type impurities in the drift layer 1 is 1.0E+12 / cm 3 ~1.0E+15 / cm 3 . Semiconductor substrates Figure 1 Shown from n + Type source layer 13 and p + The p-type contact layer 14 is within the range of the p-type collector layer 16. Figure 1 In the + Type source layer 13 and p + The upper end of the p-type contact layer 14 on the paper is called the first main surface of the semiconductor substrate, and the lower end of the p-type collector layer 16 on the paper is called the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front side of the semiconductor device, and the second main surface of the semiconductor substrate is the main surface on the back side of the semiconductor device. The semiconductor device has n between the first main surface and the second main surface opposite to the first main surface in the IGBT region 10 as the unit region. 一Type drift layer 1. Hereinafter, the first main surface side of the semiconductor substrate may sometimes be referred to as the "upper side", and the second main surface side may be referred to as the "lower side".

[0031] On the second main surface side of the n + -type source layer 13 and the p + -type contact layer 14, a p-type base layer 15 is provided. The p-type base layer 15 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity. That is, the p-type base layer 15 is located below the n + -type source layer 13 and is defined by the concentration distribution of the p-type second impurity. The concentration of the p-type impurity in the p-type base layer 15 is 1.0E+12 / cm 3 ~1.0E+19 / cm 3 . The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11.

[0032] On the first main surface side of the p-type base layer 15, an n + -type source layer 13 is provided in contact with the gate trench insulating film 11b of the active trench gate 11, and a p + -type contact layer 14 is provided in the remaining region. The n + -type source layer 13 and the p + -type contact layer 14 constitute the first main surface of the semiconductor substrate. In addition, the p + -type contact layer 14 is a region having a higher concentration of p-type impurity than the p-type base layer 15.

[0033] On the second main surface side of the p-type base layer 15, an n-type carrier accumulation layer 2 having a higher concentration of n-type impurity than the n-type impurity in the n 一 -type drift layer 1 is provided. The n-type carrier accumulation layer 2 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity. That is, the n-type carrier accumulation layer 2 is located below the p-type base layer 15 and is defined by the concentration distribution of the n-type third impurity. The concentration of the n-type impurity in the n-type carrier accumulation layer 2 is, for example, 1.0E+13 / cm 3 ~1.0E+17 / cm 3 . By providing the n-type carrier accumulation layer 2, the conduction loss when current flows through the IGBT region 10 can be reduced.

[0034] The n 一 -type drift layer 1 is located on the second main surface side of the n-type carrier accumulation layer 2. And, on the second main surface side of the n 一 -type drift layer 1, an n-type buffer layer 3 having a higher concentration of n-type impurity than the n-type impurity in the n 一 -type drift layer 1 is provided. The n-type buffer layer 3 is provided to prevent the depletion layer extending from the p-type base layer 15 to the second main surface side from punching through when the semiconductor device is in the off state. The n-type buffer layer 3 can be implanted with, for example, phosphorus (P) or protons (H +) formed, or can be formed by injecting phosphorus (P) and protons (H + ) both. The concentration of the n-type impurity in the n-type buffer layer 3 is, for example, 1.0E+12 / cm 3 ~1.0E+18 / cm 3 .

[0035] In addition, the n-type buffer layer 3 may not be provided, and an n Figure 1 type drift layer 1 may also be provided in the region of the n-type buffer layer 3 shown. The n-type buffer layer 3 and the n 一 type drift layer 1 may also be collectively referred to as the drift layer. 一

[0036] A p-type collector layer 16 is provided on the second main surface side of the n-type buffer layer 3. That is, a p-type collector layer 16 is provided between the n 一 type drift layer 1 and the second main surface. The p-type collector layer 16 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity. The concentration of the p-type impurity in the p-type collector layer 16 is, for example, 1.0E+16 / cm 3 ~1.0E+20 / cm 3 . The p-type collector layer 16 constitutes the second main surface of the semiconductor substrate.

[0037] Figure 1 As shown, the active trench gate 11 and the dummy trench gate 12 penetrate through the p-type base layer 15 and the n-type carrier accumulation layer 2 from the first main surface of the semiconductor substrate and reach the n 一 type drift layer 1. The gate trench electrode 11a of the active trench gate 11 faces the n + type source layer 13, the p-type base layer 15, the n-type carrier accumulation layer 2, and the n 一 type drift layer 1 across the gate trench insulating film 11b. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate trench insulating film 11b.

[0038] An interlayer insulating film 4 is provided on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is formed on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not provided and on the interlayer insulating film 4. The barrier metal 5 can be, for example, a conductor containing titanium (Ti), such as titanium nitride, or TiSi obtained by alloying titanium and silicon (Si). The barrier metal 5 makes an ohmic contact with the n + type source layer 13, the p + type contact layer 14, and the dummy trench electrode 12a, and makes an ohmic contact with the n + type source layer 13, the p +The type contact layer 14 is electrically connected to the dummy trench electrode 12a. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 can be formed of an aluminum alloy such as an aluminum-silicon alloy (Al-Si based alloy), or can be an electrode composed of a multi-layer metal film with a coating film formed by electroless plating or electrolytic plating on the electrode formed of an aluminum alloy. The coating film formed by electroless plating or electrolytic plating can be, for example, a nickel (Ni) coating film.

[0039] When there are areas in minute regions such as between adjacent interlayer insulating films 4 where good embedding cannot be achieved through the emitter electrode 6, tungsten with better embedding properties than the emitter electrode 6 can be disposed in the minute regions, and the emitter electrode 6 can be provided on the tungsten. It is also possible to not provide the barrier metal 5, and instead, the emitter electrode 6 is provided on the n + type source layer 13, p + type contact layer 14, and the dummy trench electrode 12a. Additionally, it is also possible to provide the barrier metal 5 only on n + type semiconductor layers such as the type source layer 13. The barrier metal 5 and the emitter electrode 6 can be collectively referred to as the emitter electrode.

[0040] In Figure 1 FIG. shows a diagram in which the interlayer insulating film 4 is not provided on the dummy trench electrode 12a of the dummy trench gate 12, but the interlayer insulating film 4 can also be formed on the dummy trench electrode 12a of the dummy trench gate 12. When the interlayer insulating film 4 is formed on the dummy trench electrode 12a of the dummy trench gate 12, it is only necessary to electrically connect the emitter electrode 6 and the dummy trench electrode 12a in other cross-sections.

[0041] A collector 7 is provided on the second main surface side of the p-type collector layer 16. The collector 7, like the emitter electrode 6, can also be formed of an aluminum alloy or a combination of an aluminum alloy and a coating film. Additionally, the collector 7 can also have a structure different from that of the emitter electrode 6. The collector 7 makes an ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0042] In addition to the above structures, the semiconductor device of Embodiment 1 includes a p-type CSC (Carrier Storage Control) layer 50 so as to overlap with the n + type source layer 13, the p-type base layer 15, and the n-type carrier accumulation layer 2. The p-type CSC layer 50 is a semiconductor layer having, for example, boron (B) or aluminum (Al) as a p-type impurity. That is, the p-type CSC layer 50 is defined by the concentration distribution of the p-type fourth impurity. In the present embodiment, boron is used as the p-type impurity constituting the p-type base layer 15.

[0043] Figure 2 FIG. shows the n in the semiconductor device of Embodiment 1+ type source layer 13, p-type base layer 15, n-type carrier accumulation layer 2, n 一 type drift layer 1, and impurity concentration distribution of p-type CSC layer 50. Figure 2 Shows along Figure 1 impurity concentration distribution in the depth direction starting from the first main surface of the semiconductor substrate for the portion along the dashed line D1 - D2.

[0044] As Figure 2 shown, it is stipulated that the concentration distribution of the fourth impurity (B) in the p-type CSC layer 50 has a gentle gradient in the depth direction of the semiconductor substrate. In addition, the position (depth) where the p-type CSC layer 50 is formed is set such that the region containing the fourth impurity of the p-type CSC layer 50 includes the region where the region containing the second impurity (B) of the p-type base layer 15 overlaps with the region containing the third impurity (P) of the n-type carrier accumulation layer 2.

[0045] In this way, the p-type CSC layer 50 is formed to overlap with the part where it is joined to the p-type base layer 15 and the n-type carrier accumulation layer 2, thereby reducing the deviation in the depth and concentration of the junction between the p-type base layer 15 and the n-type carrier accumulation layer 2. Thereby, the reduction of the RBSOA of the semiconductor device is suppressed.

[0046] In addition, as Figure 2 shown, the region containing the fourth impurity of the p-type CSC layer 50 may also include the region where the region containing the first impurity (P or As) of the n + type source layer 13 overlaps with the region containing the second impurity of the p-type base layer 15. In this case, the deviation in the depth and concentration of the junction between the n + type source layer 13 and the p-type base layer 15 is also reduced, further suppressing the reduction of the RBSOA of the semiconductor device.

[0047] Here, a method for manufacturing the semiconductor device of Embodiment 1 will be described. The method for manufacturing the semiconductor device of Embodiment 1 may be the same as that of a general RC-IGBT except for the formation processes of the n + type source layer 13, p-type base layer 15, n-type carrier accumulation layer 2, and p-type CSC layer 50. Therefore, with reference to the Figure 3 flowchart, the formation processes of the n + type source layer 13, p-type base layer 15, n-type carrier accumulation layer 2, and p-type CSC layer 50 will be described.

[0048] First, from the n 一 type drift layer 1 formed with 一On the first main surface side of the type drift layer 1, ions of the fourth impurity for the p-type CSC layer 50 are implanted, and the fourth impurity is diffused into the semiconductor substrate by heat treatment to form the p-type CSC layer 50 (step S1). By diffusing the fourth impurity, a p-type CSC layer 50 having a concentration distribution with a gentle gradient in the depth direction of the semiconductor substrate can be formed.

[0049] Next, ions of the first impurity of the n-type for the n + type source layer 13 are implanted into the semiconductor substrate from the first main surface side, so as to form an n + type source layer 13 having a peak of independent impurity concentration in the surface layer portion of the semiconductor substrate (step S2). Then, ions of the second impurity of the p-type for the p-type base layer 15 are implanted into the semiconductor substrate from the first main surface side, so as to form a p-type base layer 15 having a peak of independent impurity concentration below the n + type source layer 13 (step S3). Further, ions of the third impurity are implanted into the semiconductor substrate from the first main surface side, so as to form an n-type carrier accumulation layer 2 of the first conductivity type having a peak of independent impurity concentration below the p-type base layer 15 (step S4).

[0050] In the processes of steps S2 to S4, the n + type source layer 13, the p-type base layer 15, and the n-type carrier accumulation layer 2 are formed such that the junction of the n + type source layer 13 and the p-type base layer 15 and the junction of the p-type base layer 15 and the n-type carrier accumulation layer 2 are included in the p-type CSC layer 50 formed in step S1. In addition, the execution order of steps S2, S3, and S4 is not considered.

[0051] Thereafter, a heat treatment for activating the impurities respectively implanted into the n + type source layer 13, the p-type base layer 15, the n-type carrier accumulation layer 2, and the p-type CSC layer 50 is performed (step S5).

[0052] Through the above processes, the n + type source layer 13, the p-type base layer 15, the n-type carrier accumulation layer 2, and the p-type CSC layer 50 of the semiconductor device of Embodiment 1 can be formed.

[0053] <Embodiment 2>

[0054] The structure of the semiconductor device of Embodiment 2 is basically the same as that of Embodiment 1 ( Figure 1 ), but the impurity concentration distribution of the p-type CSC layer 50 is different from that of Embodiment 1.

[0055] Figure 4 Shows the n in the semiconductor device of Embodiment 2 +The impurity concentration distributions of the p-type source layer 13, the p-type base layer 15, the n-type carrier accumulation layer 2, the n 一 -type drift layer 1, and the p-type CSC layer 50. As Figure 4 shown, in Embodiment 2, in the region where the second-impurity-containing region of the p-type base layer 15 overlaps with the third-impurity-containing region of the n-type carrier accumulation layer 2, the concentration of the fourth impurity in the p-type CSC layer 50 is higher than the concentrations of the second impurity and the third impurity.

[0056] In the semiconductor device according to Embodiment 2, the deviation in the depth of the junction between the p-type base layer 15 and the n-type carrier accumulation layer 2 is further reduced, and thus the reduction in the RBSOA of the semiconductor device is further suppressed.

[0057] In addition, based on the manufacturing method of the semiconductor device of Embodiment 1, the semiconductor device of Embodiment 2 can be formed by changing the conditions of ion implantation and heat treatment for forming the p-type CSC layer 50.

[0058] <Embodiment 3>

[0059] The semiconductor device of Embodiment 3 is also basically the same in structure as that of Embodiment 1 ( Figure 1 ), but the impurity concentration distribution of the p-type CSC layer 50 is different from that of Embodiment 1.

[0060] Figure 5 Shows the n + -type source layer 13, the p-type base layer 15, the n-type carrier accumulation layer 2, the n 一 -type drift layer 1, and the impurity concentration distribution of the p-type CSC layer 50 in the semiconductor device of Embodiment 3. As Figure 5 shown, in Embodiment 3, the fourth-impurity-containing region of the p-type CSC layer 50 reaches the lower side of the third-impurity-containing region of the n-type carrier accumulation layer 2. Therefore, a p-type layer formed of the p-type CSC layer 50 is formed between the n-type carrier accumulation layer 2 and the n 一 -type drift layer 1.

[0061] In the semiconductor device according to Embodiment 3, the n-type carrier accumulation layer 2 and the n 一 -type drift layer 1 are separated by the p-type layer, thereby reducing the deviation in the local carrier distribution, and thus contributing to the improvement of the RBSOA of the semiconductor device.

[0062] Based on the manufacturing method of the semiconductor device of Embodiment 1, the semiconductor device of Embodiment 3 can also be formed by changing the conditions of ion implantation and heat treatment for forming the p-type CSC layer 50.

[0063] <Embodiment 4>

[0064] The semiconductor device of Embodiment 4 is also basically the same in structure as that of Embodiment 1 ( Figure 1 ), but the impurity concentration distribution of the p-type CSC layer 50 is different from that of Embodiment 1.

[0065] Figure 6 Shows the impurity concentration distributions of the n + -type source layer 13, p-type base layer 15, n-type carrier accumulation layer 2, n 一 -type drift layer 1, and p-type CSC layer 50 in the semiconductor device of Embodiment 4. As Figure 6 shown, in Embodiment 4, the position of the concentration peak of the fourth impurity in the p-type CSC layer 50 is located lower than the position of the concentration peak of the third impurity in the n-type carrier accumulation layer 2.

[0066] In the semiconductor device according to Embodiment 4, the deviation of the impurity concentration gradient at the junction between the n-type carrier accumulation layer 2 and the n 一 -type drift layer 1 is reduced, and thus an effect of reducing the deviation of the saturation voltage (Vsat) (on-state voltage) of the semiconductor device can be expected.

[0067] Based on the manufacturing method of the semiconductor device of Embodiment 1, the semiconductor device of Embodiment 4 can also be formed by changing the conditions of ion implantation and heat treatment for forming the p-type CSC layer 50.

[0068] <Embodiment 5>

[0069] The semiconductor device of Embodiment 5 is also basically the same in structure as that of Embodiment 1 ( Figure 1 ), but the impurity concentration distribution of the p-type CSC layer 50 is different from that of Embodiment1.

[0070] Figure 7 Shows the impurity concentration distributions of the n + -type source layer 13, p-type base layer 15, n-type carrier accumulation layer 2, n 一 -type drift layer 1, and p-type CSC layer 50 in the semiconductor device of Embodiment 5. Similar to Embodiment 4, the position of the concentration peak of the fourth impurity in the p-type CSC layer 50 is located lower than the position of the concentration peak of the third impurity in the n-type carrier accumulation layer 2. As Figure 7 shown, in Embodiment 5, the end portion (the lower swing portion) of the concentration distribution of the fourth impurity in the p-type CSC layer 50 reaches below the third impurity-containing region of the n-type carrier accumulation layer 2.

[0071] The semiconductor device according to Embodiment 5 can achieve both the effects of Embodiment 3 and Embodiment 4. That is, both the improvement of the RBSOA of the semiconductor device and the reduction of the deviation of the saturation voltage can be achieved.

[0072] Based on the manufacturing method of the semiconductor device of Embodiment 1, the semiconductor device of Embodiment 5 can also be formed by changing the conditions of ion implantation and heat treatment for forming the p-type CSC layer 50.

[0073] <Embodiment 6>

[0074] Figure 8 Shows the impurity concentration distributions of the n-type source layer 13, p-type base layer 15, n-type carrier accumulation layer 2, n- + type drift layer 1, and p-type CSC layer 50 in the semiconductor device of Embodiment 6. As 一 shown, in Embodiment 6, the position of the peak concentration of the fourth impurity in the p-type CSC layer 50 is located below the region containing the third impurity in the n-type carrier accumulation layer 2. Figure 8 Shown, in Embodiment 6, the position of the peak concentration of the fourth impurity in the p-type CSC layer 50 is located below the region containing the third impurity in the n-type carrier accumulation layer 2.

[0075] Figure 8 Shows the impurity concentration distributions of the n-type source layer 13, p-type base layer 15, n-type carrier accumulation layer 2, n- + type drift layer 1, and p-type CSC layer 50 in the semiconductor device of Embodiment 6. As 一 shown, in Embodiment 6, the position of the peak concentration of the fourth impurity in the p-type CSC layer 50 is located below the region containing the third impurity in the n-type carrier accumulation layer 2. Figure 8 Shown, in Embodiment 6, the position of the peak concentration of the fourth impurity in the p-type CSC layer 50 is located below the region containing the third impurity in the n-type carrier accumulation layer 2.

[0076] In the semiconductor device of Embodiment 6, both the effects of Embodiment 3 and Embodiment 4 can also be obtained. In addition, compared with Embodiment 6, the peak concentration distribution of the fourth impurity in the p-type CSC layer 50 is constant, so it can further contribute to both the improvement of the RBSOA of the semiconductor device and the reduction of the deviation of the saturation voltage.

[0077] Based on the manufacturing method of the semiconductor device of Embodiment 1, the semiconductor device of Embodiment 6 can also be formed by changing the conditions of ion implantation and heat treatment for forming the p-type CSC layer 50.

[0078] <Embodiment 7>

[0079] Figure 9FIG. 0 is a diagram showing the structure of the semiconductor device according to Embodiment 7, and is a cross-sectional view of the IGBT region 10 and the diode region 20 of the RC-IGBT. The structure of the IGBT region 10 of the semiconductor device according to Embodiment 7 is the same as that of Embodiment 3. That is, the region containing the fourth impurity of the p-type CSC layer 50 reaches the lower side of the region containing the third impurity of the n-type carrier accumulation layer 2. Therefore, a p-type layer composed of the p-type CSC layer 50 is formed between the n-type carrier accumulation layer 2 and the n 一 type drift layer 1.

[0080] Next, the diode region 20 will be described. As Figure 9 shown, a diode trench gate 21 is provided in the diode region 20. The diode trench gate 21 is configured such that a diode trench electrode 21a is provided in a trench of the semiconductor substrate formed in the diode region 20 with a diode trench insulating film 21b interposed therebetween. The diode trench electrode 21a faces the n 一 type drift layer 1 with the diode trench insulating film 21b interposed therebetween. A p + type contact layer 24 and a p-type anode layer 25 are provided between two adjacent diode trench gates 21.

[0081] The p + type contact layer 24 and the p-type anode layer 25 are semiconductor layers having, for example, boron or aluminum as a p-type impurity. The concentration of the p-type impurity in the p + type contact layer 24 is, for example, 1.0E+15 / cm 3 to 1.0E+20 / cm 3 . The concentration of the p-type impurity in the p-type anode layer 25 is set lower than that of the p + type contact layer 24, for example, 1.0E+12 / cm 3 to 1.0E+19 / cm 3 . The p + type contact layer 24 and the p-type anode layer 25 may also be alternately provided along the extending direction of the diode trench gate 21.

[0082] In the semiconductor device, similar to the IGBT region 10, the diode region 20 also has an n 一 type drift layer 1 formed of a semiconductor substrate. The n 一 type drift layer 1 in the diode region 20 and the n 一 type drift layer 1 in the IGBT region 10 are continuously and integrally formed and are formed of the same semiconductor substrate. In Figure 9 , the semiconductor substrate is within the range from the p + type contact layer 24 to the n + type cathode layer 26. In Figure 9 , the p +The upper end of the paper surface of the p-type contact layer 24 is referred to as the first main surface of the semiconductor substrate, and the lower end of the paper surface of the n-type cathode layer 26 is referred to as the second main surface of the semiconductor substrate. The first main surface of the diode region 20 and the first main surface of the IGBT region 10 are the same surface, and the second main surface of the diode region 20 and the second main surface of the IGBT region 10 are the same surface. + As shown in FIGS. and

[0083] , similar to the IGBT region 10, in the diode region 20, an n-type carrier accumulation layer 2 is provided on the first main surface side of the n-type drift layer 1, and an n-type buffer layer 3 is provided on the second main surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the diode region 20 have the same structure as the n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the IGBT region 10. In addition, it is not necessarily required to provide the n-type carrier accumulation layer 2 in the IGBT region 10 and the diode region 20. Further, similar to the IGBT region 10, the n-type drift layer 1, the n-type carrier accumulation layer 2, and the n-type buffer layer 3 may be collectively referred to as the drift layer.

[0083] As Figure 9 shown, similar to the IGBT region 10, in the diode region 20, an n-type carrier accumulation layer 2 is provided on the first main surface side of the n-type drift layer 1, and an n-type buffer layer 3 is provided on the second main surface side of the n-type drift layer 1. 一 In the diode region 20, an n-type carrier accumulation layer 2 is provided on the first main surface side of the n-type drift layer 1, and an n-type buffer layer 3 is provided on the second main surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the diode region 20 have the same structure as the n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the IGBT region 10. In addition, it is not necessarily required to provide the n-type carrier accumulation layer 2 in the IGBT region 10 and the diode region 20. Further, similar to the IGBT region 10, the n-type drift layer 1, the n-type carrier accumulation layer 2, and the n-type buffer layer 3 may be collectively referred to as the drift layer. 一 On the first main surface side of the n-type carrier accumulation layer 2, a p-type anode layer 25 is provided. The p-type anode layer 25 is provided between the n-type drift layer 1 and the first main surface. The concentration of the p-type anode layer 25 may be the same as the concentration of the p-type impurity of the p-type base layer 15 in the IGBT region 10, and the p-type anode layer 25 and the p-type base layer 15 may be formed simultaneously (that is, through the same process). Alternatively, the concentration of the p-type impurity of the p-type anode layer 25 may be made lower than the concentration of the p-type impurity of the p-type base layer 15 in the IGBT region 10 to reduce the amount of holes injected into the diode region 20 during diode operation. By reducing the amount of holes injected during diode operation, the recovery loss during diode operation can be reduced. 一 In the present embodiment, the p-type anode layer 25 and the p-type base layer 15 are formed simultaneously. As a result, the p-type anode layer 25 is located in the surface layer portion of the semiconductor layer and has the same impurity concentration distribution as the p-type base layer 15. "The same impurity concentration distribution" means that it is not necessary to be exactly the same, as long as it is substantially the same.

[0084] On the first main surface side of the p-type anode layer 25, a p-type contact layer 24 is provided. The concentration of the p-type impurity of the p-type contact layer 24 may be the same as the concentration of the p-type impurity of the p-type contact layer 14 in the IGBT region 10, or may be different. 一 On the first main surface side of the n-type carrier accumulation layer 2, a p-type anode layer 25 is provided. The p-type anode layer 25 is provided between the n-type drift layer 1 and the first main surface. The concentration of the p-type anode layer 25 may be the same as the concentration of the p-type impurity of the p-type base layer 15 in the IGBT region 10, and the p-type anode layer 25 and the p-type base layer 15 may be formed simultaneously (that is, through the same process). Alternatively, the concentration of the p-type impurity of the p-type anode layer 25 may be made lower than the concentration of the p-type impurity of the p-type base layer 15 in the IGBT region 10 to reduce the amount of holes injected into the diode region 20 during diode operation. By reducing the amount of holes injected during diode operation, the recovery loss during diode operation can be reduced.

[0085] In the present embodiment, the p-type anode layer 25 and the p-type base layer 15 are formed simultaneously. As a result, the p-type anode layer 25 is located in the surface layer portion of the semiconductor layer and has the same impurity concentration distribution as the p-type base layer 15. "The same impurity concentration distribution" means that it is not necessary to be exactly the same, as long as it is substantially the same.

[0086] On the first main surface side of the p-type anode layer 25, a p + type contact layer 24 is provided. The p + type contact layer 24 may have the same concentration of p-type impurity as the p + type contact layer 14 in the IGBT region 10, or may have a different concentration.

[0087] In this embodiment, the p + -type contact layer 24 and the p + -type contact layer 14 are formed simultaneously. Thus, the p + -type contact layer 24 is located in the surface layer portion of the semiconductor layer and has the same impurity concentration distribution as the p + -type contact layer 14.

[0088] The p-type anode layer 25 and the p + -type contact layer 24 constitute the first main surface of the semiconductor substrate. In addition, the p + -type contact layer 24 is a region where the concentration of p-type impurities is higher than that of the p-type anode layer 25. When it is necessary to distinguish between the p + -type contact layer 24 and the p-type anode layer 25, they can be called separately, or the p + -type contact layer 24 and the p-type anode layer 25 can be collectively referred to as the p-type anode layer.

[0089] In the diode region 20, an n + -type cathode layer 26 is provided on the second main surface side of the n-type buffer layer 3. The n + -type cathode layer 26 is provided between the n 一 -type drift layer 1 and the second main surface. The n + -type cathode layer 26 is, for example, a semiconductor layer having arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+16 / cm 3 ~1.0E+21 / cm 3 . The n + -type cathode layer 26 is provided in a part or all of the diode region 20. The n + -type cathode layer 26 constitutes the second main surface of the semiconductor substrate.

[0090] In Figure 9 , the p-type collector layer 16 provided on the second main surface side of the IGBT region 10 is set to protrude only by a distance U1 from the boundary between the IGBT region 10 and the diode region 20 toward the diode region 20 side. Thus, by setting the p-type collector layer 16 to protrude into the diode region 20, the distance between the n + -type cathode layer 26 of the diode region 20 and the active trench gate 11 can be increased. Even when a gate drive voltage is applied to the gate trench electrode 11a during the operation of the freewheeling diode, current flowing from the channel formed adjacent to the active trench gate 11 of the IGBT region 10 to the n + -type cathode layer 26 can be suppressed. The distance U1 can be, for example, 100 μm. In addition, depending on the use of the semiconductor device 100 or the semiconductor device 101 as an RC-IGBT, the distance U1 can also be 0 or a distance less than 100 μm.

[0091] In addition, although not shown in the drawings, p-type impurities may be selectively implanted further into the region where the n- + type cathode layer 26 is formed, and a part of the region where the n- + type cathode layer 26 is formed may be set as a p-type semiconductor to form a p-type cathode layer.

[0092] The diode trench gate 21 penetrates through the p-type anode layer 25 and the n-type carrier accumulation layer 2 from the first main surface of the semiconductor substrate to reach the n- 一 type drift layer 1. The diode trench electrode 21a faces the p-type anode layer 25, the n-type carrier accumulation layer 2, and the n- 一 type drift layer 1 with the diode trench insulating film 21b interposed therebetween.

[0093] A barrier metal 5 is provided on the diode trench electrode 21a and the p- + type contact layer 24. The barrier metal 5 makes an ohmic contact with the diode trench electrode 21a and the p- + type contact layer 24 and is electrically connected to the diode trench electrode and the p- + type contact layer 24. The barrier metal 5 in the diode region 20 may have the same structure as the barrier metal 5 in the IGBT region 10. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 provided in the diode region 20 is formed continuously with the emitter electrode 6 provided in the IGBT region 10. In addition, similar to the case of the IGBT region 10, the barrier metal 5 may not be provided, and the diode trench electrode 21a and the p- + type contact layer 24 may make an ohmic contact with the emitter electrode 6. In addition, in Figure 9 FIG., a diagram is shown in which the interlayer insulating film 4 is not provided on the diode trench electrode 21a of the diode trench gate 21, but the interlayer insulating film 4 may be formed on the diode trench electrode 21a of the diode trench gate 21. In the case where the interlayer insulating film 4 is formed on the diode trench electrode 21a of the diode trench gate 21, the emitter electrode 6 and the diode trench electrode 21a may be electrically connected at other cross-sections.

[0094] A collector 7 is provided on the second main surface side of the n- + type cathode layer 26. Similar to the emitter electrode 6, the collector 7 in the diode region 20 is formed continuously with the collector 7 provided in the IGBT region 10. The collector 7 makes an ohmic contact with the n- + type cathode layer 26 and is electrically connected to the n- + type cathode layer 26.

[0095] In addition to the above structure, the semiconductor device according to Embodiment 7 has a structure in which the p-type CSC layer 50 also extends to the diode region 20. The structure of the IGBT region 10 is the same as that of Embodiment 3, and the region containing the fourth impurity of the p-type CSC layer 50 reaches the lower side of the region containing the third impurity of the n-type carrier accumulation layer 2. Therefore, within the diode region 20, the region containing the fourth impurity of the p-type CSC layer 50 also reaches the lower side of the region containing the third impurity of the n-type carrier accumulation layer 2.

[0096] According to the semiconductor device of Embodiment 7, in addition to the effects of Embodiment 3, an effect can be obtained in which the anode injection efficiency in the diode region 20 can be adjusted by extending the p-type CSC layer 50 to the diode region 20.

[0097] <Embodiment 8>

[0098] Figure 10 FIG. is a cross-sectional view of the IGBT region 10 and the diode region 20 of an RC-IGBT, showing the structure of the semiconductor device according to Embodiment 8. The structure of the IGBT region 10 of the semiconductor device according to Embodiment 8 is also the same as that of Embodiment 3.

[0099] In the semiconductor device according to Embodiment 8, the p-type anode layer 25 of the diode region 20 is formed simultaneously with the p-type CSC layer 50. That is, the p-type anode layer 25 is formed by ion-implanting the fourth impurity into the semiconductor substrate and then diffusing the fourth impurity by heat treatment. As a result, the p-type anode layer 25 is located in the surface layer portion of the semiconductor layer and has the same concentration distribution of the second impurity as the p-type CSC layer 50.

[0100] In addition, except for the region where the p-type anode layer 25 is formed in the surface layer portion of the semiconductor layer, the diode region 20 of the semiconductor device according to Embodiment 8 includes a region where the emitter electrode 6 is Schottky-connected to the n 一 type drift layer 1, that is, the Schottky region 60. That is, the diode region 20 functions as an MPS (Merged PiN Schottky: hybrid PIN-Schottky diode) diode having a structure with a PN junction diode and a Schottky barrier diode. Hereinafter, the RC-IGBT in which the diode region 20 functions as an MPS diode is referred to as an "MPS-RC-IGBT".

[0101] According to the semiconductor device of Embodiment 8, the p-type CSC layer 50 and the p-type anode layer 25 of the diode region 20 can be formed simultaneously. As a result, there is no need to increase the manufacturing process in order to add the p-type CSC layer 50 to the IGBT region 10.

[0102] <Embodiment 9>

[0103] Figure 10 FIG. Figure 10 is a diagram showing the structure of the semiconductor device according to Embodiment 9, and is a cross-sectional view of the IGBT region 10 and the diode region 20 of the RC-IGBT. The structure of the IGBT region 10 of the semiconductor device according to Embodiment 9 is the same as that of Embodiment 3. In addition, the diode region 20 is the same as that of Embodiment 8, and includes a Schottky region 60 and functions as a diode as an MPS.

[0104] In the semiconductor device according to Embodiment 9, in the diode region 20, in the n-type drift layer 1 of the Schottky region 60, 一 a Schottky adjustment layer 61 with locally different n-type impurity concentrations is provided on the surface layer portion. In addition, the p-type CSC layer 50 also extends to the Schottky region 60.

[0105] According to the semiconductor device of Embodiment 9, the characteristics of the Schottky region 60 of the MPS-RC-IGBT can be adjusted.

[0106] In addition, the respective embodiments can be freely combined, or the respective embodiments can be appropriately modified or omitted.

[0107] <Supplementary Note>

[0108] Hereinafter, the respective aspects of the present invention will be collectively described as supplementary notes.

[0109] (Supplementary Note 1)

[0110] A semiconductor device, comprising:

[0111] a source layer of a first conductivity type, which is located in the surface layer portion of the semiconductor layer and is defined by the concentration distribution of a first impurity;

[0112] a base layer of a second conductivity type, which is located below the source layer and is defined by the concentration distribution of a second impurity;

[0113] the carrier accumulation layer of the first conductivity type, which is located below the base layer and is defined by the concentration distribution of a third impurity;

[0114] the drift layer of the first conductivity type, which is located below the carrier accumulation layer; and

[0115] the CSC layer of the second conductivity type, which is defined by the concentration distribution of a fourth impurity and is located at a position where the region containing the fourth impurity includes: the region where the region containing the second impurity of the base layer overlaps with the region containing the third impurity of the carrier accumulation layer.

[0116] (Supplementary Note 2)

[0117] The semiconductor device according to Supplementary Note 1, wherein

[0118] In a region where a region containing the second impurity in the base layer overlaps with a region containing the third impurity in the carrier accumulation layer, the concentration of the fourth impurity in the CSC layer is higher than the concentration of the second impurity and the concentration of the third impurity.

[0119] (Supplementary Note 3)

[0120] The semiconductor device according to Supplementary Note 1 or 2, wherein

[0121] The region containing the fourth impurity in the CSC layer includes: a region where the region containing the first impurity in the source layer overlaps with the region containing the second impurity in the base layer.

[0122] (Supplementary Note 4)

[0123] The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein

[0124] The region containing the fourth impurity in the CSC layer reaches a position lower than the region containing the third impurity in the carrier accumulation layer.

[0125] (Supplementary Note 5)

[0126] The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein

[0127] The position of the peak concentration of the fourth impurity in the CSC layer is located at a position lower than the position of the peak concentration of the third impurity in the carrier accumulation layer.

[0128] (Supplementary Note 6)

[0129] The semiconductor device according to Supplementary Note 5, wherein

[0130] The end portion in the concentration distribution of the fourth impurity in the CSC layer reaches a position lower than the region containing the third impurity in the carrier accumulation layer.

[0131] (Supplementary Note 7)

[0132] The semiconductor device according to Supplementary Note 5 or 6, wherein

[0133] The position of the peak concentration of the fourth impurity in the CSC layer is located at a position lower than the region containing the third impurity in the carrier accumulation layer.

[0134] (Supplementary Note 8)

[0135] The semiconductor device according to Supplementary Note 4, wherein

[0136] The semiconductor layer further includes a diode region that functions as a diode.

[0137] The diode region has an anode layer of the second conductivity type, the anode layer of the second conductivity type is located in the surface portion of the semiconductor layer, and has the same concentration distribution of the second impurity as that of the base layer.

[0138] The carrier accumulation layer, the drift layer, and the CSC layer also extend to the diode region.

[0139] (Supplementary Note 9)

[0140] The semiconductor device according to Supplementary Note 4, wherein

[0141] The semiconductor layer further has a diode region that functions as a diode.

[0142] The drift layer also extends to the diode region.

[0143] The diode region includes:

[0144] A region where an anode layer of the second conductivity type having the same concentration distribution of the fourth impurity as that of the CSC layer is formed in the surface portion of the semiconductor layer; and

[0145] A region where an electrode provided on the semiconductor layer is Schottky-connected to the drift layer, that is, a Schottky region.

[0146] (Supplementary Note 10)

[0147] The semiconductor device according to Supplementary Note 4, wherein

[0148] The semiconductor layer further has a diode region that functions as a diode.

[0149] The drift layer also extends to the diode region.

[0150] The diode region includes:

[0151] A region where the anode layer of the second conductivity type is formed in the surface portion of the semiconductor layer; and

[0152] A region where an electrode provided on the semiconductor layer is Schottky-connected to the drift layer, that is, a Schottky region,

[0153] The CSC layer also extends to the Schottky region.

[0154] (Supplementary Note 11)

[0155] A method for manufacturing a semiconductor device, comprising the following steps:

[0156] Process a: Ion-implant a fourth impurity into the semiconductor layer, and diffuse the fourth impurity through heat treatment, thereby forming a CSC layer of a second conductivity type in the semiconductor layer;

[0157] Process b: Ion-implant a first impurity into the semiconductor layer, thereby forming a source layer of a first conductivity type in the surface layer portion of the semiconductor layer;

[0158] Process c: Ion-implant a second impurity into the semiconductor layer, thereby forming the base layer of the second conductivity type located below the source layer; and

[0159] Process d: Ion-implant a third impurity into the semiconductor layer, thereby forming the carrier accumulation layer of the first conductivity type located below the base layer,

[0160] Processes b, c, and d are performed after process a,

[0161] In processes b, c, and d, the source layer, the base layer, and the carrier accumulation layer are formed such that the junction between the source layer and the base layer and the junction between the base layer and the carrier accumulation layer are included in the CSC layer formed in process a.

Claims

1. A semiconductor device, characterized in that, Comprising: A source layer of a first conductivity type, which is located in the surface layer portion of the semiconductor layer and is defined by the concentration distribution of a first impurity; A base layer of a second conductivity type, which is located below the source layer and is defined by the concentration distribution of a second impurity; The carrier accumulation layer of the first conductivity type, which is located below the base layer and is defined by the concentration distribution of a third impurity; The drift layer of the first conductivity type, which is located below the carrier accumulation layer; And The CSC layer of the second conductivity type, which is defined by the concentration distribution of a fourth impurity and is located at a position where the region containing the fourth impurity includes: the region where the region containing the second impurity in the base layer overlaps with the region containing the third impurity in the carrier accumulation layer.

2. The semiconductor device according to claim 1, wherein: In the region where the region containing the second impurity in the base layer overlaps with the region containing the third impurity in the carrier accumulation layer, the concentration of the fourth impurity in the CSC layer is higher than the concentration of the second impurity and the concentration of the third impurity.

3. The semiconductor device according to claim 1 or 2, wherein: The region containing the fourth impurity in the CSC layer includes: the region where the region containing the first impurity in the source layer overlaps with the region containing the second impurity in the base layer.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The region containing the fourth impurity in the CSC layer reaches a position lower than the region containing the third impurity in the carrier accumulation layer.

5. The semiconductor device according to any one of claims 1 to 3, wherein: The position of the concentration peak of the fourth impurity in the CSC layer is located at a position lower than the position of the concentration peak of the third impurity in the carrier accumulation layer.

6. The semiconductor device according to claim 5, wherein: The end portion in the concentration distribution of the fourth impurity in the CSC layer reaches a position lower than the region containing the third impurity in the carrier accumulation layer.

7. The semiconductor device according to claim 5 or 6, wherein: The position of the concentration peak of the fourth impurity in the CSC layer is located at a position lower than the region containing the third impurity in the carrier accumulation layer.

8. The semiconductor device according to claim 4, wherein: The semiconductor layer further includes a diode region that functions as a diode, The diode region includes the anode layer of the second conductivity type, and the anode layer of the second conductivity type is located in the surface layer portion of the semiconductor layer and has the same concentration distribution of the second impurity as the base layer, The carrier accumulation layer, the drift layer, and the CSC layer also extend to the diode region.

9. The semiconductor device according to claim 4, wherein: The semiconductor layer further includes a diode region that functions as a diode, The drift layer also extends to the diode region, The diode region includes: A region for forming an anode layer of the second conductivity type having a concentration distribution of the fourth impurity that is the same as that of the CSC layer and is located in the surface portion of the semiconductor layer; and A region where an electrode provided on the semiconductor layer is Schottky-connected to the drift layer, i.e., a Schottky region.

10. The semiconductor device according to claim 4, wherein the semiconductor layer further includes a diode region that functions as a diode, the drift layer also extends to the diode region, the diode region includes: a region where an anode layer of the second conductivity type is formed in the surface portion of the semiconductor layer; and a region where an electrode provided on the semiconductor layer is Schottky-connected to the drift layer, i.e., a Schottky region, the CSC layer also extends to the Schottky region.

11. A method of manufacturing a semiconductor device, characterized in that, Comprising the following steps: Step a, ion-implanting a fourth impurity into the semiconductor layer and diffusing the fourth impurity through heat treatment to form a CSC layer of the second conductivity type in the semiconductor layer; Step b, ion-implanting a first impurity into the semiconductor layer to form a source layer of the first conductivity type in the surface portion of the semiconductor layer; Step c, ion-implanting a second impurity into the semiconductor layer to form the base layer of the second conductivity type located below the source layer; and Step d, ion-implanting a third impurity into the semiconductor layer to form a carrier accumulation layer of the first conductivity type located below the base layer, Steps b, c, and d are performed after Step a, in Steps b, c, and d, the source layer, the base layer, and the carrier accumulation layer are formed such that the junction between the source layer and the base layer and the junction between the base layer and the carrier accumulation layer are included in the CSC layer formed in Step a.

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