Semiconductor device and forming method thereof
By setting a dummy gate structure in the second active region of the semiconductor substrate, the recession problem caused by the chemical mechanical grinding process is solved, ensuring that the metal material does not remain, avoiding pollution, and improving the stability and reliability of the semiconductor components.
Patent Information
- Application Number
- CN202410129341.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-01-12
- Filing Date
- 2024-01-30
- Publication Date
- 2025-07-18
AI Technical Summary
In semiconductor manufacturing processes, chemical mechanical grinding processes may cause recesses of semiconductor components buried in the substrate, such as shallow trench isolation trap resistors, resulting in metal material residues and peeling off in subsequent processes, causing contamination.
A dummy gate structure is provided in the second active region of the substrate, including on different parts of the insulating pattern and component isolation structures, and after chemical mechanical grinding process, the formation of recesses is avoided, thereby preventing metal material from remaining.
It effectively avoids the residue of metal materials in the depression, prevents contamination in subsequent processes, and ensures the stability and reliability of semiconductor components.
Smart Images
Figure CN120343970A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor device and a method for forming the same. Background Art
[0002] In current semiconductor manufacturing processes, replacing a traditional polysilicon gate with a high-k metal gate (HKMG) is one of the means to improve the performance of semiconductor components. In the manufacturing process of forming HKMG, a gate-last technique is usually adopted to form the metal gate of a metal-oxide-semiconductor field-effect transistor (MOSFET), that is, when forming the gate structure of a MOSFET, the metal gate in the gate structure is formed last. For example, in the gate-last technique, a dummy gate is usually formed first to reserve the position where the metal gate is to be formed subsequently. Then, after forming the insulating layer (ILD0) surrounding the gate structure, the dummy gate is removed and filled with a metal material to replace the dummy gate with the metal gate.
[0003] However, in the manufacturing process of forming the insulating layer surrounding the gate structure, a planarization manufacturing process such as chemical mechanical polishing (CMP) is usually adopted to remove the excess insulating material, so that the top surface of the dummy gate can be exposed to enable the subsequent manufacturing process of replacing the dummy gate with the metal gate. However, the above CMP manufacturing process may affect semiconductor components in other positions. For example, for some semiconductor components buried in the substrate such as a shallow trench isolation well resistor (STI well resistor), since the insulating layer formed on the substrate has a large area and no structure is formed (also called ILD0 ISO), the ILD0 ISO located on these components is prone to dishing during the above CMP manufacturing process. In this way, in the manufacturing process of replacing the dummy gate with the metal gate, the metal material is likely to remain in the depression and cannot be removed, and thus the remaining metal material may peel off in the subsequent manufacturing process and cause contamination. Summary of the Invention
[0004] The present invention provides a semiconductor device and a method for forming the same. A dummy gate structure is disposed in a second active region and includes a first pattern on a first portion of an insulating pattern, a second pattern on a second portion of the insulating pattern, and a third pattern on an element isolation structure. In this way, a second element buried in the substrate has a dummy gate structure above it, so that the insulating layer above it is not easily recessed (dished) in the CMP manufacturing process. Therefore, in the manufacturing process of replacing the dummy gate with a metal gate, the metal material will not remain in the recess generated by the CMP manufacturing process, so as to avoid contamination caused by the peeling of the metal material from the recess in the subsequent manufacturing process.
[0005] An embodiment of the present invention provides a semiconductor device, including a substrate, a first element, a second element, and a dummy gate structure. The substrate includes a first active region and a second active region defined by an element isolation structure. The first element is disposed in the first active region and includes a gate structure disposed on the substrate and source / drain regions in the first active region on opposite sides of the gate structure. The second element is disposed in the second active region and includes an insulating pattern buried in the substrate and a first doped region and a second doped region in the substrate. The insulating pattern includes a first portion and a second portion surrounding the first portion. The second portion and the element isolation structure define a region in the second active region where the first doped region is formed. The second portion and the first portion define a region in the second active region where the second doped region is formed. The dummy gate structure is disposed in the second active region and includes a first pattern, a second pattern, and a third pattern. The first pattern is disposed on the first portion of the insulating pattern. The second pattern is disposed on the second portion of the insulating pattern. The third pattern is disposed on the element isolation structure.
[0006] In some embodiments, the gate structure includes a first high-k dielectric layer, a first capping layer, and a first metal gate sequentially disposed on the substrate. The dummy gate structure includes a second high-k dielectric layer, a second capping layer, and a second metal gate sequentially disposed on the substrate, and the first metal gate and the second metal gate are disposed at the same horizontal height relative to the substrate.
[0007] In some embodiments, the first pattern includes a plurality of annular patterns, a plurality of dot patterns, or a plurality of elongated patterns arranged in a first direction and extending in a second direction.
[0008] In some embodiments, the second doped regions of the second element extend in a first direction and are spaced apart from each other in a second direction.
[0009] In some embodiments, the first doped region of the second element surrounds the insulating pattern and has a different conductivity type from the second doped region.
[0010] In some embodiments, the semiconductor device further includes a first dielectric structure and a second dielectric structure.
[0011] The first dielectric structure is disposed on the substrate and between the first pattern and the second pattern of the dummy gate structure.
[0012] The second dielectric structure is disposed on the substrate and between the second pattern and the third pattern of the dummy gate structure.
[0013] The first dielectric structure and the second dielectric structure are spaced apart from each other.
[0014] In some embodiments, the first dielectric structure covers the second doped region, and the second dielectric structure covers the first doped region.
[0015] In some embodiments, the substrate includes a first well region, a second well region, and a deep well region. The first well region is disposed in the second active region and has a first conductivity type. The second well region is disposed in the first well region and has a second conductivity type different from the first conductivity type. The first doped region is disposed in the first well region, and the second doped region is disposed in the second well region. The deep well region is disposed in the second active region below the second well region and has the second conductivity type.
[0016] In some embodiments, the dummy gate structure is electrically floating.
[0017] An embodiment of the present invention provides a method for forming a semiconductor device, which includes: forming an element isolation structure in a substrate to define a first active region and a second active region; forming a first element in the first active region of the substrate, wherein the first element includes a gate structure formed on the substrate; forming a second element in the second active region of the substrate, the second element includes an insulating pattern buried in the substrate and a first doped region and a second doped region formed in the substrate, wherein the insulating pattern includes a first part and a second part surrounding the first part, the second part and the element isolation structure define a region in the second active region where the first doped region is formed, and the second part and the first part define a region in the second active region where the second doped region is formed; and forming a dummy gate structure in the second active region of the substrate, wherein the dummy gate structure includes a first pattern, a second pattern, and a third pattern, the first pattern is formed on the first part of the insulating pattern, the second pattern is formed on the second part of the insulating pattern, and the third pattern is formed on the element isolation structure.
[0018] In some embodiments, the gate structure includes a first high-k layer, a first capping layer, and a first metal gate formed in sequence on the substrate, the dummy gate structure includes a second high-k layer, a second capping layer, and a second metal gate formed in sequence on the substrate, and the first metal gate and the second metal gate are formed at the same horizontal height relative to the substrate.
[0019] In some embodiments, the manufacturing process for forming the first metal gate and the second metal gate includes a chemical mechanical polishing manufacturing process.
[0020] In some embodiments, the second doped regions of the second element are formed to extend in a first direction and be spaced apart from each other in the second direction.
[0021] In some embodiments, the first doped region of the second element is formed to surround the insulating pattern and have a different conductivity type from the second doped region.
[0022] In some embodiments, the method of forming a semiconductor device further includes: forming a first dielectric structure between a first pattern and a second pattern of a dummy gate structure above the insulating pattern; and forming a second dielectric structure between a second pattern and a third pattern of the dummy gate structure above the insulating pattern, wherein the first dielectric structure and the second dielectric structure are spaced apart from each other.
[0023] In some embodiments, the first dielectric structure covers the second doped region, and the second dielectric structure covers the first doped region.
[0024] In some embodiments, the substrate includes a first well region, a second well region, and a deep well region. The first well region is formed in the second active region and has a first conductivity type. The second well region is formed in the first well region and has a second conductivity type different from the first conductivity type, wherein the first doped region is formed in the first well region, and the second doped region is formed in the second well region. The deep well region is formed in the second active region below the second well region and has the second conductivity type. The second well region is formed below a first portion of the insulating pattern, the first doped region has the first conductivity type, and the second doped region has the second conductivity type.
[0025] In some embodiments, the dummy gate structure is electrically floating.
[0026] Based on the above, in the above semiconductor device and its forming method, the dummy gate structure is disposed in the second active region and includes a first pattern on a first portion of the insulating pattern, a second pattern on a second portion of the insulating pattern, and a third pattern on the element isolation structure. In this way, the second element buried in the substrate has a dummy gate structure including the first pattern, the second pattern, and the third pattern above it, so that the insulating layer above the second element is not easily recessed (dishing) in the CMP manufacturing process. Therefore, in the manufacturing process of replacing the dummy gate with a metal gate, the metal material will not remain in the recesses generated by the CMP manufacturing process, so as to avoid contamination caused by the peeling of the metal material from the recesses in the subsequent manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figures 1 to 10A cross-sectional schematic diagram of a method for forming a semiconductor device according to an embodiment of the present invention;
[0028] Figure 11 A top view schematic diagram of a semiconductor device according to an embodiment of the present invention;
[0029] Figure 12 A top view schematic diagram of a semiconductor device according to another embodiment of the present invention;
[0030] Figure 13 A top view schematic diagram of a semiconductor device according to still another embodiment of the present invention.
[0031] Symbol Explanation
[0032] 10: Semiconductor device
[0033] 100: Substrate
[0034] 102a, 102b: Deep well regions
[0035] 104a, 104b: Well regions
[0036] 106: Well region
[0037] 110: Element isolation structure
[0038] 112: Insulating pattern
[0039] 112a: First part
[0040] 112b: Second part
[0041] 120: High-k dielectric material layer
[0042] 122: High-k dielectric layer
[0043] 130: Capping material layer
[0044] 132: Capping layer
[0045] 140: Sacrificial gate material layer
[0046] 142: Sacrificial gate layer
[0047] 150, 152: Spacer
[0048] 160a: Doped region
[0049] 160b: Doped region / First doped region
[0050] 162: Doped region / Second doped region
[0051] 170: Silicide layer
[0052] 180: Etch stop material layer
[0053] 182: Etch stop layer
[0054] 190: Dielectric material layer
[0055] 192: Dielectric layer
[0056] D1: First element
[0057] D2: Second element
[0058] DGS, DGS', DGS'':Dummy gate structure
[0059] GS: Gate structure
[0060] HML: Hard mask material layer
[0061] HMP: Hard mask layer
[0062] MGL: Metal material layer
[0063] MG: Metal gate / First metal gate / Second metal gate
[0064] P1, P1', P1'': First pattern
[0065] P2: Second pattern
[0066] P3: Third pattern
[0067] R1: First active region
[0068] R2: Second active region
[0069] STK: Stacked structure
[0070] SGS: Sacrificial gate structure Detailed implementation manners
[0071] The present invention will be described more comprehensively with reference to the accompanying drawings of this embodiment. However, the present invention can be embodied in various different forms and should not be limited to the embodiments described herein. The thicknesses of the layers and regions in the drawings are enlarged for clarity. The same or similar reference numerals represent the same or similar elements, and will not be repeated in the following paragraphs.
[0072] It should be understood that when an element such as is referred to as being "on" or "connected to" another element, it can be directly on the other element or connected to the other element, or there may also be intervening elements. If an element is referred to as being "directly on" or "directly connected to" another element, then there are no intervening elements. As used herein, "connected" can refer to a physical and / or electrical connection, and "electrically connected" or "coupled" may mean that there are other elements between two elements. The "electrically connected" used herein can include a physical connection (such as a wired connection) and a physical disconnection (such as a wireless connection).
[0073] As used herein, "about", "approximate" or "substantially" includes the value mentioned and an average value within an acceptable deviation range of a specific value that a person of ordinary skill in the art can determine, taking into account the specific amount of the measurement being discussed and the error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the "about", "approximate" or "substantially" used herein can select a more acceptable deviation range or standard deviation according to optical properties, etching properties or other properties, rather than applying one standard deviation to all properties.
[0074] The terms used herein are for the purpose of describing exemplary embodiments only and are not intended to limit the present invention. In such a case, unless otherwise explained in the context, the singular form includes the plural form.
[0075] Figures 1 to 10 is a cross-sectional schematic view of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 11 is a top view schematic view of a semiconductor device according to an embodiment of the present invention. Figure 10 can be along Figure 11 The cross-sectional schematic view taken along the cutting line A-A'. Figure 12 is a top view schematic view of a semiconductor device according to another embodiment of the present invention. Figure 13 is a top view schematic view of a semiconductor device according to yet another embodiment of the present invention.
[0076] In some embodiments, the method for forming a semiconductor device (such as Figure 10 The semiconductor device 10 shown) may include the following steps.
[0077] First, please refer to Figure 1, an element isolation structure 110 that defines a first active region R1 and a second active region R2 is formed in a substrate 100. The substrate 100 may include a semiconductor substrate or a semiconductor on insulator (SOI) substrate. The semiconductor material in the semiconductor substrate or SOI substrate may include elemental semiconductors, alloy semiconductors, or compound semiconductors. For example, the elemental semiconductor may include Si or Ge. The alloy semiconductor may include SiGe, SiGeC, etc. The compound semiconductor may include SiC, group III-V semiconductor materials, or group II-VI semiconductor materials. The group III-V semiconductor materials may include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNP, GaNAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs, or InAlPAs. The group II-VI semiconductor materials may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, or HgZnSTe. The semiconductor material may be doped with dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type. For example, the first conductivity type may be P-type, and the second conductivity type may be N-type. In some embodiments, the substrate 100 may be doped with P-type dopants. The element isolation structure 110 may include a material suitable for an element isolation structure, such as silicon oxide.
[0078] Next, a first element (e.g., Figure 10 the first element D1) is formed in the first active region R1 of the substrate 100, a second element (e.g., Figure 10 the second element D2) is formed in the second active region R2 of the substrate 100, and a dummy gate structure (e.g., Figure 10Dummy gate structure DGS). In some embodiments, the first element may be a metal oxide semiconductor field effect transistor (MOSFET), and the second element may be a shallow trench isolation well resistor (STI well resistor). In some embodiments, the first element, the second element, and the dummy gate structure may be formed by the following steps.
[0079] First, continue to refer to Figure 1 , in the step of forming the element isolation structure 110, an insulating pattern 112 buried in the substrate 100 is formed in the second active region R2. The insulating pattern 112 includes a first portion 112a and a second portion 112b surrounding the first portion 112a. The second portion 112b and the element isolation structure 110 define, in the second active region R2, a region in which a first doped region (such as the doped region 160b shown in Figure 5 ) is formed. The second portion 112b and the first portion 112a define, in the second active region R2, a region in which a second doped region (such as the doped region 162 shown in Figure 5 ) is formed. The insulating pattern 112 may include an insulating material such as silicon oxide. In some embodiments, the insulating pattern 112 and the element isolation structure 110 may be formed simultaneously in the same manufacturing process. In some embodiments, the insulating pattern 112 may be a continuous film layer (as shown in Figure 11 ) in which the openings therein correspond to the positions of the second doped region 162.
[0080] Next, refer to Figure 2 , deep well regions 102a and 102b having a second conductivity type (e.g., N-type) are formed in the first active region R1 and the second active region R2 of the substrate 100, respectively. In some embodiments, the deep well region 102b may be formed below the first portion 112a of the insulating pattern 112 and extend laterally below the second portion 112b of the insulating pattern 112. Then, a well region 104a having a first conductivity type (e.g., P-type) different from the second conductivity type is formed in the deep well region 102a, and a well region 104b having the first conductivity type (e.g., P-type) is formed in the second active region R2 around the deep well region 102b and the deep well region 102b. Then, a well region 106 having a second conductivity type (e.g., N-type) is formed in the well region 104b formed in the deep well region 102a. That is, as shown in Figure 2As shown, the substrate 100 may include a first well region (e.g., well region 104b) formed in the second active region R2 and having a first conductivity type, a second well region (e.g., well region 106) formed in the first well region and having a second conductivity type different from the first conductivity type, and a deep well region 102b formed in the second active region R2 below the second well region and having the second conductivity type, wherein the second well region (e.g., well region 106) may be formed below the first portion 112a of the insulating pattern 112.
[0081] Then, please refer to Figure 3 , a high-k dielectric material layer 120, a capping material layer 130, a sacrificial gate material layer 140, and a hard mask material layer HML are sequentially formed on the substrate 100.
[0082] The high-k dielectric material layer 120 may include a dielectric material having a high dielectric constant. For example, the dielectric material having a high dielectric constant may be a material having a dielectric constant greater than that of silicon oxide (about 3.9). In some embodiments, the high-k dielectric material layer 120 may include HfO2, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, Al2O3, Si3N4, SiON, or a combination thereof. The capping material layer 130 may include TiN. The sacrificial gate material layer 140 may include polysilicon. The hard mask material layer HML may include an oxide, a nitride, or a combination thereof.
[0083] Then, please refer to Figure 3 and Figure 4 , a patterning process is performed on the high-k dielectric material layer 120, the capping material layer 130, the sacrificial gate material layer 140, and the hard mask material layer HML to form a plurality of stacked structures STK each including a high-k dielectric layer 122, a capping layer 132, a sacrificial gate layer 142, and a hard mask layer HMP. In the first active region R1, the stacked structure STK may be disposed on the well region 104a of the substrate 100. In the second active region R2, the plurality of stacked structures STK may include a first stacked structure disposed on the first portion 112a of the insulating pattern 112, a second stacked structure disposed on the second portion 112b of the insulating pattern 112, and a third stacked structure disposed on the device isolation structure 110. In some embodiments, the first stacked structure, the second stacked structure, and the third stacked structure are spaced apart from each other.
[0084] Then, please refer to Figure 4 and Figure 5, spacer walls 150 are formed on opposite sidewalls of each stacked structure STK. The spacer walls 150 may include silicon oxide, silicon nitride, or a combination thereof.
[0085] Next, a first doping process is performed on the first active region R1 and the second active region R2 to form doped regions 160a of a first conductivity type in the well regions 104a at opposite sides of the stacked structure STK, and to form doped regions 160b of a first conductivity type in the region defined by the second portion 112b of the insulating pattern 112 and the element isolation structure 110 in the well region 104b. Then, a second doping process is performed on the second active region R2 to form a doped region 162 of a second conductivity type in the region defined by the second portion 112b and the first portion 112a of the insulating pattern 112 in the well region 106. In this way, a second element buried in the substrate 100 and including the insulating pattern 112, the doped region 160b, and the doped region 162 can be formed in the second active region R2. In some embodiments, as Figure 11 shown, the doped regions 162 may be formed to extend in a first direction (e.g., the vertical direction) and be spaced apart from each other in a second direction (e.g., the horizontal direction). In some embodiments, the first direction may be perpendicular to the second direction. In some embodiments, the doped region 160b may be formed to surround the insulating pattern 112 and have a different conductivity type from the doped region 162.
[0086] Then, silicide layers 170 are formed in the doped regions 160a, the doped regions 160b, and the doped region 162 through a self-aligned silicide process. In some embodiments, the second element may further include silicide layers 170 formed in the doped region 160b and the doped region 162. The silicide layers 170 may include tungsten silicide, titanium silicide, cobalt silicide, zirconium silicide, platinum silicide, molybdenum silicide, copper silicide, nickel silicide, or a combination thereof.
[0087] Then, referring to Figure 5 and Figure 6 , the hard mask layer HMP of the stacked structure STK is removed to form a sacrificial gate structure SGS. In the step of removing the hard mask layer HMP, a part of the spacer walls 150 located on the side surfaces of the hard mask layer HMP is also removed, so each of the sacrificial gate structures SGS includes a high-k dielectric layer 122, a capping layer 132, a sacrificial gate layer 142, and spacer walls 152.
[0088] After that, referring to Figure 6 and Figure 7, an etch stop material layer 180 and a dielectric material layer 190 are sequentially formed on a substrate 100. The etch stop material layer 180 can be conformally formed on the surface of the substrate 100 and the sacrificial gate structure SGS. The dielectric material layer 190 can cover the sacrificial gate structure SGS. The etch stop material layer 180 can include a material such as silicon nitride. The dielectric material layer 190 can include a dielectric material such as silicon oxide.
[0089] Then, please refer to Figure 7 and Figure 8 , and a planarization process such as CMP is performed on the dielectric material layer 190 and the etch stop material layer 180 to form a dielectric layer 192 and an etch stop layer 182. In the above-mentioned planarization process, the sacrificial gate structure SGS in the second active region R2 helps to prevent the dielectric material layer 190 formed above the second element (embedded in the second active region R2 of the substrate 100) from having a depression (dishing) after the CMP process. In this way, in the subsequent process of replacing the sacrificial gate layer 142 with a metal gate layer (such as the metal gate MG shown in Figure 10 ), the metal material will not remain in the depression generated by the CMP process, so as to avoid contamination caused by the peeling of the metal material from the depression in the subsequent process.
[0090] In some embodiments, a first dielectric structure including the dielectric layer 192 and the etch stop layer 182 is formed between the sacrificial gate structures SGS on the first part 112a and the second part 112b of the insulating pattern 112, and a second dielectric structure including the dielectric layer 192 and the etch stop layer 182 is formed between the sacrificial gate structures SGS on the second part 112b of the insulating pattern 112 and the element isolation structure 110. The first dielectric structure and the second dielectric structure are spaced apart from each other by the sacrificial gate structure SGS provided on the second part 112b of the insulating pattern 112. In some embodiments, the first dielectric structure covers the doped region 162, and the second dielectric structure covers the doped region 160b. In some embodiments, the dielectric layer 192 can be an interlayer dielectric layer (such as ILD0). In some embodiments, the etch stop layer 182 can be a contact etch stop layer (CESL).
[0091] After that, please refer to Figure 8 and Figure 9, the sacrificial gate layer 142 in the sacrificial gate structure SGS is removed, and a metal material layer MGL is filled into the space formed by removing the sacrificial gate layer 142. The metal material layer MGL is also formed on the first dielectric structure and the second dielectric structure. The metal material layer MGL may include tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), molybdenum (Mo), copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), zirconium (Zr), platinum (Pt), or other suitable materials.
[0092] Then, please refer to Figure 9 and Figure 10 , a planarization process such as CMP is performed on the metal material layer MGL to form a gate structure GS on the first active region R1 of the substrate 100, and a dummy gate structure DGS is formed on the second active region R2 of the substrate 100. The first element D1 may include the gate structure GS formed on the substrate 100. When the first element D1 is a MOSFET, the first element D1 can be operated by applying a voltage to the gate structure GS. The dummy gate structure DGS can be electrically floating. When the second element D2 is a shallow trench isolation well resistor (STI well resistor), the dummy gate structure DGS can be electrically isolated from the second element D2.
[0093] The dummy gate structure DGS may include a first pattern P1, a second pattern P2, and a third pattern P3. The first pattern P1 is formed on the first portion 112a of the insulating pattern 112. The second pattern P2 is formed on the second portion 112b of the insulating pattern 112. The third pattern P3 is formed on the element isolation structure 110. Each of the first pattern P1, the second pattern P2, and the third pattern P3 of the gate structure GS and the dummy gate structure DGS may include a high-k dielectric layer 122, a cap layer 132, a metal gate MG, and a spacer 152. In some embodiments, the metal gate MG of the gate structure GS and the metal gate MG of the dummy gate structure DGS are formed at the same horizontal height with respect to the substrate 100. In some embodiments, the manufacturing process of forming the metal gate MG of the gate structure GS and the dummy gate structure DGS includes at least two planarization processes such as CMP.
[0094] In some embodiments, please refer to Figure 10 and Figure 11, the above-mentioned first dielectric structure is formed between a first pattern P1 and a second pattern P2 of a dummy gate structure DGS above the insulating pattern 112. The first pattern P1 and the second pattern P2 can be spaced apart from each other by the first dielectric structure. The above-mentioned second dielectric structure is formed between a second pattern P2 and a third pattern P3 of the dummy gate structure DGS above the insulating pattern 112. The second pattern P2 and the third pattern P3 can be spaced apart from each other by the second dielectric structure.
[0095] In some embodiments, as Figure 11 shown, the first pattern P1 of the dummy gate structure DGS may include a plurality of elongated patterns arranged in a first direction (e.g., the vertical direction) and extending in a second direction (e.g., the horizontal direction). In some other embodiments, as Figure 12 shown, the first pattern P1' of the dummy gate structure DGS' may include a plurality of annular patterns. In some alternative embodiments, as Figure 13 shown, the first pattern P1'' of the dummy gate structure DGS'' may include a plurality of dot patterns. The dot patterns may be circular dot patterns or rectangular dot patterns, and the present invention is not limited thereto. In some embodiments, the second doped regions 162 of the second element extend in the first direction and are spaced apart from each other in the second direction.
[0096] Hereinafter, the semiconductor device 10 will be described by Figure 10 . The semiconductor device 10 can be formed by the method described above, but the present invention is not limited thereto.
[0097] Please refer to Figure 10, the semiconductor device 10 includes a substrate 100, a first element D1, a second element D2, and a dummy gate structure DGS. The substrate 100 includes a first active region R1 and a second active region R2 defined by element isolation structures 110. The first element D1 is disposed in the first active region R1 and includes a gate structure GS disposed on the substrate 100 and source / drain regions 160a in the first active region R1 on opposite sides of the gate structure GS. The second element D2 is disposed in the second active region R2 and includes an insulating pattern 112 buried in the substrate 100 and a first doped region 160b and a second doped region 162 in the substrate 100. The insulating pattern 112 includes a first portion 112a and a second portion 112b surrounding the first portion 112a. The second portion 112b and the element isolation structure 110 define a region in the second active region R2 where the first doped region 160b is formed. The second portion 112b and the first portion 112a define a region in the second active region R2 where the second doped region 162 is formed. The dummy gate structure DGS is disposed in the second active region R2 and includes a first pattern P1, a second pattern P2, and a third pattern P3. The first pattern P1 is disposed on the first portion 112a of the insulating pattern 112. The second pattern P2 is disposed on the second portion 112b of the insulating pattern 112. The third pattern P3 is disposed on the element isolation structure 110.
[0098] In some embodiments, the gate structure GS includes a first high-k layer 122, a first capping layer 132, and a first metal gate MG sequentially disposed on the substrate 100. The dummy gate structure DGS includes a second high-k layer 122, a second capping layer 132, and a second metal gate MG sequentially disposed on the substrate 100. The first metal gate MG of the gate structure GS and the second metal gate MG of the dummy gate structure DGS are disposed at the same horizontal height with respect to the substrate 100.
[0099] In some embodiments, the first pattern P1 of the dummy gate structure DGS includes a plurality of annular patterns (as Figure 12 shown), a plurality of dot patterns (as Figure 13 shown), or a plurality of elongated patterns arranged in a first direction (e.g., the vertical direction) and extending in a second direction (e.g., the horizontal direction) (as Figure 11 shown). In some embodiments, the second doped regions 162 of the second element D2 extend in the first direction and are spaced apart from each other in the second direction. In some embodiments, the first doped region 160b of the second element D2 surrounds the insulating pattern 112 and has a different conductivity type from the second doped region 162.
[0100] In some embodiments, the semiconductor device 10 further includes a first dielectric structure between a first pattern P1 and a second pattern P2 of a dummy gate structure DGS disposed above the insulating pattern 112, and a second dielectric structure between the second pattern P2 and a third pattern P3 of the dummy gate structure DGS disposed above the insulating pattern 112. The first dielectric structure and the second dielectric structure are spaced apart from each other. For example, the first dielectric structure and the second dielectric structure may be spaced apart from each other by the second pattern P2 of the dummy gate structure DGS. In some embodiments, the first dielectric structure covers the second doped region 162, and the second dielectric structure covers the first doped region 160b.
[0101] In some embodiments, the substrate 100 includes a first well region (e.g., well region 104b) having a first conductivity type disposed in the second active region R2, a second well region (e.g., well region 106) having a second conductivity type different from the first conductivity type disposed in the first well region, and a deep well region (e.g., deep well region 102b) having the second conductivity type disposed in the second active region R2 below the second well region. The first doped region 160b is disposed in the first well region, and the second doped region 162 is disposed in the second well region. In some embodiments, the second well region is disposed below the first portion 112a of the insulating pattern 112, the first doped region 160b has the first conductivity type (e.g., P-type), and the second doped region 162 has the second conductivity type (e.g., N-type). In some embodiments, the dummy gate structure DGS is electrically floating.
[0102] In summary, in the semiconductor device and the method of forming the semiconductor device in the above embodiments, the sacrificial gate structure in the second active region helps to prevent the dielectric material layer formed above the second element (embedded in the second active region of the substrate) from having a depression (dishing) after performing the CMP manufacturing process. In this way, in the subsequent manufacturing process of replacing the sacrificial gate layer with a metal gate layer, the metal material will not remain in the depression generated by the CMP manufacturing process, so as to avoid the pollution caused by the peeling of the metal material from the depression in the subsequent manufacturing process. That is to say, after the manufacturing process of replacing the sacrificial gate layer with a metal gate layer, the sacrificial gate structure in the second active region is formed into a dummy gate structure, and the dummy gate structure includes a first pattern on the first portion of the insulating pattern, a second pattern on the second portion of the insulating pattern, and a third pattern on the element isolation structure, and the insulating layer (e.g., the insulating layer including the first dielectric structure and the second dielectric structure) formed above the second element will not have a depression generated by the CMP manufacturing process, and there will be no unwanted metal material remaining therein.
Claims
1. A semiconductor device, comprising: A substrate including a first active region and a second active region defined by an element isolation structure; A first element disposed in the first active region and including a gate structure disposed on the substrate and source / drain regions in the first active region on opposite sides of the gate structure; A second element disposed in the second active region and including an insulating pattern buried in the substrate and a first doped region and a second doped region in the substrate, the insulating pattern including a first portion and a second portion surrounding the first portion, wherein the second portion and the element isolation structure define a region in the second active region where the first doped region is formed, and the second portion and the first portion define a region in the second active region where the second doped region is formed; And A dummy gate structure disposed in the second active region and including a first pattern, a second pattern, and a third pattern, the first pattern disposed on the first portion of the insulating pattern, the second pattern disposed on the second portion of the insulating pattern, and the third pattern disposed on the element isolation structure.
2. The semiconductor device according to claim 1, wherein the gate structure includes a first high-k layer, a first capping layer, and a first metal gate sequentially disposed on the substrate, the dummy gate structure includes a second high-k layer, a second capping layer, and a second metal gate sequentially disposed on the substrate, and The first metal gate and the second metal gate are disposed at the same horizontal height with respect to the substrate.
3. The semiconductor device according to claim 1, wherein the first pattern includes a plurality of annular patterns, a plurality of dot patterns, or a plurality of elongated patterns arranged in a first direction and extending in a second direction.
4. The semiconductor device according to claim 3, wherein the second doped regions of the second element extend in the first direction and are spaced apart from each other in the second direction.
5. The semiconductor device according to claim 4, wherein the first doped region of the second element surrounds the insulating pattern and has a different conductivity type from the second doped region.
6. The semiconductor device according to claim 1, further comprising: A first dielectric structure disposed between the first pattern and the second pattern of the dummy gate structure above the insulating pattern; And A second dielectric structure disposed between the second pattern and the third pattern of the dummy gate structure above the insulating pattern, Wherein the first dielectric structure and the second dielectric structure are spaced apart from each other.
7. The semiconductor device according to claim 6, wherein the first dielectric structure covers the second doped region, and the second dielectric structure covers the first doped region.
8. The semiconductor device according to claim 1, wherein the substrate includes: A first well region disposed in the second active region and having a first conductivity type; A second well region is disposed in the first well region and has a second conductivity type different from the first conductivity type, wherein the first doping region is disposed in the first well region, and the second doping region is disposed in the second well region; and a deep well region is disposed in the second active region below the second well region and has the second conductivity type, wherein the second well region is disposed under the first part of the insulating pattern, the first doping region has the first conductivity type, and the second doping region has the second conductivity type.
9. The semiconductor device according to claim 1, wherein the dummy gate structure is electrically floating.
10. A method of forming a semiconductor device, comprising: forming an element isolation structure in a substrate to define a first active region and a second active region; forming a first element in the first active region of the substrate, wherein the first element includes a gate structure formed on the substrate; forming a second element in the second active region of the substrate, the second element including an insulating pattern buried in the substrate and a first doping region and a second doping region formed in the substrate, wherein the insulating pattern includes a first part and a second part surrounding the first part, the second part and the element isolation structure define a region in the second active region where the first doping region is formed, and the second part and the first part define a region in the second active region where the second doping region is formed; and forming a dummy gate structure in the second active region of the substrate, wherein the dummy gate structure includes a first pattern, a second pattern, and a third pattern, the first pattern is formed on the first part of the insulating pattern, the second pattern is formed on the second part of the insulating pattern, and the third pattern is formed on the element isolation structure.
11. The method according to claim 10, wherein the gate structure includes a first high-k dielectric layer, a first capping layer, and a first metal gate sequentially formed on the substrate, the dummy gate structure includes a second high-k dielectric layer, a second capping layer, and a second metal gate sequentially formed on the substrate, and the first metal gate and the second metal gate are formed at the same horizontal height with respect to the substrate.
12. The method according to claim 11, wherein the manufacturing process of forming the first metal gate and the second metal gate includes a chemical mechanical polishing manufacturing process.
13. The method according to claim 10, wherein the second doping region of the second element is formed to extend in a first direction and be spaced apart from each other in a second direction.
14. The method according to claim 13, wherein the first doping region of the second element is formed to surround the insulating pattern and has a different conductivity type from the second doping region.
15. The method according to claim 10, further comprising: forming a first dielectric structure between the first pattern and the second pattern of the dummy gate structure above the insulating pattern; and A second dielectric structure is formed between the second pattern and the third pattern of the dummy gate structure above the insulating pattern, wherein the first dielectric structure and the second dielectric structure are spaced apart from each other.
16. The method according to claim 15, wherein the first dielectric structure covers the second doped region, and the second dielectric structure covers the first doped region.
17. The method according to claim 10, wherein the substrate comprises: a first well region formed in the second active region and having a first conductivity type; a second well region formed in the first well region and having a second conductivity type different from the first conductivity type, wherein the first doped region is formed in the first well region, and the second doped region is formed in the second well region; and a deep well region formed in the second active region below the second well region and having the second conductivity type, wherein the second well region is formed below the first portion of the insulating pattern, the first doped region has the first conductivity type, and the second doped region has the second conductivity type.
18. The method according to claim 11, wherein the dummy gate structure is electrically floating.