Semiconductor device including gate separation region

Abstract

A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; an interlayer insulating layer on the isolation region; a gate line structure overlapping the active region, the gate line structure on the isolation region and having end portions opposite to each other; and a gate separation region on the isolation region, the gate separation region being between opposite end portions of the gate line structure and between the interlayer insulating layers. The gate separation region comprises a gap filling layer and a buffer structure, the buffer structure comprises a buffer lining layer, and the buffer lining layer is located between the gap filling layer and the isolation region and located between the opposite ends of the gate line structure and the side surface of the gap filling layer. And the insulating layer is located between the interlayer insulating layer and the side surface of the gap filling layer.

Description

[0001] This application is a divisional application of a Chinese patent application (application number: 201910279488.9) titled "Semiconductor Device Including Gate Separation Region" with a filing date of April 8, 2019.

[0002] Cross-reference to Related Applications

[0003] Korean Patent Application No. 10-2018-0048632, titled "Semiconductor Device Including Gate Separation Region", filed with the Korean Intellectual Property Office on April 26, 2018, is hereby incorporated by reference in its entirety. Technical Field

[0004] Embodiments relate to a semiconductor device including a gate separation region. Background Art

[0005] Generally, as the trend of higher integration in semiconductor devices increases, the area occupied by transistors can be reduced. Therefore, as the size of transistors can be reduced, the process of forming components constituting the transistors (e.g., smaller-sized gates) becomes increasingly important. Summary of the Invention

[0006] Embodiments may be achieved by providing a semiconductor device including: an isolation region between active regions; an interlayer insulating layer on the isolation region; a gate line structure overlapping with the active regions, the gate line structure being located on the isolation region and having opposite ends; and a gate separation region on the isolation region, the gate separation region being located between the opposite ends of the gate line structure and between the interlayer insulating layers, wherein the gate separation region includes a gap-fill layer and a buffer structure, and the buffer structure includes a buffer liner located between the gap-fill layer and the isolation region, between the opposite ends of the gate line structure and the side surface of the gap-fill layer, and between the interlayer insulating layer and the side surface of the gap-fill layer.

[0007] An embodiment can be implemented by providing a semiconductor device including: a first active region and a second active region, the first active region and the second active region being located on a semiconductor substrate and spaced apart from each other; an isolation region on the semiconductor substrate, the isolation region including a region between the first active region and the second active region; a first gate line structure overlapping with the first active region and the isolation region; a second gate line structure overlapping with the second active region and the isolation region, the second gate line structure having a second end portion facing the first end portion of the first gate line structure above the isolation region; a spacer covering a side surface of the first gate line structure, the spacer extending in a longitudinal direction of the first gate line structure to cover a side surface of the second gate line structure; and a first gate separation region located between the first end portion of the first gate line structure and the second end portion of the second gate line structure, and between the spacers, wherein the first gate separation region includes a first gap filling layer and a first buffer structure, and a dielectric constant of the first buffer structure is less than a dielectric constant of the first gap filling layer; the spacer includes: a first spacer portion covering side surfaces of the first gate line structure and the second gate line structure; and a second spacer portion covering a side surface of the first gate separation region, and a thickness of each of the second spacer portions is less than a thickness of each of the first spacer portions.

[0008] An embodiment can be implemented by providing a semiconductor device including: a first active region and a second active region spaced apart from each other; an isolation region including a region between the first active region and the second active region; a first transistor including: a first channel region in the first active region; a first source / drain region located on two side surfaces of the first channel region and applying compressive stress or tensile stress to the first channel region; and a first gate line structure extending over the first channel region and above the isolation region; a second transistor including: a second channel region in the second active region; a second source / drain region located on two side surfaces of the second channel region and applying compressive stress or tensile stress to the second channel region; and a second gate line structure extending over the second channel region and above the isolation region; and a gate separation region on the isolation region and located between end portions of the first gate line structure and the second gate line structure, wherein the gate separation region includes a buffer structure and a gap filling layer; and wherein the buffer structure is formed of an insulating material having a dielectric constant lower than that of the gap filling layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Features will be apparent to those skilled in the art from a detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0010] Figure 1 Shows a perspective view of a semiconductor device according to an embodiment;

[0011] Figure 2 Shows a plan view of a semiconductor device according to an embodiment;

[0012] Figure 3 、 Figure 4A and Figure 4B respectively show cross-sectional views of exemplary examples of a semiconductor device according to an embodiment;

[0013] Figure 5 Shows a cross-sectional view of an example of a semiconductor device according to an embodiment;

[0014] Figures 6 to 18 respectively show cross-sectional views of various modified examples of a semiconductor device according to an embodiment;

[0015] Fig.19 Shows a plan view of a modified example of a semiconductor device according to an embodiment;

[0016] Fig. 20A and Fig. 20B respectively show cross-sectional views of modified examples of a semiconductor device according to an embodiment;

[0017] Figure 21 to Figure 27 respectively show cross-sectional views of various modified examples of a semiconductor device according to an embodiment;

[0018] Fig.28 Shows a cross-sectional view of a modified example of a semiconductor device according to an embodiment;

[0019] Fig.29 Shows a cross-sectional view of a modified example of a semiconductor device according to an embodiment;

[0020] Fig.30 Shows a view of a modified example of a semiconductor device according to an embodiment;

[0021] Fig.31 Shows a cross-sectional view of a modified example of a semiconductor device according to an embodiment;

[0022] Fig.32 Shows a view of a modified example of a semiconductor device according to an embodiment;

[0023] Fig.33 Shows a cross-sectional view of a modified example of a semiconductor device according to an embodiment; and

[0024] Figures 34 to 37B Shows a flowchart and views of stages in a method of forming a semiconductor device according to an embodiment. Detailed Description

[0025] First, reference Figure 1 will be made to an exemplary example of a semiconductor device according to an embodiment. Figure 1 A perspective view of a semiconductor device according to an embodiment is shown.

[0026] Reference Figure 1 , a semiconductor device 1 according to an exemplary embodiment may include a first circuit region C1.

[0027] A semiconductor device 1 according to an exemplary embodiment may include a semiconductor chip, a semiconductor package formed using a single semiconductor chip, a semiconductor package formed using two or more semiconductor chips, or an electronic device formed using such a semiconductor package. In one embodiment, the semiconductor device 1 may include: a first circuit region C1, in which transistors and the like are formed.

[0028] Next, reference will be made to Figures 2 to 4B describe an exemplary example of the semiconductor device 1 including the first circuit region C1. In Figures 2 to 4B , Figure 2 a plan view of the first circuit region C1 of the semiconductor device 1 described above is shown, Figure 3 showing a cross-sectional view of a region taken along line I-I' in Figure 2 , Figure 4A showing a cross-sectional view of a region taken along line IIa-IIa' in Figure 2 , and Figure 4B showing a cross-sectional view of a region taken along line IIb-IIb' in Figure 2 .

[0029] Reference Figure 2 , Figure 3 , Figure 4A and Figure 4B , a semiconductor substrate 3 may be provided. The semiconductor substrate 3 may be formed of a semiconductor material such as silicon.

[0030] An active region 9a and an active region 9b and an isolation region 6 may be on the semiconductor substrate 3.

[0031] The active region 9a and the active region 9b may include a first active region 9a and a second active region 9b. The first active region 9a may include a first lower active region 9a_1 and a first upper active region 9a_2 on the first lower active region 9a_1. The second active region 9b may include a second lower active region 9b_1 and a second upper active region 9b_2 on the second lower active region 9b_1.

[0032] The first lower active region 9a_1 and the second lower active region 9b_1 may protrude from the semiconductor substrate 3 in a vertical direction Z perpendicular to the semiconductor substrate 3 (e.g., perpendicular to the flat surface of the semiconductor substrate 3). The first upper active region 9a_2 may protrude from the first lower active region 9a_1 in the vertical direction Z and may be spaced apart from each other. The second upper active region 9b_2 may protrude from the second lower active region 9b_1 in the vertical direction Z and may be spaced apart from each other.

[0033] The isolation region 6 may include: a second isolation region 6b surrounding the side surfaces of the first lower active region 9a_1 and the second lower active region 9b_1 and defining the first lower active region 9a_1 and the second lower active region 9b_1; and a first isolation region 6a overlapping the first lower active region 9a_1 and the second lower active region 9b_1 and covering the side surfaces of the first upper active region 9a_2 on the first lower active region 9a_1 and the second upper active region 9b_2 on the second lower active region 9b_1. The isolation region 6 may include silicon oxide. The first upper active region 9a_2 and the second upper active region 9b_2 may protrude from the first lower active region 9a_1 and the second lower active region 9b_1 in the vertical direction Z and may extend through the first isolation region 6a. For example, the upper surfaces of the first upper active region 9a_2 and the second upper active region 9b_2 may be at a height higher than the upper surface of the first isolation region 6a (e.g., the upper surfaces of the first upper active region 9a_2 and the second upper active region 9b_2 may be farther from the semiconductor substrate 3 than the upper surface of the first isolation region 6a).

[0034] The gate line structures 63a and 63b may be respectively on the first active region 9a and the second active region 9b and the isolation region 6. The gate line structures 63a and 63b may include one or more first gate line structures 63a overlapping the first active region 9a and extending onto the isolation region 6, and one or more second gate line structures 63b overlapping the second active region 9b and extending onto the isolation region 6.

[0035] Referring to a plan view or a top view, the first upper active region 9a_2 and the second upper active region 9b_2 may be in a linear form extending in a first direction X, and the gate line structures 63a and 63b may be in a linear form extending in a second direction Y perpendicular to the first direction X. The first direction X and the second direction Y may be in a direction parallel to the horizontal portion (e.g., flat surface) of the semiconductor substrate 3. When viewed from the plan view or the top view, the first upper active region 9a_2 and the second upper active region 9b_2 may intersect the gate line structures 63a and 63b.

[0036] In the one or more first gate line structures 63a, when a plurality of first gate line structures 63a are provided, a part of the plurality of first gate line structures 63a may be a first dummy line structure 63d1 that partially overlaps with the active region 9a, and the remaining part of the plurality of first gate line structures 63a may overlap with and cross the first active region 9a.

[0037] In the one or more second gate line structures 63b, when a plurality of second gate line structures 63b are provided, a part of the plurality of second gate line structures 63b may be a second dummy line structure 63d2 that partially overlaps with the active region 9b, and the remaining part of the plurality of second gate line structures 63b may overlap with and cross the second active region 9b.

[0038] Each of the one or more first gate line structures 63a may include a first gate electrode line 69a and a first gate dielectric 66a that covers the lower surface of the first gate electrode line 69a and covers the side surface of the first gate electrode line 69a.

[0039] In one embodiment, each of the one or more first gate line structures 63a may include a first cover line 72a on the first gate electrode line 69a. The first cover line 72a may cover the upper surface of the first gate electrode line 69a and the upper end portion of the first gate dielectric 66a. The upper end portion of the first gate dielectric 66a may be below the first cover line 72a (e.g., closer to the semiconductor substrate 3 than the first cover line 72a).

[0040] Each of the one or more second gate line structures 63b may include a second gate electrode line 69b and a second gate dielectric 66b that covers the lower surface of the second gate electrode line 69b and covers the side surface of the second gate electrode line 69b.

[0041] In one embodiment, each of the one or more second gate line structures 63b may include a second cover line 72b on the second gate electrode line 69b. The second cover line 72b may cover the upper surface of the second gate electrode line 69b and the upper end portion of the second gate dielectric 66b.

[0042] The first gate dielectric 66a and the second gate dielectric 66b may include silicon oxide and / or a high-k dielectric having a dielectric constant higher than that of silicon oxide. The first gate electrode line 69a and the second gate electrode line 69b may be formed of any one or a combination of doped polysilicon, metal nitrides (e.g., TiN, TaN, WN, etc.), and metals (e.g., Ti, Ta, W, etc.).

[0043] Depending on the characteristics or types of transistors that can be formed on the first active region 9a and the second active region 9b, the first gate dielectric 66a and the second gate dielectric 66b can be formed of the same material with different thicknesses from each other, or of different materials from each other, and the first gate electrode line 69a and the second gate electrode line 69b can be formed of a conductive material having the same work function, or can be formed of conductive materials having different work functions from each other.

[0044] In one embodiment, the first capping line 72a and the second capping line 72b can be formed of the same material as each other. In one embodiment, the first capping line 72a and the second capping line 72b can be formed of silicon nitride or a silicon nitride-based insulating material. In one embodiment, the first capping line 72a and the second capping line 72b can be formed of a metallic material such as tungsten, which has a higher conductivity than that of a metal nitride, to improve the electrical characteristics of the semiconductor device.

[0045] For convenience or for better understanding of the following, one first gate line structure 63a crossing the first active region 9a in one or more first gate line structures 63a and one second gate line structure 63b crossing the second active region 9b in one or more second gate line structures 63b will be mainly described. In one embodiment, the semiconductor device can include a plurality of first gate line structures 63a crossing the first active region 9a in the one or more first gate line structures 63a and a plurality of second gate line structures 63b crossing the second active region 9b in the one or more second gate line structures 63b.

[0046] The first source / drain region 24a can be on the first active region 9a, and the second source / drain region 24b can be on the second active region 9b. The first source / drain region 24a can include a portion filling the first recessed region 21a in the first upper active region 9a_2 of the first active region 9a. The second source / drain region 24b can include a portion filling the second recessed region 21b in the second upper active region 9b_2 of the second active region 9b. For example, each first source / drain region 24a can have a strip shape on the first lower active region 9a_1 and cross the first upper active region 9a_2. Each second source / drain region 24b can have a strip shape on the second lower active region 9b_1 and cross the second upper active region 9b_2.

[0047] The first channel region CH1 may be formed in a first upper active region 9a_2 located between the first source / drain regions 24a, and the second channel region CH2 may be formed in a second upper active region 9b_2 located between the second source / drain regions 24b. The first gate line structure 63a crossing the first active region 9a may include a portion over the first channel region CH1, and the second gate line structure 63b crossing the second active region 9b may include a portion over the second channel region CH2. When the first gate line structure 63a crossing the first active region 9a is provided in plurality, the first channel region CH1 may be provided in plurality to correspond to the plurality of first gate line structures 63a. When the second gate line structure 63b crossing the second active region 9b is provided in plurality, the second channel region CH2 may be provided in plurality to correspond to the plurality of second gate line structures 63b.

[0048] In one embodiment, the first source / drain region 24a, the first channel region CH1 in the first upper active region 9a_2 between the first source / drain regions 24a, the first gate dielectric 66a over the first channel region CH1, and the first gate electrode line 69a may constitute a first transistor TR1. The second source / drain region 24b, the second channel region CH2 in the second upper active region 9b_2 between the second source / drain regions 24b, the second gate dielectric 66b over the second channel region CH2, and the second gate electrode line 69b may constitute a second transistor TR2.

[0049] In one embodiment, the first transistor TR1 and the second transistor TR2 may be NMOS transistors or PMOS transistors. In one embodiment, the first transistor TR1 may be an NMOS transistor, and the second transistor TR2 may be a PMOS transistor.

[0050] In one embodiment, when the first transistor TR1 and the second transistor TR2 are NMOS transistors, the first source / drain region 24a and the second source / drain region 24b may have N-type conductivity and may be formed of a silicon epitaxial layer capable of imparting tensile stress to the first channel region CH1 and the second channel region CH2.

[0051] In one embodiment, when the first transistor TR1 and the second transistor TR2 are PMOS transistors, the first source / drain region 24a and the second source / drain region 24b may have P-type conductivity and may be formed of a silicon-germanium (SiGe) epitaxial layer capable of imparting compressive stress to the first channel region CH1 and the second channel region CH2.

[0052] In one embodiment, when the first transistor TR1 can be an NMOS transistor, the first source / drain region 24a can be formed of a silicon epitaxial layer capable of imparting tensile stress to the first channel region CH1. When the second transistor TR2 is a PMOS transistor, the second source / drain region 24b can be formed of a silicon-germanium (SiGe) epitaxial layer capable of applying compressive stress to the second channel region CH2.

[0053] As described above, the first gate line structure 63a can overlap with the first active region 9a and can extend onto the isolation region 6, and the second gate line structure 63b can overlap with the second active region 9b and can extend onto the isolation region 6. The first gate line structure 63a and the second gate line structure 63b can have ends that face each other on the isolation region 6 between the first active region 9a and the second active region 9b. For example, the first end 63e1 of the first gate line structure 63a can face the second end 63e2 of the second gate line structure 63b on the isolation region 6 between the first active region 9a and the second active region 9b.

[0054] The gate separation region 40 can be located on the isolation region 6 between the first active region 9a and the second active region 9b. In one embodiment, when the first gate line structure 63a is provided in plurality and the second gate line structure 63b is provided in plurality, the gate separation region 40 can be provided in plurality.

[0055] In one embodiment, the gate separation region 40 can have an upper surface coplanar with the upper surfaces of the first gate line structure 63a and the second gate line structure 63b. For example, the gate separation region 40 can have an upper surface coplanar with the upper surfaces of the first covering line 72a and the second covering line 72b of the first gate line structure 63a and the second gate line structure 63b.

[0056] In one embodiment, the gate separation region 40 can impart tensile stress to the first channel region CH1 and the second channel region CH2 to help improve the performance of the first transistor TR1 and the second transistor TR2.

[0057] The spacer 18 can be on the side surfaces of the first gate line structure 63a and the second gate line structure 63b and can extend onto the side surface of the gate separation region 40. Thus, the first gate line structure 63a, the second gate line structure 63b, and the gate separation region 40 can be between adjacent spacers 18. Referring to a plan view or a top view, the spacer 18 can be in a linear form extending in the second direction Y. The spacer 18 can be formed of an insulating material. For example, the spacer 18 can be formed of an insulating material such as SiN, SiCN, SiOCN, etc.

[0058] The spacer 18 may include a first spacer portion 18a covering the side surfaces of the first gate line structure 63a and the second gate line structure 63b, and a second spacer portion 18b covering the side surface of the gate separation region 40. In one embodiment, the width of the first spacer portion 18a may be wider than the width of the second spacer portion 18b. For example, the second spacer portion 18b may be narrower than the first spacer portion 18a.

[0059] The first gate dielectric 66a may cover the lower surface of the first gate electrode line 69a, may extend between the first gate electrode line 69a and the spacer 18, and may extend between the first gate electrode line 69a and the gate separation region 40. The second gate dielectric 66b may cover the lower surface of the second gate electrode line 69b, may extend between the second gate electrode line 69b and the spacer 18, and may extend between the second gate electrode line 69b and the gate separation region 40.

[0060] The interlayer insulating layer 27 may be located on the second isolation region 6b of the isolation region 6. On the second isolation region 6b, the spacer 18 may be formed between the gate line structures 63a and 63b and the interlayer insulating layer 27, and between the gate separation region 40 and the interlayer insulating layer 27.

[0061] The interlayer insulating layer 27 may be formed as a single layer that may be formed of silicon oxide, or may be formed as a stacked structure including silicon oxide and silicon nitride stacked in sequence. The first contact structure 78a may be on the first source / drain region 24a, and the second contact structure 78b may be on the second source / drain region 24b.

[0062] The first cover line 72a, the second cover line 72b, the spacer 18, and the gap fill layer 52 of the gate separation region 40 may serve as an etch mask in the etching process for forming the first contact structure 78a and the second contact structure 78b. Accordingly, the first contact structure 78a and the second contact structure 78b may be formed by a self-aligned contact process.

[0063] Reference will be made Figure 5 to the exemplary example of the gate separation region 40 described above with reference Figures 2 to 4B to. Figure 5 Cross-sectional views of regions taken along lines IIIa-IIIa' and IVa-IVa' in Figure 2 are shown.

[0064] Referring Figure 5 together with Figures 2 to 4B , the gate separation region 40 may be a gate separation region 40a including a gap fill layer 52 and a buffer structure. The buffer structure may include a buffer liner 46 covering the bottom surface and the side surfaces of the gap fill layer 52.

[0065] In a first direction X (i.e., in the width direction X of the first gate line structure 63a and the second gate line structure 63b), the width of each of the first gate line structure 63a and the second gate line structure 63b can be narrower than the width of the gate separation region 40.

[0066] The buffer layer 46 of the buffer structure can be located between the gap filling layer 52 and the isolation region 6, between the gap filling layer 52 and the second spacer portion 18b of the spacer 18, between the gap filling layer 52 and the first end portion 63e1 of the first gate line structure 63a, and between the gap filling layer 52 and the second end portion 63e2 of the second gate line structure 63b.

[0067] In one embodiment, the gate separation region 40a can further include a lower insulating layer 12a between the buffer layer 46 and the isolation region 6.

[0068] The buffer layer 46 can be formed of an insulating material having a dielectric constant higher than that of silicon oxide and lower than that of silicon nitride. In the case where the isolation region 6 includes silicon oxide, the dielectric constant of the buffer layer 46 can be higher than that of the silicon oxide of the isolation region 6. The dielectric constant of the buffer layer 46 can be higher than the dielectric constant of the lower insulating layer 12a. The gap filling layer 52 can be formed of an insulating material having a dielectric constant higher than that of the insulating material of the buffer layer 46.

[0069] The buffer layer 46 can be formed of an insulating material having a dielectric constant between about 4 and about 5. The gap filling layer 52 can be formed of an insulating material having a dielectric constant higher than that of the buffer layer 46 (e.g., an insulating material having a dielectric constant of about 5 or greater). For example, the buffer layer 46 can be formed of an insulating material such as SiOCN, SiON, etc., and the gap filling layer 52 can be formed of an insulating material such as SiN.

[0070] Reference will be made to Figure 6 the modified embodiment of the gate separation region 40 described above with reference to Figures 2 to 4B the description above. Figure 6 A cross-sectional view of the region represented by the line IIIa-IIIa' in Figure 2 is shown.

[0071] In the modified embodiment, and with reference to Figure 6 together with Figures 2 to 4B, between the second spacer portions 18b of the spacer 18, the gate separation region 40 can be a gate separation region 40b that can be between the second spacer portions 18b and can extend into the isolation region 6. The gate separation region 40b can include a gap-fill layer 52 and a buffer structure, and a buffer liner 46 of the buffer structure covers the bottom surface and side surfaces of the gap-fill layer 52. The lower surface of the gate separation region 40b can be below the lower surface of the spacer 18.

[0072] Reference will be made to Figure 7 to describe another modified embodiment of the gate separation region 40 described above with reference to Figures 2 to 4B described. Figure 7 FIG. Figure 2 shows a cross-sectional view of the region represented by line IIIa-IIIa' in

[0073] In another modified embodiment, and with reference to Figure 7 together with Figures 2 to 4B , between the second spacer portions 18b of the spacer 18, the gate separation region 40 can be a gate separation region 40c that can be between the second spacer portions 18b and can extend into the isolation region 6, and the width of the lower portion thereof can be greater than the width of the upper portion. The gate separation region 40c can include a gap-fill layer 52 and a buffer structure, and a buffer liner 46 of the buffer structure covers the bottom surface and side surfaces of the gap-fill layer 52. The lower surface of the gate separation region 40c can be below the lower surface of the spacer 18.

[0074] Reference will be made to Figure 8 to describe another modified embodiment of the gate separation region 40 described above with reference to Figures 2 to 4B described. Figure 8 FIG. Figure 2 shows a cross-sectional view of the region represented by line IVa-IVa' in

[0075] In another modified embodiment, and with reference to Figure 8 together with Figures 2 to 4B , between the first end portion 63e1 and the second end portion 63e2 that face each other in the first gate line structure 63a and the second gate line structure 63b, the gate separation region 40 can be a gate separation region 40d that can be located between the first end portion 63e1 and the second end portion 63e2 and can extend into the isolation region 6. The gate separation region 40d can include a gap-fill layer 52 and a buffer structure, and a buffer liner 46 of the buffer structure covers the bottom surface and side surfaces of the gap-fill layer 52. The lower surface of the gate separation region 40d can be below the lower surfaces of the first gate line structure 63a and the second gate line structure 63b.

[0076] Reference will be made to Fig. 9 to describe another modified embodiment of the gate separation region 40 described above with reference to Figures 2 to 4BAnother modified embodiment of the described gate separation region 40. Fig. 9 A cross-sectional view of the region indicated by line IVa-IVa' in Figure 2 is shown.

[0077] In another modified embodiment, and with reference to Fig. 9 along with Figures 2 to 4B , between the first end 63e1 and the second end 63e2 that face each other in the first gate line structure 63a and the second gate line structure 63b, the gate separation region 40 can be a gate separation region 40e that can be located between the first end 63e1 and the second end 63e2, can extend into the isolation region 6, and the width of its lower portion can be greater than the width of its upper portion. The gate separation region 40e can include a gap-fill layer 52 and a buffer structure, and a buffer liner 46 of the buffer structure covers the bottom surface and the side surface of the gap-fill layer 52.

[0078] In Figures 6 to 9 , the buffer liner 46 and the gap-fill layer 52 described with the same reference numerals can be formed of the same materials as the buffer liner 46 and the gap-fill layer 52 described in Figure 5 . In one embodiment, the following components represented by the same reference numerals as the above components can be formed of the same materials as the above materials. Therefore, with reference to the components described with the same reference numerals, the description of the components repeatedly referred to after the description of the first-mentioned components can be understood based on the first-mentioned components, and thus can be omitted.

[0079] Reference will be made to Fig.10 to describe another modified embodiment of the gate separation region 40 described above with reference to Figures 2 to 4B . Fig.10 A cross-sectional view of the regions indicated by lines IIIa-IIIa' and IVa-IVa' in Figure 2 is shown respectively.

[0080] In another modified embodiment, and with reference to Fig.10 along with Figures 2 to 4B , the gate separation region 40 can be a gate separation region 40f that includes a buffer structure and a gap-fill layer 152 on the buffer structure. The buffer structure can include a lower buffer layer 150.

[0081] In one embodiment, the gate separation region 40f can further include a lower insulating layer 12a between the lower buffer layer 150 and the isolation region 6.

[0082] The lower buffer layer 150 may be formed of an insulating material having better gap filling characteristics and a dielectric constant lower than that of the gap filling layer 152. For example, the gap filling layer 152 may be formed of an insulating material such as silicon nitride, and the lower buffer layer 150 may be formed of an insulating material such as silicon oxide. The lower insulating layer 12a may be formed using a flowable oxide.

[0083] Reference will be made to Fig.11 describe another modified embodiment of the gate isolation region 40 described above with reference to Figures 2 to 4B described. Fig.11 FIGS. show cross-sectional views of regions respectively represented by Figure 2 lines IIIa-IIIa' and IVa-IVa' in

[0084] In another modified embodiment and with reference to Fig.11 together with Figures 2 to 4B , the gate isolation region 40 may be a gate isolation region 40g including a buffer structure including a lower buffer layer 150 and a buffer liner 146 and a gap filling layer 152.

[0085] The lower buffer layer 150 and the gap filling layer 152 may be stacked in sequence. The buffer liner 146 may be located between the lower buffer layer 150 and the isolation region 6, between the side surface of the lower buffer layer 150 and the interlayer insulating layer 27, between the side surface of the lower buffer layer 150 and the ends 63e1 of the first gate line structure 63a and the ends 63e2 of the second gate line structure 63b, between the side surface of the gap filling layer 152 and the interlayer insulating layer 27, and between the side surface of the gap filling layer 152 and the ends 63e1 of the first gate line structure 63a and the ends 63e2 of the second gate line structure 63b.

[0086] The buffer liner 146 may be formed of an insulating material having a dielectric constant lower than that of the gap filling layer 152 and higher than that of the lower buffer layer 150. For example, the lower buffer layer 150 may be formed of silicon oxide or a silicon oxide-based insulating material, the gap filling layer 152 may be formed of silicon nitride, and the buffer liner 146 may be formed of an insulating material having a dielectric constant of about 4 to about 5 (e.g., an insulating material such as SiOCN, SiON, etc.).

[0087] In one embodiment, the gate isolation region 40g may further include a lower insulating layer 12a between the lower buffer layer 150 and the isolation region 6.

[0088] Reference will be made to Fig.12 describe another modified embodiment of the gate isolation region 40 described above with reference to Figures 2 to 4B described. Fig.12 FIGS. show cross-sectional views of regions respectively represented by Figure 2Cross-sectional view of the regions represented by lines IIIa-IIIa' and IVa-IVa' in

[0089] In another modified embodiment and with reference to Fig.12 Together with Figures 2 to 4B , the gate isolation region 40 can be a gate isolation region 40h including a lower buffer layer 150, a gap-fill layer 152 on the lower buffer layer 150, and a buffer liner 146' between the buffer layer 150 and the gap-fill layer 152 and between the side surfaces of the gap-fill layer 152 and the second spacer portion 18b. The lower buffer layer 150 and the buffer liner 146' can form a buffer structure.

[0090] In one embodiment, the gate isolation region 40h can further include a lower insulating layer 12a between the lower buffer layer 150 and the isolation region 6.

[0091] Reference will be made respectively to Fig.13 , Fig.14 and Fig.15 to describe various modified examples of the gate isolation region 40 described above with reference to Figures 2 to 4B described. Fig.13 , Fig.14 and Fig.15 respectively show cross-sectional views of the regions represented by the line IIIa-IIIa' in Figure 2

[0092] In another modified embodiment and with reference respectively to Fig.13 , Fig.14 and Fig.15 Together with Figures 2 to 4B , between the second spacer portions 18b of the spacer 18, the gate isolation region 40 can be a gate isolation region ( Fig.13 40i in Fig.14 40j in Fig.15 40k in

[0093] In another modified embodiment, with reference to Fig.13 ​, the gate isolation region 40i may include a lower buffer layer 150 and a gap-fill layer 152 stacked in sequence. The lower buffer layer 150 may constitute a buffer structure. The gate isolation region 40i may include a lower region and an upper region on the lower region. The width of the lower region may be greater than the width of the upper region. The buffer structure (i.e., the lower buffer layer 150) may be located on the upper surface of the gate isolation region 40i. The gap-fill layer 152 may be located in the upper region of the gate isolation region 40i. The lower buffer layer 150 may be formed of a material having good gap-fill characteristics (e.g., a flowable oxide), and the gate isolation region 40i may be formed without defects such as seams.

[0094] In another modified embodiment, referring to Fig.14 , the gate isolation region 40j may include a lower buffer layer 150 and a gap-fill layer 152 stacked in sequence, and a buffer liner layer 146' covering the bottom surface and side surfaces of the lower buffer layer 150 and the side surface of the gap-fill layer 152. The lower buffer layer 150 and the buffer liner layer 146' may constitute a buffer structure.

[0095] In another modified embodiment, referring to Fig.15 , the gate isolation region 40k may include a lower buffer layer 150 and a gap-fill layer 152 stacked in sequence, and a buffer liner layer 146' covering the side surface of the gap-fill layer 152 and located between the gap-fill layer 152 and the lower buffer layer 150. The lower buffer layer 150 and the buffer liner layer 146' may constitute a buffer structure.

[0096] Reference will be made respectively to Fig.16 、 Fig.17 and Fig.18 to describe various modified examples of the gate isolation region 40 described above with reference to Figures 2 to 4B . Fig.16 、 Fig.17 and Fig.18 respectively show cross-sectional views of the regions represented by the line IVa-IVa' in Figure 2 .

[0097] In another modified embodiment, and referring to Fig.16 、 Fig.17 and Fig.18 together with Figures 2 to 4B , between the first end portion 63e1 and the second end portion 63e2 facing each other in the first gate line structure 63a and the second gate line structure 63b, the gate isolation region 40 may be a gate isolation region capable of being located between the first end portion 63e1 and the second end portion 63e2, extending into the isolation region 6, and having a width of the lower portion greater than the width of the upper portion ( Fig.16 401 in Fig.17 40m in Fig.18of 40n).

[0098] In another modified embodiment, referring to Fig.16 , the gate isolation region 40l may include a buffer structure including a lower buffer layer 150 and a gap-fill layer 152 stacked on the buffer structure.

[0099] In another modified embodiment, referring to Fig.17 , the gate isolation region 40m may include a lower buffer layer 150 and a gap-fill layer 152 stacked in sequence, and a buffer liner 146 covering the bottom surface and side surfaces of the lower buffer layer 150 and the side surface of the gap-fill layer 152. The lower buffer layer 150 and the buffer liner 146 may constitute a buffer structure.

[0100] In another modified embodiment, referring to Fig.18 , the gate isolation region 40n may include a lower buffer layer 150 and a gap-fill layer 152 stacked in sequence, and a buffer liner 146' between the gap-fill layer 152 and the lower buffer layer 150 and covering the side surface of the gap-fill layer 152. The lower buffer layer 150 and the buffer liner 146' may constitute a buffer structure.

[0101] Next, referring to Fig.19 the modified embodiments of the above-described gate isolation region 40 and spacer 18 will be described. Fig.19 FIG. shows a plan view of an example of a first circuit region C1 of a semiconductor device ( Figure 1 in 1) according to an embodiment including another modified embodiment of the above-described gate isolation region 40. Modified examples of the above-described gate isolation region 40 and the above-described spacer 18 will be mainly described. Components other than the gate isolation region 40 and the spacer 18 will be substantially the same as the components described with reference to Figures 2 to 4B Therefore, some components may be omitted from the following description, and some components will be directly referred to.

[0102] Referring to Fig.19 , the same active regions 9a and 9b and a first gate line structure 63a and a second gate line structure 63b as those described with reference to Figures 2 to 4B may be provided.

[0103] The gate isolation region 240 may be between the first gate line structure 63a and the second gate line structure 63b. The spacer 18' may also cover a part of the side surface of each gate isolation region 240, and may cover the side surfaces of the first gate line structure 63a and the second gate line structure 63b. The extension portion 253 may extend from at least a part of the gate isolation region 240 in the first direction X. The first direction X may be the longitudinal direction of the first upper active region 9a_2 and the second upper active region 9b_2, and the width direction of the first gate line structure 63a and the second gate line structure 63b, as in reference Figures 2 to 4B as described above

[0104] Reference will be made to Fig. 20A and Fig. 20B to describe various examples of the gate separation region 240 and the spacer 18'. Fig. 20A A cross-sectional view of a region taken along line IIIb-IIIb' and line IVb-IVb' in Fig.19 is shown, and Fig. 20B A cross-sectional view of a region taken along line IV-IV' in Fig.19 is shown.

[0105] Reference Fig. 20A and Fig. 20B together with Fig.19 , the gate separation region 240 may be a gate separation region 240a between the first end portion 63e1 of the first gate line structure 63a and the second end portion 63e2 of the second gate line structure 63b and including an extension portion 253 connected to each other.

[0106] Each gate separation region 240a may include a gap-fill layer 252, a buffer liner 246 covering the bottom surface and side surfaces of the gap-fill layer 252 and extending onto the lower surface of the extension portion 253, and a lower insulating layer 12a located between the buffer liner 246 and the isolation region 6. The extension portion 253 may extend from an upper region of the gap-fill layer 252 in a first direction X (e.g., in the width direction of the first gate line structure 63a and the second gate line structure 63b) to integrally form the gap-fill layer 252. The buffer liner 246 may be a buffer structure.

[0107] The spacer 18' may include a first spacer portion 18a' covering the side surfaces of the first gate line structure 63a and the second gate line structure 63b, and a second spacer portion 18b' extending from the first spacer portion 18a' and connected to the first spacer portion 18a'. The thickness of each second spacer portion 18b' may be less than the thickness of each first spacer portion 18a'. The position of the upper surface of the second spacer portion 18b' may be lower than the position of the upper surface of the first spacer portion 18a' (e.g., closer to the semiconductor substrate 3 compared to the upper surface of the first spacer portion 18a').

[0108] The interlayer insulating layer 27 may be located on the second isolation region 6b of the isolation region 6. On the second isolation region 6b, the spacer 18' may be located between the gate line structures 63a and 63b and the interlayer insulating layer 27, and between the gate separation region 240 and the interlayer insulating layer 27.

[0109] The extension portion 253 may extend from the upper region of the gap-fill layer 252 in the first direction X and may cover the second spacer portion 18b' and the interlayer insulating layer 27. Accordingly, the extension portion 253 may overlap with the second spacer portion 18b' and the interlayer insulating layer 27.

[0110] Reference will be made respectively Fig.21 、 Fig. 22 and Fig.23 to describe various modified examples of the gate separation region 240. Fig.21 、 Fig. 22 and Fig.23 show cross-sectional views of regions taken along lines IIIb-IIIb' and IVb-IVb' in Fig.19 .

[0111] Referring to Fig.21 、 Fig. 22 and Fig.23 each together with Fig.19 , the gate separation region 240 may be a gate separation region that may include a lower buffer layer 250 and a gap-fill layer 252' stacked in sequence, and an extension portion 253 connected to the upper region of the gap-fill layer 252' and extending in the first direction X ( Fig.21 240b in Fig. 22 240c in Fig.23 240d in

[0112] In a modified embodiment, referring to Fig.21 , each gate separation region 240b may further include a lower insulating layer 12a between the lower buffer layer 250 and the isolation region 6. The lower buffer layer 250 may be a buffer structure.

[0113] In a modified embodiment, referring to Fig. 22 , each gate separation region 240c may further include: a buffer liner 246 covering the lower surface and the side surfaces of the lower buffer layer 250, covering the side surfaces of the gap-fill layer 252' and extending to the lower surface of the extension portion 253. Each gate separation region 240c may further include a lower insulating layer 12a between the buffer liner 246 and the isolation region 6. The buffer liner 246 and the lower buffer layer 250 may constitute a buffer structure.

[0114] In a modified embodiment, referring to Fig.23, each gate separation region 240d may further include: a buffer layer 246', between the lower surface of the gap-fill layer 252' and the lower buffer layer 250, covering the side surface of the gap-fill layer 252', and extending onto the lower surface of the extension portion 253. The lower buffer layer 250 and the buffer layer 246' may constitute a buffer structure. Each gate separation region 240d may further include a lower insulating layer 12a between the lower buffer layer 250 and the isolation region 6.

[0115] Reference will be made respectively to Fig.24 , Fig.25 , Fig.26 and Fig. 27 to describe various modified examples of the gate separation region 240. Fig.24 , Fig.25 , Fig.26 and Fig. 27 respectively show cross-sectional views of the regions taken along the line IIIb-IIIb' in Fig.19 .

[0116] Reference is made respectively to Fig.24 , Fig.25 , Fig.26 and Fig. 27 Together with Fig.19 , between the second spacer portions 18b of the spacers 18, the gate separation region 240 may be a gate separation region that can be located between the second spacer portions 18b, can extend into the isolation region 6, and the width of its lower portion may be greater than the width of its upper portion ( Fig.24 240e in Fig.25 240f in Fig.26 240g in Fig. 27 240h in

[0117] In a modified embodiment, referring to Fig.24 , each gate separation region 240e may include a gap-fill layer 252, an extension portion 253 connected to the upper region of the gap-fill layer 252, and a buffer layer 246 covering the bottom surface and the side surface of the gap-fill layer 252 and extending between the extension portion 253 and the interlayer insulating layer 27. The buffer layer 246 may be a buffer structure.

[0118] In a modified embodiment, referring to Fig.25 , each gate separation region 240f may include a lower buffer layer 250 and a gap-fill layer 252' stacked in sequence, and an extension portion 253 connected to the upper region of the gap-fill layer 252' and extending in the first direction X. The lower buffer layer 250 may be a buffer structure.

[0119] In a modified embodiment, referring to Fig.26, each gate isolation region 240g may include a lower buffer layer 250 and a gap filling layer 252' stacked in sequence, and a buffer liner 246. The buffer liner 246 covers the lower surface and side surfaces of the lower buffer layer 250, covers the side surfaces of the gap filling layer 252' and extends onto the lower surface of the extension portion 253. The lower buffer layer 250 and the buffer liner 246 may form a buffer structure.

[0120] In a modified embodiment, referring to Fig. 27 , each gate isolation region 240h may include a lower buffer layer 250 and a gap filling layer 252' stacked in sequence, and a buffer liner 246'. The buffer liner 246' is between the lower surface of the gap filling layer 252' and the lower buffer layer 250, covers the side surfaces of the gap filling layer 252' and extends onto the lower surface of the extension portion 253. The lower buffer layer 250 and the buffer liner 246' may form a buffer structure.

[0121] In the components described with reference to Figures 1 to 27 , the "buffer liners" denoted by the same reference numerals or various reference numerals may be formed of the same material as each other. The "gap filling layers" denoted by the same reference numerals or various reference numerals may be formed of the same material as each other. The "lower buffer layers" denoted by the same reference numerals or various reference numerals may be formed of the same material as each other. For example, referring to Figure 5 the buffer liner 46 described, referring to Fig.11 the buffer liner 146 described, referring to Fig.12 the buffer liner 146' described, referring to Fig. 20A the buffer liner 246 described, and referring to Fig. 20B the buffer liner 246 described may be formed of the same material. Referring to Figure 5 the gap filling layer 52 described, referring to Fig.11 the gap filling layer 152 described, and referring to Fig. 20A the gap filling layer 252 described may be formed of the same material as each other.

[0122] Next, a modified embodiment of the active regions 9a and 9b described above with reference to Fig.28 will be described with reference to Figures 2 to 27 .

[0123] In a modified embodiment, referring to Fig.28 , the gate isolation regions 40 and 240 may be disposed between the first gate line structure 63a and the second gate line structure 63b, and between the opposite ends 63e1 and 63e2 of the first gate line structure 63a and the second gate line structure 63b, the same as described above with reference to Figures 2 to 27 .

[0124] The first active region 9a' may include a first lower active region 9a_1, a first upper active region 9a_2 protruding from the first lower active region 9a_1 in the vertical direction Z, and a first floating active region 9a_3 on an upper portion of the first upper active region 9a_2 and spaced apart from the first upper active region 9a_2. The second active region 9b' may include a second lower active region 9b_1, a second upper active region 9b_2 protruding from the second lower active region 9b_1 in the vertical direction Z, and a second floating active region 9b_3 on an upper portion of the active region 9b_2 and spaced apart from the second upper active region 9b_2. The first floating active region 9a_3 may be surrounded by a first gate line structure 63a, and the second floating active region 9b_3 may be surrounded by a second gate line structure 63b.

[0125] Next, referring to Fig.29 , reference will be made to Figures 2 to 27 to describe a modified example of the first gate line structure 63a and the second gate line structure 63b.

[0126] In a modified embodiment, referring to Fig.29 , each first gate line structure 63a' may include a first gate electrode line 69a and a first gate dielectric 66a that covers a lower surface of the first gate electrode line 69a and covers a side surface of the first gate electrode line 69a. Each second gate line structure 63b' may include a second gate electrode line 69b and a second gate dielectric 66b that covers a lower surface of the second gate electrode line 69b and covers a side surface of the second gate electrode line 69b. Thus, in the modified embodiment, upper surfaces of the first gate electrode line 69a and the second gate electrode line 69b may be coplanar with upper surfaces of the gate isolation regions 40 and 240 described above with reference to Figures 1 to 27 .

[0127] As described above with reference to Figures 1 to 29 , the semiconductor device 1 according to an embodiment may include the above-described first circuit region C1. In one embodiment, the semiconductor device 1 may include other circuit regions together with the above-described first circuit region C1. Exemplary examples of the semiconductor device 1 including a second circuit region C2 together with the above-described first circuit region C1 will now be described with reference to Fig.30 and Fig.31 , and exemplary examples of the semiconductor device 1 including a third circuit region C3 together with the above-described first circuit region C1 will be described with reference to Fig.32 and Fig.33 .

[0128] Hereinafter, the semiconductor device 1 of the exemplary examples described with reference to Fig.30 and Fig.31 as well as Fig.32 and Fig.33 may include a second circuit region ( Fig.30in C2) or the third circuit region ( Fig.32 in C3) together with the first circuit region C1 described above with reference to Figures 1 to 29 Description of the first circuit region C1. In this case, the description of the first circuit region C1 (for example, the components constituting the first circuit region C1 and various modified examples thereof) described with reference to Figures 1 to 29 can be omitted. Among the components constituting the first circuit region C1 described with reference to Figures 1 to 29 , components that will be applied to the second circuit region ( Fig.30 in C2) or the third circuit region ( Fig.32 in C3) in the same manner can be omitted, or these components can be directly referred to, but the detailed description of the components can be omitted.

[0129] First, with reference to Fig.30 and Fig.31 , an exemplary example of the semiconductor device 1 including the second circuit region C2 together with the first circuit region C1 described above with reference to Figures 1 to 29 will be described. Fig.30 FIG. shows a perspective view of the semiconductor device 1 according to an embodiment and a plan view of an enlarged portion of the perspective view. Fig.31 FIG. shows cross-sectional views of regions taken along lines VI-VI' and VII-VII' in Fig.30 respectively.

[0130] With reference to Fig.30 and Fig.31 together with Figures 1 to 29 , the semiconductor device 1 according to an embodiment may include the second circuit region C2 together with the first circuit region C1 described with reference to Figures 1 to 29 .

[0131] The second circuit region C2 may include a third active region 109 corresponding to the first active region 9a and the second active region 9b of the first circuit region C1. Therefore, among the third active regions 109 adjacent to each other, one of the third active regions 109 may have the same structure as the first active region 9a, and the other of the third active regions 109 may have the same structure as the second active region 9b. For example, each third active region 109 may include a third lower active region 109_1 having the same structure as the first lower active region 9a_1 and a third upper active region 109_2 having the same structure as the first upper active region 9a_2. In one embodiment, the third active region 109 may be defined by an isolation region 6 including a first isolation region 6a and a second isolation region 6b in the same manner as the first active region 9a and the second active region 9b. The second circuit region C2 may include: a third source / drain region 124, which may correspond to the first source / drain region 24a and the second source / drain region 24b of the first circuit region C1.

[0132] The second circuit region C2 may include: a third gate line structure 163, which may correspond to the first gate line structure 63a and the second gate line structure 63b of the first circuit region C1. For example, each third gate line structure 163 may include a third gate electrode line 169 and a third gate dielectric 166, and the third gate dielectric 166 covers the lower surface and the side surface of the third gate electrode line 169. In one embodiment, each third gate line structure 163 may include a third cover line 172, and the third cover line 172 covers the upper surface of the third gate electrode line 169 and the upper end portion of the third gate dielectric 166. The third cover line 172 may be formed of the same material as the first cover line 72a and the second cover line 72b. The second circuit region C2 may include a gate separation region 340 between opposite ends 163e of the third gate line structure 163 on the second isolation region 6b. For the sake of clearly distinguishing components, the gate separation regions 40 and 240 in the first circuit region C1 will be referred to as the first gate separation regions 40 and 240, and the gate separation region 340 in the second circuit region C2 will be referred to as the second gate separation region 340.

[0133] The second circuit region C2 may include spacers 18 corresponding to the spacers 18 of the first circuit region C1. Thus, in the same manner as in the first circuit region C1, the spacers 18 may include a first spacer portion 18a covering the side surface of the third gate line structure 163 and a second spacer portion 18b covering the side surface of the second gate separation region 340.

[0134] The second gate separation region 340 may have a different structure from the first gate separation regions 40 and 240. For example, the second gate separation region 340 may be formed of a gap filling layer 352 that fills between opposite ends 163e in the third gate line structure 163 and between the second spacer portions 18b. The second gate separation region 340 may further include a lower insulating layer 12a between the gap filling layer 352 and the second isolation region 6b. The gap filling layer 352 may be formed of silicon nitride, and the lower insulating layer 12a may be formed of silicon oxide.

[0135] In one embodiment, when the transistors formed in the first circuit region C1 are PMOS transistors and the transistors formed in the second circuit region C2 are NMOS transistors, the first gate separation regions 40 and 240 and the second gate separation region 340 may jointly include a gap filling layer formed of an insulating material having a dielectric constant of about 5 or greater, and the first gate separation regions 40 and 240 may further include a buffer structure (e.g., the buffer liner 46 described before the description of the second gate separation region 340). As described above, the buffer liner 46 may be formed of an insulating material having a dielectric constant of about 4 to 5.

[0136] Next, referring to Fig.32 and Fig.33 , an exemplary example of the semiconductor device 1 including the third circuit region C3 together with the first circuit region C1 described above with reference to Figures 1 to 29 can be described. Fig.32 FIG. shows a plan view and a partial perspective view of the semiconductor device 1 according to an embodiment. Fig.33 FIG. shows cross-sectional views of regions taken along lines VIII-VIII' and IX-IX' in Fig.32 respectively.

[0137] Referring to Fig.32 and Fig.33 together with Figures 1 to 29 , the semiconductor device 1 according to an embodiment may include the third circuit region C3 together with the first circuit region C1 described above with reference to Figures 1 to 29 . In this case, the descriptions referring directly to and describing the exemplary examples of the first circuit region C1 with reference to Figure 6 and Figure 8 will be directly cited and described.

[0138] The third circuit region C3 may include a fourth active region 209. Each fourth active region 209 may include a fourth lower active region 209_1 and a fourth upper active region 209_2, and the fourth upper active region 209_2 protrudes from the fourth lower active region 209_1 in the upward direction Z. The fourth active region 209 may be defined by the isolation region 6 in the same manner as the first active region 9a and the second active region 9b of the first circuit region C1. The second isolation region 6b of the isolation region 6 may be located between the fourth lower active regions 209_1, and the first isolation region 6a of the isolation region 6 may be located on the fourth lower active regions 209_1. In this case, the fourth upper active region 209_2 may extend from the first lower active region 209_1 in the upward direction Z and may pass through the first isolation region 6a.

[0139] The third circuit region C3 may include: a fourth source / drain region 424, which may correspond to the first source / drain region 24a and the second source / drain region 24b of the first circuit region C1.

[0140] The third circuit region C3 may include a fourth gate line structure 463 having ends 463e opposite to each other on the second isolation region 6b of the isolation region 6 between the fourth active regions 209.

[0141] Each fourth gate line structure 463 may include a fourth gate electrode line 469 and a fourth gate dielectric 466. The fourth gate dielectric 466 covers the lower surface of the fourth gate electrode line 469 and covers the side surface of the fourth gate electrode line 469. In one embodiment, each fourth gate line structure 463 may include a fourth cover line 472. The fourth cover line 472 covers the upper surface of the fourth gate electrode line 469 and the upper end portion of the fourth gate dielectric 466. The fourth cover line 472 may be formed of the same material as the first cover line 72a and the second cover line 72b.

[0142] The third circuit region C3 may include a gate isolation region 440 between opposite end portions 463e of the fourth gate line structures 463 on the second isolation region 6b. The gate isolation regions 40 and 240 in the first circuit region C1 will be referred to as the first gate isolation regions 40 and 240, and the gate isolation region 440 in the third circuit region C3 will be referred to as the third gate isolation region 440.

[0143] The third circuit region C3 may include spacers 18 corresponding to the spacers 18 and 18' of the first circuit region C1. Thus, the spacer 18 may include a first spacer portion 18a covering the side surface of the fourth gate line structure 463 and a second spacer portion 18b covering the side surface of the third gate isolation region 440, as in the first circuit region C1.

[0144] Except for the dimensions, the third gate isolation region 440 may be substantially the same as the first gate isolation regions 40 and 240. For example, the lower surface of the third gate isolation region 440 may be at a lower height than the lower surfaces of the first gate isolation regions 40 and 240. The third gate isolation region 440 may have a greater width or a greater planar dimension (e.g., area) than the first gate isolation regions 40 and 240. For example, among the various examples of the first gate isolation regions 40 and 240 of the first circuit region C1 described with reference to Figures 1 to 29 when the first gate isolation regions 40 and 240 are the first gate isolation regions ( Figure 6 and Figure 8 described in Figure 6 40b and / or Figure 8 40d in Figure 6 ), the third gate isolation region 440 may include a buffer liner 446 and a gap fill layer 452. The buffer liner 446 may correspond to the buffer liner 46 in the first gate isolation region ( Figure 8 40b and / or Figure 6 40d in Figure 8 ), and the gap fill layer 452 may correspond to the gap fill layer 52 in the first gate isolation region (

[0145] The thickness of the portion of the buffer liner 446 of the third gate isolation region 440 between the gap fill layer 452 and the isolation region 6 in the third circuit region C3 may be thicker than that of the portion of the buffer liner 46 of the first gate isolation region ( Figure 6 40b in Figure 8 and / or Figure 6 40d in Figure 8 ), between the gap fill layer 52 and the isolation region 6 of the first gate isolation region (

[0146] Throughout the specification, terms such as "first", "second", "third", and "fourth" may be used to describe various components. These terms are only used for the purpose of distinguishing one component from another. For example, without departing from the scope of the inventive concept, a "third component" may be referred to as a "second component", and a "second component" may be referred to as a "third component". For example, the third circuit region C3 may be referred to as the second circuit region C2, and the second circuit region C2 may be referred to as the third circuit region C3.

[0147] Next, an exemplary example of a method of forming a semiconductor device according to an embodiment will be described.

[0148] Hereinafter, reference will be made to Figure 2 and Figures 34 to 37B to describe various examples of a method of forming a semiconductor device according to an embodiment. Fig.34 FIG. shows a process flow diagram of an exemplary method of forming a semiconductor device according to an embodiment, and FIG. 35A to FIG. 37B FIG. shows a cross-sectional view of a stage in a method of forming a semiconductor device according to an embodiment. In Figures 35A to 37B , Fig.35A , Fig.36A and Fig.37A are cross-sectional views showing a region taken along line I-I' in Figure 2 , and Fig.35B , Fig.36B and Fig.37B are cross-sectional views showing a region taken along line IIIa-IIIa' in Figure 2 .

[0149] Referring to Figure 2 , Fig.34 , Fig.35A and Fig.35B , active regions 9a and 9b and an isolation region 6 (S10) may be formed. The active regions 9a and 9b and the isolation region 6 may be formed on the semiconductor substrate 3.

[0150] The formation of the isolation region 6 may include, for example, forming a first isolation region 6a that defines an active line in a linear shape on the semiconductor substrate 3; forming a second isolation region 6b that passes through the first isolation region 6a and the active line and extends into the semiconductor substrate 3; and partially etching the first isolation region 6a and the second isolation region 6b to expose the upper regions of the remaining active lines.

[0151] By forming the second isolation region 6b, a first lower active region 9a_1 and a second lower active region 9b_1 can be formed below the remaining active lines. The active line remaining on the first lower active region 9a_1 can be defined as the first upper active region 9a_2, and the active line remaining on the second lower active region 9b_1 can be defined as the second upper active region 9b_2.

[0152] The first lower active region 9a_1 and the first upper active region 9a_2 can constitute the first active region 9a, and the second lower active region 9b_1 and the second upper active region 9b_2 can constitute the second active region 9b. Therefore, the active regions 9a and 9b can include the first active region 9a and the second active region 9b.

[0153] The primary gate line 15 can be formed on the active regions 9a and 9b and the isolation region 6 (S20). Before forming the primary gate line 15, the lower base layer 12 can be formed.

[0154] The formation of the lower base layer 12 and the primary gate line 15 can include: forming an insulating layer and a primary gate layer on the semiconductor substrate 3, where the active regions 9a and 9b and the isolation region 6 are formed on the semiconductor substrate 3; and patterning the insulating layer and the primary gate layer into a linear shape. Therefore, the insulating layer can be patterned to form the lower base layer 12, and the primary gate layer can be patterned to form the primary gate line 15.

[0155] The spacer 18 can be formed on the side surfaces of the primary gate line 15 (S30). The spacer 18 can be formed of any one or a combination of SiN, SiON, and SiCN.

[0156] The source / drain regions ( Figure 4A 24a in Figure 4B and Figure 4A 24b in Figure 4B ) can be formed on the active regions 9a and 9b. For example, the formation of the source / drain regions ( Figure 4A 24a in Figure 4B and Figure 4B 24b in Figure 4Ain 21b).

[0157] Referring to Figure 2 、 Fig.34 、 Fig.36A and Fig.36B ,an interlayer insulating layer 27 filled between the primary gate lines 15 can be formed. The interlayer insulating layer 27 can be formed of silicon oxide.

[0158] A mask pattern 30 can be formed on the primary gate lines 15 and the interlayer insulating layer 27, and an etching process using the mask pattern 30 as an etching mask can be performed to form an opening 33 for separating the primary gate lines 15 on the isolation region 6. When there are multiple primary gate lines 15 to be separated, the opening 33 can be formed in multiple.

[0159] In one embodiment, the opening 33 can expose the lower base layer 12.

[0160] In one embodiment, the opening 33 can pass through the lower base layer 12 and extend into the second isolation region 6b of the isolation region 6.

[0161] Referring to Figure 2 、 Fig.34 、 Fig.37A and Fig.37B ,in an exemplary example, while forming the opening 33, the thickness of the spacer 18 adjacent to the opening 33 can be reduced.

[0162] A gate separation region 40 (S50) for separating the primary gate lines 15 on the isolation region 6 can be formed. For example, the primary gate lines 15 can be etched through a patterning process to form an opening between the primary gate lines 15 ( Fig.36A and Fig.36B in 33), a buffer liner 46 covering the inner wall of the opening ( Fig.36A and Fig.36B in 33) can be formed, and a gap-fill layer 52 filling the opening ( Fig.36A and Fig.36B in 33) can be formed.

[0163] In one embodiment, the gate separation region 40 can include a lower insulating layer 12a retained under the buffer liner 46, as well as the gap-fill layer 52 and the buffer liner 46.

[0164] The exemplary method of forming the above gate separation region 40 can be applied to the methods of forming the gate separation regions 240, 340, and 440 having the above various shapes or structures.

[0165] Referring again to Figure 4A 、 Figure 4B and Figure 5 together with Figure 2 and Fig.34 , the primary gate lines ( Fig.37A and Fig.37B 15 in) can be replaced by gate line structures 63a and 63b (S60). For example, replacing the primary gate lines ( Fig.37A and Fig.37B 15 in) can include: removing the primary gate lines ( Fig.37A and Figure 37B 15 in) to form gate trenches; forming a gate dielectric covering the inner walls of the gate trenches; forming gate electrode lines for filling the gate trenches on the gate dielectric; partially etching the gate electrode lines and the gate dielectric; and forming covering lines for filling the remaining portions of the gate trenches. Thus, gate line structures 63a and 63b as shown in Figure 4A and Figure 4B can be formed. The gate line structures 63a and 63b can include a first gate line structure 63a and a second gate line structure 63b having end portions 63e1 and 63e2 opposite to each other.

[0166] Then, contact structures 78a and 78b can be formed (S70). For example, the contact structures 78a and 78b can be formed on the first source / drain regions 24a and the second source / drain regions 24b. The contact structures 78a and 78b can be formed of any one or a combination of doped silicon, metal silicide, metal nitride, and metal.

[0167] In one embodiment, the above gate isolation regions 40, 240, 340, and 440 can apply a tensile stress to the channel region of the transistor along the longitudinal direction of the gate line structure. For example, the performance of the transistors adjacent to the above gate isolation regions 40, 240, 340, and 440 can be improved.

[0168] In one embodiment, the above gate isolation regions 40, 240, 340, and 440 can be formed without defects such as seams. For example, defects can be reduced, and the productivity of the semiconductor device can be improved.

[0169] According to an embodiment, a semiconductor device including a gate isolation region formed between gate line structures can be provided. The gate isolation region can include a buffer structure, and the buffer structure includes a material having a dielectric constant higher than that of silicon oxide and lower than that of silicon nitride. In one embodiment, such a gate isolation region can provide a tensile stress on the channel region of the transistor along the longitudinal direction of the gate line structure, thereby improving the performance of the transistor. For example, a semiconductor device including transistors with improved performance can be provided.

[0170] An embodiment can provide a semiconductor device including a gate isolation region separating gate line structures.

[0171] Embodiments may provide a semiconductor device including a gate isolation region, in which the performance of a transistor may be improved.

[0172] Example embodiments have been disclosed herein, and although specific terms are employed, they are used only for and will be interpreted as having a general descriptive meaning and not for a limiting purpose. In some instances, as would be recognized by one of ordinary skill in the art to which this application pertains, unless otherwise explicitly stated, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Accordingly, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: a first active region and a second active region spaced apart from each other in a first direction; an isolation region on side surfaces of lower regions of the first active region and the second active region; a first gate structure on a first region of the isolation region and the first active region, and comprising a first gate dielectric layer and a first gate electrode; a second gate structure on a second region of the isolation region and the second active region, and comprising a second gate dielectric layer and a second gate electrode; and a gate separation region on a third region of the isolation region and between the first gate structure and the second gate structure, wherein the gate separation region comprises: a lower buffer layer; a gap filling layer on the lower buffer layer; and a buffer liner covering side surfaces and a lower surface of the lower buffer layer.

2. The semiconductor device according to claim 1, Among them, wherein a dielectric constant of a material of the gap filling layer is higher than a dielectric constant of a material of the lower buffer layer.

3. The semiconductor device according to claim 2, Among them, wherein a dielectric constant of a material of the buffer liner is higher than a dielectric constant of a material of the lower buffer layer.

4. The semiconductor device according to claim 2, Among them, wherein a dielectric constant of a material of the buffer liner is lower than a dielectric constant of a material of the gap filling layer.

5. The semiconductor device according to claim 1, Among them, wherein a lower end of the gate separation region is located at a height lower than lower surfaces of the first gate structure and the second gate structure adjacent to the gate separation region.

6. The semiconductor device according to claim 1, Among them, wherein the gate separation region further comprises a lower insulating layer between the third region of the isolation region and the buffer liner.

7. The semiconductor device according to claim 6, Among them, wherein a material of the lower insulating layer is different from a material of the buffer liner.

8. The semiconductor device according to claim 1, Among them, wherein in the first direction, the first gate structure covers an upper surface and side surfaces of an upper region of the first active region, and wherein in the first direction, the second gate structure covers an upper surface and side surfaces of an upper region of the second active region.

9. The semiconductor device according to claim 1, Among them, wherein a vertical thickness of the lower buffer layer is greater than a vertical thickness of the first gate electrode.

10. The semiconductor device according to claim 1, Among them, wherein the first gate dielectric layer covers a lower surface of the first gate electrode and extends between the first gate electrode and the buffer liner, and wherein the second gate dielectric layer covers a lower surface of the second gate electrode and extends between the second gate electrode and the buffer liner.

11. The semiconductor device according to claim 1, Among them, wherein the first gate structure further comprises a first gate capping layer on the first gate electrode, and wherein the second gate structure further comprises a second gate capping layer on the second gate electrode.

12. The semiconductor device according to claim 11, Among them, wherein an upper surface of the gap filling layer and an upper surface of the first gate capping layer are substantially at the same height.

13. The semiconductor device according to claim 11, Among them, The lower buffer layer is at a height lower than that of the first gate covering layer.

14. A semiconductor device, comprising: A semiconductor substrate; A first active region and a second active region, the first active region and the second active region being spaced apart from each other in a first direction and on the semiconductor substrate; An isolation region, the isolation region being on side surfaces of lower regions of the first active region and the second active region and on the semiconductor substrate; A first gate structure, on a first region of the isolation region and on the first active region, and comprising a first gate dielectric layer and a first gate electrode; A second gate structure, on a second region of the isolation region and on the second active region, and comprising a second gate dielectric layer and a second gate electrode; And A gate separation region, the gate separation region being on a third region of the isolation region and between the first gate structure and the second gate structure, wherein, in the first direction, the first gate structure covers an upper surface and side surfaces of an upper region of the first active region, and wherein, in the first direction, the second gate structure covers an upper surface and side surfaces of an upper region of the second active region, wherein a lower end of the gate separation region is at a height lower than lower surfaces of the first gate structure and the second gate structure adjacent to the gate separation region, wherein the gate separation region comprises: A lower buffer layer; A gap filling layer, on the lower buffer layer; and A buffer liner, covering side surfaces and a lower surface of the lower buffer layer, wherein the first gate structure further comprises a first gate covering layer on the first gate electrode, wherein the second gate structure further comprises a second gate covering layer on the second gate electrode, and wherein the lower buffer layer is at a height lower than those of the first gate covering layer and the second gate covering layer.

15. The semiconductor device according to claim 14, Among them, The dielectric constant of the material of the gap filling layer is higher than the dielectric constant of the material of the lower buffer layer.

16. The semiconductor device according to claim 15, Among them, The dielectric constant of the material of the buffer liner is higher than the dielectric constant of the material of the lower buffer layer.

17. The semiconductor device according to claim 15, Among them, The dielectric constant of the material of the buffer liner is lower than the dielectric constant of the material of the gap filling layer.

18. The semiconductor device according to claim 14, Among them, The first gate dielectric layer covers a lower surface of the first gate electrode and extends between the first gate electrode and the buffer liner, and wherein the second gate dielectric layer covers a lower surface of the second gate electrode and extends between the second gate electrode and the buffer liner.

19. A semiconductor device, comprising: A semiconductor substrate; A first active region and a second active region, the first active region and the second active region being spaced apart from each other in a first direction and on the semiconductor substrate; An isolation region, the isolation region being on side surfaces of lower regions of the first active region and the second active region and on the semiconductor substrate; A first gate structure, on a first region of the isolation region and the first active region, and including a first gate dielectric layer and a first gate electrode; A second gate structure, on a second region of the isolation region and the second active region, and including a second gate dielectric layer and a second gate electrode; And A gate separation region, the gate separation region on a third region of the isolation region and between the first gate structure and the second gate structure, wherein, in the first direction, the first gate structure covers an upper surface and a side surface of an upper region of the first active region, and wherein, in the first direction, the second gate structure covers an upper surface and a side surface of an upper region of the second active region, wherein, the gate separation region includes: A lower buffer layer; A gap filling layer, on the lower buffer layer; and A buffer liner, covering a side surface and a lower surface of the lower buffer layer, wherein, the first gate structure further includes a first gate capping layer on the first gate electrode, wherein, the second gate structure further includes a second gate capping layer on the second gate electrode, wherein, the lower buffer layer is at a height lower than the first gate capping layer and the second gate capping layer, wherein, the gate separation region further includes a lower insulating layer between the third region of the isolation region and the buffer liner, wherein, a material of the lower insulating layer is different from a material of the buffer liner.

Images