Sensor structure, manufacturing method thereof and wafer bonding method

Abstract

The invention provides a sensor structure and a manufacturing method thereof, and a wafer bonding method, the sensor structure comprises a substrate, the substrate comprises a semiconductor layer, a dielectric layer on the substrate and an opening penetrating through the dielectric layer, the opening exposes the semiconductor layer, the sensor structure further comprises a second doping layer on the dielectric layer and in the opening, and the second doping layer comprises a first doping layer and a second doping layer. The detector further comprises an intrinsic absorption layer and a third doping layer which are stacked on the second doping layer, the doping types of the third doping layer and the second doping layer are different, the second doping layer is formed on the semiconductor layer, the opening of the first dielectric layer can reduce dislocation of the second doping layer, the dislocation defect density in the second doping layer is reduced, and the sensitivity of the detector is improved. The semiconductor layer and the dielectric layer help to improve peak response and quantum efficiency of the sensor. A part of the second doping layer in the opening is used as a micro-nano structure, so that incident light can be efficiently limited in a micro region, and the light absorption efficiency of the germanium-based image sensor is further remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to a sensor structure, a manufacturing method thereof, and a wafer bonding method. Background Art

[0002] Germanium semiconductor materials highly compatible with the CMOS process have outstanding advantages. For example, they can be epitaxially grown on large-size Si substrates, have excellent optical response in the short-wave infrared (SWIR) band, and adjustable band gaps, etc. For this reason, it is regarded as an important candidate sensing material for the next-generation short-wave infrared imaging technology. Through the unremitting efforts of researchers, Ge image sensors based on the germanium-on-insulator (GOI) wafer structure have significantly improved in performance indicators such as light absorption efficiency, dark current, peak response, and quantum efficiency, and are expected to be widely used in fields such as consumer electronics, industrial inspection, and medical diagnosis.

[0003] However, although its dark current has been reduced to the nA level, it still cannot compare with commercial InGaAs short-wave infrared image sensors (dark current in the fA level). Therefore, further reducing the dark current of GOI image sensors is crucial for mass production. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a sensor structure, a manufacturing method thereof, and a wafer bonding method, which can form high-quality short-wave infrared sensors on large-size substrates, reduce dark current, and facilitate large-scale commercial use of the sensors.

[0005] An embodiment of this application provides a sensor structure, including:

[0006] A substrate, the substrate including a semiconductor layer;

[0007] A dielectric layer on the substrate and an opening penetrating the dielectric layer, the opening exposing the semiconductor layer;

[0008] A second doped layer on the dielectric layer and within the opening;

[0009] An intrinsic absorption layer on the second doped layer;

[0010] A third doped layer on the intrinsic absorption layer, the doping types of the third doped layer and the second doped layer are different, and the materials of the second doped layer, the intrinsic absorption layer, and the third doped layer include germanium.

[0011] Optionally, the material of the semiconductor layer includes germanium.

[0012] Optionally, the substrate includes a germanium-on-insulator substrate, a germanium-on-sapphire substrate, or a germanium-on-glass substrate, and the germanium layer in the substrate serves as the semiconductor layer.

[0013] Optionally, the substrate includes a silicon substrate, a silicon-on-insulator substrate, a silicon-on-sapphire substrate, or a silicon-on-glass substrate, and the silicon layer in the substrate serves as the semiconductor layer.

[0014] Optionally, the intrinsic absorption layer includes an intrinsic germanium layer or a Ge / GeSi quantum well structure.

[0015] Optionally, the dielectric layer includes one or more stacked negative capacitance material structures, or one or more stacked oxide material structures, or a periodically stacked Bragg reflector structure.

[0016] Optionally, the second doped layer, the intrinsic absorption layer, and the third doped layer form a stacked layer, and the stacked layer is isolated into multiple parts by isolation trenches along the first direction, and each part serves as a pixel corresponding to a pair of first electrodes and second electrodes.

[0017] Optionally, in a plane perpendicular to the extending direction of the isolation trenches, the shape of at least one part of the multiple parts is a trapezoidal structure.

[0018] Optionally, the semiconductor layer is doped to be a first doped layer, and the doping types of the first doped layer and the second doped layer are the same; the isolation trenches extend to the first doped layer.

[0019] Optionally, the sensor structure further includes:

[0020] A passivation layer covering the stacked layer and the isolation trenches, the first electrode penetrating the passivation layer at the bottom of the isolation trenches, and the second electrode penetrating the passivation layer on the third doped layer.

[0021] Optionally, the sensor structure further includes:

[0022] The first electrode and the second electrode;

[0023] A readout circuit wafer on the first electrode and the second electrode, the readout circuit wafer having a readout circuit, and the readout circuit being respectively connected to the first electrode and the second electrode.

[0024] An embodiment of the present application further provides a manufacturing method of a sensor structure, including:

[0025] Providing a substrate, the substrate including a semiconductor layer;

[0026] Forming a dielectric layer on the substrate and an opening penetrating the dielectric layer, the opening exposing the semiconductor layer;

[0027] Form a second doped layer on the dielectric layer and within the opening;

[0028] Form an intrinsic absorption layer on the second doped layer;

[0029] Form a third doped layer on the intrinsic absorption layer, the third doped layer having a different doping type from the second doped layer, and the materials of the second doped layer, the intrinsic absorption layer, and the third doped layer include germanium.

[0030] Optionally, the material of the semiconductor layer includes germanium.

[0031] Optionally, the substrate includes a germanium-on-insulator substrate, a germanium-on-sapphire substrate, or a germanium-on-glass substrate, and the germanium layer in the substrate serves as the semiconductor layer.

[0032] Optionally, the substrate includes a silicon substrate, a silicon-on-insulator substrate, a silicon-on-sapphire substrate, or a silicon-on-glass substrate, and the silicon layer in the substrate serves as the semiconductor layer.

[0033] Optionally, the intrinsic absorption layer includes an intrinsic germanium layer or a Ge / GeSi quantum well structure.

[0034] Optionally, the dielectric layer includes one or more stacked negative capacitance material structures, or one or more stacked oxide material structures, or a periodically stacked Bragg reflector structure.

[0035] Optionally, the second doped layer, the intrinsic absorption layer, and the third doped layer form a stacked layer, and the method further includes:

[0036] Etch the stacked layer to obtain isolation trenches penetrating the stacked layer, and the isolation trenches are isolated into multiple parts, each part serving as a pixel corresponding to a pair of first electrodes and second electrodes.

[0037] Optionally, in a plane perpendicular to the extending direction of the isolation trenches, the shape of at least one part of the multiple parts is a trapezoidal structure.

[0038] Optionally, the method further includes:

[0039] Dope the semiconductor layer so that the semiconductor layer serves as a first doped layer; the first doped layer has the same doping type as the second doped layer; and the isolation trenches extend to the first doped layer.

[0040] Optionally, after etching the stacked layer to obtain isolation trenches penetrating the stacked layer, the method further includes:

[0041] A passivation layer is formed to cover the stacked layer and the isolation trench. After formation, the first electrode penetrates the passivation layer at the bottom of the isolation trench, and after formation, the second electrode penetrates the passivation layer on the surface of the third doped layer.

[0042] An embodiment of the present application also provides a wafer bonding method, including:

[0043] Providing the sensor structure as described above;

[0044] Forming the first electrode and the second electrode;

[0045] Through bump bonding, a readout circuit wafer is formed on the first electrode and the second electrode. The readout circuit wafer has a readout circuit, and the readout circuit is respectively connected to the first electrode and the second electrode.

[0046] The present application provides a sensor structure, a manufacturing method thereof, and a wafer bonding method. The sensor structure may include a substrate, the substrate includes a semiconductor layer, and further includes a dielectric layer on the substrate and an opening penetrating the dielectric layer. The opening exposes the semiconductor layer. The sensor structure further includes a second doped layer on the dielectric layer and within the opening, and further includes an intrinsic absorption layer and a third doped layer stacked on the second doped layer. The doping types of the third doped layer and the second doped layer are different. The materials of the second doped layer, the intrinsic absorption layer, and the third doped layer include germanium. In this way, a second doped layer is epitaxially formed on the semiconductor layer. The opening in the first dielectric layer can reduce the dislocations in the second doped layer and lower the dislocation defect density in the second doped layer, thereby obtaining a second doped layer with a lower defect density compared to the semiconductor layer. In this way, it is convenient to use the substrate to achieve large size, use the second doped layer to achieve high-quality film layers, reduce carrier recombination, promote the effective collection of photo-generated carriers, reduce the dark current of the detector, improve the signal-to-noise ratio of the detector, and improve the sensitivity of the detector. The semiconductor layer and the dielectric layer together form the bottom reflection structure of the image sensor. This design introduces a resonant cavity effect in the sensor, which helps to improve the peak response and quantum efficiency of the sensor. Part of the second doped layer in the opening in the dielectric layer serves as a micro-nano structure, which can efficiently confine the incident light in a small area, thereby significantly improving the light absorption efficiency of the germanium-based image sensor. Description of the Drawings

[0047] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0048] Figure 1 Shows a schematic diagram of a sensor structure provided by an embodiment of the present application;

[0049] Figure 2 Schematic diagram of another sensor structure provided by an embodiment of the present application;

[0050] Figure 3 Flowchart of a manufacturing method of a sensor structure provided by an embodiment of the present application;

[0051] Figures 4 - 18 Shows a schematic diagram of the sensor structure provided by an embodiment of the present application during the manufacturing process. Detailed implementation manners

[0052] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0053] Many specific details are set forth in the following description in order to provide a thorough understanding of the present application, but the present application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar generalizations without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0054] The present application is described in detail with reference to the schematic diagrams. When describing the embodiments of the present application in detail, for the sake of convenience of explanation, the cross-sectional views showing the device structure will be enlarged locally out of the general proportion, and the schematic diagrams are only examples, which should not limit the protection scope of the present application herein. In addition, in actual production, three-dimensional spatial dimensions including length, width and depth should be included.

[0055] In order to better understand the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0056] See Figure 1 , this figure is a schematic diagram of a sensor structure provided by an embodiment of the present application. The sensor structure includes: a substrate, a dielectric layer 250 on the substrate, and a stacked layer 220 / 230 / 240 on the dielectric layer 250.

[0057] In the embodiments of the present application, the substrate is used to provide support for the film layers thereon, and it includes a semiconductor layer 130. The semiconductor layer 130 can be doped, and the doped semiconductor layer can be used as a first doped layer. The doping type of the semiconductor layer 130 can be denoted as the first doping type. The material of the semiconductor layer 130 can include silicon, or can also include germanium, etc.

[0058] The substrate may include a single structure, such as a silicon substrate, a germanium substrate, etc. The semiconductor layer 130 may be a partial film layer of the substrate, and the first doped layer is obtained by doping this partial film layer.

[0059] The substrate may also include a composite structure. For example, the substrate may include a base layer 110, an insulating layer 120, and a semiconductor layer 130. The base layer 110 may be silicon, sapphire, glass, etc., and the insulating layer 120 may be silicon oxide. The semiconductor layer 130 may be silicon, thus forming a Silicon-On-Insulator (SOI) substrate, a Silicon on Sapphire (SOS) substrate, a Silicon on Glass (SOG) substrate, etc. That is, the silicon layer in the substrate can be used as the semiconductor layer 130, which is doped to be the first doped layer; the semiconductor layer 130 may also be germanium, thus forming a Germanium On Insulator (GOI) substrate, a Germanium on Sapphire (GOS) substrate, a Germanium on Glass (GOG) substrate, etc. That is, the germanium layer in the substrate can be used as the semiconductor layer 130, which is doped to be the first doped layer. Among them, the thickness range of the semiconductor layer 130 is 20 - 500 nm. The insulating layer 120 can also be an buried oxide layer, which can reduce substrate leakage, high crystal quality, low defect density vertical stacked PIN structure epitaxy, and isosceles trapezoid pixel structure, effectively reducing electric field concentration and suppressing dark current.

[0060] In actual operation, the defect density of the top germanium layer of GOI, GOS or GOG wafers (usually in the range of 10 7 ~10 8 cm -2 level) is 1 - 2 orders of magnitude higher than that of Ge wafers (usually in the range of 10 4 ~10 6 cm -2 level). There are many defect states in the top Ge layer, and these defects will act as carrier recombination centers, resulting in more electron-hole pairs recombining in the GOI photodetector, thereby increasing the dark current. In addition, these defects may also cause changes in the Ge energy band structure, making it easier to generate carriers without light illumination, further increasing the dark current level of the GOI photodetector, which will undoubtedly have a negative impact on the photon absorption rate, peak response, and sensitivity of the detector, and is not conducive to the mass production of GOI image sensors. However, with the increasingly broad application scenarios, higher requirements are put forward for the integration, dark current, peak response, peak quantum efficiency, resolution, pixel accuracy, and miniaturization of GOI short-wave infrared image sensors.

[0061] Therefore, in the embodiments of the present application, a dielectric layer 250 is additionally provided, and a stacked layer is provided on the dielectric layer 250. The stacked layer has a higher quality relative to the semiconductor layer 130, and the device formed based on the stacked layer has higher performance than the device formed based on the semiconductor layer 130.

[0062] The sensor structure may further include a dielectric layer 250 and an opening 251 penetrating the dielectric layer 250. The opening 251 exposes the semiconductor layer 130. The opening 251 serves as an epitaxial window for subsequent epitaxial processes. Its size can be in the micrometer or nanometer scale, and its range can be 1 micrometer - 1000 micrometers, or 1 nanometer - 1000 nanometers. The dielectric layer 250 includes a layer of negative capacitance material or a multi-layer stacked negative capacitance material structure, or a layer of oxide material or a multi-layer stacked oxide material structure, or a periodically stacked Bragg reflector structure. Using the negative capacitance structure can reduce the total capacitance of the short-wave infrared image sensor, reduce the parasitic capacitance, increase the equivalent electric field strength, and thus improve the photoelectric conversion efficiency, quantum efficiency, sensitivity, and response speed of the short-wave infrared image sensor, greatly enhancing the performance of the short-wave infrared image sensor and realizing the rapid and efficient manufacturing of the image sensor. Using the Bragg reflector structure can achieve multiple reflections and absorptions of light in the absorption layer, improve the light absorbance in the absorption layer, and reduce the loss of light during transmission, thereby achieving high performance of the short-wave infrared image sensor.

[0063] The stacked layer includes a second doped layer 240, an intrinsic absorption layer 230, and a third doped layer 220 sequentially stacked in a first direction (i.e., longitudinally) perpendicular to the substrate surface. The second doped layer 240 is also formed within the opening 251. The doping types of the semiconductor layer 130 and the second doped layer 240 are the same. Then, the doping type of the second doped layer 240 can be denoted as the first doping type, and the doping types of the third doped layer 220 and the second doped layer 240 are different. The doping type of the third doped layer 220 can be denoted as the second doping type. The materials of the second doped layer 240, the intrinsic absorption layer 230, and the third doped layer 220 may include germanium.

[0064] Wherein the first doping type and the second doping type are opposite. The first doping type can be one of P-type doping and N-type doping, and the second doping type can be the other of P-type doping and N-type doping. For example, the first doping type can be P-type doping, and the second doping type can be N-type doping. In this way, the stacked layer forms a longitudinal PIN structure (Vertical PIN Structure), and the second doped layer 240 and the third doped layer 220 can be used as an electron transport layer or a hole transport layer for charge response.

[0065] The intrinsic absorption layer 230 includes an intrinsic germanium layer or Ge / GeSi. This can improve the absorption efficiency of the intrinsic absorption layer 230 and enhance the photosensitivity of the sensor.

[0066] When the material of the semiconductor layer 130 includes germanium, since the opening 251 of the dielectric layer 250 exposes the semiconductor layer 130, when the second doped layer 240 is formed on the opening 251 and the dielectric layer 250, and the material of the second doped layer 240 is the same as that of the semiconductor layer 130, the formation method of the second doped layer 240 is homoepitaxy. The formed second doped layer 240 can also be an epitaxial layer. Therefore, the lattice matching between the second doped layer 240 and the semiconductor layer 130 of the second doped layer 240 is excellent, making the arrangement of germanium atoms in the second doped layer 240 more regular, and the number of crystal defects such as defects and dislocations greatly reduced. Thus, the integrity and quality of the Ge crystal in the Ge epitaxial layer are improved, and the defect degree of the second doped layer 240 is comparable to that of the germanium wafer. In addition, the growth process of Ge homoepitaxy is relatively stable, the process is simple, the crystal quality is high, and the performance predictability is strong. This makes it very suitable for large-scale production, can ensure the consistency and reliability of the GOI image sensor, reduce the scrap rate, and improve production efficiency and economic benefits.

[0067] In addition, the dielectric layer 250 has an opening 251. The dielectric layer 250 between the openings 251 serves as a mask region. When germanium grows laterally in the opening 251, when the Ge epitaxial layer grown from the window region laterally expands to the dielectric layer (such as SiO2) mask region, dislocations will be blocked by the SiO2 mask. Under this blocking effect, the dislocations will bend, and their propagation direction will also change accordingly. Some dislocations may be restricted under the SiO2 mask (i.e., inside the opening 251), or cancel each other out during the bending process, so that they cannot continue to propagate upward to the laterally grown Ge epitaxial layer (i.e., the part on the dielectric layer 250). In this way, the dislocation defect density in the Ge epitaxial layer is effectively reduced. Therefore, by performing lateral homoepitaxial growth of the Ge layer on the GOI wafer, the Ge epitaxial layer can bypass some defect regions during the lateral growth process, so as to effectively obtain a Ge epitaxial layer with a lower defect density than the Ge layer on the top of the GOI wafer, and finally obtain a vertically stacked Ge PIN photodetection structure with extremely high crystal quality, solving the problem of the relatively high defect density of the Ge PIN structure on the GOI used in conventional GOI image sensors, further reducing its dark current, and improving the photon absorption rate, peak response, and sensitivity of the GOI image sensor.

[0068] In the embodiments of the present application, the semiconductor layer 130 and the dielectric layer 250 form a bottom reflection structure, which helps to improve the peak response and quantum efficiency of the sensor. When the substrate includes a base layer 110, an insulating layer 120, and a semiconductor layer 130, the insulating layer 120 and the dielectric layer 250 are included below the stacked layer, and an extremely thin germanium layer (i.e., the semiconductor layer 130) is provided between them. A partial structure below the stacked layer is formed by stacking the base layer 110, the insulating layer 120, the semiconductor layer 130, and the dielectric layer 250, jointly forming the bottom reflection structure of the GOI image sensor. This design introduces a resonant cavity effect in the sensor, which helps to improve the peak response and quantum efficiency of the sensor. Although the semiconductor layer 130 will absorb a small part of the short-wave infrared light signal, due to its extremely thin thickness, the absorption amount is negligible and can be ignored.

[0069] Part of the second doped layer 240 in the opening 251 of the dielectric layer 250 serves as a micro-nano structure, which can efficiently confine the incident light in a tiny area, thereby significantly improving the light absorption efficiency of the GOI image sensor. This structure not only enhances the photon capture ability of the sensor and prolongs the interaction time of light and matter, thus improving the photon absorption rate; moreover, by designing Ge micro-nano structures of different sizes, the GOI image sensor can achieve a higher absorption rate for light in a wider wavelength band. In addition, the Ge micro-nano structure also introduces additional detection dimensions for the GOI image sensor, such as polarization, wavelength, etc., which helps to perform more complex detection tasks and enhances the flexibility and adaptability of the sensor.

[0070] Specifically, the stacked layer can be isolated into multiple parts by isolation trenches 20A along the first direction, and each part serves as a pixel 20B, corresponding to a pair of first electrodes 260 and second electrodes 270. The distance between adjacent pixels 20B is called the pixel pitch, which can be the distance between the center points of two adjacent isolation trenches 20A. The isolation trenches can penetrate the intrinsic absorption layer 230 and the third doped layer 220, and partially penetrate the second doped layer 240, so that the bottom of the isolation trenches exposes the second doped layer 240; the isolation trenches can also penetrate the stacked layer, so that the bottom of the isolation trenches exposes the semiconductor layer 130. When the isolation trenches do not coincide with the opening 251, they can penetrate the dielectric layer 250.

[0071] When the stacked layer is separated into multiple parts by the isolation trenches 20A, in the plane perpendicular to the extending direction of the isolation trenches 20A, the shapes of the multiple parts can be rectangular structures. Refer to Figure 2As shown in the figure, it is a schematic diagram of another sensor structure provided by the embodiment of the present application. The shapes of multiple parts can also be trapezoidal structures. That is, the shape of at least one part of the multiple parts is a trapezoidal structure, and the remaining parts can be rectangular structures or trapezoidal structures. For the convenience of manufacturing, the shapes of all multiple parts can be set as rectangular structures or trapezoidal structures. The trapezoidal structure can be an isosceles trapezoid.

[0072] This is because the trapezoidal GOI pixel structure can better adapt to the irregular chip shape and layout requirements, thereby improving the space utilization rate, achieving a more compact layout, and improving the space utilization rate and resolution of the image sensor. In addition, the trapezoidal pixel structure can reduce the waste of the pitch between pixels by adjusting the angle and size of the isosceles trapezoid. The hypotenuse of the isosceles trapezoid can be designed to be more inclined, so that the pitch between adjacent pixels becomes smaller. Thus, in the same chip area, this structure can accommodate more GOI pixels, thereby improving the resolution of the GOI image sensor. Secondly, the high space utilization rate also brings a reduction in production costs because the same performance can be achieved on a smaller chip size.

[0073] In addition, the inclined side of the trapezoidal GOI pixel can capture incident light from different angles, increasing the light collection area, thereby improving the light collection efficiency. This is very beneficial for image sensing in low-light environments and can improve the brightness and clarity of the image. At the same time, the characteristic of reducing reflection loss also helps to improve the light collection efficiency, enabling more light to be effectively utilized.

[0074] The special shape of the trapezoidal pixel structure increases the folding angle at the edge of the pixel structure, which is equivalent to making the outer surface of the pixel structure flatter, and can reduce the problems of electric field concentration and leakage current that are prone to occur at the edge of traditional rectangular pixels. Its inclined side can make the electric field distribution more uniform, reduce the carrier accumulation at the edge, and thus reduce the dark current; at the same time, the angle and size of the trapezoidal pixel can be optimized through design to make the electric field more uniformly distributed inside the pixel, reduce carrier diffusion and recombination, promote the effective collection of photo-generated carriers, and thus reduce the generation of dark current.

[0075] During the manufacturing process of GOI image sensors, the manufacturing process of trapezoidal pixel structures is compatible with many traditional semiconductor manufacturing processes, such as lithography, etching, deposition, etc., which can all be applied to the manufacturing of trapezoidal pixels. This enables manufacturers to introduce trapezoidal pixel structures without large-scale equipment upgrades or process modifications, reducing production costs and technical risks. In addition, the trapezoidal pixel structure has good scalability and can be adjusted and optimized according to different application requirements. By changing parameters such as the angle and size of the trapezoid, the requirements for different resolutions, sensitivities, and dynamic ranges can be met, improving the scalability, flexibility, and adaptability of GOI image sensors, which is beneficial for realizing miniaturized, high-resolution, and high-pixel-precision GOI image sensors and promoting their wide applications in scenarios such as smartphones, wearable devices, drones, action cameras, industrial automation, robots, and medical devices.

[0076] The sensor structure may further include a passivation layer 290 on the stacked layer. The passivation layer 290 covers the stacked layer and is used to protect the stacked layer. The material of the passivation layer 290 is an insulating material, such as silicon oxide, etc. The passivation layer 290 may cover the bottom and sidewalls of the isolation trench 20A. After the first electrode 260 and the second electrode 270 are formed, the first electrode 260 may penetrate the passivation layer 290 on the first doped layer to connect to the first doped layer, or penetrate the passivation layer on the second doped layer 240 to connect to the second doped layer 240; the second electrode 270 penetrates the passivation layer 290 on the third doped layer 220 to connect to the third doped layer 220. The first electrode 260 may penetrate the passivation layer 290 at the bottom of the isolation trench 20A to connect to the first doped layer or the second doped layer 240.

[0077] The sensor structure may further include a first electrode 260 and a second electrode 270. The sensor structure may further include a readout integrated circuit (ROIC) wafer 300 on the first electrode 260 and the second electrode 270. The readout integrated circuit wafer 300 includes a readout circuit, and the readout circuit is respectively connected to the first electrode 260 and the second electrode 270. In actual operation, the readout circuit may be connected to the first electrode 260 through a first connection structure 310 and connected to the second electrode 270 through a second connection structure 320. In this way, the photo-generated carriers generated in the sensing layer can be respectively transmitted to the first electrode 260 and the second electrode 270 through the first doped layer (or the second doped layer 240) and the third doped layer 220, so that the readout circuit can obtain the current information of the first electrode 260 and the second electrode 270, thereby obtaining the light detection result.

[0078] In summary, the GOI image sensor in the embodiments of the present application adopts a vertically stacked GePIN photodetection structure with a low defect density. The defect density level of this structure can be comparable to that of a Ge wafer, significantly reducing the number of defect states in the Ge layer on the top of the GOI wafer. This improvement effectively reduces the carrier recombination centers introduced by defects, thereby weakening the recombination process of electron-hole pairs in the GOI photodetector, and thus effectively suppressing the generation of dark current. On the basis of effectively reducing the dark current of the GOI image sensor, it not only significantly enhances its resonant cavity effect, but also innovatively introduces Ge micro-nano structures into the GOI wafer, which greatly improves the photon capture ability of the GOI image sensor. In addition, the Ge micro-nano structures exhibit various advantages in detection dimensions such as polarization and wavelength, opening up a broader path for the development and application of GOI image sensors.

[0079] Therefore, the present invention is expected to be widely applied in many fields and promote its further development. The GOI image sensor with low dark current is regarded as one of the key technical approaches to promote the large-scale production of germanium short-wave infrared image sensors and is also one of the key technical approaches to realize miniaturized germanium image sensors. The successful implementation of this technology will greatly promote the wide application of germanium short-wave infrared image sensors in consumer electronics, industrial inspection, medical diagnosis, and civilian fields, and has important research significance and practical application value.

[0080] The present application provides a sensor structure, including a semiconductor layer, a dielectric layer on a substrate, and an opening penetrating the dielectric layer, the opening exposing the semiconductor layer. The sensor structure further includes a second doped layer on the dielectric layer and within the opening, and an intrinsic absorption layer and a third doped layer stacked on the second doped layer. The doping types of the third doped layer and the second doped layer are different. The materials of the second doped layer, the intrinsic absorption layer, and the third doped layer include germanium. In this way, a second doped layer is epitaxially formed on the semiconductor layer. The opening in the first dielectric layer can reduce the dislocations of the second doped layer and lower the dislocation defect density in the second doped layer, thereby obtaining a second doped layer with a lower defect density compared to the semiconductor layer. This facilitates the use of the substrate to achieve large size, the use of the second doped layer to achieve high-quality film layers, reduces carrier recombination, promotes the effective collection of photo-generated carriers, reduces the dark current of the detector, improves the signal-to-noise ratio of the detector, and improves the sensitivity of the detector. The semiconductor layer and the dielectric layer together constitute the bottom reflection structure of the image sensor. This design introduces a resonant cavity effect in the sensor, which helps to improve the peak response and quantum efficiency of the sensor. Part of the second doped layer in the opening in the dielectric layer serves as a micro-nano structure, which can efficiently confine the incident light in a tiny area, thereby significantly improving the light absorption efficiency of the germanium-based image sensor.

[0081] Based on the sensor structure provided in the above embodiments, the embodiments of the present application further provide a manufacturing method of a sensor structure. Refer to Figure 3 As shown in the flowchart of a manufacturing method of a sensor structure provided by the embodiments of the present application. Refer to Figures 4 - 18 , which is a schematic structural diagram of the sensor structure in the manufacturing process in the embodiments of the present application. The method may include:

[0082] S101, provide a substrate, the substrate includes a semiconductor layer 130. Refer to Figure 4 As shown.

[0083] In the embodiments of the present application, the substrate is used to provide support for the film layer thereon. It includes a semiconductor layer 130. Refer to Figure 4 , the semiconductor layer 130 can be doped, that is, the semiconductor layer can be doped to make the semiconductor layer as the first doped layer. The doping method can be ion implantation or the like. The doping type of the semiconductor layer 130 can be denoted as the first doping type. The material of the semiconductor layer 130 can include silicon, germanium, or the like.

[0084] The substrate can include a single structure, such as a silicon substrate, a germanium substrate, or the like. Then the semiconductor layer 130 can be a partial film layer of the substrate, and the first doped layer is obtained by doping this partial film layer.

[0085] The substrate can also include a composite structure. For example, the substrate can include a base layer 110, an insulating layer 120, and a semiconductor layer 130. The base layer 110 can be silicon, sapphire, or glass, etc., and the insulating layer 120 can be silicon oxide. The semiconductor layer 130 can be silicon, thereby forming a Silicon-On-Insulator (SOI) substrate, a Silicon on Sapphire (SOS) substrate, or a Silicon on Glass (SOG) substrate, etc. That is, the silicon layer in the substrate can be used as the semiconductor layer 130, which is doped as the first doped layer; the semiconductor layer 130 can also be germanium, thereby forming a Germanium On Insulator (GOI) substrate, a Germanium on Sapphire (GOS) substrate, or a Germanium on Glass (GOG) substrate, etc. That is, the germanium layer in the substrate can be used as the semiconductor layer 130, which is doped as the first doped layer. Among them, the thickness range of the semiconductor layer 130 is 20 - 500 nm. The insulating layer 120 can also be an buried oxide layer, which can reduce substrate leakage, high crystal quality, low defect density vertical stacked PIN structure epitaxy, and isosceles trapezoidal pixel structure, effectively reducing electric field concentration and suppressing dark current.

[0086] S102. Form a dielectric layer 250 on a substrate, and an opening 251 penetrating through the dielectric layer 250, where the opening 251 exposes the semiconductor layer 130. Refer to Figure 5 and Figure 6 as shown.

[0087] In an embodiment of the present application, a dielectric layer 250 can be formed on the substrate, and the dielectric layer 250 covers the semiconductor layer 130 on the substrate. Refer to Figure 5 as shown; then, the dielectric layer 250 is etched to obtain an opening 251 penetrating through the dielectric layer, and the opening 251 exposes the semiconductor layer 130. Refer to Figure 6 as shown. The dielectric layer 250 can be formed on the substrate through a deposition process. The opening 251 serves as an epitaxial window for a subsequent epitaxial process, and its size can be in the micron or nanometer scale, and its range can be from 1 micron to 1000 microns, or from 1 nanometer to 1000 nanometers.

[0088] The dielectric layer 250 includes a layer of negative capacitance material or a multi-layer stacked negative capacitance material structure, or a layer of oxide material or a multi-layer stacked oxide material structure, or a periodically stacked Bragg reflector structure. The use of the negative capacitance structure reduces the total capacitance of the short-wave infrared image sensor, reduces the parasitic capacitance, increases the equivalent electric field strength, thereby improving the photoelectric conversion efficiency, quantum efficiency, sensitivity, and response speed of the short-wave infrared image sensor, greatly enhancing the performance of the short-wave infrared image sensor, and realizing the rapid and efficient manufacturing of the image sensor. The use of the Bragg reflector structure can achieve multiple reflections and absorptions of light in the absorption layer, improve the light absorbance in the absorption layer, and reduce the loss of light during transmission, thereby realizing the high performance of the short-wave infrared image sensor.

[0089] S103. Form a second doped layer 240 on the dielectric layer 250 and within the opening 251. Refer to Figure 7 and Figure 8 as shown.

[0090] S104. Form an intrinsic absorption layer 230 on the second doped layer 240. Refer to Figure 9 as shown.

[0091] S105. Form a third doped layer 220 on the intrinsic absorption layer 230. The doping type of the third doped layer 220 is different from that of the second doped layer 240. Refer to Figures 10 - 18 as shown.

[0092] In S103, S104, and S105, a stacked layer is disposed on the dielectric layer 250. The stacked layer includes a second doped layer 240, an intrinsic absorption layer 230, and a third doped layer 220. The second doped layer 240 has a higher quality relative to the semiconductor layer 130, and the device formed based on the second doped layer 240 has higher performance compared to the device formed based on the semiconductor layer 130.

[0093] The stacked layer includes the second doped layer 240, the intrinsic absorption layer 230, and the third doped layer 220 that are sequentially stacked in a first direction (i.e., longitudinally) along the vertical substrate surface. The second doped layer 240 is also formed within the opening 251. If the doping types of the first doped layer and the second doped layer 240 are the same, the doping type of the second doped layer 240 can be denoted as the first doping type. The doping types of the third doped layer 220 and the second doped layer 240 are different, and the doping type of the third doped layer 220 can be denoted as the second doping type. The materials of the second doped layer 240, the intrinsic absorption layer 230, and the third doped layer 220 can include germanium. The second doped layer 240, the intrinsic absorption layer 230, and the third doped layer 220 can be formed by an epitaxial process (such as molecular beam epitaxy process, etc.) or a deposition process (such as chemical vapor deposition, etc.), and the doping elements can be added to the second doped layer 240 and the third doped layer 220 by in-situ doping.

[0094] Wherein the first doping type and the second doping type are opposite. The first doping type can be one of P-type doping and N-type doping, and the second doping type can be the other of P-type doping and N-type doping. For example, the first doping type can be P-type doping, and the second doping type can be N-type doping. In this way, the stacked layer constitutes a longitudinal PIN structure (Vertical PIN Structure), and the second doped layer 240 and the third doped layer 220 can be used as an electron transport layer or a hole transport layer to respond to charges.

[0095] The intrinsic absorption layer 230 includes an intrinsic germanium layer or Ge / GeSi. This can improve the absorption efficiency of the intrinsic absorption layer 230 and enhance the photosensitive ability of the sensor.

[0096] When the material of the semiconductor layer 130 includes germanium, since the opening 251 of the dielectric layer 250 exposes the semiconductor layer 130, when the second doped layer 240 is formed on the opening 251 and the dielectric layer 250, the material of the second doped layer 240 is the same as that of the semiconductor layer 130. Then the formation method of the second doped layer 240 is homoepitaxy, and the formed second doped layer 240 can also be an epitaxial layer. Therefore, the lattice matching between the second doped layer 240 and the semiconductor layer 130 is excellent, making the arrangement of germanium atoms in the second doped layer 240 more regular, and greatly reducing the number of crystal defects such as defects and dislocations. Thus, the integrity and quality of the Ge crystal in the Ge epitaxial layer are improved, and the defect degree of the second doped layer 240 is equivalent to that of the germanium wafer. In addition, the growth process of Ge homoepitaxy is relatively stable, the process is simple, the crystal quality is high and the performance predictability is strong. This makes it very suitable for large-scale production, can ensure the consistency and reliability of the GOI image sensor, reduce the scrap rate, and improve the production efficiency and economic benefits.

[0097] In addition, the dielectric layer 250 has an opening 251, and the dielectric layer 250 between the openings 251 serves as a mask region. When germanium grows laterally in the opening 251, when the Ge epitaxial layer grown from the window region laterally expands to the dielectric layer (such as SiO2) mask region, dislocations will be blocked by the SiO2 mask. Under this blocking effect, the dislocations will bend and their propagation direction will also change accordingly. Some dislocations may be restricted under the SiO2 mask (i.e., inside the opening 251), or cancel each other out during the bending process, so that they cannot continue to propagate upward to the laterally grown Ge epitaxial layer (i.e., the part on the dielectric layer 250). In this way, the dislocation defect density in the Ge epitaxial layer is effectively reduced. Therefore, by performing lateral homoepitaxial growth of the Ge layer on the GOI wafer, the Ge epitaxial layer can bypass some defect regions during the lateral growth process, so as to effectively obtain a Ge epitaxial layer with a lower defect density than the Ge layer on the top of the GOI wafer, and finally obtain a vertically stacked Ge PIN photodetection structure with extremely high crystal quality, solving the problem of the relatively high defect density of the Ge PIN structure on the GOI used in conventional GOI image sensors, further reducing its dark current, and improving the photon absorption rate, peak response and sensitivity of the GOI image sensor.

[0098] The process of forming the second doped layer 240 may include forming a doped material layer 241 on the substrate. Due to the existence of the opening 251, there are protruding parts in the doped material layer 241, as shown in Figure 7 shown; therefore, the doped material layer 241 can be planarized to obtain the second doped layer 240, as shown in Figure 8 shown; then an intrinsic absorption layer 230 is formed on the flat second doped layer 240, as shown in Figure 9 shown; a third doped layer 220 is formed on the intrinsic absorption layer 230, as shown inFigure 10 as described above

[0099] Part of the second doped layer 240 in the opening 251 of the dielectric layer 250 serves as a micro-nano structure, which can efficiently confine the incident light in a tiny area, thereby significantly improving the light absorption efficiency of the GOI image sensor.

[0100] In the embodiment of the present application, the stacked layer can be isolated into multiple parts by isolation trenches 20A along the first direction. Each part serves as a pixel 20B, corresponding to a pair of first electrodes 260 and second electrodes 270. The distance between adjacent pixels 20B is called the pixel pitch, which can be the distance between the center points of two adjacent isolation trenches 20A.

[0101] After forming the third doped layer 220, the stacked layer can also be etched to obtain isolation trenches 20A penetrating the stacked layer. The isolation trenches 20A are along the first direction, refer to Figure 11 and Figure 12 as shown.

[0102] The isolation trenches can penetrate the intrinsic absorption layer 230 and the third doped layer 220, and partially penetrate the second doped layer 240, exposing the second doped layer 240 at the bottom of the isolation trenches. That is, the isolation trenches can be obtained by etching the third doped layer 220, the intrinsic absorption layer 230 and the second doped layer 240; the isolation trenches can also penetrate the stacked layer, exposing the semiconductor layer 130 at the bottom of the isolation trenches. When the isolation trenches do not coincide with the openings 251, they can penetrate the dielectric layer 250. That is, the isolation trenches can be obtained by etching the third doped layer 220, the intrinsic absorption layer 230 and the second doped layer 240 and then etching the dielectric layer 250 or the first doped layer.

[0103] When the stacked layer is separated into multiple parts by the isolation trenches 20A, in the plane perpendicular to the extension direction of the isolation trenches 20A, the shapes of the multiple parts can be rectangular structures (that is, the top and bottom of the isolation trenches 20A have substantially the same width), or trapezoidal structures (that is, the top width of the isolation trenches 20A is greater than the bottom width, making the top width of the pixel less than the bottom width). That is, the shape of at least one of the multiple parts is a trapezoidal structure, and the remaining parts can be rectangular structures or trapezoidal structures. For ease of fabrication, the shapes of all the multiple parts can be set as rectangular structures (refer to Figure 11 as shown) or trapezoidal structures (refer to Figure 12 as shown). The trapezoidal structure can be an isosceles trapezoid.

[0104] In the manufacturing process of GOI image sensors, the manufacturing process of trapezoidal pixel structures is compatible with many traditional semiconductor manufacturing processes, such as lithography, etching, deposition, etc., which can all be applied to the manufacturing of trapezoidal pixels. This enables manufacturers to introduce trapezoidal pixel structures without large-scale equipment upgrades or process modifications, reducing production costs and technical risks. In addition, the trapezoidal pixel structure has good scalability and can be adjusted and optimized according to different application requirements. By changing parameters such as the angle and size of the trapezoid, the requirements for different resolutions, sensitivities, and dynamic ranges can be met, improving the scalability, flexibility, and adaptability of GOI image sensors, which is beneficial for realizing miniaturized, high-resolution, and high-pixel-precision GOI image sensors and promoting their wide applications in scenarios such as smartphones, wearable devices, drones, action cameras, industrial automation, robots, and medical devices.

[0105] The sensor structure may further include a passivation layer 290 on the stacked layer. The passivation layer 290 covers the stacked layer and is used to protect the stacked layer. Then, a passivation layer 290 covering the stacked layer may also be formed, as referred to Figure 13 and Figure 14 shown. The material of the passivation layer 290 is an insulating material, for example, it may be silicon oxide, etc. The passivation layer 290 may cover the bottom and sidewalls of the isolation trench 20A. After forming the first electrode 260 and the second electrode 270, the first electrode 260 may penetrate the passivation layer 290 on the first doped layer to connect to the first doped layer, or penetrate the passivation layer on the second doped layer 240 to connect to the second doped layer 240; the second electrode 270 penetrates the passivation layer 290 on the third doped layer 220 to connect to the third doped layer 220. The first electrode 260 may penetrate the passivation layer 290 at the bottom of the isolation trench 20A to connect to the first doped layer or the second doped layer 240.

[0106] The sensor structure may further include a first electrode 260 and a second electrode 270. After forming the passivation layer 290, the first electrode 260 and the second electrode 270 may also be formed. Specifically, the first electrode 260 may be formed first, as referred to Figure 15 and Figure 16 shown. Before forming the first electrode 260, the passivation layer 290 at the bottom of the isolation trench 20A may also be etched to expose the first doped layer or the second doped layer 240, and then the first electrode 260 in contact with the first doped layer or the second doped layer 240 is formed; then the second electrode 270 is formed, as referred to Figure 17 and Figure 18As shown, before forming the second electrode 270, the passivation layer 290 on the third doping layer 220 can also be etched to expose the third doping layer 220, and then the second electrode 270 in contact with the third doping layer 220 is formed. The first electrode 260 and the second electrode 270 can have the same height or different heights.

[0107] During the manufacturing process of the sensor structure, a wafer bonding method can also be included to realize the bonding of the substrate and the readout circuit wafer. Specifically, the substrate and the film layer thereon can be used as the sensor wafer. After forming the stacked layers included in the sensor structure, the wafer bonding method can be performed, and the wafer bonding method can include: forming the first electrode 260 and the second electrode 270, and then through bump bonding, forming the readout circuit wafer on the first electrode 260 and the second electrode 270.

[0108] In this way, the finally formed sensor structure can also include a readout integrated circuit (ROIC) wafer 300. The readout circuit wafer 300 includes a readout circuit, and the readout circuit is respectively connected to the first electrode 260 and the second electrode 270. In actual operation, the readout circuit can be connected to the first electrode 260 through the first connection structure 310 and connected to the second electrode 270 through the second connection structure 320. In this way, the photo-generated carriers generated in the sensing layer can be respectively transmitted to the first electrode 260 and the second electrode 270 through the first doping layer (or the second doping layer 240) and the third doping layer 220, so that the readout circuit can obtain the current information of the first electrode 260 and the second electrode 270, and thus obtain the optical detection result.

[0109] In this way, after forming the first electrode 260 and the second electrode 270, the sensor wafer including the substrate and the readout circuit wafer 300 can be bonded, refer to Figure 1 and 2 As shown, wherein the first electrode 260 and the second electrode 270 face the readout circuit wafer 300, so that the first electrode 260 and the second electrode 270 can be respectively connected to the readout circuits in the readout circuit wafer. Specifically, the substrate and the readout circuit wafer 300 can be subjected to bump bonding. After that, the substrate can be thinned so that the optical signal can better pass through the acceptor substrate 100 to reach the optoelectronic sensing layer. A dielectric material can be filled between the readout circuit wafer 300 and the passivation layer 290.

[0110] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the structural embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can refer to the description of the method embodiments. A person of ordinary skill in the art can understand and implement it without creative work.

[0111] The above is only the preferred embodiment of the present application. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present application by using the methods and technical contents disclosed above, or modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of protection of the technical solution of the present application.

Claims

1. A sensor structure, characterized in that, Comprising: A substrate including a semiconductor layer; A dielectric layer on the substrate and an opening penetrating the dielectric layer, the opening exposing the semiconductor layer; A second doped layer on the dielectric layer and within the opening; An intrinsic absorption layer on the second doped layer; A third doped layer on the intrinsic absorption layer, the third doped layer having a different doping type from the second doped layer, and the materials of the second doped layer, the intrinsic absorption layer, and the third doped layer include germanium.

2. The sensor structure according to claim 1, characterized in that, The material of the semiconductor layer includes germanium.

3. The sensor structure according to claim 2, wherein, The substrate includes a germanium-on-insulator substrate, a germanium-on-sapphire substrate, or a germanium-on-glass substrate, and the germanium layer in the substrate serves as the semiconductor layer.

4. The sensor structure according to claim 1, wherein, The substrate includes a silicon substrate, a silicon-on-insulator substrate, a silicon-on-sapphire substrate, or a silicon-on-glass substrate, and the silicon layer in the substrate serves as the semiconductor layer.

5. The sensor structure according to claim 1, wherein, The intrinsic absorption layer includes an intrinsic germanium layer or a Ge / GeSi quantum well structure.

6. The sensor structure according to claim 1, wherein The dielectric layer includes one or more stacked negative capacitance material structures, or one or more stacked oxide material structures, or a periodically stacked Bragg reflector structure.

7. The sensor structure according to any one of claims 1-6, characterized in that, The second doped layer, the intrinsic absorption layer, and the third doped layer form a stacked layer, and the stacked layer is isolated into multiple parts by isolation trenches along the first direction, and each part serves as a pixel corresponding to a pair of a first electrode and a second electrode.

8. The sensor structure according to claim 7, wherein, In a plane perpendicular to the extension direction of the isolation trenches, the shape of at least one part among the multiple parts is a trapezoidal structure.

9. The sensor structure according to claim 7, characterized in that The semiconductor layer is doped to be a first doped layer, and the first doped layer has the same doping type as the second doped layer; the isolation trenches extend to the first doped layer.

10. The sensor structure according to claim 7, characterized in that, Further comprising: A passivation layer covering the stacked layer and the isolation trenches, the first electrode penetrating the passivation layer at the bottom of the isolation trenches, and the second electrode penetrating the passivation layer on the third doped layer.

11. The sensor structure according to claim 7, characterized in that, Further comprising: The first electrode and the second electrode; A readout circuit wafer on the first electrode and the second electrode, the readout circuit wafer having a readout circuit, and the readout circuit is respectively connected to the first electrode and the second electrode.

12. A manufacturing method of a sensor structure, characterized in that, Comprising: Providing a substrate including a semiconductor layer; Forming a dielectric layer on the substrate and an opening penetrating the dielectric layer, the opening exposing the semiconductor layer; Forming a second doped layer on the dielectric layer and within the opening; Forming an intrinsic absorption layer on the second doped layer; Forming a third doped layer on the intrinsic absorption layer, the third doped layer having a different doping type from the second doped layer, and the materials of the second doped layer, the intrinsic absorption layer, and the third doped layer include germanium.

13. The method according to claim 12, characterized in that, The material of the semiconductor layer includes germanium.

14. The method according to claim 13, characterized in that, The substrate includes a germanium-on-insulator substrate, a germanium-on-sapphire substrate, or a germanium-on-glass substrate, and the germanium layer in the substrate serves as the semiconductor layer.

15. The method according to claim 12, characterized in that, The substrate includes a silicon substrate, a silicon-on-insulator substrate, a silicon-on-sapphire substrate, or a silicon-on-glass substrate, and the silicon layer in the substrate serves as the semiconductor layer.

16. The method according to claim 12, wherein The intrinsic absorption layer includes an intrinsic germanium layer or a Ge / GeSi quantum well structure.

17. The method according to claim 12, wherein The dielectric layer includes one or more stacked negative capacitance material structures, or one or more stacked oxide material structures, or a periodically stacked Bragg reflector structure.

18. The method according to any one of claims 12-17, characterized in that, The second doped layer, the intrinsic absorption layer, and the third doped layer form a stacked layer, and the method further includes: Etching the stacked layer to obtain isolation trenches penetrating the stacked layer, and the isolation trenches are isolated into multiple parts, and each part serves as a pixel corresponding to a pair of first electrodes and second electrodes.

19. The method according to claim 18, wherein In a plane perpendicular to the extending direction of the isolation trenches, the shape of at least one part of the multiple parts is a trapezoidal structure.

20. The method according to claim 18, wherein The method further includes: Doping the semiconductor layer to make the semiconductor layer serve as a first doped layer; the doping types of the first doped layer and the second doped layer are the same; the isolation trenches extend to the first doped layer.

21. The method according to claim 18, wherein After etching the stacked layer to obtain isolation trenches penetrating the stacked layer, the method further includes: Forming a passivation layer covering the stacked layer and the isolation trenches, the first electrode penetrates the passivation layer at the bottom of the isolation trenches after being formed, and the second electrode penetrates the passivation layer on the surface of the third doped layer after being formed.

22. A wafer bonding method, characterized in that, Including: Providing a sensor structure according to any one of claims 1-10; Forming the first electrode and the second electrode; Forming a readout circuit wafer on the first electrode and the second electrode through bump bonding, the readout circuit wafer has a readout circuit, and the readout circuit is respectively connected to the first electrode and the second electrode.

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