Memory device for precharging bit lines pre sensing memory cells

Abstract

Systems, methods, and apparatus relate to memory devices. In one method, a memory device uses an architecture having a pre-charge transistor in parallel with a cascode transistor. The pre-charge transistor (e.g., a p-channel device) performs pre-charging a bit line to a fixed constant voltage to prepare a sense memory cell. The cascode transistor (e.g., an n-channel device) is used to determine a voltage of the bit line during sensing, and to discharge a sense node if the memory cells switch (e.g., transiently). The sensing node is coupled to an input of a detector that determines a logic state of the memory cell.

Description

[0001] Related applications

[0002] This application claims the benefit of priority of U.S. Patent Application No. 18 / 537,685, filed Dec. 12, 2023, which claims the benefit of priority of U.S. Provisional Patent Application No. 63 / 476,918, filed Dec. 22, 2022, the entire disclosure of which is hereby incorporated herein by reference. Technical Field

[0003] At least some embodiments disclosed herein generally relate to memory devices, and more particularly, but not limited to, a memory device that pre-charges bit lines and / or other access lines prior to sensing the state of memory cells. Background Art

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, a binary device has two states, typically represented by a logic "1" or a logic "0". In other systems, more than two states can be stored. To access the stored information, components of the electronic device can read or sense the stored state in the memory device. To store information, components of the electronic device can write or program a state in the memory device.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and others. Memory devices can be volatile or non-volatile. Non-volatile memory cells can maintain their stored logical state for an extended period even in the absence of an external power source. Volatile memory cells can lose their stored state over time unless they are periodically refreshed by an external power source.

[0006] Storage devices are examples of memory devices. A typical computer storage device has a controller that receives data access requests from a host computer and performs programmed computational tasks to implement the requests in a manner that may be specific to the media and structure configured in the storage device. In some instances, a memory controller manages data stored in memory and communicates with a computer device. In some instances, a memory controller is used in a solid state drive for a mobile device or a laptop computer or in media for a digital camera.

[0007] Firmware can be used to operate the memory controller of a specific storage device. In one instance, when a computer system or device reads data from or writes data to a memory device, it communicates with the memory controller.

[0008] Memory devices typically store data in memory cells. In some cases, the memory cells exhibit non-uniform, variable electrical characteristics, which can stem from various factors, including statistical process variations, cycling events (e.g., read or write operations on the memory cells), or drift (e.g., resistance changes in chalcogenide alloys), etc.

[0009] In one instance, reading a set of data (e.g., a codeword, a page) is performed by determining the read voltage of the memory cells storing the set of data (e.g., the estimated median of the threshold voltages). In some cases, the memory device can include an array of PCM cells arranged in a 3D architecture (e.g., a cross-point architecture) to store a set of data. The PCM cells in the cross-point architecture can represent a first logic state (e.g., logic 1, set state) associated with a first set of threshold voltages, or a second logic state (e.g., logic 0, reset state) associated with a second set of threshold voltages. In some cases, coding (e.g., error correction coding (ECC)) can be used to store data to recover data from errors in the data stored in the memory cells.

[0010] For resistive variable memory cells (e.g., PCM cells), one of several states (e.g., resistance states) can be set. For example, a single-level cell (SLC) can be programmed to one of two states (e.g., logic 1 or 0), which can depend on whether the cell is programmed to a resistance higher or lower than a specific level. As an additional example, various resistive variable memory cells can be programmed to one of multiple different states corresponding to multiple data states, such as 10, 01, 00, 11, 111, 101, 100, 1010, 1111, 0101, 0001, etc. Such cells can be referred to as multi-state cells, multi-digit cells, and / or multi-level cells (MLC).

[0011] The state of a resistive variable memory cell can be determined (e.g., read) by sensing the current passing through the cell in response to an applied interrogation voltage. The sensed current (which varies based on the resistance of the cell) can indicate the state of the cell (e.g., the binary data stored by the cell). The resistance of a programmed resistive variable memory cell can drift (e.g., shift) over time. Resistance drift can lead to incorrect sensing of the resistive variable memory cell (e.g., determining that the cell is in a state different from the state it was programmed to, and other problems).

[0012] For example, a PCM cell can be programmed to a reset state (amorphous state) or a set state (crystalline state). A reset pulse (e.g., a pulse used to program a cell to a reset state) can include a relatively high current pulse applied to the cell for a relatively short period of time so that the cell's phase change material melts and cools quickly, resulting in a relatively small amount of crystallization. Conversely, a set pulse (e.g., a pulse used to program a cell to a set state) can include a relatively low current pulse applied to the cell for a relatively long time interval and with a slower quenching rate (which results in increased crystallization of the phase change material).

[0013] A program signal may be applied to a selected memory cell to program the cell to a target state. A read signal may be applied to a selected memory cell to read the cell (e.g., determine the state of the cell). The program signal and the read signal may be, for example, current and / or voltage pulses. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like reference numerals indicate similar elements.

[0015] Figure 1 A memory device according to some embodiments is shown that first precharges the bit lines in a precharge phase in preparation for sensing memory cells in a memory array, and then turns off the precharge during sensing of the memory cells.

[0016] Figure 2 Exemplary current-voltage (IV) curves of memory cells according to some embodiments are shown.

[0017] Figure 3 Circuitry with parallel precharge and sense paths for detecting the state of a memory cell is shown in accordance with some embodiments.

[0018] Figure 4 Demonstrating some embodiments Figure 3 Exemplary voltage waveforms of a circuit system of FIG.

[0019] Figure 5 Bias circuitry coupled to a fixed voltage source for precharging a bit line and sensing circuitry including a cascode transistor (eg, N1) having a gate coupled to the fixed voltage source are shown in accordance with some embodiments.

[0020] Figure 6 An exemplary three-dimensional memory array structure including memory cells sensed by a detector is shown in accordance with some embodiments.

[0021] Figure 7

[0013] Methods of precharging bit lines prior to sensing memory cells according to some embodiments are shown. Detailed implementation manners

[0022] The following disclosure describes various embodiments of a memory device that senses memory cells in a memory array by using a detector. The memory device first pre-charges bit lines during a pre-charge phase to prepare for sensing the memory cells. After the bit lines are pre-charged, the memory device turns off the pre-charge. Then, the detector senses the logic state of the memory cells.

[0023] The memory device can store, for example, data used by a host device (such as a computing device of an autonomous vehicle or another computing device accessing data stored in the memory device). In one example, the memory device is a solid-state drive installed in an electric vehicle.

[0024] In existing memory devices, a sense amplifier is required to read the memory cells to detect the switching of the cells. In one example, the memory cell is a phase change memory cell (such as a chalcogenide cell), which exhibits snap-back behavior when switching. There are several different types of detectors that can be used to sense the state of the cell by sensing the voltage on the bit line. For example, the detector can use a cascode-based architecture, a sense amplifier-based architecture, or an inverter-based architecture.

[0025] In one example of a cascode-based architecture, a cascode transistor is used in series with a transistor that provides a power supply voltage for pre-charging the memory cell. The presence of the cascode transistor (and sometimes other transistors) in series with the power supply voltage for pre-charging results in a large amount of time being required to pre-charge the memory cell. In addition, due to the voltage drop across the series cascode transistor, the cascode transistor requires a higher power supply voltage. In part, because an n-channel cascode transistor is used with a positive power supply voltage, the length of the pre-charge is longer. This results in an exponential pre-charge bit line voltage waveform with a long tail.

[0026] Another problem is that a reference current is used to sense each memory cell, but the leakage current of other cells in the memory array is highly variable and affects the sensing. Due to the random nature of the leakage (such as variations at different positions and / or for different patterns of cells in the memory array), it is difficult to select an appropriate reference current that is greater than this leakage. Therefore, in practice, the reference current must be set higher than desired. This results in excessive power consumption. The leakage current can also cause false detection of memory cell switching by prematurely pulling down the voltage on the input node of the detector of the sense circuit system.

[0027] In addition, there is a problem that the threshold voltage of the cascode transistor may vary significantly from one sense amplifier to another. This results in a variation in the voltage reached by the bit line, even if the gate voltage on the cascode transistor is constant for all sense amplifiers.

[0028] To solve the above and other technical problems, the memory device uses an architecture having a precharge transistor in parallel with the cascode transistor. The precharge transistor (e.g., a p-channel MOS device) performs precharging of the bit line to prepare for sensing the memory cell. The cascode transistor is used to determine the voltage of the bit line during sensing.

[0029] The advantage of using the precharge transistor is that the bit line can be raised to a fixed value of the supply voltage (e.g., vp). The precharge transistor (e.g., Figure 3 P1) provides a precharge current to increase the bit line voltage. This avoids passing the precharge current through the cascode transistor as in the above-mentioned existing devices.

[0030] This parallel precharge structure can provide another advantage. For example, the supply voltage can be provided by a voltage regulator. The supply voltage is a constant fixed value for all sense amplifiers in the memory device. Therefore, when the sensing operation starts, the cascode device does not determine the initial voltage of the bit line.

[0031] Furthermore, the precharging is faster because the precharge current does not need to pass through the cascode transistor. Instead, the precharge transistor (e.g., a PMOS device) pulls up the bit line voltage faster than the existing devices. In one example, the bit line can reach the supply voltage (e.g., vp) in about 5 nanoseconds (ns). In contrast, existing devices precharged through the cascode transistor require about 20 ns.

[0032] In one embodiment, the memory device includes a memory array having memory cells. The bit line is coupled to at least one first memory cell. The bias circuit system includes a first transistor (e.g., P1) that couples a supply voltage (e.g., vp) to the bit line. The first transistor is configured to precharge the bit line.

[0033] The sense circuit system includes a detector having an input (e.g., node qv) coupled to the bit line. The detector is configured to detect whether the first memory cell has reached a threshold (e.g., a transient). A current source (e.g., iref) is coupled to provide a reference current to set the voltage of the input of the detector.

[0034] The sense circuit system further includes a second transistor (e.g., an n-channel cascode transistor) (e.g., N1) that couples the input of the detector to the bit line. The second transistor is configured to change the voltage of the detector input when the first memory cell reaches the threshold.

[0035] In one example, a memory array has chalcogenide memory cells in a three-dimensional cross-point architecture. Word lines and bit lines are each biased to access at least one memory cell in the array.

[0036] The embodiments described herein provide various advantages. For example, these advantages include a higher read window budget, lower power consumption, lower supply voltage, and / or faster timing.

[0037] In one example, the precharge voltage is equal for all bit lines, and the cascode device characteristic mismatch does not affect the read window budget (rwb). The precharge timing is fast. The supply voltage is the same as the voltage biasing the bit lines. For example, the supply voltage can be 2.5V instead of 3.2V in existing devices.

[0038] In one exemplary advantage, the charge that leaks away during sensing flows through a precharge transistor (e.g., P1 pass transistor) and not through the cascode transistor. Thus, the gate-to-source voltage (vgs) of the detector is zero before the memory cell snapback, which avoids false reads of the memory cell (e.g., node qv remains at vp).

[0039] Figure 1 A memory device 101 is shown in accordance with some embodiments that precharges bit lines during a precharge phase to prepare to sense memory cells 110 in a memory array 102 and turns off precharging during sensing of the memory cells. In one example, the memory cells 110 are chalcogenide memory cells. In one example, a controller 120 controls the timing of turning precharging on and off.

[0040] A sense circuit system 122 senses the state of the memory cells 110. The sense circuit system 122 includes a detector 130. In one example, the detector 130 is a transistor, an inverter, or a differential amplifier. Access lines 140 are used to select the memory cells 110. In one example, the access lines 140 include word lines and bit lines in a cross-point memory array.

[0041] A bias circuit system 124 biases selected access lines in the access lines 140 for selecting a portion of the memory cells 110 to be sensed. The bias circuit system 124 also powers the sense circuit system 122, including powering the detector 130.

[0042] A memory controller 120 controls various operations of the memory device 101, including read and write operations to the memory cells 110. The memory controller 120 includes a processing device 116 and a memory 118. Some operations are controlled by the controller 120 in response to various commands received from a host device 126 at a communication interface 150.

[0043] In one embodiment, the communication interface 150 receives a read command from the host device 126. In response to receiving the read command, the controller 120 initiates a read operation. As part of the read operation, a memory cell 110 is selected such that its logical state is determined by the sense circuitry 122.

[0044] The bias circuitry 124 drives the voltage on the access lines 140 to select the memory cell, including driving the voltage on the bit lines used to select the memory cell. To sense the state of the memory cell, the detector 130 monitors the voltage on the bit lines.

[0045] In one embodiment, during a precharge phase, the precharge circuitry as discussed above is used to first drive the voltage on the bit lines to an initial voltage (e.g., vp). After the bit lines reach the initial voltage, the precharge is turned off. Then, the detector 130 is used to detect whether the bit line voltage has been pulled down because the memory cell 110 has reached a switching threshold.

[0046] The voltage regulator 160 provides one or more fixed supply voltages used by the memory device 101. In one embodiment, a fixed supply voltage (e.g., vp) is provided to the bias circuitry 124 for precharging the bit lines connected to one of the memory cells 110. The same fixed supply voltage can be used to power the detector 130.

[0047] It should be noted that various embodiments herein relate to precharging the bit lines under a positive supply voltage polarity. In other embodiments, the polarity can be reversed such that the circuitry uses a negative supply voltage in a manner similar to that described herein for the positive supply voltage. Additionally, in other embodiments, instead of or in addition to the bit lines as discussed herein, word lines or other access lines can be precharged and sensed.

[0048] The detector 130 detects a change in the voltage on the bit lines caused by the switching of the memory cell (e.g., exhibiting a snapback). The output of the detector 130 is used by the sense circuitry 122 to determine the logical state (e.g., 1 or 0) of the read memory cell.

[0049] In one embodiment, the memory cell 110 stores user data for the host device 126. The memory cell 110 stores data in a first logical state or a second logical state. In an example, the bias circuitry 124 includes word line and bit line drivers (not shown) to bias the word lines and bit lines of the memory array 102.

[0050] The sense circuitry 122 can include sense amplifiers for sensing characteristics associated with the memory cells of the memory array 102. The characteristics can be, for example, the voltage and / or current associated with the selected memory cell.

[0051] In one embodiment, the controller 120 causes the bias circuitry 124 to apply a voltage to a selected memory cell 110. In one example, the voltage is a voltage value that increases in magnitude in steps (e.g., 0.5V steps), such as +2, +2.5, +3, +3.5, +4, +4.5, +5V.

[0052] In one embodiment, the memory controller 120 includes one or more processing devices 116 and memory 118. In one example, the memory 118 stores firmware that is executed by the processing device 116 to select and apply read voltages. The memory controller 120 may use the bias circuitry 124 to generate voltages for applying read and other voltages (e.g., initial read and read retry). The bias circuitry 124 may also generate a voltage to apply a write voltage to the memory cell 110 as part of a programming operation.

[0053] In one embodiment, if the sense circuitry 122 determines that the current of the memory cell is greater than a fixed threshold (e.g., a predetermined current level), then the memory controller 120 determines that the memory cell has switched (e.g., transient).

[0054] In one embodiment, the memory controller 120 receives a write command from the host device 126. The write command is accompanied by data to be written to the memory array 102 (e.g., user data of a user of the host device 126). In response to receiving the write command, the controller 120 initiates a programming operation.

[0055] In one example, the polarity of a read or write pulse may be a first polarity or a second polarity. For example, a write pulse may apply a voltage to the memory cell with a first polarity (e.g., the bit line at 6V and the word line at 0V).

[0056] In one example, a read pulse is provided using circuitry coupled to an access line to which the memory cell may be coupled (e.g., an access line driver included in a decoder circuit). The circuitry may be controlled by an internal control signal provided by control logic (e.g., the controller 120). The read voltage or pulse may be a voltage applied to the memory cell for a period of time (e.g., 10 to 50 ns, 1 to 100 ns, 1 ns to 1 microsecond). In some embodiments, the read pulse may be a square pulse. In some embodiments, the read pulse may be a ramp, i.e., a linearly increasing voltage may be applied across the memory cell.

[0057] In one example, after being accessed (e.g., selected), a memory cell can be read or sensed by a sensing component (e.g., sensing circuitry 122) to determine the storage state of the memory cell. For example, a voltage can be applied to the memory cell (using a word line and a bit line), and the presence of a resulting current can depend on the applied voltage and the threshold voltage of the memory cell. In some cases, more than one voltage can be applied. Additionally, if the applied voltage does not cause current flow, other voltages can be applied until the sensing component detects a current.

[0058] By evaluating the voltage that causes current flow, the stored logical state of the memory cell can be determined. In some cases, the magnitude of the voltage can be ramped up until current flow is detected (e.g., the memory cell turns on, conducts, conducts current, or becomes activated). Similarly, a current can be applied to the memory cell, and the magnitude of the voltage used to generate the current can depend on the resistance or threshold voltage of the memory cell.

[0059] In some cases, a memory cell (e.g., a PCM cell) includes a material that changes its crystal configuration (e.g., between a crystalline phase and an amorphous phase), and the crystal configuration in turn determines the threshold voltage of the memory cell for storing information. In other cases, a memory cell includes a material that is maintained in a crystal configuration (e.g., an amorphous phase) that can exhibit a variable threshold voltage for storing information.

[0060] The sensing component can include various transistors or amplifiers to detect and amplify differences in signals. Then, the detected logical state of the memory cell can be output as an output through a column decoder. In some cases, the sensing component can be part of a column decoder or a row decoder.

[0061] At least some embodiments herein relate to a memory device that uses bipolar operation for a memory array (e.g., for multi-level memory cells). In one example, bipolar select voltages are used to select memory cells of a memory array. In one example, the memory cells are arranged in a cross-point architecture. In one example, each memory cell is formed using a single select device. In one example, the select device includes a chalcogenide material that switches (e.g., transients) when a sufficient voltage is applied across the memory cell.

[0062] In some cases, a memory device can include an array of memory cells arranged in a three-dimensional (3D) architecture (e.g., a cross-point architecture) to store a set of data. The memory cells in the cross-point architecture can represent, for example, a first logical state (e.g., logic 1, set state) associated with a first set of threshold voltages, or a second logical state (e.g., logic 0, reset state) associated with a second set of threshold voltages.

[0063] In other embodiments, memory cells may be arranged in a three-dimensional (3D) vertical architecture. The 3D vertical architecture may include memory cells located at intersections between vertical access lines (e.g., bit line pillars) and each of a plurality of second access lines (e.g., word lines) formed in horizontal planes or levels parallel to each other.

[0064] More generally, integrated circuit memory cells (e.g., cross-point memory or memory cells in a 3D vertical array) may be programmed to store data by their state under a voltage applied across the memory cell. For example, if a memory cell is configured or programmed to allow a large amount of current to pass through the state of the memory cell at a voltage in a predefined voltage region, then the memory cell is considered to have been configured or programmed to store a first bit value (e.g., 1 or 0); otherwise, the memory cell stores a second bit value (e.g., 0 or 1).

[0065] Optionally, a memory cell may be configured or programmed to store more than one bit of data by being configured or programmed to have a threshold voltage, for example, in one of more than two separate voltage regions.

[0066] In one example, the threshold voltage of a memory cell is such that when the voltage applied across the memory cell increases above the threshold voltage, the memory cell switches by a rapid or sudden change, a transient (e.g., for a chalcogenide memory cell), or a jump from a non-conducting state to a conducting state. The non-conducting state allows a small leakage current to pass through the memory cell; and in contrast, the conducting state allows a current above a threshold amount to pass through. Thus, a memory device may use a detector (e.g., a sense amplifier) to detect the change, or to determine the conducting / non-conducting state of the memory device under one or more applied voltages, to evaluate or classify the level of the threshold voltage of the memory cell and thus evaluate or classify the data stored therein.

[0067] The threshold voltages of memory cells configured / programmed to be in different voltage regions may be used to represent different data values stored in the memory cells. For example, the threshold voltage of a memory cell may be programmed to be in any one of four predefined voltage regions; and each of the regions may be used to represent the bit values of different two-bit data items. Thus, when a given two-bit data item is provided, one of the four voltage regions may be selected based on the mapping between the two-bit data item and the voltage region; and the threshold voltage of the memory cell may be adjusted, programmed, or configured to be in the selected voltage region to represent or store the given two-bit data item.

[0068] To retrieve, determine, or read a data item from a memory cell, one or more read voltages may be applied across the memory cell to determine which of four voltage regions contains the threshold voltage of the memory cell. Identification of the voltage region containing the threshold voltage of the memory cell provides the two-bit data item that has been stored, programmed, or written into the memory cell.

[0069] For example, a memory cell may be configured or programmed to store one-bit data items in a single-level cell (SLC) mode, or two-bit data items in a multi-level cell (MLC) mode, or three-bit data items in a three-level cell (TLC) mode, or four-bit data items in a four-level cell (QLC) mode.

[0070] Figure 2 Exemplary current-voltage (I-V) curves of a memory cell according to some embodiments are shown. As illustrated, the current I through the memory cell increases monotonically (in the leakage region) as the voltage V applied across the memory cell increases.

[0071] The current increases as the voltage increases until the threshold voltage of the memory cell is reached. At this point, the memory cell switches and exhibits snapback behavior as illustrated, where the current through the memory cell rapidly increases. For example, this current through the memory cell after snapback pulls down the voltage on the selected bit line, such that the detector 130 detects that the memory cell has reached the threshold and has switched.

[0072] As an example, the illustrated I-V curves are for chalcogenide memory cells. Other types of phase change memory cells exhibit similar snapback behavior. In one example, the illustrated I-V curves are for one of the memory cells 110.

[0073] Figure 3 Circuitry according to some embodiments is shown having a parallel precharge and sense path for precharging the bit line 310 and then detecting the state of the memory cell 302. The precharge path includes a p-channel transistor P1 that couples the supply voltage vp to the bit line 310. The sense path includes a cascode transistor N1 that couples to the bit line 310.

[0074] The bit line 310 is used to select the memory cell 302 for sensing. The memory cell 302 is an example of a memory cell 110. A word line 312 is also connected to the memory cell 302. When sensing, a bias voltage is applied across the memory cell 302. The bias voltage is applied by biasing the bit line 310 and the word line 312.

[0075] When precharging the bit line 310, the voltage of the bit line 310 rises to the supply voltage vp through the pull-up transistor P1. The transistor P1 is turned on and off by applying a gate voltage (such as the signal ignite! as described).

[0076] When the bit line voltage has been precharged to vp, the transistor N1 is in the off state. The gate voltage casc of the select transistor N1 is selected such that vp > v(casc) - vt(N1), where v(casc) is the gate voltage of the transistor N1 and vt(N1) is the threshold voltage of the transistor N1.

[0077] After precharging the bit line 310 to the voltage vp, the transistor P1 is turned off to enter the sensing phase to determine the state of the memory cell 302. If the memory cell 302 has switched during the precharging phase, then in the sensing phase, the memory cell current (e.g., the cell current due to snapback) will sufficiently pull down the bit line voltage such that the transistor N1 turns on. The transistor N1 turns on when the voltage of the bit line 310 is less than v(casc) - vt(N1).

[0078] When turned on, the transistor N1 pulls down the voltage of the node qv. This reduces the gate voltage of the detector transistor 304 such that the voltage of the evaluation node 306 is pulled up to the voltage vp by the transistor 304. The evaluation node 306 can be provided as an output from the detection circuit system. For example, this output can be used by the controller 120 to determine the logical state of the memory cell 302. In one instance, the transistor 304 is part of the detector 130.

[0079] The current source 314 provides a reference current iref for precharging the node qv and raising the voltage of the node qv to the supply voltage vp. In the case where the memory cell 302 does not switch, the voltage of the bit line 310 remains high enough such that the transistor N1 does not turn on and the node qv remains at the voltage vp. In this case, the detector transistor 304 remains off and the evaluation node 306 does not change state (e.g., the voltage of the node 306 remains low) (e.g., remains at the negative supply voltage VSS).

[0080] It should be noted that the reference current iref can be relatively small because, as discussed above, the transistor N1 is in the off state at the end of the precharging of the bit line 310. This allows the node qv to be maintained at the voltage vp such that false detection of memory cell switching is avoided.

[0081] The transistor 308 is used to reset the detection circuit system to prepare for each memory cell sensing operation. The gate voltage Reset is applied to the transistor 308 to control the reset of the detection circuit system. For example, the transistor 308 pulls down the voltage of the evaluation node 306 to VSS during reset.

[0082] In one example, the voltage regulator 160 provides a fixed voltage vp. The n-channel cascode transistor N1 is turned on only when the bitline voltage is less than vp. Thus, precharging the bitline to vp means that the transistor N1 is off. For example, if vp is equal to 2V and the gate voltage casc is equal to 1.5V, then the bitline 310 must drop to 1V to turn on the transistor N1. The reference current iref maintains the node qv at vp until the transistor N1 conducts.

[0083] In one example, the transistor P1 is turned off after the memory cell 302 has switched. The bitline 310 voltage is pulled down by a significant current through the memory cell 302. The transistor N1 conducts. The reference current has been selected to be 0.1 to 0.5 μA. The node qv drops and the detector transistor 304 conducts. In contrast, if the memory cell 302 has not switched, then the bitline 310 remains floating and the bitline voltage remains high (except to the extent reduced by leakage current in the memory array; see, for example Figure 4 the waveform portion 410 in).

[0084] In one example, the bitline 302 is precharged by setting the voltage ignite! low (e.g., at VSS) to turn on the transfer transistor P1. This avoids the problem of slow precharging obtained through the cascode transistor N1 as in the above-described prior art devices. Since the voltage casc is selected such that the voltage vp > v(casc) - vt(N1), the transfer transistor N1 is off.

[0085] The snapback of the memory cell 302 is detected by comparing the total cell current with the reference current iref. To this end, during the precharging of the bitline, the transfer transistor P1 is maintained in the on state only for a defined time interval. In other words, the transistor P1 is only used to trigger (cause) the snapback of the cell 302. After the time interval ends, the transistor P1 is turned off (the voltage of the signal ignite! goes high).

[0086] When the transistor P1 is turned off (e.g., disconnected), two possible cases for the memory cell 302 are expected: (i) the cell has not been switched, or (ii) the cell has been switched.

[0087] If the cell has not been switched, then leakage in the memory array slowly discharges the main bitline 310. As the bitline voltage decreases, then the leakage itself will decrease and the transistor N1 remains off. Alternatively, if the bitline voltage decreases enough to turn on the transistor N1, then the leakage will be lower than the reference current iref. Thus, the node qv remains high and the detector is off.

[0088] If the cell has switched (e.g., a snapback has occurred), then the bitline voltage will see a drop and transistor N1 will conduct. The cell current is compared to a reference current iref, and if higher, then node qv goes low and the detector will turn on (detection of cell switching has occurred).

[0089] The reference current iref will flow in transistor N1 only when the voltage (bitline) < v(casc) - vt(N1). There is design flexibility in choosing the desired voltage level under which the reference current is compared to the cell current (icell). For example, if vp = 2.5V, then v(casc) can be chosen such that v(casc) - vt(N1) = 1.5V.

[0090] Thus, when the current iref starts to flow (e.g., v(bitline) = 1.5V), the leakage will be very low compared to the leakage of the prior art devices discussed above (e.g., measured when the voltage (bitline) = vp). Thus, the leakage will not cause the gate voltage of detector transistor 304 to change, and this avoids false detection by the detector. Additionally, the precharged bitline voltage will be equal for each sense amplifier, and for this reason, device characteristic mismatches of transistor N1 between the various sense amplifiers in the memory device will not affect the various read operations.

[0091] An exemplary advantage of the above architecture is that the precharge voltage is equal for all bitlines of the memory device, and the cascode transistor N1 device characteristic mismatches do not affect the read window budget. The bitline voltage is determined by the regulated voltage vp of the architecture, so there is no difference between different bitlines from the perspective of the bias voltage.

[0092] In an alternative embodiment, current source 314 is not required. Node qv has a relatively low capacitance. Node qv can be kept floating without using a reference current. In one embodiment, a small capacitor can be added to node qv if desired.

[0093] Figure 4 Shows exemplary voltage waveforms of a Figure 3 circuit system in accordance with some embodiments. The vertical axis indicates voltage and the horizontal axis indicates time.

[0094] The sense operation starts by resetting the detection circuit system. This is done by switching the reset voltage high at time 401. This causes the voltage of evaluation node 306 to be pulled low to prepare to sense memory cell 302.

[0095] The transistor P1 is turned on and off at various stages at an exemplary timing, as illustrated by changing the gate voltage using the signal ignite!. For example, the transistor P1 is turned on at stages 400, 404, 416, and is turned off at stages 402, 405, 418.

[0096] At time 401, the transistor P1 is turned on. As a result, the bit line voltage increases to the voltage vp, as discussed above. Additionally, the node qv is pulled up to the voltage vp by the reference current iref, as discussed above. As discussed above, the transistor N1 is turned off near the end of the precharge phase. The point at which the transistor N1 is turned off is partially determined by the gate voltage casc that is selected to be used.

[0097] After precharge is complete, the transistor P1 is turned off at stage 402. As a result, due to leakage in the memory array, the bit line voltage begins to decrease at section 410. The memory cell has not yet switched, so the evaluation node voltage remains low because the detector has not been triggered by the input voltage of node qv.

[0098] The transistor P1 is turned on again at stage 404. This again pulls up the voltage of the bit line to the voltage vp. The magnitude of the word line voltage is increased in the first increment step 412.

[0099] In stage 405, the transistor P1 is turned off again. However, the voltage across the memory cell is not yet sufficient to cause the memory cell to switch. Therefore, at stage 416, the transistor P1 is turned on again to precharge the bit line back to the voltage vp. The magnitude of the word line voltage is increased in the next increment step 414.

[0100] In stage 418, the transistor P1 is turned off again so that the senseable memory cell can be determined whether the cell has switched. The difference between the bit line voltage and the word line voltage applied across the memory cell is now sufficient (e.g., exceeds the threshold voltage of the memory cell) to cause the memory cell to switch. At time 406, this switching of the cell is detected at node qv by pulling down node qv due to significant current flowing through the switched memory cell. This causes the output of the evaluation node 306 to change state by going from low to high.

[0101] As a result of the memory cell switching, the voltage of the bit line is pulled to a lower voltage level below 408. More generally, it should be noted that the leakage current is greater when the voltage of the bit line is close to the higher voltage level 407. The leakage current is lower when the voltage of the bit line is close to the lower voltage level 408. In one example, the lower voltage level 408 is the gate voltage casc applied to the transistor N1 minus the threshold voltage of the transistor N1, which can be expressed as v(casc) - vt(N1).

[0102] In one embodiment, the gate voltage v(casc) is selected such that the leakage current at the lower voltage level 408 is negligible and the transistor N1 is not turned on at the lower voltage level 408. Instead, the transistor N1 is turned on only when the memory cell switches and pulls the bit line voltage below the lower voltage level 408. The leakage current cannot conduct the cascode transistor N1 because the leakage becomes negligible as the bit line voltage decreases. This allows for the use of a lower reference current iref compared to existing sense amplifiers.

[0103] The transistor N1 discharges the node qv such that its voltage is pulled down when the memory cell switches. As mentioned above, this causes the detector transistor 304 to pull up the voltage of the evaluation node 306, indicating that the memory cell has switched. For example, the voltage of the evaluation node 306 can be provided as an output to the controller 120 to indicate the logical state of the memory cell.

[0104] In one instance, the timing of memory cell sensing is implemented as follows:

[0105] 1. Reset the evaluation node 306 and start bit line precharging (ignite!= 0).

[0106] 2. Precharging is off (ignite!= 1), and leakage slowly discharges the bit line.

[0107] 3. Precharging is on (ignite!= 0), and the word line starts from the first increment step.

[0108] 4. Precharging is off (ignite!= 1).

[0109] 5. Precharging is on (ignite!= 0), and a snapback occurs; the bit line voltage drops.

[0110] When ignite!= 0, an attempt is made to trigger (switch) the memory cell. The magnitude of the voltage across the memory cell can be expressed as cell voltage = vp + v(word line). When the cell voltage has sufficient magnitude, the cell switches. When ignite!= 1, if a snapback has occurred, then the voltage of the node qv drops to trigger (turn on) the detector.

[0111] In one embodiment, the leakage is an exponential function of the bit line voltage. As illustrated (e.g., bit line waveform portion 410), the leakage rate decreases as the bit line voltage decreases. Thus, below the lower voltage level 408, the leakage is negligible.

[0112] When the memory cell transients, the bit line voltage is pulled down and the transistor N1 is turned on. The voltage of the node qv drops and the detector conducts. The advantage of this architecture is that the initial voltage of the node qv is equal to the bit line precharge voltage vp. This reduces the power consumption compared to existing sense amplifiers.

[0113] In one embodiment, the reference current iref is not used to balance the leakage current associated with the bit line. This is because transistor N1 is turned on only when the leakage is negligible, as mentioned above. Thus, the reference current iref can be, for example, 0.1 microampere (μA). In contrast, the reference current of existing sense amplifiers needs to be 5 to 10 μA.

[0114] In one embodiment, as a design choice, the reference current iref can be slightly increased to compensate for a tolerable low level of leakage at the lower voltage level 408. This will allow the lower voltage level 408 to be raised to a slightly higher level. For example, this increase in the reference current iref may be 0.1 μA.

[0115] Figure 5 Disclosed is a bias circuit system coupled to a fixed voltage source (e.g., vp) for precharging a bit line, according to some embodiments, and a sense circuit system including a transistor (e.g., N1) having a gate coupled to the fixed voltage source. The bias circuit system includes transistor P1, which has a current terminal coupled to the fixed voltage vp.

[0116] Figure 5 has an architecture similar to Figure 3 except that the gate 504 of transistor N1 is connected to the fixed voltage source. In addition, transistor 502 has been added to latch the output value on the evaluation node 306.

[0117] In one instance, the fixed voltage source is a constant value vp. In one instance, the voltage vp is provided by a voltage regulator 160.

[0118] This architecture provides advantages by using the fixed voltage vp as the gate voltage of transistor N1. This can avoid the need to create an additional voltage regulator in the periphery of the memory device chip. In addition, the fixed voltage vp for precharging the bit line is constructed to be higher than the bit line voltage vp - vt(N1) required to turn on transistor N1 on the bit line, as discussed above.

[0119] Figure 6 Disclosed is an exemplary three-dimensional memory array structure including memory cells sensed by a detector, according to some embodiments. In one instance, the memory cells are memory cells 110 sensed by Figure 1 detector 130.

[0120] The memory arrays and memory cells described herein are not limited to use in a planar architecture (e.g., where the cells are at the intersections of word lines (WL) and bit lines (BL) on different levels). Instead, the method can also be used in a vertical architecture (e.g., where vertical BL columns intersect horizontal WL planes).

[0121] Figure 6 Describe examples of a vertical architecture that can be used with the embodiments described in this disclosure. As illustrated, the memory array includes memory cells 1102, 1103. The memory array is formed above a semiconductor substrate 902. In one example, the semiconductor substrate 902 includes logic circuitry. In one example, the logic circuitry provides at least a portion of the bias circuitry 124 and / or the sense circuitry 122.

[0122] Each memory cell 1102, 1103 can be selected using word lines (e.g., 1106, 1107, or 1108) and digit lines (e.g., 1110). Each digit line is coupled to a bit line post (e.g., 1104) through a selection transistor (selector). The memory cells 1102, 1103 are Figure 1 examples of the memory cells 110 of

[0123] In one embodiment, each word line extends in one of a plurality of horizontal planes of word lines 1106, 1107, 1108 stacked vertically above the semiconductor substrate 902. Each digit line (e.g., 1110) is coupled to a bit line post 1104. Each bit line post 1104 extends vertically away from the semiconductor substrate 902. Each memory cell 1102, 1103 is located on a side of one of the bit line posts 1104.

[0124] In one embodiment, the memory array has a vertical array architecture that includes vertical bit lines (e.g., vertical posts 1104) that intersect a plurality of horizontal levels of word lines (e.g., even word lines 1106 and odd word lines 1107). Each level is configured as two intersecting word line combs such that each bit line forms two cells 1102, 1103 at each level. In one example, the even word lines 1106 and the odd word lines 1107 intersect in a comb-like structure as illustrated.

[0125] Figure 7 Show a method for precharging a bit line before sensing a memory cell according to some embodiments. For example, Figure 7 the method can be implemented in a Figure 1 system. In one example, the bit line is one or more of the access lines 140 precharged by the bias circuitry 124 using a fixed voltage provided by a voltage regulator 160.

[0126] Figure 7 The method can be executed by processing logic that can include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, Figure 7The method is at least partially performed by one or more processing devices (e.g., Figure 1 controller 120).

[0127] Although shown in a particular sequence or order, the order of the process may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in a different order and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Accordingly, not all processes are required in every embodiment. Other process flows are possible.

[0128] At block 701, reset the detector to prepare for the sensing operation. In one example, reset detector 130. In one example, turn on transistor 308 to reset evaluation node 306.

[0129] At block 703, precharge the bit line to prepare for the sensing operation. In one example, precharge bit line 310 to voltage vp by turning on transistor P1.

[0130] At block 705, apply a read voltage to the word line as part of the sensing operation. In one example, apply a voltage to word line 312 at step 414.

[0131] At block 707, turn off the precharge of the bit line. In one example, turn off the precharge by turning off transistor P1 in phase 418.

[0132] At block 709, detect the logic state of the memory cell. In one example, sense memory cell 302 to determine whether memory cell 302 has switched. In one example, memory cell 302 switches such that the voltage of node qv is pulled down, which turns on detector transistor 304.

[0133] At block 711, provide an output indicating the logic state of the memory cell. In one example, detector transistor 304 turns on and raises evaluation node 306 to a high voltage state indicating that a switch of memory cell 302 has been detected. In one example, controller 120 determines the logic state of the memory cell based on sampling the voltage of evaluation node 306.

[0134] In one embodiment, a device includes: a memory array having memory cells; bit lines coupled to at least one first memory cell; a first transistor (e.g., P1) that couples a supply voltage (e.g., vp) to the bit line, wherein the first transistor is configured to precharge the bit line; a detector having an input (e.g., node qv) coupled to the bit line, wherein the detector is configured to detect whether the first memory cell has reached a threshold; a current source (e.g., iref) coupled to provide a reference current to set the voltage of the input of the detector; and a second transistor (e.g., N1) that couples the input of the detector to the bit line, wherein the second transistor is configured to change the voltage of the detector input when the first memory cell reaches the threshold.

[0135] In one embodiment, the second transistor is in an off state at the end of the precharging of the bit line by the first transistor (e.g., when the bit line voltage has been precharged to vp, transistor N1 turns off).

[0136] In one embodiment, the first transistor is in an on state when precharging the bit line and in an off state when the detector is detecting whether the first memory cell has reached the threshold.

[0137] In one embodiment, the first transistor is a p-channel device and the second transistor is an n-channel device.

[0138] In one embodiment, the first current terminal of the first transistor (e.g., Figure 5 P1) is coupled to the gate of the second transistor (e.g., Figure 5 N1), and the second current terminal of the first transistor is coupled to the bit line (e.g., 310).

[0139] In one embodiment, the current source (e.g., 314) is configured to drive the input of the detector to the supply voltage.

[0140] In one embodiment, the first transistor is configured to precharge the bit line to the supply voltage.

[0141] In one embodiment, a system includes: a communication interface (e.g., 150) configured to receive a read command from a host device (e.g., 126); sensing circuitry (e.g., transistor N1 and p-channel detector) configured to sense memory cells of a memory device; biasing circuitry (e.g., transistor P1) configured to bias a first access line and a second access line each coupled to at least one first memory cell, the biasing including biasing the first access line to a first voltage to prepare for sensing the first memory cell, wherein the biasing circuitry is further configured to turn off biasing the first access line to the first voltage when sensing the first memory cell; and a controller configured to: in response to receiving the read command, initiate a read operation; as part of the read operation, use the biasing circuitry to bias the first access line (e.g., bit line) to the first voltage (e.g., vp); as part of the read operation, use the biasing circuitry to apply a voltage to the second access line (e.g., word line); and after applying the voltage to the second access line, use the sensing circuitry to sense the first memory cell to determine whether the first memory cell has reached a threshold.

[0142] In one embodiment, the first access line is a bit line and the second access line is a word line.

[0143] In one embodiment, the first access line is coupled to an input (e.g., the gate of detector transistor 304) of a detector (e.g., 130), and in response to the first memory cell reaching a threshold, the voltage of the input reaches a detection threshold (e.g., node qv drops below the threshold voltage of the p-channel detector).

[0144] In one embodiment, the sensing circuitry includes an n-channel transistor (e.g., cascode transistor N1), and the first access line is coupled to the input of the detector through the n-channel transistor.

[0145] In one embodiment, the system further includes a voltage regulator (e.g., voltage source vp) having an output for providing the first voltage, wherein the biasing circuitry includes a p-channel transistor (e.g., P1), and the p-channel transistor couples the output of the voltage regulator to the first access line.

[0146] In one embodiment, the controller is further configured to: after sensing a first memory cell that has not switched, turn on the bias of the first access line to a first voltage (e.g., stage 404); after biasing the first access line to the first voltage, turn off the bias of the first access line to the first voltage (e.g., stage 405); increase the magnitude of the voltage applied to the second access line (e.g., increase the step voltage on the word line) (e.g., increase the voltage to a new level at step 414); and after increasing the magnitude of the voltage applied to the second access line, sense the first memory cell (e.g., sense the memory cell in stage 418), while the bias of the first access line to the first voltage is turned off.

[0147] In one embodiment, the sense circuit system (e.g., 122) includes a transistor (e.g., N1) that couples the sense circuit system to the first access line; and the first voltage is applied to the gate of the transistor when the first access line is biased to the first voltage and when the first memory cell is sensed.

[0148] In one embodiment, a method includes: resetting a detector (e.g., 130) to prepare for a sensing operation, where the detector is configured to determine a logical state of a memory cell in a three-dimensional cross-point memory array formed over a semiconductor substrate, where bit lines of the memory array are coupled to at least one first memory cell and extend above the semiconductor substrate in a vertical direction, and where word lines of the memory array are coupled to the first memory cell and extend above the semiconductor substrate in a horizontal direction; precharging the bit lines to prepare for the sensing operation; as part of the sensing operation, applying a read voltage to the word lines; turning off the precharging of the bit lines; after turning off the precharging of the bit lines, detecting the logical state of the first memory cell; and providing an output (e.g., evaluation node 306) indicative of the logical state of the first memory cell.

[0149] In one embodiment, the first memory cell is a self-selecting memory cell, and the magnitude of the bias voltage applied across the first memory cell during a sensing operation corresponds to the threshold voltage of the first memory cell.

[0150] In one embodiment, applying the read voltage includes incrementing the read voltage by increasing the magnitude of the read voltage for each increment during the sensing operation. In one example, during the sensing operation, the voltage on the word line is increased at steps 412 and 414.

[0151] In one embodiment, a voltage source (e.g., regulator 160 providing a constant voltage vp) is coupled to a bit line through a first transistor (e.g., P1), and precharging the bit line includes turning on the first transistor (e.g., using the signal ignite!).

[0152] In one embodiment, a second transistor (e.g., N1) couples the bit line to an input of a detector, and the voltage source is coupled to a gate of the second transistor.

[0153] In one embodiment, the voltage at a detector input (e.g., node qv) changes by switching of a first memory cell, and the change in voltage causes the output of the detector to change state (e.g., evaluation node 306 changes from a low voltage to a high voltage to indicate the logical state of the first memory cell).

[0154] The present disclosure includes various apparatuses that perform the methods described above and implement the systems described above, including a data processing system that performs these methods and a computer-readable medium containing instructions that, when executed on a data processing system, cause the system to perform these methods.

[0155] The description and drawings are illustrative and should not be construed as restrictive. Many specific details are described to provide a thorough understanding. However, in certain instances, well-known or conventional details are not described to avoid obscuring the description. References in this disclosure to one or an embodiment do not necessarily refer to the same embodiment; and such references mean at least one.

[0156] As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without an intervening component), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0157] References in this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. The phrase "in one embodiment" appearing in various places in the specification does not necessarily refer to the same embodiment, and separate or alternative embodiments are not mutually exclusive of other embodiments. Additionally, various features are described that may be exhibited by some embodiments but not by others. Similarly, various requirements are described that may be requirements of some embodiments but not of others.

[0158] In this description, various functions and operations may be described as being performed or caused by software code to simplify the description. However, those skilled in the art will recognize that such a statement means that the functions and / or operations are produced by executing code by one or more processing devices such as a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit, and / or a field programmable gate array (FPGA). Alternatively or in combination, the functions and operations may be implemented using special circuit systems (e.g., logic circuitry) with or without software instructions. Embodiments may be implemented using hardwired circuitry without software instructions or in combination with software instructions. Thus, the technology is not limited to any particular combination of hardware circuitry and software, nor to any particular source of instructions executed by a computing device.

[0159] Although some embodiments may be implemented in fully operational computers and computer systems, various embodiments can be distributed in a variety of forms as a computing product and can be applied regardless of the specific type of computer-readable medium used to actually effect the distribution.

[0160] At least some aspects of the disclosure may be embodied, at least in part, in software. That is, the technology may be practiced in a computing device or other system in response to its processing device (e.g., a microprocessor) executing a sequence of instructions contained in a memory (e.g., ROM, volatile RAM, non-volatile memory, cache, or remote storage device).

[0161] The routines executed to implement the embodiments may be implemented as part of an operating system, middleware, a service delivery platform, an SDK (software development kit) component, a network service, or other specific application, component, program, object, module, or sequence of instructions (sometimes referred to as a “computer program”). The call interfaces to these routines may be open to the software development community as an API (application programming interface). Computer programs typically include one or more sets of instructions at various times in various memories and storage devices in a computer, and when the sets of instructions are read and executed by one or more processors in the computer, cause the computer to perform the operations necessary to execute the elements involved in the various aspects.

[0162] A computer-readable medium can be used to store software and data which, when executed by a computing device, cause the device to perform various methods. The executable software and data can be stored in various places, including for example ROM, volatile RAM, non-volatile memory, and / or cache. Portions of this software and / or data can be stored in any one of these storage devices. In addition, data and instructions can be obtained from a centralized server or a peer-to-peer network. Different portions of the data and instructions can be obtained at different times and in different communication sessions or in the same communication session from different centralized servers and / or peer-to-peer networks. The complete data and instructions can be obtained before an application is executed. Alternatively, portions of the data and instructions can be obtained dynamically and in a timely manner as needed during execution. Thus, in a particular example in time, it is not required that all of the data and instructions be on the computer-readable medium.

[0163] Examples of computer-readable media include in particular but are not limited to recordable and non-recordable types of media such as volatile and non-volatile memory devices, read-only memory (ROM), random access memory (RAM), flash memory devices, solid state drive storage media, removable disks, magnetic disk storage media, optical storage media (such as, compact disc read-only memory (CD ROM), digital versatile disc (DVD), etc.), and so on. A computer-readable medium can store instructions. Other examples of computer-readable media include but are not limited to non-volatile embedded devices using NOR flash memory or NAND flash memory architectures. The media used in these architectures can include unmanaged NAND devices and / or managed NAND devices, including for example eMMC, SD, CF, UFS, and SSD.

[0164] Generally speaking, a non-transitory computer-readable medium includes any mechanism that provides (e.g., stores) information in a form accessible by a computing device (such as a computer, a mobile device, a network device, a personal digital assistant, a manufacturing tool having a controller, any device having a set of one or more processors, etc.). As used herein, "computer-readable medium" can include a single medium or multiple media (e.g., which store one or more sets of instructions).

[0165] In various embodiments, hardwired circuitry can be combined with software and firmware instructions to implement the techniques. Thus, the techniques are not limited to any particular combination of hardware circuitry and software, nor to any particular source of the instructions executed by the computing device.

[0166] The various embodiments described herein can be implemented using a variety of different types of computing devices. As used herein, examples of "computing devices" include, but are not limited to, servers, centralized computing platforms, systems of multiple computing processors and / or components, mobile devices, user terminals, vehicles, personal communication devices, wearable digital devices, electronic kiosks, general-purpose computers, electronic document readers, tablet computers, laptop computers, smartphones, digital cameras, residential household appliances, televisions, or digital music players. Additional examples of computing devices include devices that are part of the so-called "Internet of Things" (IoT). Such "things" can occasionally interact with their owners or administrators who can monitor the things or modify settings regarding these things. In some cases, these owners or administrators act in the role of users with respect to the "thing" devices. In some instances, a user's primary mobile device (e.g., an Apple iPhone) can be an administrator server with respect to a paired "thing" device (e.g., an Apple Watch) worn by the user.

[0167] In some embodiments, the computing device can be a computer or a host system, which can be implemented as, for example, a desktop computer, a laptop computer, a network server, a mobile device, or other computing devices that include a memory and a processing device. The host system can include or be coupled to a memory subsystem such that the host system can read data from or write data to the memory subsystem. The host system can be coupled to the memory subsystem via a physical host interface. Generally, the host system can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0168] In some embodiments, the computing device is a system that includes one or more processing devices. Examples of processing devices can include a microcontroller, a central processing unit (CPU), application-specific logic circuitry (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), a system on a chip (SoC), or another suitable processor.

[0169] In one example, the computing device is a controller of a memory system. The controller includes a processing device and a memory that contains instructions executed by the processing device to control various operations of the memory system.

[0170] Although some figures illustrate several operations in a particular order, operations that are not order-dependent can be reordered, and other operations can be combined or decomposed. Although some reorderings or other groupings are specifically mentioned, other reorderings or other groupings will be apparent to those of ordinary skill in the art, and thus an exhaustive list of alternatives is not presented. Additionally, it should be recognized that the stages can be implemented in hardware, firmware, software, or any combination thereof.

[0171] Unless otherwise specifically stated, disjunctive language such as the phrase "at least one of X, Y or Z" is understood in context to typically mean that items, terms, etc. may be X, Y or Z or any combination thereof (e.g., X, Y and / or Z). Thus, this disjunctive language is generally not intended and should not be construed to imply that certain embodiments require the presence of each of at least one X, at least one Y or at least one Z.

[0172] In the foregoing specification, the disclosure has been described with reference to specific exemplary embodiments thereof. Obviously, various modifications can be made thereto without departing from the broader spirit and scope set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. An apparatus, comprising: A memory array having memory cells; Bit lines coupled to at least one first memory cell; A first transistor that couples a power supply voltage to the bit lines, wherein the first transistor is configured to precharge the bit lines; A detector having an input coupled to the bit lines, wherein the detector is configured to detect whether the first memory cell has reached a threshold; A current source coupled to provide a reference current to set the voltage of the input of the detector; And A second transistor that couples the input of the detector to the bit lines, wherein the second transistor is configured to change the voltage of the detector input when the first memory cell reaches the threshold.

2. The apparatus according to claim 1, wherein the second transistor is in an off state at the end of the precharging of the bit lines by the first transistor.

3. The apparatus according to claim 1, wherein the first transistor is in an on state when precharging the bit lines, and the first transistor is in an off state when the detector is detecting whether the first memory cell has reached the threshold.

4. The apparatus according to claim 1, wherein the first transistor is a p-channel device and the second transistor is an n-channel device.

5. The apparatus according to claim 1, wherein a first current terminal of the first transistor is coupled to a gate of the second transistor, and a second current terminal of the first transistor is coupled to the bit lines.

6. The apparatus according to claim 1, wherein the current source is configured to drive the input of the detector to the power supply voltage.

7. The apparatus according to claim 1, wherein the first transistor is configured to precharge the bit lines to the power supply voltage.

8. A system, comprising: A communication interface configured to receive a read command from a host device; A sense circuitry configured to sense memory cells of a memory device; A bias circuitry configured to bias a first access line and a second access line each coupled to at least one first memory cell, the bias including biasing the first access line to a first voltage to prepare for sensing the first memory cell, wherein the bias circuitry is further configured to turn off the bias of the first access line to the first voltage when sensing the first memory cell; And A controller configured to: In response to receiving the read command, initiate a read operation; As part of the read operation, use the bias circuitry to bias the first access line to the first voltage; As part of the read operation, use the bias circuitry to apply a voltage to the second access line; And After applying the voltage to the second access line, use the sense circuitry to sense the first memory cell to determine whether the first memory cell has reached a threshold.

9. The system according to claim 8, wherein the first access line is a bit line and the second access line is a word line.

10. The system according to claim 8, wherein the first access line is coupled to an input of the detector, and in response to the first memory cell reaching the threshold, the voltage of the input reaches a detection threshold.

11. The system according to claim 10, wherein the sense circuitry includes an n-channel transistor, and the first access line is coupled to the input of the detector through the n-channel transistor.

12. The system according to claim 8, further comprising a voltage regulator having an output for providing the first voltage, wherein the bias circuitry includes a p-channel transistor, and the p-channel transistor couples the output of the voltage regulator to the first access line.

13. The system according to claim 8, wherein the controller is further configured to: After sensing the first memory cell, turn on the bias of the first access line to the first voltage; After biasing the first access line to the first voltage, turn off the bias of the first access line to the first voltage; Increase the magnitude of the voltage applied to the second access line; And After increasing the magnitude of the voltage applied to the second access line, sense the first memory cell when turning off the bias of the first access line to the first voltage.

14. The system according to claim 8, wherein: The sense circuitry includes a transistor that couples the sense circuitry to the first access line; And When biasing the first access line to the first voltage and when sensing the first memory cell, the first voltage is applied to the gate of the transistor.

15. A method, comprising: Resetting a detector to prepare for a sensing operation, wherein the detector is configured to determine a logical state of a memory cell in a three-dimensional cross-point memory array formed above a semiconductor substrate, wherein bit lines of the memory array are coupled to at least one first memory cell and extend above the semiconductor substrate in a vertical direction, and wherein word lines of the memory array are coupled to the first memory cell and extend above the semiconductor substrate in a horizontal direction; Pre-charging the bit lines to prepare for the sensing operation; As part of the sensing operation, applying a read voltage to the word lines; Turning off the pre-charging of the bit lines; After turning off the pre-charging of the bit lines, detecting the logical state of the first memory cell; And Providing an output indicating the logical state of the first memory cell.

16. The method according to claim 15, wherein the first memory cell is a self-selecting memory cell, and the magnitude of the bias voltage applied across the first memory cell during the sensing operation corresponds to the threshold voltage of the first memory cell.

17. The method according to claim 15, wherein applying the read voltage includes incrementing the read voltage by increasing the magnitude of the read voltage for each increment during the sensing operation.

18. The method according to claim 15, wherein the voltage source is coupled to the bit line through a first transistor, and precharging the bit line includes turning on the first transistor.

19. The method according to claim 18, wherein a second transistor couples the bit line to an input of the detector, and the voltage source is coupled to a gate of the second transistor.

20. The method according to claim 19, wherein the voltage at the detector input is changed by switching of the first memory cell, and the change in voltage causes the output of the detector to change state.

Images