Semiconductor device

Abstract

The invention provides a semiconductor device capable of preventing a decrease in heat dissipation performance. A semiconductor device (1) is provided with: an insulating circuit board (20) having a lower surface (23a); a heat dissipation base plate (40) that includes a front surface (40a) and that has, on the front surface (40a), an arrangement region (40b) in which the lower surface (23a) of the insulating circuit board (20) is arranged via solder (27); a plating film (41) that is formed on the front surface (40a) of the heat-dissipating base plate (40) in a region other than a solder region in which the solder (27) expands over a region (40b) in which the front surface (40a) is disposed; and an alloy layer that is included between the solder (27) and the placement region (40b) of the heat dissipation base plate (40), and that contains a solder component contained in the solder (27). In particular, in the semiconductor device (1), a plating film (41) is formed on the entire surface of the heat dissipation base plate (40) excluding an opening region (41a) that surrounds the outer periphery of a configuration region (40b) in which the insulating circuit board (20) is configured via the solder (27).

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] A semiconductor device includes a metal substrate and an insulating substrate provided on the metal substrate via solder (for example, refer to Patent Document 1). As another example, it includes a collector lead frame and a semiconductor element provided on the collector lead frame via solder (for example, refer to Patent Document 2). Further, a concave-shaped depression is formed on the upper surface of the base material, a plating layer is formed on the upper surface including the depression, and the lower surface of the base material and the upper surface on which the plating layer is formed are polished. Thereby, the plating layer filled in the depression of the base material functions as a through electrode (for example, refer to Patent Document 3). Further, a resist pattern formed on a base substrate can be used as an anti-plating coating film, and a copper plating film can be formed in a pattern-formed area by electroless reduction plating (for example, refer to Patent Document 4). Further, a plated film can be peeled off by irradiating a laser (for example, refer to Patent Document 5).

[0003] Prior Art Documents Patent Documents Patent Document 1: Japanese Patent Application Laid-Open No. 2019-080014 Patent Document 2: Japanese Patent Application Laid-Open No. 2018-085360 Patent Document 3: Japanese Patent Application Laid-Open No. 2013-055114 Patent Document 4: Japanese Patent Application Laid-Open No. 2012-140705 Patent Document 5: Japanese Patent Application Laid-Open No. 10-183382 Summary of the Invention

[0004] Technical Problem An object of the present invention is to provide a semiconductor device that prevents a decrease in heat dissipation performance.

[0005] Technical Solution According to one aspect of the present invention, there is provided a semiconductor device having: a substrate including a lower surface; a heat dissipation base plate including a main surface and having a configuration area on the main surface for disposing the lower surface of the substrate via solder; a first plating film formed in an area of the main surface of the heat dissipation base plate other than a solder area where the solder extends on the configuration area of the main surface; and an alloy layer included between the solder and the configuration area of the heat dissipation base plate and containing a solder component contained in the solder.

[0006] Further, the alloy layer may further contain a first metal material contained in the heat dissipation base plate together with the solder component.

[0007] In addition, the first metal material may contain copper.

[0008] In addition, the first plating film may be composed mainly of nickel.

[0009] In addition, in a plan view, the periphery of the placement region may be located at a position closer to the inside than the periphery of the substrate.

[0010] In addition, the first plating film may be further formed in a region of the main surface of the heat dissipation base plate other than an opening region that surrounds the entire periphery of the solder region.

[0011] In addition, the placement region may be recessed in a concave shape with respect to the main surface other than the placement region.

[0012] In addition, the solder may include solder legs that extend outward from the lower surface of the substrate in a plan view.

[0013] In addition, in a plan view, the outer peripheral edge of the solder legs of the solder may be located outside the placement region.

[0014] The substrate may include: an insulating board; a conductive pattern formed on the front surface of the insulating board; and a metal plate formed on the back surface of the insulating board and including the lower surface. A second plating film is formed on the side surface of the metal plate in a manner that surrounds the entire periphery of the lower surface except for the lower surface.

[0015] In addition, the metal plate may be composed mainly of copper.

[0016] In addition, the second plating film may be composed mainly of nickel.

[0017] In addition, a resist material may be formed to surround the entire periphery of the opening edge portion of the first plating film formed on the front surface of the heat dissipation base plate.

[0018] In addition, the alloy layer may further contain a second metal material that constitutes the first plating film together with the solder component and the first metal material.

[0019] In addition, the second metal material may contain nickel.

[0020] In addition, the first plating film may be further formed on a surface of the heat dissipation base plate other than the main surface, and the thickness of the first plating film formed on the main surface is thinner than the thickness of the first plating film formed on the surface other than the main surface.

[0021] In addition, the thickness of the first plating film formed on the main surface may be less than 0.2 μm.

[0022] It should be noted that the above-described invention content does not list all the essential features of the present invention. In addition, sub-combinations of these feature groups can also form inventions.

[0023] Technical effects According to the disclosed technology, it is possible to prevent a decrease in heat dissipation performance and suppress a decrease in reliability.

[0024] The above and other objects, features, and advantages of the present invention will become clearly understood from the following description in connection with the accompanying drawings showing preferred embodiments of the present invention by way of example. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a cross-sectional view of a semiconductor device according to a first embodiment.

[0026] Figure 2 is a top view of a main part of a semiconductor device according to a first embodiment (sealing member omitted).

[0027] Figure 3 is a flowchart showing a manufacturing method of a semiconductor device according to a first embodiment.

[0028] Figure 4 is a top view showing a manufacturing process of a heat dissipation unit included in the manufacturing method of a semiconductor device according to a first embodiment (preparing a heat dissipation base plate).

[0029] Figure 5 is a top view showing a manufacturing process of a heat dissipation unit included in the manufacturing method of a semiconductor device according to a first embodiment (plating process).

[0030] Figure 6 is a top view showing a manufacturing process of a heat dissipation unit included in the manufacturing method of a semiconductor device according to a first embodiment (grinding process).

[0031] Figure 7 is a cross-sectional view showing a manufacturing process of a heat dissipation unit included in the manufacturing method of a semiconductor device according to a first embodiment (grinding process).

[0032] Figure 8 is a top view showing a manufacturing process of a heat dissipation unit included in the manufacturing method of a semiconductor device according to a first embodiment (setting a mask).

[0033] Figure 9 is a top view showing a manufacturing process of a heat dissipation unit included in the manufacturing method of a semiconductor device according to a first embodiment (plating process).

[0034] Figure 10It is a top view showing the manufacturing process (mask removal) of the heat dissipation unit included in the manufacturing method of the semiconductor device of the first embodiment.

[0035] Figure 11 It is a cross-sectional view showing the manufacturing process (mask removal) of the heat dissipation unit included in the manufacturing method of the semiconductor device of the first embodiment.

[0036] Figure 12 It is a cross-sectional view showing the arrangement process included in the manufacturing method of the semiconductor device of the first embodiment.

[0037] Figure 13 It is a schematic cross-sectional view showing the atomic arrangement in the arrangement process included in the manufacturing method of the semiconductor device of the first embodiment.

[0038] Figure 14 It is a cross-sectional view showing the bonding process included in the manufacturing method of the semiconductor device of the first embodiment.

[0039] Figure 15 It is a schematic cross-sectional view showing the atomic arrangement in the bonding process included in the manufacturing method of the semiconductor device of the first embodiment.

[0040] Figure 16 It is a cross-sectional view showing the arrangement process included in the manufacturing method of the semiconductor device of the reference example.

[0041] Figure 17 It is a schematic cross-sectional view showing the atomic arrangement in the arrangement process included in the manufacturing method of the semiconductor device of the reference example.

[0042] Figure 18 It is a first schematic cross-sectional view showing the atomic arrangement in the bonding process (when heated) included in the manufacturing method of the semiconductor device of the reference example.

[0043] Figure 19 It is a second schematic cross-sectional view showing the atomic arrangement in the bonding process (when heated) included in the manufacturing method of the semiconductor device of the reference example.

[0044] Figure 20 It is a third schematic cross-sectional view showing the atomic arrangement in the bonding process (when heated) included in the manufacturing method of the semiconductor device of the reference example.

[0045] Figure 21 It is a cross-sectional view showing the bonding process (after bonding) included in the manufacturing method of the semiconductor device of the reference example.

[0046] Figure 22 It is a cross-sectional view of the semiconductor device of the second embodiment.

[0047] Figure 23It is a rear - side perspective view of an insulating circuit board included in the semiconductor device of the second embodiment.

[0048] Figure 24 It is a top view of the main part of the semiconductor device of the third embodiment (sealing member omitted).

[0049] Figure 25 It is a cross - sectional view of the semiconductor device of the fourth embodiment.

[0050] Figure 26 It is a flowchart showing the manufacturing method of the semiconductor device of the fourth embodiment.

[0051] Figure 27 It is a cross - sectional view showing the manufacturing process (plating process) of the heat - dissipation unit included in the manufacturing method of the semiconductor device of the fourth embodiment.

[0052] Figure 28 It is a cross - sectional view showing the manufacturing process (thinning process) of the heat - dissipation unit included in the manufacturing method of the semiconductor device of the fourth embodiment.

[0053] Figure 29 It is a cross - sectional view showing the arrangement process included in the manufacturing method of the semiconductor device of the fourth embodiment.

[0054] Figure 30 It is a schematic cross - sectional view of the atomic arrangement in the arrangement process included in the manufacturing method of the semiconductor device of the fourth embodiment.

[0055] Figure 31 It is a cross - sectional view showing the bonding process included in the manufacturing method of the semiconductor device of the fourth embodiment.

[0056] Figure 32 It is a schematic cross - sectional view of the atomic arrangement in the bonding process included in the manufacturing method of the semiconductor device of the fourth embodiment.

[0057] Symbol Explanation 1, 1a Semiconductor device 2 Semiconductor unit 3 Housing 4, 4a Heat - dissipation unit 20 Insulating circuit board 21 Insulating plate 22 Conductive pattern 22a Upper surface 23 Metal plate 23a Lower surface 24 Plated film 25 Semiconductor chip 26, 27 Solder Solder plates 26a and 27a Solder leg portion 27b Frame portion 31 Upper opening portion 31a Lower opening portion 31b Upper inner wall 31c Step 31d Lower inner wall 31e Storage area 31f External connection terminal 32 Internal wiring portion 32a External wiring portion 32b Heat dissipation base plate 40 Front surface 40a Configuration area 40b Back surface 40c Side surface 40d Plated film 41 Opening area 41a Solder area 41b Mask 42 Resist film 43 Alloy layer 44 Sealing member 50 Wire 51 Detailed implementation manners

[0058] Hereinafter, the embodiments will be described with reference to the drawings. It should be noted that, in the following description, "front surface" and "upper surface" refer to the X-Y plane facing the upper side (+Z direction) in the semiconductor device 1 Figure 1 . Similarly, "upper" refers to the direction of the upper side (+Z direction) in the semiconductor device 1 Figure 1 . "Back surface" and "lower surface" refer to the X-Y plane facing the lower side (-Z direction) in the semiconductor device 1 Figure 1 . Similarly, "lower" refers to the direction of the lower side (-Z direction) in the semiconductor device 1 Figure 1 . As needed, the same directionality as described above is also shown in other drawings. "Higher position" and "upper position" refer to the position in the semiconductor device 1 Figure 1The position on the upper side (+Z direction) in the semiconductor device 1. Similarly, "low position" and "lower position" indicate the position on the lower side (-Z direction) in the semiconductor device 1 in the figure. "Front", "upper surface", "upper", "back", "lower surface", "lower", and "side" are just expressions for facilitating the determination of the relative positional relationship and do not limit the technical idea of the present invention. For example, "upper" and "lower" do not necessarily refer to the vertical direction relative to the ground. That is, the directions of "upper" and "lower" are not limited to the direction of gravity. In addition, in the following description, "main component" means a case where it contains 80 vol% or more (in the case of containing a filler, it is the ratio obtained by excluding the filler). In addition, "substantially the same" means a range within ±10%. In addition, "perpendicular", "orthogonal", and "parallel" mean a range within ±10°.

[0059] [First Embodiment] Use Figure 1 And Figure 2 To describe the semiconductor device. Figure 1 Is a cross-sectional view of the semiconductor device of the first embodiment. Figure 2 Is a top view of the main part of the semiconductor device of the first embodiment (the sealing member is omitted). It should be noted that Figure 2 Is enlarged to show the region including the semiconductor chip 25 obtained by removing the sealing member 50 and the wire 51 from the Figure 1 Semiconductor device 1. Therefore, since Figure 2 Is enlarged to show Figure 1 The main part inside the housing 3, the description of the housing 3 is omitted. Figure 1 Is a cross-sectional view taken along the single dotted line Y-Y of Figure 2 In the case of including the housing 3.

[0060] As Figure 1 Shown, the semiconductor device 1 includes a semiconductor unit 2, a heat dissipation unit 4 having the semiconductor unit 2 disposed on the front surface, and a housing 3 provided at the outer edge portion of the heat dissipation unit 4 for housing the semiconductor unit 2. The inside of the housing 3 of the semiconductor device 1 is sealed by a sealing member 50.

[0061] It should be noted that examples of the sealing member 50 include silicone gel. In addition, the sealing member 50 may be a thermosetting resin mixed with a filler. In this case, the thermosetting resin is, for example, an epoxy resin, a phenolic resin, a maleimide resin, or a polyester resin. The filler is an insulating and highly thermally conductive ceramic. Examples of such a filler include silica, alumina, boron nitride, or aluminum nitride. The filler content may be 10 vol% or more and 70 vol% or less with respect to the entire sealing member 50.

[0062] The semiconductor unit 2 includes an insulating circuit board 20 and a semiconductor chip 25 disposed on the front surface of the insulating circuit board 20 via solder 26. The insulating circuit board 20 includes an insulating board 21, a plurality of conductive patterns 22 provided on the front surface of the insulating board 21, and a metal plate 23 provided on the back surface of the insulating board 21. The insulating board 21 and the metal plate 23 are rectangular in plan view. In addition, the corners of the insulating board 21 and the metal plate 23 may be R-chamfered or C-chamfered. The size of the metal plate 23 is smaller than that of the insulating board 21 in plan view and is formed inside the insulating board 21.

[0063] Examples of the insulating board 21 include a ceramic substrate. The ceramic substrate is made of a ceramic having good thermal conductivity. The ceramic is made of a material mainly composed of, for example, alumina, aluminum nitride, or silicon nitride. In addition, such an insulating board 21 is rectangular in plan view.

[0064] The semiconductor chip 25 is disposed on the upper surface 22a of the conductive pattern 22. The conductive pattern 22 is formed over the entire surface of the insulating board 21 except for the edge portion. Preferably, in plan view, the end portion of the conductive pattern 22 facing the outer periphery of the insulating board 21 overlaps with the end portion on the outer peripheral side of the metal plate 23. Therefore, the insulating circuit board 20 maintains the stress balance between the conductive pattern 22 and the metal plate 23 on the back surface of the insulating board 21. Excessive warping, cracking, and other damages of the insulating board 21 are suppressed. The conductive pattern 22 is made of a material having excellent conductivity. Examples of such a material include copper, aluminum, or an alloy containing at least one of them. The conductive pattern 22 may be plated with a material having excellent corrosion resistance. Such a material is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy. The thickness of the plating film is 10 μm or less. The conductive pattern 22 facing the insulating board 21 can be obtained by forming a metal plate on the front surface of the insulating board 21 and performing etching or the like on the metal plate. Alternatively, the conductive pattern 22 cut out from a metal plate in advance may be joined to the front surface of the insulating board 21. It should be noted that the conductive pattern 22 included in the semiconductor device 1 of the present embodiment is merely an example. The number, shape, size, etc. of the conductive patterns may be appropriately selected as needed. It should be noted that the upper surface 22a of the conductive pattern 22 is also the upper surface 22a of the insulating circuit board 20.

[0065] The lower surface 23a of the metal plate 23 is disposed on the heat dissipation unit 4. The metal plate 23 is made of a metal with excellent thermal conductivity. As such a material, for example, it is made of copper, aluminum, or an alloy containing at least one of them. Here, copper is included. In addition, in order to improve the corrosion resistance, the surface of the metal plate 23 may be subjected to a plating treatment. The plating material in this case contains nickel. Such a plating material is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy. The thickness of the plating film is 3 μm or more and 7 μm or less. It should be noted that the lower surface 23a of the metal plate 23 is also the lower surface 23a of the insulating circuit board 20. In addition, other forms of the plating film formed on the metal plate 23 will be described in the second embodiment.

[0066] As the insulating circuit board 20 having such a structure, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate can be used. Alternatively, a resin insulating substrate can be used. The insulating circuit board 20 dissipates the heat generated by the semiconductor chip 25 described later through the conductive pattern 22, the insulating plate 21, and the metal plate 23 to the back side of the insulating circuit board 20.

[0067] The semiconductor chip 25 includes, for example, a switching element mainly composed of silicon. The switching element is, for example, an RC (Reverse-Conducting)-IGBT (Insulated Gate Bipolar Transistor). The RC-IGBT is a semiconductor element in which an IGBT and an FWD (Free Wheeling Diode) are reversely connected in parallel in one chip.

[0068] The semiconductor chip 25 has a collector electrode as an input electrode on the back surface, and a gate electrode as a control electrode and an emitter electrode as an output electrode on the front surface. It should be noted that the control electrode may be provided at the center of one side edge of the front surface of the semiconductor chip 25. Alternatively, the control electrode may not be provided at the center of one side edge of the front surface of the semiconductor chip 25, and may be positionally offset in the ±X direction relative to the center.

[0069] As other switching elements, a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) mainly composed of silicon carbide can be used. The body diode of the power MOSFET can function as an FWD. Such a semiconductor chip 25 has, for example, an input electrode (drain electrode) as a main electrode on the back surface, and an output electrode (source electrode) and a control electrode (gate electrode) as main electrodes on the front surface.

[0070] Alternatively, a semiconductor chip mainly composed of silicon and including a set of switching elements and diode elements can be used instead of the semiconductor chip 25. The switching elements are, for example, power MOSFETs, IGBTs. The semiconductor chip including the switching elements has, for example, an input electrode (drain electrode in the power MOSFET, collector electrode in the IGBT) as a main electrode on the back surface, a gate electrode as a control electrode, and an output electrode (source electrode in the power MOSFET, emitter electrode in the IGBT) as a main electrode on the front surface. In addition, for the diode element, for example, an SBD (Schottky Barrier Diode), a PiN (P-intrinsic-N) diode is used as the FWD. The semiconductor chip including the diode element has an output electrode (cathode electrode) as a main electrode on the back surface, and an input electrode (anode electrode) as a main electrode on the front surface.

[0071] The back side of the semiconductor chip 25 is bonded to the conductive pattern 22 using a solder 26. The solder 26 is composed of a solder composition. The solder composition is a substance constituting the solder, and includes a lead-free solder mainly composed of a predetermined alloy. The predetermined alloy contains tin. Such an alloy is, for example, at least any one of an alloy composed of tin-silver, an alloy composed of tin-silver-copper, an alloy composed of tin-zinc-bismuth, an alloy composed of tin-copper, an alloy composed of tin-silver-indium-bismuth, and an alloy composed of tin-antimony. Further, additives can be included in such a solder composition. Examples of the additives include nickel, germanium, cobalt, or silicon. Therefore, the solder composition can include, for example, at least one of silver, zinc, copper, bismuth, indium, and antimony together with tin. Further, the solder composition can include, for example, at least one of nickel, germanium, cobalt, and silicon. It should be noted that the solder composition in the following embodiments is the same as that in the first embodiment. Alternatively, a sintered body can be used instead of the solder 26. The sintering material for bonding with the sintered body is, for example, powder of silver, iron, copper, aluminum, titanium, nickel, tungsten, or molybdenum. It should be noted that here, the solder 26 is composed of the same solder as the solder 27 described later.

[0072] The housing 3 includes a frame portion 31 and external connection terminals 32 embedded in the frame portion 31. The frame portion 31 has a rectangular shape when viewed from above and forms a frame shape surrounding the storage area 31f. The storage area 31f is an area that opens from the upper opening portion 31a on the front surface of the housing 3 to the lower opening portion 31b on the back surface. The area of the upper opening portion 31a may be larger than the area of the lower opening portion 31b. It should be noted that a heat dissipation unit 4 described later is mounted on the step on the back surface of the frame portion 31 to block the storage area 31f.

[0073] In addition, the upper inner wall 31c of the frame portion 31 surrounds the periphery of the upper part of the storage area 31f and forms the upper opening portion 31a leading to the storage area 31f. The lower inner wall 31e of the frame portion 31 surrounds the periphery of the lower part of the storage area 31f and forms the lower opening portion 31b leading to the storage area 31f. When viewed from above, steps 31d are respectively formed between the upper inner wall 31c and the lower inner wall 31e on the short side of the frame portion 31. The upper inner wall 31c is arranged substantially perpendicular to the front surface of the frame portion 31. The steps 31d are arranged substantially perpendicular to the upper inner wall 31c. The lower inner wall 31e is arranged substantially perpendicular to the steps 31d. According to the above, when viewed from above, the lower inner wall 31e on the short side protrudes from the upper inner wall 31c toward the storage area 31f by the amount of the steps 31d.

[0074] Such a frame portion 31 is made of a thermoplastic resin containing a filler and is formed by injection molding. It should be noted that such resins include, for example, polyphenylene sulfide (PPS) resin, polybutylene terephthalate (PBT) resin, or polyamide (PA) resin. The filler is composed of, for example, glass fiber, glass beads, calcium carbide, talc, magnesium oxide, and aluminum hydroxide.

[0075] The external connection terminal 32 is in a flat plate shape and is L-shaped when viewed from the side. The external connection terminal 32 is integrally formed with the frame portion 31. The external connection terminal 32 includes an internal wiring portion 32a and an external wiring portion 32b provided substantially vertically with respect to the internal wiring portion 32a. The internal wiring portion 32a is included in the frame portion 31 in parallel with the front surface of the frame portion 31. One end of the internal wiring portion 32a extends substantially at a right angle from the upper inner wall 31c toward the storage area 31f, and the front surface of this one end is exposed from the step 31d. The external wiring portion 32b is included in the frame portion 31 substantially parallel to the upper inner wall 31c of the frame portion 31. The other end of the external wiring portion 32b extends substantially perpendicular to the front surface of the frame portion 31. One end of the external wiring portion 32b is integrally connected to the other end of the internal wiring portion 32a within the frame portion 31.

[0076] Such an external connection terminal 32 is made of a material with excellent conductivity. As such a material, for example, it is made of copper, aluminum, or an alloy containing at least one of them. The thickness of the external connection terminal 32 is uniform throughout. The external connection terminal 32 can also be plated with a material having excellent corrosion resistance. Such a material is, for example, aluminum, nickel, titanium, chromium, molybdenum, tantalum, niobium, tungsten, vanadium, bismuth, zirconium, hafnium, gold, silver, platinum, palladium, or an alloy containing at least one of them.

[0077] The frame portion 31 of such a housing 3 is joined to the outer peripheral edge of the front surface of the heat dissipation unit 4 to which the semiconductor unit 2 is joined by an adhesive (not shown) on the back surface side of the lower opening portion 31b thereof. Thus, the semiconductor unit 2 is housed in the housing area 31f of the frame portion 31. Although not shown, a lid (not shown) can also be joined to the front surface side of the upper opening portion 31a of the frame portion 31 by an adhesive. It should be noted that, for example, a thermosetting resin-based adhesive or an elastic system adhesive is used as the adhesive. The thermosetting resin-based adhesive has, for example, epoxy resin or phenolic resin as the main component. The elastic system adhesive has, for example, silicone rubber or chloroprene rubber as the main component.

[0078] The bonding area exposed from the step 31d of the internal wiring portion 32a is electrically connected to the conductive pattern 22 of the insulating circuit board 20 through a wiring component, and the bonding area exposed from the step 31d of the internal wiring portion 32a is electrically connected to the semiconductor chip 25 through a wiring component. Examples of the wiring component include Figure 1 the wire 51 shown. The wire 51 is made of a material with excellent conductivity. As this material, for example, it is made of gold, silver, copper, or an alloy containing at least one of them. It should be noted that such a wiring component is not limited to the wire 51, and a lead frame can also be used.

[0079] The heat dissipation unit 4 includes a heat dissipation base plate 40 and a plating film 41. The heat dissipation base plate 40 is mainly composed of copper. The heat dissipation base plate 40 includes a disposition area 40b on the front surface 40a where the lower surface 23a of the insulating circuit board 20 is disposed via the solder 27. The disposition area 40b is the range where the metal plate 23 of the insulating circuit board 20 is disposed on the heat dissipation base plate 40. The disposition area 40b is rectangular in a plan view, similar to the insulating circuit board 20. The size of the disposition area 40b can be equal to or smaller than the size of the insulating plate 21 and equal to or larger than the size of the metal plate 23 in a plan view. It should be noted that the case where the size of the disposition area 40b is the same as the size of the metal plate 23 is shown here. The thickness of the heat dissipation base plate 40 depends on the size of the semiconductor device 1, but can be, for example, 2.5 mm or more and 3.5 mm or less. The plating film 41 is formed on the front surface 40a of the heat dissipation base plate 40 in an area other than the opening area 41a that surrounds the entire outer periphery of the disposition area 40b. It should be noted that the thickness of the portion of the plating film 41 other than the opening area 41a is, for example, a commonly used thickness and can be, for example, 1 μm or more and 10 μm or less.

[0080] The disposition area 40b can be rectangular in a plan view, similar to the insulating circuit board 20, and the size of the disposition area 40b is larger than the size of the insulating circuit board 20. The disposition area 40b only needs to include the insulating circuit board 20 in a plan view and does not have to be rectangular. In addition, the corners of the disposition area 40b do not have to be right angles in a plan view and can have an R angle.

[0081] The disposition area 40b can be recessed in the -Z direction with respect to the front surface 40a of the heat dissipation base plate 40 other than the disposition area 40b. Here, the disposition area 40b is smoothly connected to the front surface 40a of the heat dissipation base plate 40 other than the disposition area 40b. At this time, the depth of the deepest position of the disposition area 40b can be deeper than the thickness of the plating film 24 described later. It should be noted that the disposition area 40b can be flush with the front surface 40a of the heat dissipation base plate 40 other than the disposition area 40b.

[0082] As Figure 1 and Figure 2 shown, the solder 27 is disposed in the disposition area 40b to join the insulating circuit board 20 and the front surface 40a of the heat dissipation base plate 40. It should be noted that the thickness of the solder 27 is 100 μm or more and 500 μm or less. The solder 27 includes solder legs 27b that extend outward from the lower surface 23a of the insulating circuit board 20 (metal plate 23) in a plan view and are disposed outside the disposition area 40b.

[0083] The solder foot portion 27b (outer edge of the solder 27) may extend more outwardly than the outer edge of the insulating circuit board 20 (insulating board 21) in a plan view. However, the solder foot portion 27b is preferably located inside the outer edge of the insulating board 21. It should be noted that in Figure 2 , only to clarify the position of the solder 27 relative to the insulating circuit board 20 and the plating film 41, a case where the outer edge of the solder 27 extends more outwardly than the outer edge of the insulating circuit board 20 (insulating board 21) is shown. It should be noted that the area where the solder 27 extends on the arrangement area 40b on the front surface 40a of the heat dissipation base plate 40 is the solder area (the reference numeral is omitted here. Refer to Figure 25 for the solder area 41b). The size of the solder area is wider than the size of the arrangement area 40b in a plan view and may include the arrangement area 40b.

[0084] The opening area 41a of the plating film 41 around the arrangement area 40b includes an area where the plating film 41 is not provided to prevent the solder 27 from extending to a position more outward than the arrangement area 40b. The opening area 41a may be rectangular in the same manner as the arrangement area 40b, and the opening area 41a is wider than the arrangement area 40b. The opening area 41a is preferably at least 1 mm away from the arrangement area 40b, for example. In addition, the opening area 41a may coincide with the solder area or extend more outwardly than the solder area.

[0085] The plating film 41 is formed on the surface of the heat dissipation base plate 40 except for the arrangement area 40b by a plating process. The corrosion resistance of the heat dissipation base plate 40 is improved by the plating film 41. The plating material of the plating film 41 contains nickel. Such plating materials include, for example, nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0086] In addition, a cooling unit (not shown) may be mounted on the back surface of the housing 3 including the heat dissipation unit 4 via a heat conductive member. The heat conductive member is a thermal interface material (TIM: Thermal Interface Material). TIM includes, for example, a general term for various materials such as heat conductive grease, elastomer sheet, RTV (Room Temperature Vulcanization) rubber, gel, phase change material, solder, and silver brazing material. Thereby, the heat dissipation performance of the semiconductor device 1 can be improved. In this case, the cooling unit is made of a metal having excellent heat conductivity, for example. The metal is, for example, aluminum, iron, silver, copper, or an alloy containing at least one of them. In addition, the cooling unit is, for example, a radiator having one or more fins or a water-cooled cooling device.

[0087] Next, Figure 3 the manufacturing method of the semiconductor device 1 will be described. Figure 3This is a flowchart showing a manufacturing method of a semiconductor device according to the first embodiment. It should be noted that Figure 3 The flowchart showing the manufacturing method is just an example. As long as the semiconductor device 1 includes the heat dissipation unit 4 to which the semiconductor unit 2 is bonded, it can also be manufactured by a method other than Figure 3 the flowchart.

[0088] First, a preparation process of preparing the components of the semiconductor device 1 ( Figure 3 step S1) is performed. At this time, the prepared components are, for example, the insulating circuit board 20, the semiconductor chip 25, the housing 3, and the heat dissipation unit 4. In addition, components required as components of the semiconductor device 1 are also prepared. In addition, manufacturing devices for manufacturing the semiconductor device 1 may also be prepared.

[0089] For the heat dissipation unit 4, two manufacturing methods can be considered, for example. First, use Figures 4 - 7 for Figure 1 the manufacturing method of the heat dissipation unit 4 included in the semiconductor device 1 shown ( Figure 3 steps S10, S11a, S12a, S14) will be described. Figure 4 This is a top view showing the manufacturing process of the heat dissipation unit (preparing the heat dissipation base plate) included in the manufacturing method of the semiconductor device according to the first embodiment. Figure 5 This is a top view showing the manufacturing process of the heat dissipation unit (plating process) included in the manufacturing method of the semiconductor device according to the first embodiment. Figure 6 This is a top view showing the manufacturing process of the heat dissipation unit (grinding process) included in the manufacturing method of the semiconductor device according to the first embodiment, Figure 7 This is a cross-sectional view showing the manufacturing process of the heat dissipation unit (grinding process) included in the manufacturing method of the semiconductor device according to the first embodiment. It should be noted that Figure 7 This is Figure 6 the cross-sectional view at the single-dot chain line X-X of Figure 1 In addition, Figures 4 - 7 shows the case of observing the heat dissipation base plate 40 (heat dissipation unit 4) of

[0090] First, a heat dissipation base plate 40 is prepared ( Figure 3 step S10). For example, a metal plate is sheared, as shown in Figure 4As shown, a heat dissipation base plate 40 having a size corresponding to the heat dissipation unit 4 of the semiconductor device 1 is obtained. Shearing can be performed using, for example, stamping or a cutter. Such a heat dissipation base plate 40 is formed in a flat plate shape that is rectangular when viewed from above. The front surface 40a of the heat dissipation base plate 40 is substantially smooth. In addition, arrangement regions 40b are respectively set on the front surface 40a of the heat dissipation base plate 40. The arrangement regions 40b are regions where the metal plates 23 of the insulating circuit board 20 are arranged. The arrangement regions 40b are set according to the number of insulating circuit boards 20 included in the semiconductor device 1. Here, two arrangement regions 40b are set side by side on the front surface 40a of the heat dissipation base plate 40.

[0091] Next, the heat dissipation base plate 40 is subjected to a plating process ( Figure 3 step S11a). As Figure 5 shown, the entire surface of the heat dissipation base plate 40 including the front surface 40a is plated to form a plating film 41. The plating process is a generally known method and can be, for example, an electrolytic plating method or an electroless plating method.

[0092] Next, the heat dissipation base plate 40 formed with the plating film 41 is subjected to a grinding process ( Figure 3 step S12a). The plating film 41 corresponding to the opening region 41a including the arrangement region 40b of the heat dissipation base plate 40 formed with the plating film 41 is ground and removed. As Figure 6 shown, the plating film 41 is formed with an opening region 41a that is removed in a manner wider than the arrangement region 40b. It should be noted that on the heat dissipation base plate 40, the plating film 41 is formed in regions other than the opening region 41a. If the plating film 41 corresponding to the opening region 41a including the arrangement region 40b of the heat dissipation base plate 40 is removed by grinding, the plating film 41 on the arrangement region 40b is removed, and the front surface 40a of the heat dissipation base plate 40 in the arrangement region 40b is also ground. Therefore, as Figure 7 shown, the arrangement region 40b is more recessed than the front surface 40a other than the arrangement region 40b. In addition, when the front surface 40a of the heat dissipation base plate 40 is ground, the bottom surface of the recess is connected to the front surface 40a by a smooth surface. As described above, the heat dissipation unit 4 as Figure 1 shown can be prepared ( Figure 3 step S14).

[0093] In addition, the heat dissipation unit 4 can also be manufactured by the following manufacturing method. The manufacturing method in this case ( Figure 4 and Figures 8 - 11 is described with Figure 3 steps S10, S11b, S12b, S13b, S14). Figure 8It is a top view showing a manufacturing process (mask setting) of a heat dissipation unit included in a manufacturing method of a semiconductor device according to a first embodiment. Figure 9 It is a top view showing a manufacturing process (plating process) of a heat dissipation unit included in a manufacturing method of a semiconductor device according to a first embodiment. Figure 10 It is a top view showing a manufacturing process (mask removal) of a heat dissipation unit included in a manufacturing method of a semiconductor device according to a first embodiment. Figure 11 It is a cross-sectional view showing a manufacturing process (mask removal) of a heat dissipation unit included in a manufacturing method of a semiconductor device according to a first embodiment. It should be noted that Figure 11 It is Figure 10 A cross-sectional view taken along the single dotted line X-X of

[0094] Here, too, first, a heat dissipation base plate 40 is prepared ( Figure 3 Step S10). Step S10 is as described above. Next, a mask is set on the heat dissipation base plate 40 ( Figure 3 Step S11b). As Figure 8 shown, the mask 42 is set in the arrangement region 40b on the front surface 40a of the heat dissipation base plate 40. The set mask 42 has the same shape as the arrangement region 40b in a top view, and a mask having a size one size larger than the size of the arrangement region 40b is used.

[0095] Next, the heat dissipation base plate 40 is subjected to a plating process ( Figure 3 Step S12b). A plating film 41 is formed on the entire surface of the heat dissipation base plate 40 including the front surface 40a in the same manner as in step S11a. The front surface 40a of the heat dissipation base plate 40 that has been subjected to the plating process has a plating film 41 formed in a range except for the mask 42.

[0096] Next, the mask 42 is removed ( Figure 3 Step S13b). The mask 42 is removed after step S12b. As Figure 10 shown, a plating film 41 is formed on a portion of the front surface 40a of the heat dissipation base plate 40 except for the opening region 41a including the arrangement region 40b. In addition, as Figure 11 shown, the arrangement region 40b on the front surface 40a of the heat dissipation base plate 40 is not cut, and the arrangement region 40b is flush with the front surface 40a. As described above, it is possible to prepare Figure 1 the heat dissipation unit 4 shown in Figure 3 Step S14).

[0097] Next, a configuration process of sequentially arranging the heat dissipation unit 4, the insulating circuit board 20, and the semiconductor chip 25 is performed ( Figure 3 Step S2). Using Figure 12 andFigure 13 Describe the placement process. Figure 12 FIG. is a cross-sectional view showing the placement process included in the manufacturing method of the semiconductor device of the first embodiment. Figure 13 FIG. is a schematic cross-sectional view showing the atomic arrangement in the placement process included in the manufacturing method of the semiconductor device according to the first embodiment. It should be noted that Figure 13 schematically shows Figure 12 the atomic arrangement in the range B surrounded by the dashed line. In addition, Figure 13 only schematically shows the arrangement of atoms, and the number of stacked atoms does not necessarily represent the thickness of the atomic layer. Furthermore, in Figure 13 , only tin, which is a constituent element of the solder composition, is described. The solder composition may contain elements other than tin, and the description of elements other than tin is omitted. In addition, not limited to Figure 13 , in the following schematic cross-sectional views showing the atomic arrangement, only tin, which is a constituent element of the solder composition, is also described. In these cross-sectional views, the solder composition may contain elements other than tin, and the description of elements other than tin is omitted.

[0098] The insulating circuit board 20 is respectively disposed in the placement region 40b within the opening region 41a of the plating film 41 formed on the heat dissipation unit 4 via the solder plate 27a. The solder plate 27a is formed by curing the solder 27 in a plate shape. The solder plate 27a is disposed at the bottom of the recess in the placement region 40b of the heat dissipation unit 4. The solder plate 27a may have, for example, the same size as the lower surface 23a of the metal plate 23 of the insulating circuit board 20 in a top view.

[0099] The semiconductor chip 25 is disposed on the upper surface 22a of the conductive pattern 22 of the insulating circuit board 20 via the solder plate 26a. The solder plate 26a is formed by curing the solder 26 in a plate shape. The solder plate 26a may have, for example, the same size as the semiconductor chip 25 in a top view.

[0100] As Figure 12 shown, through such a placement process, the insulating circuit board 20 is disposed in the placement region 40b of the heat dissipation unit 4 via the solder plate 27a, and the semiconductor chip 25 is disposed on the conductive pattern 22 of the insulating circuit board 20 via the solder plate 26a.

[0101] In addition, Figure 12 the range B is near the boundary between the heat dissipation base plate 40 and the solder plate 27a in the heat dissipation unit 4. As Figure 13As shown, at the boundary within the range B, the copper atoms contained in the heat dissipation base plate 40 and the tin atoms contained in the solder plate 27a are regularly arranged across the boundary L. This boundary L corresponds to the boundary between the solder plate 27a and the arrangement region 40b of the heat dissipation base plate 40 when the solder plate 27a is arranged in the arrangement region 40b of the heat dissipation unit 4 (heat dissipation base plate 40). It should be noted that since the solder plate 27a is not joined at the stage of being placed on the heat dissipation base plate 40, an air layer included in the unevenness of the solder plate 27a exists between the solder plate 27a and the metal plate 23, and between the solder plate 27a and the heat dissipation base plate 40, but its description is omitted.

[0102] Next, the joining process of the heat dissipation unit 4 and the insulating circuit board 20, and the insulating circuit board 20 and the semiconductor chip 25 is performed ( Figure 3 step S3). The Figure 14 and Figure 15 are used to explain the joining process. Figure 14 is a cross-sectional view showing the joining process included in the manufacturing method of the semiconductor device of the first embodiment. Figure 15 is a schematic cross-sectional view showing the atomic arrangement in the joining process included in the manufacturing method of the semiconductor device according to the first embodiment. It should be noted that Figure 15 schematically shows Figure 14 the atomic arrangement in the range B surrounded by the dashed line. In addition, Figure 15 only schematically shows the arrangement of the atoms, and the number of stacked atoms does not necessarily represent the thickness of the atomic layer.

[0103] The solder plate 27a between the heat dissipation unit 4 and the insulating circuit board 20 configured in step S2, and the solder plate 26a between the conductive pattern 22 of the insulating circuit board 20 and the semiconductor chip 25 are heated respectively. The solder plates 26a and 27a are each melted and transformed into solders 26 and 27.

[0104] If heated in this way, as Figure 15 shown, the copper atoms of the heat dissipation base plate 40 move across the boundary L and diffuse into the tin atoms of the solder 27. In addition, the tin atoms of the solder 27 diffuse into the copper atoms of the heat dissipation base plate 40 due to the diffusion of the copper atoms across the boundary L. In this way, an alloy layer 44 is formed near the boundary L. It should be noted that the alloy layer 44 contains copper atoms and tin atoms. Such an alloy layer 44 is included at the boundary between the solder 27 and the heat dissipation base plate 40 in a manner not limited to the position within the range B.

[0105] In this way, the solders 26 and 27 obtained by melting the solder plates 26a and 27a are cooled and solidified. Then, as Figure 14As shown, the insulating circuit board 20 is respectively joined to the arrangement region 40b of the heat dissipation unit 4 via the cured solder 27. Further, similarly, the semiconductor chip 25 is joined to the upper surface 22a of the insulating circuit board 20 via the cured solder 26.

[0106] Accordingly, a semiconductor unit 2 including the insulating circuit board 20 and the semiconductor chip 25 is formed. Further, the semiconductor unit 2 is respectively joined to the arrangement region 40b of the heat dissipation unit 4 by the solder 27.

[0107] Next, a housing process ( Figure 3 step S4) of mounting the heat dissipation unit 4 on the lower opening 31b of the housing 3 and housing the semiconductor unit 2 in the housing 3 is performed. The outer peripheral edge of the heat dissipation unit 4 is mounted on a step on the back surface of the housing 3 (frame portion 31) via an adhesive (not shown). Thereby, the semiconductor unit 2 is housed in the housing region 31f of the housing 3.

[0108] Next, a wiring process ( Figure 3 step S5) of wiring the semiconductor unit 2 housed in the housing 3 is performed. The internal wiring portion 32a of the external connection terminal 32 exposed from the upper opening 31a of the housing 3 and the conductive pattern 22 are connected by the lead wire 51. Further, the output electrode of the semiconductor chip 25 and the internal wiring portion 32a of the external connection terminal 32 are connected by the lead wire 51.

[0109] Next, a sealing process ( Figure 3 step S6) of sealing the housing region 31f in the housing 3 with the sealing member 50 is performed. The sealing member 50 is filled from the upper opening 31a of the housing 3 to seal the semiconductor unit 2 on the heat dissipation unit 4 in the housing region 31f. As described above, the Figure 1 shown semiconductor device 1 is obtained.

[0110] Here, Figure 3 (and Figure 16 and Figure 17 described later) are used to describe a semiconductor device (not shown) of a reference example with respect to the semiconductor device 1 of the first embodiment. The semiconductor device (not shown) of the reference example also includes a heat dissipation unit 4a. A plating film 41 is formed on the entire surface including the arrangement region 40b of the heat dissipation base plate 40 included in the heat dissipation unit 4a of the reference example. That is, the plating film 41 in the arrangement region 40b of the heat dissipation unit 4a is not removed. Such a semiconductor device including the heat dissipation unit 4a is also manufactured according to the Figure 3 flowchart.

[0111] First, a preparation process ( Figure 3Step S1). The heat dissipation unit 4a prepared here is manufactured through Figure 3 Steps S10, S11a, and S14. Alternatively, it is manufactured through Figure 3 Steps S10, S12b, and S14.

[0112] Next, a configuration process of sequentially arranging the heat dissipation unit 4, the insulating circuit board 20, and the semiconductor chip 25 is performed ( Figure 3 Step S2). Figure 16 And Figure 17 are used to explain the configuration process. Figure 16 is a cross-sectional view showing the configuration process included in the manufacturing method of the semiconductor device of the reference example. Figure 17 is a schematic cross-sectional view showing the atomic arrangement in the configuration process included in the manufacturing method of the semiconductor device of the reference example. It should be noted that Figure 17 schematically shows Figure 16 the atomic arrangement in the range B surrounded by the dashed line. In addition, Figure 17 only schematically shows the atomic configuration, and the number of stacked atoms does not necessarily represent the thickness of the atomic layer. In this case, since the solder plate 27a is not joined at the stage of being placed on the heat dissipation base plate 40 (plated film 41), an air layer included in the unevenness of the solder plate 27a also exists between the solder plate 27a and the metal plate 23, and between the solder plate 27a and the plated film 41, but its description is omitted.

[0113] As Figure 16 shown, the insulating circuit board 20 is respectively arranged in the arrangement region 40b of the heat dissipation unit 4a formed with the plated film 41 via the solder plate 27a. In addition, the semiconductor chip 25 is arranged on the upper surface 22a of the conductive pattern 22 of the insulating circuit board 20 via the solder plate 26a. It should be noted that the thickness of the plated film 41 formed on the entire surface of the heat dissipation base plate 40 is the same as that commonly used in the first embodiment, and can be, for example, 1 μm or more and 10 μm or less.

[0114] In addition, Figure 16 the range B is near the boundary between the heat dissipation base plate 40 of the heat dissipation unit 4a formed with the plated film 41 and the solder plate 27a. As Figure 17 shown, at the boundary in this range B, the copper atoms included in the heat dissipation base plate 40, the nickel atoms included in the plated film 41, and the tin atoms included in the solder plate 27a are regularly arranged across the boundaries L1 and L2 respectively. The boundary L1 corresponds to the boundary between the solder plate 27a and the plated film 41 when the solder plate 27a is arranged in the arrangement region 40b of the heat dissipation unit 4a (heat dissipation base plate 40). Similarly, the boundary L2 corresponds to the boundary between the heat dissipation base plate 40 and the plated film 41.

[0115] Next, a bonding process of the heat dissipation unit 4a to the insulating circuit board 20 and the insulating circuit board 20 to the semiconductor chip 25 is performed ( Figure 3 step S3). The bonding process will be described using Figures 18 - 20 . Figure 18 FIG. is a first cross-sectional schematic view showing the atomic arrangement in the bonding process (during heating) included in the manufacturing method of the semiconductor device of the reference example, Figure 19 FIG. is a second cross-sectional schematic view showing the atomic arrangement in the bonding process (during heating) included in the manufacturing method of the semiconductor device of the reference example, Figure 20 FIG. is a third cross-sectional schematic view showing the atomic arrangement in the bonding process (during heating) included in the manufacturing method of the semiconductor device of the reference example. It should be noted that Figures 18 - 20 is Figure 16 the atomic arrangement in the range B surrounded by the dashed line, and schematically shows the change with respect to Figure 17 . In addition, Figures 18 - 20 only schematically shows the arrangement of atoms, and the number of stacked atoms does not necessarily represent the thickness of the atomic layer.

[0116] The solder plates 27a between the heat dissipation unit 4a and the insulating circuit board 20 and the solder plate 26a between the conductive pattern 22 of the insulating circuit board 20 and the semiconductor chip 25, which are arranged in step S2, are heated respectively. The solder plates 26a and 27a are melted and transformed into solders 26 and 27.

[0117] When heated in this way, as Figure 18 shown, nickel atoms in any part of the plating film 41 move across the boundary L1 and diffuse into the tin atoms of the molten solder 27. On the other hand, tin atoms in any part of the solder 27 cross the boundary L1 and diffuse into the nickel atoms of the plating film 41. Therefore, an alloy layer containing nickel atoms and tin atoms starts to be formed near the boundary L1.

[0118] When heating continues, the diffusion of nickel atoms in the plating film 41 into the solder 27 and the diffusion of tin atoms in the solder 27 into the plating film 41 progress. As Figure 19 shown, an alloy layer containing nickel atoms and tin atoms near the boundary L1 is further formed. The plating film 41 is thinner than the solder 27. Therefore, the plating film 41 locally reduces nickel atoms and increases tin atoms. In this way, the plating film 41 is locally replaced by nickel atoms with tin atoms, resulting in solder corrosion. It should be noted that when the plating film 41 is thin enough, if all the nickel atoms in the plating film 41 are replaced by tin atoms, the plating film 41 will disappear.

[0119] Furthermore, if continuous heating is carried out, copper atoms with a fast diffusion rate in the heat dissipation base plate 40 cross the boundary L2, causing the part of the plating film 41 where solder corrosion has occurred to move and diffuse into the solder 27. In addition, tin atoms in the solder plate 27a near the boundary L1 cross the boundary L2 and diffuse into the heat dissipation base plate 40. At this time, as Figure 20 shown, the traces of copper atom movement in the heat dissipation base plate 40 become vacancies (Kirkendall voids). Kirkendall voids are mostly generated in the part of the heat dissipation base plate 40 under the remaining plating film 41.

[0120] Use Figure 21 to illustrate the case where after heating, the molten solders 26 and 27 are solidified by cooling, so that the heat dissipation unit 4 is joined to the insulating circuit board 20, and the insulating circuit board 20 is joined to the semiconductor chip 25. Figure 21 is a cross-sectional view showing the bonding process (after bonding) included in the manufacturing method of the semiconductor device of the reference example.

[0121] In this way, the molten solders 26 and 27 are cooled and solidified. Then, as Figure 21 shown, the insulating circuit board 20 is joined to the arrangement region 40b of the heat dissipation unit 4a via the solidified solder 27 respectively. Similarly, the semiconductor chip 25 is joined to the upper surface 22a of the insulating circuit board 20 via the solidified solder 26. However, a plurality of Kirkendall voids (vacancies V) are included in the heat dissipation base plate 40.

[0122] Next, a housing process ( Figure 3 step S4) of mounting the heat dissipation unit 4 on the lower opening 31b of the housing 3 and housing the semiconductor unit 2 in the housing 3, and a wiring process ( Figure 3 step S5) of wiring the semiconductor unit 2 housed in the housing 3 are performed in sequence. Finally, a sealing process ( Figure 3 step S6) of sealing the housing area 31f of the housing 3 with the sealing member 50 is performed. As described above, a semiconductor device including the heat dissipation unit 4a is manufactured.

[0123] In such a heat dissipation unit 4a, as described in Figure 20 , solder corrosion (being eroded by the solder 27) locally occurs in the plating film 41 directly below the solder 27. In addition, as Figure 21As shown, a plurality of Kirkendall voids (vacancies V) are generated below the plating film 41 remaining locally on the heat dissipation base plate 40. If the heat dissipation base plate 40 contains a plurality of Kirkendall voids (vacancies V), the thermal resistance of the heat dissipation base plate 40 increases. In addition, the case where Kirkendall voids are generated in the heat dissipation unit 4a (heat dissipation base plate 40) due to heating in the bonding process is described here. It is not limited to this case, and Kirkendall voids are also generated in the heat generated due to the long-term operation of the semiconductor device 1. In a semiconductor device including such a heat dissipation unit 4a, the heat dissipation performance is reduced.

[0124] Therefore, the above-mentioned semiconductor device 1 includes: an insulating circuit board 20 including a lower surface 23a; a heat dissipation base plate 40 including a front surface 40a, and having a configuration area 40b on the front surface 40a where the lower surface 23a of the insulating circuit board 20 is disposed via a solder 27; a plating film 41 formed on the front surface 40a of the heat dissipation base plate 40 in an area other than a solder area 41b where the solder 27 extends on the configuration area 40b on the front surface 40a; and an alloy layer 44 included between the solder 27 and the configuration area 40b of the heat dissipation base plate 40 and containing the solder components contained in the solder 27. In particular, in the semiconductor device 1, the plating film 41 is formed on the entire surface of the heat dissipation base plate 40 except for an opening area 41a, and the opening area 41a surrounds the outer periphery of the periphery of the configuration area 40b where the insulating circuit board 20 is disposed via the solder 27. That is, the solder 27 for bonding the insulating circuit board 20 is bonded to the heat dissipation base plate 40 without passing through the plating film 41. Therefore, in the configuration area 40b of the heat dissipation base plate 40, the plating film 41 is not eroded by the solder 27. Therefore, the movement of the atoms constituting the heat dissipation base plate 40 is not generated, thereby suppressing the generation of vacancies in the heat dissipation base plate 40. Furthermore, even in the case of heat generated due to the long-term operation of the semiconductor device 1, the generation of vacancies is similarly suppressed. As a result, an increase in the thermal resistance of the heat dissipation base plate 40 is suppressed, thereby suppressing a decrease in the heat dissipation performance of the semiconductor device 1 including the heat dissipation base plate 40. In addition, a decrease in the reliability of the semiconductor device 1 is also prevented.

[0125] [Second Embodiment] In the second embodiment, Figure 22 and Figure 23 are used to describe the case where no plating film is provided on the lower surface 23a of the insulating circuit board 20 in contact with the solder 27 in the semiconductor device 1. Figure 22 is a cross-sectional view of the semiconductor device of the second embodiment. Figure 23 is a rear-side perspective view of the insulating circuit board included in the semiconductor device of the second embodiment.

[0126] On the surface of the metal plate 23 of the insulating circuit board 20 of the semiconductor device 1, as described in the first embodiment, in order to improve the corrosion resistance, a plating treatment may be performed. The insulating circuit board 20 is joined to the arrangement region 40b of the heat dissipation unit 4 via the solder 27. The metal plate 23 that has undergone the plating treatment is in contact with the solder 27 via the plating film. Therefore, solder corrosion of the plating film also occurs in the metal plate 23.

[0127] Therefore, as Figure 22 and Figure 23 shown, a plating film 24 is formed on the surfaces of the metal plate 23 of the insulating circuit board 20 of the second embodiment except for the lower surface 23a. That is, the metal plate 23 does not have the plating film 24 on the lower surface 23a, and the lower surface 23a is arranged in the arrangement region 40b of the heat dissipation base plate 40 via the solder 27. Except for the lower surface 23a, the plating film 24 is formed on the side surfaces in a manner that surrounds the entire periphery of the lower surface 23a.

[0128] Therefore, the solder 27 for joining the heat dissipation unit 4 is joined to the metal plate 23 of the insulating circuit board 20 without passing through the plating film 24. Therefore, on the lower surface 23a of the metal plate 23, the plating film 24 is not eroded by the solder 27. Therefore, the movement of the atoms constituting the metal plate 23 does not occur either, thereby suppressing the generation of vacancies in the metal plate 23. Furthermore, even due to the heat generated by the long-term operation of the semiconductor device 1, the generation of vacancies is similarly suppressed. As a result, an increase in the thermal resistance of the heat dissipation unit 4 and an increase in the thermal resistance of the metal plate 23 are suppressed, thereby suppressing a decrease in the heat dissipation performance of the semiconductor device 1 including the heat dissipation unit 4 and the metal plate 23, and also preventing a decrease in the reliability of the semiconductor device 1.

[0129] [Third Embodiment] Use Figure 24 to describe the heat dissipation unit 4 of the third embodiment. Figure 24 is a top view of the main part of the semiconductor device according to the third embodiment (the sealing member is omitted). It should be noted that the heat dissipation unit 4 of the third embodiment is included in the semiconductor device 1 of the first embodiment.

[0130] A resist film 43 is continuously formed in a ring shape along the opening edge portion of the opening region 41a of the plating film 41 included in the heat dissipation unit 4 of the third embodiment. Examples of the resist film 43 include epoxy resin and acrylic resin.

[0131] There are cases where the solder 27 provided between the configuration region 40b of the heat dissipation base plate 40 and the insulating circuit board 20 extends outward from the configuration region 40b. However, if there is a resist film 43, the extension of the solder 27 is suppressed. If there is no resist film 43 and the solder 27 extends outward from the configuration region 40b, there is a risk that the solder 27 reaches the plating film 41 around the configuration region 40b. If the solder 27 comes into contact with the plating film 41, as described above, voids are generated in the heat dissipation base plate 40 below the plating film 41. By providing the resist film 43 at the opening edge of the opening region 41a of the plating film 41, it is possible to suppress the generation of voids in the heat dissipation base plate 40. In addition, due to the resist film 43, the opening region 41a can be made narrower. The region on the heat dissipation base plate 40 where there is neither the plating film 41 nor the solder 27 can be reduced or eliminated.

[0132] The resist film 43 opposite to the opening region 41a of the plating film 41 can be formed by coating along the opening edge of the opening region 41a of the plating film 41 after performing the Figure 3 steps S10, S11a, and S12a. Alternatively, after step S11a, the resist film 43 can be formed in the opening region 41a of the plating film 41, and then step S12a can be performed.

[0133] In addition, the resist film 43 can be formed by coating along the opening edge of the opening region 41a of the plating film 41 after performing the Figure 3 steps S10, S11b, S12b, and S13b.

[0134] [Fourth Embodiment] The semiconductor device of the fourth embodiment has the same structure as the semiconductor device 1 of the first embodiment except for the heat dissipation unit 4. The following describes such a semiconductor device of the fourth embodiment. Figure 25 This Figure 25 is a cross-sectional view of the semiconductor device of the fourth embodiment. It should be noted that Figure 25 corresponds to that of the first embodiment Figure 1 .

[0135] As Figure 25 shown, the semiconductor device 1a includes a semiconductor unit 2, a heat dissipation unit 4a having the semiconductor unit 2 disposed on the front surface, and a housing 3 provided at the outer edge of the heat dissipation unit 4a for housing the semiconductor unit 2. The inside of the housing 3 of the semiconductor device 1a is sealed by a sealing member 50. The semiconductor unit 2, the housing 3, and the sealing member 50 have the same structure as in the first embodiment. In addition, the solders 26 and 27 provided on the upper surface 22a and the lower surface 23a of the semiconductor unit 2 are also as described in the first embodiment.

[0136] The heat dissipation unit 4a includes a heat dissipation base plate 40 and a plating film 41. The heat dissipation base plate 40 is made of the same material as that in the first embodiment and has the same dimensions. In addition, the front surface 40a of the heat dissipation base plate 40 also includes a configuration area 40b similar to that in the first embodiment, and the lower surface 23a of the insulating circuit board 20 is joined to the configuration area 40b via solder 27. However, the configuration area 40b on the front surface 40a of the heat dissipation base plate 40 in the fourth embodiment is different from that in the first embodiment, and it does not recess in the -Z direction with respect to the front surface 40a of the heat dissipation base plate 40 other than the configuration area 40b. That is, the entire surface of the front surface 40a of the heat dissipation base plate 40 in the fourth embodiment is substantially smooth. The front surface 40a of the heat dissipation base plate 40 includes a solder area 41b formed by the extension of the solder 27 on the configuration area 40b.

[0137] The plating film 41 is made of the same material as in the case of the first embodiment. In addition, the plating film 41 is formed in the area of the front surface 40a of the heat dissipation base plate 40 other than the solder area 41b. Further, the plating film 41 is also formed on the entire surface of the heat dissipation base plate 40 other than the front surface 40a. That is, the plating film 41 is formed on the front surface 40a of the heat dissipation base plate 40 other than the solder area 41b, the back surface 40c opposite to the front surface 40a, and the four side surfaces 40d surrounding the front surface 40a and the back surface 40c, respectively.

[0138] In addition, the thickness of the plating film 41 formed on the front surface 40a is thinner than the thickness of the plating film 41 formed on the back surface 40c and the side surfaces 40d. The thickness of the plating film 41 formed on the front surface 40a is, for example, 0.2 μm or less.

[0139] The insulating circuit board 20 is joined to the solder area 41b of the heat dissipation base plate 40 included in such a heat dissipation unit 4a via solder 27. The plating film 41 is formed on the surface of the heat dissipation base plate 40 other than the solder 27 (solder area 41b). Further, an alloy layer is included between the solder 27 and the front surface 40a of the heat dissipation base plate 40, and the alloy layer contains the solder components contained in the solder 27. Details of this alloy layer will be described later.

[0140] Next, use Figure 26 to describe the manufacturing method of such a semiconductor device 1a. Figure 26 is a flowchart showing the manufacturing method of the semiconductor device according to the fourth embodiment. It should be noted that Figure 26 the flowchart showing the manufacturing method is merely an example. As long as the semiconductor device 1a includes a heat dissipation unit 4a to which the semiconductor unit 2 is joined, it can also be manufactured by a method other than Figure 26 the flowchart. In addition, Figure 26 the processes after step S2 in the flowchart are the same as those in Figure 3The processes after step S2 of the flowchart are the same. Therefore, the description of the processes after step S2 may be simplified here.

[0141] First, a preparation process of preparing the components of the semiconductor device 1a ( Figure 26 step S1a) is performed. The prepared components are, for example, an insulating circuit board 20, a semiconductor chip 25, a housing 3, and a heat dissipation unit 4a. In addition to these, the components required as the components of the semiconductor device 1a are also prepared. Further, a manufacturing device for manufacturing the semiconductor device 1a may also be prepared.

[0142] Here, using Figure 5 , Figure 27 and Figure 28 , the manufacturing method of the heat dissipation unit 4a included in the semiconductor device 1a shown in Figure 25 ( Figure 26 steps S10, S11c, S12c, S14) will be described. Figure 27 is a cross-sectional view showing the manufacturing process (plating process) of the heat dissipation unit included in the manufacturing method of the semiconductor device according to the fourth embodiment. Figure 28 is a cross-sectional view showing the manufacturing process (thinning process) of the heat dissipation unit included in the manufacturing method of the semiconductor device according to the fourth embodiment. It should be noted that Figure 27 and Figure 28 correspond to the cross-sectional part at the single-dot chain line X-X in Figure 6 .

[0143] First, similar to the first embodiment, a heat dissipation base plate 40 ( Figure 26 step S10) is prepared. Next, the entire surface of the heat dissipation base plate 40 is subjected to a plating process to form a plating film 41 ( Figure 26 step S11c). For example, as shown in Figure 27 , the front surface 40a, the back surface 40c, and the side surface 40d of the heat dissipation base plate 40 are subjected to a plating process to form a plating film 41. The plating process is a generally known method, and for example, it may be an electrolytic plating method or an electroless plating method. The thickness of the plating film 41 formed on the entire surface of the heat dissipation base plate 40 may be the same thickness. It should be noted that in this case, the thickness may be, for example, 1 μm or more and 10 μm or less.

[0144] Next, the plating film 41 on the front surface 40a of the heat dissipation base plate 40 is thinned ( Figure 26 step S12c). The entire plating film 41 on the front surface 40a of the plating film 41 formed on the surface of the heat dissipation base plate 40 is uniformly ground. As shown in Figure 28As shown, the plating film 41 on the front surface 40a of the heat dissipation base plate 40 becomes thinner than other surfaces, and its thickness is 0.2 μm or less. As described above, it is possible to prepare the heat dissipation unit 4a ( Figure 26 step S14).

[0145] In addition, the heat dissipation unit 4a can also be manufactured by the following manufacturing method. For example, in Figure 26 the plating process of step S11c, the plating film 41 formed on the front surface 40a of the heat dissipation base plate 40 can be plated in such a way that its thickness is thinner than the plating film 41 formed on other surfaces.

[0146] In addition, in the above, the case where the entire plating film 41 on the front surface 40a of the heat dissipation base plate 40 becomes thinner than other surfaces is taken as an example. It is not limited to this case, and only the solder region 41b of the plating film 41 formed on the front surface 40a of the heat dissipation base plate 40 can be thinned. The formation of such a plating film 41 can be the same as step S11c above, forming a plating film 41 on the entire surface of the heat dissipation base plate 40, and only grinding the plating film 41 in the solder region 41b in step S12c to thin it.

[0147] Alternatively, a plating film 41 can be formed on the entire surface of the heat dissipation base plate 40 until the thickness of the plating film 41 becomes at least 0.2 μm, a mask is provided in the solder region 41b of the plating film 41, and then a plating film 41 is formed and the mask is removed. It should be noted that in this case, the plating film 41 is also formed on the heat dissipation base plate 40 using the electrolytic plating method or the electroless plating method until the thickness of the plating film 41 becomes the desired thickness. As described above, it is possible to make only the solder region 41b of the plating film 41 formed on the front surface 40a of the heat dissipation base plate 40 thinner than other parts.

[0148] Alternatively, the thickness of the plating film 41 formed on the entire surface of the heat dissipation base plate 40 including the solder region 41b can be set to 0.2 μm or less. In this case, the plating film 41 is also formed on the heat dissipation base plate 40 using the electrolytic plating method or the electroless plating method until the thickness of the plating film 41 becomes the desired thickness.

[0149] Next, a configuration process ( Figure 26 step S2) of sequentially arranging the heat dissipation unit 4a, the insulating circuit board 20, and the semiconductor chip 25 is performed. Use Figure 29 and Figure 30 to illustrate the configuration process. Figure 29 is a cross-sectional view showing the configuration process included in the manufacturing method of the semiconductor device according to the fourth embodiment. Figure 30It is a cross-sectional schematic view showing the atomic arrangement in the configuration process included in the manufacturing method of the semiconductor device according to the fourth embodiment. It should be noted that Figure 30 schematically shows Figure 29 the atomic arrangement in the range B surrounded by the dashed line. Additionally, Figure 30 only schematically shows the atomic configuration, and the number of stacked atoms does not necessarily represent the thickness of the atomic layer.

[0150] The insulating circuit board 20 is respectively disposed via the solder plate 27a in the arrangement region 40b of the plating film 41 formed on the heat dissipation unit 4a. The solder plate 27a is formed by curing the solder 27 in a plate shape. In this case, similarly to the first embodiment, the solder plate 27a can be, for example, the same size as the lower surface 23a of the metal plate 23 of the insulating circuit board 20 in a top view.

[0151] The semiconductor chip 25 is disposed via the solder plate 26a on the upper surface 22a of the conductive pattern 22 of the insulating circuit board 20. The solder plate 26a is formed by curing the solder 26 in a plate shape. The solder plate 26a can be, for example, the same size as the semiconductor chip 25 in a top view.

[0152] As Figure 29 shown, through such a configuration process, the insulating circuit board 20 is disposed via the solder plate 27a in the arrangement region 40b of the heat dissipation unit 4a, and the semiconductor chip 25 is disposed via the solder plate 26a on the conductive pattern 22 of the insulating circuit board 20.

[0153] Additionally, Figure 29 the range B is near the boundary between the heat dissipation base plate 40 and the solder plate 27a in the heat dissipation unit 4a. As Figure 30 shown, at the boundary of this range B, the tin atoms as the solder component contained in the solder plate 27a and the nickel atoms contained in the plating film 41 are regularly arranged across the boundary L1. The boundary L1 corresponds to the boundary between the solder plate 27a and the plating film 41 when the solder plate 27a is disposed on the plating film 41. It should be noted that in addition to tin, the boundary can also contain solder components such as silver and zinc. Hereinafter, only the representative tin is described as the solder component, but other solder components can also be included.

[0154] Additionally, the nickel atoms contained in the plating film 41 and the copper atoms contained in the heat dissipation base plate 40 are regularly arranged across the boundary L2. The boundary L2 corresponds to the boundary between the plating film 41 and the arrangement region 40b of the heat dissipation base plate 40 when the plating film 41 is formed in the arrangement region 40b of the heat dissipation unit 4a (heat dissipation base plate 40).

[0155] It should be noted that since the solder plate 27a is not joined at the stage of being placed on the heat dissipation base plate 40 (plated film 41), an air layer included in the unevenness of the solder plate 27a exists between the solder plate 27a and the metal plate 23, and between the solder plate 27a and the heat dissipation base plate 40 (plated film 41), but its description is omitted.

[0156] Next, a bonding process of the heat dissipation unit 4a to the insulating circuit board 20 and the insulating circuit board 20 to the semiconductor chip 25 ( Figure 26 step S3). Use Figure 31 and Figure 32 to describe the bonding process. Figure 31 is a cross-sectional view showing the bonding process included in the manufacturing method of the semiconductor device of the fourth embodiment. Figure 32 is a schematic cross-sectional view showing the atomic arrangement in the bonding process included in the manufacturing method of the semiconductor device of the fourth embodiment. It should be noted that Figure 32 schematically shows Figure 31 the atomic arrangement of the range B surrounded by the dashed line. In addition, Figure 32 only schematically shows the arrangement of atoms, and the number of stacked atoms does not necessarily represent the thickness of the atomic layer.

[0157] The solder plates 27a between the heat dissipation unit 4a and the insulating circuit board 20 and the solder plate 26a between the conductive pattern 22 of the insulating circuit board 20 and the semiconductor chip 25, which are arranged in step S2, are heated respectively. The solder plates 26a and 27a are each melted and transformed into solders 26 and 27.

[0158] When heated in this way, the tin atoms of the molten solder 27 and the nickel atoms of the plated film 41 move across the boundary L1 and diffuse respectively. In addition, the copper atoms of the heat dissipation base plate 40 and the nickel atoms of the plated film 41 move across the boundary L2 and diffuse respectively. Furthermore, the tin atoms of the molten solder 27 further move across the boundary L2 and diffuse into the copper atoms of the heat dissipation base plate 40. In addition, the copper atoms of the heat dissipation base plate 40 further move across the boundary L1 and diffuse into the tin atoms of the molten solder 27.

[0159] The plated film 41 on the front surface 40a of the heat dissipation base plate 40 is formed thin enough. Therefore, the plated film 41 is replaced by tin atoms and copper atoms with nickel atoms, resulting in plating corrosion. As a result, as Figure 32 shown, near the boundaries L1 and L2, the plated film 41 is corroded between the solder 27 and the heat dissipation base plate 40, and an alloy layer 44 is formed. At this time, in Figure 20In the heat dissipation base board 40 shown, the traces of copper atom movement do not become vacancies (Kirkendall voids). It should be noted that the alloy layer 44 contains copper atoms, tin atoms, and nickel atoms. Such an alloy layer 44 can be included at the boundary between the solder 27 and the heat dissipation base board 40 in a manner not limited to the position within range B.

[0160] The molten solders 26 and 27 are thus cooled and solidified, and the insulating circuit boards 20 are respectively joined to the arrangement regions 40b of the heat dissipation unit 4a (the front surface 40a of the heat dissipation base board 40) via the solidified solder 27. Similarly, the semiconductor chips 25 are joined to the upper surface 22a of the insulating circuit boards 20 via the solidified solder 26.

[0161] Therefore, the semiconductor unit 2 including the insulating circuit boards 20 and the semiconductor chips 25 is formed. In addition, the semiconductor unit 2 is respectively joined to the arrangement regions 40b of the heat dissipation unit 4a by the solder 27.

[0162] After that, in the same manner as in the first embodiment, the processes of the flowchart, namely, the housing process ( Figure 26 step S4), the wiring process ( Figure 26 step S5), and the sealing process ( Figure 26 step S6), are sequentially performed. As described above, the Figure 25 semiconductor device 1a shown is obtained.

[0163] In the semiconductor device 1a described above, the insulating circuit board 20 and the heat dissipation base board 40 having the plating film 41 on the front surface 40a are also joined by the solder plate 27a. Therefore, in the arrangement region 40b of the heat dissipation base board 40, the plating film 41 is corroded. That is, the thickness of the plating film 41 on the front surface 40a of the heat dissipation base board 40 of the semiconductor device 1a is sufficiently thin compared to the case of the reference example shown in Figure 16 and disappears during joining. Therefore, an alloy layer 44 including the atoms constituting the heat dissipation base board 40, the tin atoms constituting the solder 27, and the nickel atoms constituting the plating film 41 is formed, thereby suppressing the generation of vacancies in the heat dissipation base board 40. Furthermore, even due to the heat generated by the long-term operation of the semiconductor device 1a, the generation of vacancies is similarly suppressed. As a result, an increase in the thermal resistance of the heat dissipation base board 40 is suppressed, thereby suppressing a decrease in the heat dissipation performance of the semiconductor device 1a including the heat dissipation base board 40. Also, a decrease in the reliability of the semiconductor device 1a is prevented.

[0164] The above only shows the principle of the present invention. In addition, many deformations and changes can be made by those skilled in the art. The present invention is not limited to the exact configurations and application examples shown and described above, and all corresponding deformation examples and equivalents are considered to be within the scope of the present invention based on the appended claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, comprising: a substrate including a lower surface; a heat dissipation base plate including a main surface and having a configuration area on the main surface for disposing the lower surface of the substrate via solder; a first plating film formed in an area of the main surface of the heat dissipation base plate other than a solder area where the solder extends on the configuration area of the main surface; and an alloy layer included between the solder and the configuration area of the heat dissipation base plate and containing a solder component contained in the solder.

2. The semiconductor device according to claim 1, wherein the alloy layer further contains a first metal material contained in the heat dissipation base plate together with the solder component.

3. The semiconductor device according to claim 2, wherein the first metal material contains copper.

4. The semiconductor device according to claim 1, wherein the first plating film is mainly composed of nickel.

5. The semiconductor device according to claim 1, wherein the periphery of the configuration area is located more inward than the periphery of the substrate in a top view.

6. The semiconductor device according to claim 1, wherein the first plating film is further formed in an area of the main surface of the heat dissipation base plate other than an opening area surrounding the entire periphery of the solder area.

7. The semiconductor device according to claim 6, wherein the configuration area is recessed into a concave shape with respect to the main surface other than the configuration area.

8. The semiconductor device according to claim 7, wherein the solder includes solder legs extending outward from the lower surface of the substrate in a top view.

9. The semiconductor device according to claim 8, wherein the outer peripheral edge of the solder legs of the solder is located outside the configuration area in a top view.

10. The semiconductor device according to claim 6, wherein the substrate includes: an insulating plate; a conductive pattern formed on the front surface of the insulating plate; and a metal plate formed on the back surface of the insulating plate and including the lower surface, a second plating film is formed on the side surface of the metal plate in a manner surrounding the entire periphery of the lower surface except for the lower surface.

11. The semiconductor device according to claim 10, wherein the metal plate is mainly composed of copper.

12. The semiconductor device according to claim 10, wherein the second plating film is mainly composed of nickel.

13. The semiconductor device according to claim 6, wherein the semiconductor device is formed with a resist material surrounding the entire periphery of the opening edge of the first plating film formed on the front surface of the heat dissipation base plate.

14. The semiconductor device according to claim 2, wherein the alloy layer further contains a second metal material constituting the first plating film together with the solder component and the first metal material.

15. The semiconductor device according to claim 14, wherein The second metal material contains nickel.

16. The semiconductor device according to claim 14, wherein the first plating film is further formed on the surface of the heat dissipation base plate other than the main surface, and the thickness of the first plating film formed on the main surface is thinner than the thickness of the first plating film formed on the surface other than the main surface.

17. The semiconductor device according to claim 14, wherein the thickness of the first plating film formed on the main surface is less than 0.2 μm.

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