Battery cell testing system and multi-stage boost speed control system

Abstract

The present invention discloses a battery cell testing system and a multi-stage boost speed control system. The battery cell testing system includes a power supply circuit, a bus output power modulation circuit, a transformer, a rectifier bridge, a switching circuit, a current measurement circuit, a voltage measurement circuit and a controller. The controller first calculates the capacitance of the load to be tested, and controls the voltage output by the power supply circuit, the on-off state of the switching circuit and the working state of the bus output power modulation circuit according to the capacitance until the voltage across the load to be tested reaches a set voltage. After that, the MOS tube Q7 and the MOS tube Q8 are controlled to be disconnected, and the load to be tested is in a self-discharge state. When the voltage of the load to be tested measured by the voltage measurement circuit is higher than a second set voltage, the load to be tested is qualified, otherwise, it is unqualified. The battery cell testing system of the present invention can effectively identify the load size and select an appropriate topological structure and boost speed according to the load size, so that the boost speed is consistent with the load, avoiding overshoot of small loads and the technical problem of low efficiency of large load testing.

Description

Technical Field

[0001] The present invention belongs to the technical field of battery cell testing, and in particular relates to a battery cell testing system and a multi-stage boost speed regulation control system. Background Art

[0002] With the promotion of new energy, the application of lithium batteries is becoming increasingly widespread. The quality of lithium batteries is directly related to safety issues. Therefore, lithium battery testing is necessary during the production process. Lithium-ion batteries are structurally required to maintain insulation between the positive and negative electrodes, as well as between each electrode and the outer casing. During the lithium-ion battery production process, the intrusion of metallic foreign matter or damage to the separator can cause the insulation resistance to decrease. If the insulation state cannot be maintained, it can lead to a shortened battery life or even fire accidents.

[0003] To meet the needs of the electric vehicle industry, lithium-ion batteries used in electric vehicles must have high energy density, be capable of high-current charging, have a long lifespan, and be safe and fire-resistant. To achieve these characteristics, performance testing of lithium-ion batteries is required during the battery manufacturing process. Currently, there are two main methods for testing lithium battery cells. The first uses a pulse test, charging the battery cell to a specified voltage and then stopping to test whether the battery voltage drops rapidly. After the test time is reached, the cell is discharged. The second insulation test method applies a specified voltage to the cell and then tests its insulation resistance. Both test methods use a high-voltage DC source, and have high requirements for the output voltage fluctuation of the high-voltage DC source.

[0004] The equivalent model of a lithium battery cell before liquid injection is a capacitor, and cells of different capacities have different equivalent capacitance values. A small capacitance value will cause the high-voltage DC source output to overshoot, and the voltage overshoot will cause a certain degree of damage to the cell. The cell with large capacitance has a slow voltage boost speed, which seriously affects the test efficiency.

[0005] In addition, battery cells of the same capacity will perform differently at different boost speeds. When the battery cells are impacted by instantaneous pulses, the metal ions on their internal diaphragms will also behave differently under the influence of rapidly changing electric field forces.

[0006] The above information disclosed in this background technology is only used to increase the understanding of the background technology of this application. Therefore, it may contain information that does not constitute the prior art known to ordinary technicians in this field. Summary of the Invention

[0007] The present invention proposes a battery cell testing system to solve the technical problems that the existing battery cell testing system may cause high-voltage DC source output overshoot for small-capacitance batteries, resulting in damage to the batteries, and low testing efficiency for large-capacitance batteries.

[0008] In order to achieve the above invention / design purpose, the present invention adopts the following technical solutions:

[0009] A battery cell testing system, comprising:

[0010] Power supply circuit;

[0011] A bus output power modulation circuit includes a MOS transistor driver chip, a MOS transistor Q7, a MOS transistor Q8, a capacitor C1, and a capacitor C2; the gates of the MOS transistors Q7 and Q8 are connected to the MOS transistor driver chip, the source of the MOS transistor Q7 is connected to the drain of the MOS transistor Q8, and the capacitors C1 and C2 connected in series are connected between the drain of the MOS transistor Q7 and the source of the MOS transistor Q8;

[0012] A transformer, wherein the primary coil of the transformer is connected between the capacitor C1 and the capacitor C2, and between the source of the MOS transistor Q7 and the drain of the MOS transistor Q8;

[0013] A rectifier bridge includes a diode D1, a diode D2, a diode D3, and a diode D4, wherein the anode of the diode D1 and the cathode of the diode D3, and the anode of the diode D2 and the cathode of the diode D4 are respectively connected to the secondary coil of the transformer; the cathode of the diode D1 and the cathode of the diode D2, and the anode of the diode D3 and the anode of the diode D4 are connected in series via a load to be measured C4 and a resistor R2;

[0014] A first switch circuit is connected between the power circuit, the drain of the MOS transistor Q7 and the capacitor C1;

[0015] a second switch circuit connected between the primary coil of the transformer, the capacitor C1 and the capacitor C2;

[0016] a third switch circuit connected between the power supply circuit, the primary coil of the transformer, and the second switch circuit;

[0017] a fourth switch circuit connected between the anode of the diode D2 and the cathode of the diode D4;

[0018] A voltage measuring circuit, used for measuring the voltage of the load C4 to be measured;

[0019] a current measuring circuit, configured to measure the current flowing through the resistor R2;

[0020] A controller outputs control signals to the power supply circuit, the MOS transistor driver chip, the first switch circuit, the second switch circuit, and the third switch circuit, and receives signals from the voltage measurement circuit and the current measurement circuit;

[0021] Controlling the first switch circuit to be disconnected, the second switch circuit to be disconnected, the third switch circuit to be turned on, and the fourth switch circuit to be disconnected; controlling the power supply circuit to output a first voltage, controlling the MOS transistor Q8 to be turned on and off according to a first duty cycle, receiving the current I detected by the current measurement circuit and the voltage V detected by the voltage measurement circuit, and timing t to calculate the capacitance of the load C4 to be measured;

[0022] Controlling the voltage output by the power supply circuit according to the capacitance of the load C4 to be tested, controlling the on and off of the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit; and controlling the working state of the bus output power modulation circuit until the voltage across the load C4 to be tested reaches a set voltage;

[0023] After the voltage across the load C4 to be tested reaches a set voltage, the MOS transistor Q7 and the MOS transistor Q8 are controlled to be disconnected, and the load C4 to be tested is in a self-discharge state. When the voltage of the load C4 to be tested measured by the voltage measurement circuit is higher than a second set voltage, the load C4 to be tested is judged to be qualified; otherwise, it is unqualified;

[0024] Wherein, the second set voltage is lower than the set voltage.

[0025] In the battery cell testing system as described above, the controller is configured as follows:

[0026] When the capacitance of the load C4 to be tested is in the first capacitance range, the power supply circuit is controlled to output a first voltage, the first switch circuit is controlled to be disconnected, the second switch circuit is controlled to be disconnected, the third switch circuit is controlled to be connected, and the fourth switch circuit is controlled to be disconnected; and the MOS transistor Q8 is controlled to be turned on and off according to a first duty cycle until the voltage across the load C4 to be tested reaches a set voltage;

[0027] When the capacitance of the load C4 to be measured is in the second capacitance range, the power supply circuit is controlled to output a first voltage, the first switch circuit is controlled to be turned on, the second switch circuit is controlled to be turned on, the third switch circuit is controlled to be turned off, and the fourth switch circuit is controlled to be turned on; the MOS transistor Q7 and the MOS transistor Q8 are controlled to be turned on and off according to a second duty cycle, and the output voltage of the power supply circuit is adjusted according to the capacitance of the load C4 to be measured until the voltage across the load C4 to be measured reaches a first set voltage; the first switch circuit is controlled to be turned off, the second switch circuit is controlled to be turned off, the third switch circuit is controlled to be turned on, and the fourth switch circuit is controlled to be turned off; and the MOS transistor Q8 is controlled to be turned on and off according to the first duty cycle until the voltage across the load C4 to be measured reaches the set voltage;

[0028] When the capacitance of the load C4 to be measured is within a third capacitance range, the power supply circuit is controlled to output a first voltage, the first switch circuit is controlled to be turned on, the second switch circuit is controlled to be turned on, the third switch circuit is controlled to be turned off, and the fourth switch circuit is controlled to be turned on; the MOS transistor Q7 and the MOS transistor Q8 are controlled to be turned on and off according to a second duty cycle, and the output voltage of the power supply circuit is adjusted according to the capacitance of the load C4 to be measured until the voltage across the load C4 to be measured reaches a set voltage;

[0029] The capacitance value of the first capacitance range is lower than that of the second capacitance range, and the capacitance value of the second capacitance range is lower than that of the third capacitance range;

[0030] Wherein, the first set voltage is lower than the set voltage.

[0031] In the battery cell testing system described above, the controller is configured to Calculate C, where C is the capacitance of the load C4 to be measured, and t represents time.

[0032] The battery cell testing system as described above, the testing system comprises:

[0033] a digital-to-analog converter, connected to the controller;

[0034] A comparator A2, having a non-inverting input connected to the digital-to-analog converter, an inverting input connected to the voltage measurement circuit, and an output connected to the fifth switch circuit;

[0035] a fifth switch circuit connected to the cathodes of the diode D1 and the diode D2 and the load C4 to be measured;

[0036] an anti-overshoot capacitor C3, one end of which is connected to the anodes of the diodes D3 and D4, and the other end of which is connected to the cathodes of the diodes D1 and D2 via a diode D6, wherein the anode of the diode D6 is connected to the cathodes of the diodes D1 and D2, and the cathode of the diode D6 is connected to the anti-overshoot capacitor C3;

[0037] The controller is configured to receive the set maximum rising voltage of each step, calculate the maximum value of the next voltage boost based on the current voltage detected by the voltage measurement circuit and the maximum rising voltage, and send it to the digital-to-analog converter; when the voltage at the non-inverting input terminal of the comparator A2 is lower than the voltage at the inverting input terminal, the output terminal of the comparator A2 controls the fifth switch circuit to be disconnected, and stops charging the load C4 to be tested until the controller calculates the maximum value of the next voltage boost.

[0038] The battery cell testing system as described above, the system comprises:

[0039] a first voltage measurement circuit connected between the anti-overshoot capacitor C3 and the cathode of the diode D6;

[0040] A comparator A1, having a non-inverting input connected to the digital-to-analog converter, an inverting input connected to the first voltage measurement circuit, and an output connected to the sixth switch circuit;

[0041] a sixth switch circuit connected to the resistor R1 and to the anodes of the diodes D3 and D4; the resistor R1 is connected between the diode D6 and the anti-overshoot capacitor C3;

[0042] When the voltage at the non-inverting input terminal of the comparator A1 is lower than the voltage at the inverting input terminal, the output terminal of the comparator A1 controls the sixth switch circuit to be turned on, and the electric energy of the anti-overshoot capacitor C3 is released through the resistor R1. When the voltage at the non-inverting input terminal of the comparator A1 is higher than the voltage at the inverting input terminal, the output terminal of the comparator A1 controls the sixth switch circuit to be turned off.

[0043] In the battery cell testing system as described above, the controller is configured to send data to the digital-to-analog converter after the test is completed, output a low-voltage analog quantity, and the output end of the comparator A1 controls the sixth switch circuit to turn on, releasing the electrical energy of the anti-overshoot capacitor C3 and the load to be tested C4.

[0044] A multi-stage boost speed control system, comprising:

[0045] Power supply circuit;

[0046] A bus output power modulation circuit includes a MOS transistor driver chip, a MOS transistor Q7, a MOS transistor Q8, a capacitor C1, and a capacitor C2; the gates of the MOS transistors Q7 and Q8 are connected to the MOS transistor driver chip, the source of the MOS transistor Q7 is connected to the drain of the MOS transistor Q8, and the capacitors C1 and C2 connected in series are connected between the drain of the MOS transistor Q7 and the source of the MOS transistor Q8;

[0047] A transformer, wherein the primary coil of the transformer is connected between the capacitor C1 and the capacitor C2, and between the source of the MOS transistor Q7 and the drain of the MOS transistor Q8;

[0048] A rectifier bridge includes a diode D1, a diode D2, a diode D3, and a diode D4, wherein the anode of the diode D1 and the cathode of the diode D3, and the anode of the diode D2 and the cathode of the diode D4 are respectively connected to the secondary coil of the transformer; the cathode of the diode D1 and the cathode of the diode D2, and the anode of the diode D3 and the anode of the diode D4 are connected in series via a load to be measured C4 and a resistor R2;

[0049] A first switch circuit is connected between the power circuit, the drain of the MOS transistor Q7 and the capacitor C1;

[0050] a second switch circuit connected between the primary coil of the transformer, the capacitor C1 and the capacitor C2;

[0051] a third switch circuit connected between the power supply circuit, the primary coil of the transformer, and the second switch circuit;

[0052] a fourth switch circuit connected between the anode of the diode D2 and the cathode of the diode D4;

[0053] A voltage measuring circuit, used for measuring the voltage of the load C4 to be measured;

[0054] a current measuring circuit, configured to measure the current flowing through the resistor R2;

[0055] A controller outputs control signals to the power supply circuit, the MOS transistor driver chip, the first switch circuit, the second switch circuit, and the third switch circuit, and receives signals from the voltage measurement circuit and the current measurement circuit;

[0056] The controller is configured to control the first switch circuit to be disconnected, the second switch circuit to be disconnected, the third switch circuit to be turned on, and the fourth switch circuit to be disconnected; control the power supply circuit to output a first voltage, control the MOS transistor Q8 to be turned on and off according to a first duty cycle, receive the current I detected by the current measurement circuit and the voltage V detected by the voltage measurement circuit, and time t to calculate the capacitance of the load C4 to be measured;

[0057] The voltage output by the power supply circuit is controlled according to the capacitance of the load C4 to be tested, and the on and off of the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit are controlled; and the working state of the bus output power modulation circuit is controlled until the voltage across the load C4 to be tested reaches the set voltage.

[0058] The multi-stage boost speed control system described above,

[0059] The controller is configured as follows:

[0060] When the capacitance of the load C4 to be tested is in the first capacitance range, the power supply circuit is controlled to output a first voltage, the first switch circuit is controlled to be disconnected, the second switch circuit is controlled to be disconnected, the third switch circuit is controlled to be connected, and the fourth switch circuit is controlled to be disconnected; and the MOS transistor Q8 is controlled to be turned on and off according to a first duty cycle until the voltage across the load C4 to be tested reaches a set voltage;

[0061] When the capacitance of the load C4 to be measured is in the second capacitance range, the power supply circuit is controlled to output a first voltage, the first switch circuit is controlled to be turned on, the second switch circuit is controlled to be turned on, the third switch circuit is controlled to be turned off, and the fourth switch circuit is controlled to be turned on; the MOS transistor Q7 and the MOS transistor Q8 are controlled to be turned on and off according to a second duty cycle, and the output voltage of the power supply circuit is adjusted according to the capacitance of the load C4 to be measured until the voltage across the load C4 to be measured reaches a first set voltage; the first switch circuit is controlled to be turned off, the second switch circuit is controlled to be turned off, the third switch circuit is controlled to be turned on, and the fourth switch circuit is controlled to be turned off; and the MOS transistor Q8 is controlled to be turned on and off according to the first duty cycle until the voltage across the load C4 to be measured reaches the set voltage;

[0062] When the capacitance of the load C4 to be measured is within a third capacitance range, the power supply circuit is controlled to output a first voltage, the first switch circuit is controlled to be turned on, the second switch circuit is controlled to be turned on, the third switch circuit is controlled to be turned off, and the fourth switch circuit is controlled to be turned on; the MOS transistor Q7 and the MOS transistor Q8 are controlled to be turned on and off according to a second duty cycle, and the output voltage of the power supply circuit is adjusted according to the capacitance of the load C4 to be measured until the voltage across the load C4 to be measured reaches a set voltage;

[0063] The capacitance value of the first capacitance range is lower than that of the second capacitance range, and the capacitance value of the second capacitance range is lower than that of the third capacitance range; and the first set voltage is lower than the set voltage.

[0064] The multi-stage boost speed control system as described above comprises:

[0065] a digital-to-analog converter, connected to the controller;

[0066] A comparator A2, having a non-inverting input connected to the digital-to-analog converter, an inverting input connected to the voltage measurement circuit, and an output connected to the fifth switch circuit;

[0067] a fifth switch circuit connected to the cathodes of the diode D1 and the diode D2 and the load C4 to be measured;

[0068] an anti-overshoot capacitor C3, one end of which is connected to the anodes of the diodes D3 and D4, and the other end of which is connected to the cathodes of the diodes D1 and D2 via a diode D6, wherein the anode of the diode D6 is connected to the cathodes of the diodes D1 and D2, and the cathode of the diode D6 is connected to the anti-overshoot capacitor C3;

[0069] The controller is configured to receive the set maximum rising voltage of each step, calculate the maximum value of the next voltage boost based on the current voltage detected by the voltage measurement circuit and the maximum rising voltage, and send it to the digital-to-analog converter; when the voltage at the non-inverting input terminal of the comparator A2 is lower than the voltage at the inverting input terminal, the output terminal of the comparator A2 controls the fifth switch circuit to be disconnected, and stops charging the load C4 to be tested until the controller calculates the maximum value of the next voltage boost.

[0070] The multi-stage boost speed control system as described above comprises:

[0071] a first voltage measurement circuit connected between the anti-overshoot capacitor C3 and the cathode of the diode D6;

[0072] A comparator A1, having a non-inverting input connected to the digital-to-analog converter, an inverting input connected to the first voltage measurement circuit, and an output connected to the sixth switch circuit;

[0073] a sixth switch circuit connected to the resistor R1 and to the anodes of the diodes D3 and D4; the resistor R1 is connected between the diode D6 and the anti-overshoot capacitor C3;

[0074] When the voltage at the non-inverting input terminal of the comparator A1 is lower than the voltage at the inverting input terminal, the output terminal of the comparator A1 controls the sixth switch circuit to be turned on, and the electric energy of the anti-overshoot capacitor C3 is released through the resistor R1. When the voltage at the non-inverting input terminal of the comparator A1 is higher than the voltage at the inverting input terminal, the output terminal of the comparator A1 controls the sixth switch circuit to be turned off.

[0075] Compared with the prior art, the advantages and positive effects of the present invention are as follows: the battery cell testing system of the present invention includes a power supply circuit, a bus output power modulation circuit, a transformer, a rectifier bridge, a switching circuit, a current measurement circuit, a voltage measurement circuit and a controller. The controller first calculates the capacitance of the load to be tested, and controls the voltage output by the power supply circuit, the on-off state of the switching circuit and the working state of the bus output power modulation circuit according to the capacitance until the voltage across the load to be tested reaches the set voltage. After the voltage across the load to be tested reaches the set voltage, the MOS tube Q7 and the MOS tube Q8 are controlled to be disconnected, and the load to be tested is in a self-discharge state. When the voltage of the load to be tested measured by the voltage measurement circuit is higher than the second set voltage, the load to be tested is qualified, otherwise, it is unqualified. The battery cell testing system of the present invention can effectively identify the load size and select an appropriate topology and boost speed according to the load size, so that the boost speed is consistent with the load, avoiding the technical problems of overshoot of small loads and low efficiency of large load testing.

[0076] The multi-stage boost speed control system of the present invention includes a power supply circuit, a bus output power modulation circuit, a transformer, a rectifier bridge, a switching circuit, a current measurement circuit, a voltage measurement circuit, and a controller. The controller first calculates the capacitance of the load to be measured and, based on the capacitance, controls the voltage output by the power supply circuit, the on / off state of the switching circuit, and the operating state of the bus output power modulation circuit until the voltage across the load to be measured reaches a set voltage. The multi-stage boost speed control system of the present invention can effectively identify the load size and select the appropriate topology and boost speed based on the load size, thereby ensuring that the boost speed matches the load, avoiding the technical problems of overshoot under small loads and slow boost speed under large loads.

[0077] Other features and advantages of the present invention will become more apparent after reading the detailed description of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0079] Figure 1 This is a circuit architecture principle block diagram of a battery cell testing system according to a specific embodiment of the present invention;

[0080] Figure 2 A schematic diagram of a flyback busbar structure according to a specific embodiment of the present invention;

[0081] Figure 3 This is a schematic diagram of a half-bridge busbar structure according to a specific embodiment of the present invention:

[0082] Figure 4 This is a gate voltage waveform diagram of the N-type MOS transistor Q7 and the N-type MOS transistor Q8 when the capacitance of the load to be measured is in the first capacitance range according to a specific embodiment of the present invention;

[0083] Figure 5 This is a waveform diagram of the gate voltage of the N-type MOS transistor Q7 and the N-type MOS transistor Q8 when the capacitance of the load to be measured is in the second capacitance range according to a specific embodiment of the present invention;

[0084] Figure 6 This is a waveform diagram of the gate voltage of the N-type MOS transistor Q7 and the N-type MOS transistor Q8 when the capacitance of the load to be measured is in the third capacitance range according to a specific embodiment of the present invention;

[0085] Figure 7 This is a test comparison chart of three load types in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0086] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0087] In the description of the present invention, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be understood as a limitation on the present invention.

[0088] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections. A person of ordinary skill in the art will understand the specific meanings of the above terms in the present invention in specific circumstances. In the description of the embodiments, specific features, structures, materials, or characteristics may be combined in any appropriate manner in any one or more embodiments or examples.

[0089] The terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the quantity of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features.

[0090] In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0091] like Figure 1 As shown, the battery cell test system includes a power supply circuit, a bus output power modulation circuit, a transformer, a rectifier bridge, a first to fourth switch circuit, a voltage measurement circuit, a current measurement circuit and a controller. The following is a detailed description of each part:

[0092] The power supply circuit, in some embodiments, is a BUCK-BOOST power supply circuit with an output voltage range of 3V to 48V.

[0093] The bus output power modulation circuit includes a MOS transistor driver chip, a MOS transistor Q7, a MOS transistor Q8, a capacitor C1, and a capacitor C2.

[0094] In some embodiments, the MOS transistor driver chip is an EG1160MOS driver chip. The EG1160MOS driver chip is directly controlled by an MCU and can realize single MOS transistor control. The MOS transistor's on-time and duty cycle can be adjusted by the MCU control chip through a program, providing flexible control.

[0095] MOS transistors Q7 and MOS transistors Q8 are N-type MOS transistors. The gates of MOS transistors Q7 and MOS transistors Q8 are connected to a MOS transistor driver chip. The source of MOS transistor Q7 is connected to the drain of MOS transistor Q8. Capacitors C1 and C2 are connected in series between the drain of MOS transistor Q7 and the source of MOS transistor Q8. Capacitor C1 is connected to the drain of MOS transistor Q7, and capacitor C2 is connected to the source of MOS transistor Q8.

[0096] N-type MOS transistor Q7 and N-type MOS transistor Q8 operate at a cycle of 4 kHz, and their duty cycle is adjustable from 1% to 40%.

[0097] The first switch circuit is connected between the power circuit, the drain of the MOS transistor Q7 and the capacitor C1.

[0098] In some embodiments, the first switch circuit includes an N-type MOS transistor Q1 , an N-type MOS transistor Q2 , and a MOS transistor driving circuit 1 .

[0099] The gates of MOS transistors Q1 and Q2 are connected to MOS transistor drive circuit 1 , the drain of MOS transistor Q1 is connected to the power circuit, the source of MOS transistor Q1 is connected to the source of MOS transistor Q2 , and the drain of MOS transistor Q2 is connected between MOS transistor Q7 and capacitor C1 .

[0100] The MOS tube driving circuit 1 is connected to the controller.

[0101] The primary coil of the transformer T1 is connected between the capacitor C1 and the capacitor C2 and between the source of the MOS transistor Q7 and the drain of the MOS transistor Q8.

[0102] The second switching circuit is connected between the primary coil of the transformer T1 , the capacitor C1 , and the capacitor C2 .

[0103] The second switch circuit includes an N-type MOS transistor Q5, an N-type MOS transistor Q6 and a MOS transistor driving circuit.

[0104] The gates of MOS transistors Q5 and Q6 are connected to the MOS transistor drive circuit. The drain of MOS transistor Q5 is connected between capacitors C1 and C2. The source of MOS transistor Q5 is connected to the source of MOS transistor Q6. The drain of MOS transistor Q6 is connected to the primary coil of transformer T1.

[0105] The third switching circuit is connected between the power supply circuit, the primary coil of the transformer, and the second switching circuit.

[0106] The third switch circuit includes an N-type MOS transistor Q3, an N-type MOS transistor Q4 and a MOS transistor driving circuit.

[0107] The gates of MOS transistors Q3 and Q4 are connected to the MOS transistor drive circuit, the drain of MOS transistor Q3 is connected to the power circuit, the source of MOS transistor Q3 is connected to the source of MOS transistor Q4, and the drain of MOS transistor Q4 is connected to the primary coil of transformer T1.

[0108] In some embodiments, the second switch circuit and the third switch circuit share a MOS transistor driving circuit 2 , and the MOS transistor driving circuit 2 is connected to the controller.

[0109] The gates of the MOS transistors Q5 , Q6 , Q3 , and Q4 are connected to the MOS transistor driving circuit 2 .

[0110] The rectifier bridge includes diodes D1, D2, D3, and D4. The anode of diode D1 and the cathode of diode D3, as well as the anode of diode D2 and the cathode of diode D4, are connected to the secondary winding of the transformer, respectively. A load to be tested C4 and a resistor R2 are connected in series between the cathode of diode D1 and the cathode of diode D2, and between the anode of diode D3 and the anode of diode D4. The load to be tested C4 is connected to the cathodes of diodes D1 and D2, while the resistor R2 is connected to the anodes of diodes D3 and D4.

[0111] The fourth switch circuit is connected between the anode of the diode D2 and the cathode of the diode D4.

[0112] The fourth switch circuit includes an N-type MOS transistor Q11 and a MOS transistor driving circuit 3. The gate of the MOS transistor Q11 is connected to the MOS transistor driving circuit 3, the drain of the MOS transistor Q11 is connected to the cathode of the diode D4, and the source of the MOS transistor Q11 is connected to the anode of the diode D2.

[0113] The MOS transistor driving circuit 3 is connected to the controller.

[0114] The voltage measurement circuit 2 is used to measure the voltage of the load C4 to be measured.

[0115] The current measurement circuit is used to measure the current flowing through the resistor R2.

[0116] The voltage measurement circuit 2 and the current measurement circuit are connected to the controller via an ADC chip.

[0117] The controller outputs control signals to the power supply circuit, the MOS tube driver chip, the first switch circuit, the second switch circuit, and the third switch circuit, and receives signals from the voltage measurement circuit and the current measurement circuit;

[0118] The controller is configured to control the first switch circuit to be disconnected, the second switch circuit to be disconnected, the third switch circuit to be turned on, and the fourth switch circuit to be disconnected; control the power supply circuit to output a first voltage, control the MOS transistor Q8 to be turned on and off according to a first duty cycle, receive the current I detected by the current measurement circuit and the voltage V detected by the voltage measurement circuit, and time t to calculate the capacitance of the load C4 to be measured.

[0119] The controller is configured according to the formula Calculate C, where C is the capacitance of the load C4 to be measured, and t is the time.

[0120] The voltage output by the power supply circuit is controlled according to the capacitance of the load C4 to be tested, and the on and off of the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit are controlled; and the working state of the bus output power modulation circuit is controlled until the voltage across the load C4 to be tested reaches the set voltage.

[0121] In order to adapt to loads of different sizes and quickly reach the set voltage without overshoot, the working state, switching frequency and duty cycle of MOS transistors Q7 and Q8 are different under different loads.

[0122] The controller is configured to control the MOS tube Q7 and the MOS tube Q8 to be disconnected after the voltage across the load C4 to be tested reaches a set voltage, so that the load C4 to be tested is in a self-discharge state. When the voltage of the load C4 to be tested measured by the voltage measurement circuit is higher than the second set voltage, the load C4 to be tested is qualified; otherwise, it is unqualified.

[0123] The second set voltage is lower than the set voltage. In some embodiments, the second set voltage is 85%-95% of the set voltage.

[0124] The controller configuration is:

[0125] When the capacitance of the load C4 to be tested is in the first capacitance range, the power supply circuit is controlled to output the first voltage, the first switch circuit is controlled to be disconnected, the second switch circuit is controlled to be disconnected, the third switch circuit is controlled to be connected, and the fourth switch circuit is controlled to be disconnected. The MOS transistor Q7 is always disconnected. The set voltage can be quickly reached by simply adjusting the duty cycle of the MOS transistor Q8. The MOS transistor Q8 is controlled to be turned on and off according to the first duty cycle until the voltage across the load C4 to be tested reaches the set voltage. The gate voltage waveforms of the MOS transistors Q7 and Q8 are shown in FIG. Figure 4 shown.

[0126] When the capacitance of the load C4 to be measured is in the second capacitance range, in order to quickly reach the set voltage, it is necessary to simultaneously adjust the switching frequencies of the MOS tubes Q7 and Q8: control the power supply circuit to output the first voltage, control the first switch circuit to be turned on, the second switch circuit to be turned on, the third switch circuit to be turned off, and the fourth switch circuit to be turned on; control the MOS tubes Q7 and Q8 to be turned on and off according to the second duty cycle, and adjust the output voltage of the power supply circuit according to the capacitance of the load C4 to be measured until the voltage across the load C4 to be measured reaches the first set voltage; control the first switch circuit to be turned off, the second switch circuit to be turned off, the third switch circuit to be turned on, and the fourth switch circuit to be turned off; disconnect the MOS tube Q7, and control the MOS tube Q8 to be turned on and off according to the first duty cycle until the voltage across the load C4 to be measured reaches the set voltage; adjust the duty cycle of the MOS tube Q8 to reduce the output power to achieve rapid and overshoot reaching the set voltage. Among them, the gate voltage waveforms of the MOS tubes Q7 and Q8 are shown as follows: Figure 5 shown.

[0127] When the capacitance of the load C4 to be measured is within the third capacitance range, the load is relatively large, and the switching frequencies of the MOS transistors Q7 and Q8 need to be adjusted simultaneously: the power supply circuit is controlled to output the first voltage, the first switching circuit is controlled to be turned on, the second switching circuit is controlled to be turned on, the third switching circuit is controlled to be turned off, and the fourth switching circuit is controlled to be turned on; the MOS transistors Q7 and Q8 are controlled to be turned on and off according to the second duty cycle, and the output voltage of the power supply circuit is adjusted according to the capacitance of the load C4 to be measured until the voltage across the load C4 to be measured reaches the set voltage. Since the load is relatively large and the voltage rises slowly, only the switching frequencies of the MOS transistors Q7 and Q8 need to be adjusted to achieve the set voltage without overshoot.

[0128] Among them, the gate voltage waveforms of MOS tube Q7 and MOS tube Q8 are as follows: Figure 6 shown.

[0129] The capacitance value of the first capacitance range is lower than that of the second capacitance range, and the capacitance value of the second capacitance range is lower than that of the third capacitance range.

[0130] The first set voltage is lower than the set voltage. In some embodiments, the first set voltage is 70%-90% of the set voltage.

[0131] The size of the load to be tested can be effectively identified, and the appropriate topology and boost speed can be selected according to the size of the load cell.

[0132] The system further includes: a digital-to-analog converter, a comparator A2 and a fifth switch circuit.

[0133] The digital-to-analog converter is connected to the controller, and the digital-to-analog converter is a DAC chip.

[0134] The comparator A2 has a non-inverting input terminal connected to the digital-to-analog converter, an inverting input terminal connected to the voltage measurement circuit, and an output terminal connected to the fifth switch circuit.

[0135] The fifth switch circuit is connected to the cathodes of the diode D1 and the diode D2 and the load to be measured C4.

[0136] The fifth switch circuit includes an N-type MOS transistor Q9 and a MOS transistor driving circuit 4. The gate of the MOS transistor Q9 is connected to the MOS transistor driving circuit 4. The source of the MOS transistor Q9 is connected to the load C4 to be tested. The drain of the MOS transistor Q9 is connected to the cathodes of the diodes D1 and D2.

[0137] The MOS transistor driving circuit 4 is connected to the output end of the comparator A2.

[0138] The controller is configured to receive the maximum rising voltage of each step set by the user, calculate the maximum value of the next voltage boost based on the current voltage detected by the voltage measurement circuit and the maximum rising voltage, and send it to the digital-to-analog converter; when the voltage at the non-inverting input terminal of the comparator A2 is lower than the voltage at the inverting input terminal, the output terminal of the comparator A2 controls the fifth switch circuit to be disconnected, and stops charging the load C4 to be tested until the controller calculates the maximum value of the next voltage boost.

[0139] The system also includes an anti-overshoot capacitor C3, one end of which is connected to the anodes of diodes D3 and D4, and the other end is connected to the cathodes of diodes D1 and D2 through diode D6. The anode of diode D6 is connected to the cathodes of diodes D1 and D2, and the cathode of diode D6 is connected to the anti-overshoot capacitor C3.

[0140] The system further includes: a first voltage measurement circuit, a comparator A1 and a sixth switch circuit.

[0141] The first voltage measurement circuit (voltage measurement circuit 1 in the figure) is connected between the overshoot prevention capacitor C3 and the cathode of the diode D6;

[0142] Comparator A1, having a non-inverting input terminal connected to the digital-to-analog converter, an inverting input terminal connected to the first voltage measurement circuit, and an output terminal connected to the sixth switch circuit;

[0143] The sixth switch circuit is connected to the resistor R1 and to the anodes of the diodes D3 and D4. The resistor R1 is connected between the diode D6 and the anti-overshoot capacitor C3.

[0144] The first switch circuit is a P-type MOS transistor Q10 , the gate of the MOS transistor Q10 is connected to the output end of the comparator A1 , the source of the MOS transistor Q10 is connected to the anodes of the diodes D3 and D4 , and the drain of the MOS transistor Q10 is connected to the resistor R1 .

[0145] When the voltage at the non-inverting input of comparator A1 is lower than the voltage at the inverting input, the output of comparator A1 controls the sixth switch circuit to turn on, and the energy of the anti-overshoot capacitor C3 is released through the resistor R1. When the voltage at the non-inverting input of comparator A1 is higher than the voltage at the inverting input, the output of comparator A1 controls the sixth switch circuit to turn off.

[0146] The comparator, DAC, and MOS tube drive circuit can effectively control the maximum rising voltage of the load to be measured within the cycle, thereby effectively reducing the overshoot voltage when the output undergoes transient changes.

[0147] The controller is configured to send data to the digital-to-analog converter after the test is completed, output a low-voltage analog quantity, and the output end of the comparator A1 controls the sixth switch circuit to conduct, releasing the power of the anti-overshoot capacitor C3 and the load to be tested C4.

[0148] The working process is:

[0149] The MCU control chip sends instructions through MOS tube drive circuit 1 to control the N-type MOS tube Q1 and N-type MOS tube Q2 to be disconnected. The MCU control chip sends instructions through MOS tube drive circuit 2 to control the N-type MOS tube Q3 and N-type MOS tube Q4 to be turned on. The MCU control chip sends instructions through MOS tube drive circuit 2 to control the N-type MOS tube Q5 and N-type MOS tube Q6 to be disconnected. The MCU control chip sends instructions through MOS tube drive circuit 3 to control the N-type MOS tube Q11 to be disconnected. The electrical structure at this time is as follows: Figure 2 Schematic diagram of a new flyback bus structure for a high-voltage output speed control system.

[0150] The MCU controls the buck-boost power supply circuit to output 24V. The MCU then sends instructions to the EG1160 MOSFET driver, turning on N-type MOSFET Q8 for 5µs and then off for 245µs. Due to the flyback switch's structural characteristics, the voltage across load C4 increases, and current flows through current-sensing resistor R2.

[0151] The voltage measurement circuit 2 transmits the real-time voltage V of the load C4 to be measured to the ADC chip. The current measurement circuit measures the current I across the current measuring resistor R2 and transmits it to the ADC chip in real time. The ADC chip sends the current I and voltage V to the MCU control chip, which calculates the load capacitance value according to the following formula:

[0152]

[0153] Wherein, C is the capacitance of the load C4 to be measured, and t represents time.

[0154] The MCU control chip calculates the capacitance of the load C4 to be tested and adjusts the structure and combination of the bus voltage according to the peak voltage set by the user.

[0155] 1. The capacitance of the load C4 to be tested is between 0.01 uf and 0.5 uf.

[0156] The MCU control chip sends instructions to control the output voltage of the BUCK-BOOST power supply circuit to 24V. The MCU control chip sends instructions through MOS tube drive circuit 1 to control the disconnection of N-type MOS tube Q1 and N-type MOS tube Q2. The MCU control chip sends instructions through MOS tube drive circuit 2 to control the conduction of N-type MOS tube Q3 and N-type MOS tube Q4. The MCU control chip sends instructions through MOS tube drive circuit 2 to control the disconnection of N-type MOS tube Q5 and N-type MOS tube Q6. The MCU control chip sends instructions through MOS tube drive circuit 3 to control the disconnection of N-type MOS tube Q11. At this time, the electrical structure is in a flyback bus structure, and its equivalent electrical structure diagram is shown as follows. Figure 2 As shown. The MCU control chip controls the EG1160MOS driver chip by sending instructions to output the duty cycle of the PWM signal that drives the N-type MOS tube Q8 to adapt to different loads. Figure 4 shown.

[0157] 2. The capacitance of the load C4 to be tested is between 0.5uf and 20uf.

[0158] The MCU control chip sends instructions through MOS tube drive circuit 1 to control the conduction of N-type MOS tube Q1 and N-type MOS tube Q2. The MCU control chip sends instructions through MOS tube drive circuit 2 to control the disconnection of N-type MOS tube Q3 and N-type MOS tube Q4. The MCU control chip sends instructions through MOS tube drive circuit 2 to control the conduction of N-type MOS tube Q5 and N-type MOS tube Q6. The MCU control chip sends instructions through MOS tube drive circuit 3 to control the conduction of N-type MOS tube Q11. The electrical structure at this time is in a half-bridge busbar structure, and its equivalent electrical structure diagram is shown as follows. Figure 3 As shown in the figure. The MCU control chip controls the EG1160MOS driver chip by sending instructions to output and drive the N-type MOS transistors Q7 and Q8. The alternating conduction mode converts the 24V DC voltage into AC. After voltage doubling by the transformer, the DC high voltage is output through the H-bridge structure composed of rectifier diodes D1, D2, D3, and D4. The time when the N-type MOS transistors Q7 and Q8 are alternately turned on is a fixed ratio to the time when the N-type MOS transistors Q7 and Q8 are completely turned off. Figure 6As shown. The MCU control chip sends instructions to control the output voltage of the BUCK-BOOST power supply circuit to change from 24V to 48V to adapt to different loads. When the output voltage reaches 80% of the set voltage, the MCU control chip sends instructions to control MOS tube drive circuit 1, MOS tube drive circuit 2, and MOS tube drive circuit 3 to control each N-type MOS to adjust the busbar structure to Figure 2 The voltage waveforms of the gates of N-type MOS tubes Q7 and Q8 are as follows: Figure 5 As shown, overshoot can be effectively prevented.

[0159] 3. The capacitance of the load capacitor is greater than 20uf.

[0160] The MCU control chip sends instructions to control the output voltage of the BUCK-BOOST power supply circuit to 24V. The MCU control chip sends instructions through MOS tube drive circuit 1 to control the conduction of N-type MOS tubes Q1 and N-type MOS tubes Q2. The MCU control chip sends instructions through MOS tube drive circuit 2 to control the disconnection of N-type MOS tubes Q3 and N-type MOS tubes Q4. The MCU control chip sends instructions through MOS tube drive circuit 2 to control the conduction of N-type MOS tubes Q5 and N-type MOS tubes Q6. The MCU control chip sends instructions through MOS tube drive circuit 3 to control the conduction of N-type MOS tube Q11. The electrical structure at this time is a half-bridge bus structure. Its equivalent electrical structure diagram is shown as follows. Figure 3 As shown. The MCU control chip controls the EG1160MOS driver chip by sending instructions to output and drive the N-type MOS tube Q7 and N-type MOS tube Q8. By alternating conduction, the 24V DC voltage is converted into AC. After voltage doubling by the transformer, the DC high voltage is output through the H-bridge structure composed of rectifier diodes D1, D2, D3, and D4. By adjusting the ratio of the time when the N-type MOS tubes Q7 and Q8 are alternately turned on to the time when the N-type MOS tubes Q7 and Q8 are completely turned off, the voltage waveforms of the N-type MOS tubes Q7 and Q8 with different load gates are adapted as shown below. Figure 6 shown.

[0161] The user can set the maximum voltage rise for each step. The MCU control chip monitors the output voltage in real time through voltage measurement circuit 2. The MCU-controlled chip calculates the maximum value for the next voltage rise based on the current voltage and the maximum voltage rise for each step. The MCU sends this calculated value to the DAC chip, which converts it into an analog value and transmits it to the non-inverting input of comparator A2. When voltage measurement circuit 2 transmits the output voltage value to the inverting input of comparator A2, and the voltage value at the non-inverting input of comparator A2 is lower than the voltage value at its inverting input, comparator A2 outputs a signal to MOS transistor drive circuit 3, shutting off N-type MOS transistor Q9 and stopping charging C4 until the next time the MCU control chip sends a new upper limit value, at which point N-type MOS transistor Q9 turns on again.

[0162] After the N-type MOS transistor Q9 is turned off, all the electric energy output by the transformer will flow into the anti-overshoot capacitor C3. If the voltage across the anti-overshoot capacitor C3 is higher than the voltage across C4, the anti-overshoot function will be lost. To prevent the voltage across the anti-overshoot capacitor C3 from increasing, it needs to be discharged. The MCU control chip can monitor the voltage value across the anti-overshoot capacitor C3 in real time through the voltage measurement circuit 1. The chip controlled by the MCU calculates the maximum value of the next voltage boost based on the current voltage value and the maximum rising voltage of each step. The MCU sends the calculated value to the DAC chip, which converts it into an analog value and transmits it to the non-inverting input terminal of the comparator A1. When the voltage measurement circuit 1 transmits the voltage value of the output terminal to the inverting input terminal of the comparator A1, and when the voltage value of the non-inverting input terminal of the comparator A1 is lower than the voltage value of its inverting input terminal, the comparator A1 controls the N-type MOS transistor Q10 to turn on. The electric energy in the anti-overshoot capacitor C3 is released through the resistor R1 until the voltage value at the non-inverting input terminal of the comparator A1 is higher than the voltage value at the inverting input terminal thereof, and the comparator A1 controls the MOS tube Q10 to be turned off.

[0163] When the voltage across C4 reaches the set voltage, the MCU control chip sends a command to the EG1160MOS driver chip to control the N-type MOS tube Q7. The N-type MOS tube Q8 is disconnected and stops outputting. C4 is in the self-discharge stage. The voltage measurement circuit 2 measures the voltage drop value of the C4 voltage in the self-discharge stage. If the drop value is lower than 10% of the set voltage, the load to be tested meets the requirements. Otherwise, it does not meet the requirements. After the test is completed, the MCU control chip sends data to the DAC chip. The DAC chip outputs a low-voltage analog signal to control the comparator A1 to drive the MOS tube Q10 to open, releasing all the energy in C3 and C4.

[0164] The load to be tested is a battery cell, for example, a lithium battery cell.

[0165] like Figure 7The following diagram shows test waveforms for three different loads, with the first load < the second load < the third load. As can be seen, the time differences between the three loads in reaching the set voltage of 200V are very small. The first load is light, resulting in a fast voltage rise but no overshoot. The third load is heavy, but the time difference in reaching the set voltage is very small compared to the first load. All three loads never exceed the set voltage during the voltage rise process.

[0166] This embodiment also proposes a multi-stage boost speed control system, including a power supply circuit, a bus output power modulation circuit, a transformer, a rectifier bridge, first to fourth switch circuits, a voltage measurement circuit, a current measurement circuit, and a controller. Each component is described in detail below:

[0167] The power supply circuit, in some embodiments, is a BUCK-BOOST power supply circuit with an output voltage range of 3V to 48V.

[0168] The bus output power modulation circuit includes a MOS transistor driver chip, a MOS transistor Q7, a MOS transistor Q8, a capacitor C1, and a capacitor C2.

[0169] In some embodiments, the MOS transistor driver chip is an EG1160MOS driver chip. The EG1160MOS driver chip is directly controlled by an MCU and can realize single MOS transistor control. The MOS transistor's on-time and duty cycle can be adjusted by the MCU control chip through a program, providing flexible control.

[0170] MOS transistors Q7 and MOS transistors Q8 are N-type MOS transistors. The gates of MOS transistors Q7 and MOS transistors Q8 are connected to a MOS transistor driver chip. The source of MOS transistor Q7 is connected to the drain of MOS transistor Q8. Capacitors C1 and C2 are connected in series between the drain of MOS transistor Q7 and the source of MOS transistor Q8. Capacitor C1 is connected to the drain of MOS transistor Q7, and capacitor C2 is connected to the source of MOS transistor Q8.

[0171] N-type MOS transistor Q7 and N-type MOS transistor Q8 operate at a cycle of 4 kHz, and their duty cycle is adjustable from 1% to 40%.

[0172] The first switch circuit is connected between the power circuit, the drain of the MOS transistor Q7 and the capacitor C1.

[0173] In some embodiments, the first switch circuit includes an N-type MOS transistor Q1 , an N-type MOS transistor Q2 , and a MOS transistor driving circuit 1 .

[0174] The gates of MOS transistors Q1 and Q2 are connected to MOS transistor drive circuit 1 , the drain of MOS transistor Q1 is connected to the power circuit, the source of MOS transistor Q1 is connected to the source of MOS transistor Q2 , and the drain of MOS transistor Q2 is connected between MOS transistor Q7 and capacitor C1 .

[0175] The MOS tube driving circuit 1 is connected to the controller.

[0176] The primary coil of the transformer T1 is connected between the capacitor C1 and the capacitor C2 and between the source of the MOS transistor Q7 and the drain of the MOS transistor Q8.

[0177] The second switching circuit is connected between the primary coil of the transformer T1 , the capacitor C1 , and the capacitor C2 .

[0178] The second switch circuit includes an N-type MOS transistor Q5, an N-type MOS transistor Q6 and a MOS transistor driving circuit.

[0179] The gates of MOS transistors Q5 and Q6 are connected to the MOS transistor drive circuit. The drain of MOS transistor Q5 is connected between capacitors C1 and C2. The source of MOS transistor Q5 is connected to the source of MOS transistor Q6. The drain of MOS transistor Q6 is connected to the primary coil of transformer T1.

[0180] The third switching circuit is connected between the power supply circuit, the primary coil of the transformer, and the second switching circuit.

[0181] The third switch circuit includes an N-type MOS transistor Q3, an N-type MOS transistor Q4 and a MOS transistor driving circuit.

[0182] The gates of MOS transistors Q3 and Q4 are connected to the MOS transistor drive circuit, the drain of MOS transistor Q3 is connected to the power circuit, the source of MOS transistor Q3 is connected to the source of MOS transistor Q4, and the drain of MOS transistor Q4 is connected to the primary coil of transformer T1.

[0183] In some embodiments, the second switch circuit and the third switch circuit share a MOS transistor driving circuit 2 , and the MOS transistor driving circuit 2 is connected to the controller.

[0184] The gates of the MOS transistors Q5 , Q6 , Q3 , and Q4 are connected to the MOS transistor driving circuit 2 .

[0185] The rectifier bridge includes diodes D1, D2, D3, and D4. The anode of diode D1 and the cathode of diode D3, as well as the anode of diode D2 and the cathode of diode D4, are connected to the secondary winding of the transformer, respectively. A load to be tested C4 and a resistor R2 are connected in series between the cathode of diode D1 and the cathode of diode D2, and between the anode of diode D3 and the anode of diode D4. The load to be tested C4 is connected to the cathodes of diodes D1 and D2, while the resistor R2 is connected to the anodes of diodes D3 and D4.

[0186] The fourth switch circuit is connected between the anode of the diode D2 and the cathode of the diode D4.

[0187] The fourth switch circuit includes an N-type MOS transistor Q11 and a MOS transistor driving circuit 3. The gate of the MOS transistor Q11 is connected to the MOS transistor driving circuit 3, the drain of the MOS transistor Q11 is connected to the cathode of the diode D4, and the source of the MOS transistor Q11 is connected to the anode of the diode D2.

[0188] The MOS transistor driving circuit 3 is connected to the controller.

[0189] The voltage measurement circuit 2 is used to measure the voltage of the load C4 to be measured.

[0190] The current measurement circuit is used to measure the current flowing through the resistor R2.

[0191] The voltage measurement circuit 2 and the current measurement circuit are connected to the controller via an ADC chip.

[0192] The controller outputs control signals to the power supply circuit, the MOS tube driver chip, the first switch circuit, the second switch circuit, and the third switch circuit, and receives signals from the voltage measurement circuit and the current measurement circuit;

[0193] The controller is configured to control the first switch circuit to be disconnected, the second switch circuit to be disconnected, the third switch circuit to be turned on, and the fourth switch circuit to be disconnected; control the power supply circuit to output a first voltage, control the MOS transistor Q8 to be turned on and off according to a first duty cycle, receive the current I detected by the current measurement circuit and the voltage V detected by the voltage measurement circuit, and time t to calculate the capacitance of the load C4 to be measured.

[0194] The controller is configured according to the formula Calculate C, where C is the capacitance of the load C4 to be measured, and t is the time.

[0195] The voltage output by the power supply circuit is controlled according to the capacitance of the load C4 to be tested, and the on and off of the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit are controlled; and the working state of the bus output power modulation circuit is controlled until the voltage across the load C4 to be tested reaches the set voltage.

[0196] In order to adapt to loads of different sizes and quickly reach the set voltage without overshoot, the working state, switching frequency and duty cycle of MOS transistors Q7 and Q8 are different under different loads.

[0197] The controller configuration is:

[0198] When the capacitance of the load C4 to be tested is in the first capacitance range, the power supply circuit is controlled to output the first voltage, the first switch circuit is controlled to be disconnected, the second switch circuit is controlled to be disconnected, the third switch circuit is controlled to be connected, and the fourth switch circuit is controlled to be disconnected. The MOS transistor Q7 is always disconnected. The set voltage can be quickly reached by simply adjusting the duty cycle of the MOS transistor Q8. The MOS transistor Q8 is controlled to be turned on and off according to the first duty cycle until the voltage across the load C4 to be tested reaches the set voltage. The gate voltage waveforms of the MOS transistors Q7 and Q8 are shown in FIG. Figure 4 shown.

[0199] When the capacitance of the load C4 to be measured is in the second capacitance range, in order to quickly reach the set voltage, it is necessary to simultaneously adjust the switching frequencies of the MOS tubes Q7 and Q8: control the power supply circuit to output the first voltage, control the first switch circuit to be turned on, the second switch circuit to be turned on, the third switch circuit to be turned off, and the fourth switch circuit to be turned on; control the MOS tubes Q7 and Q8 to be turned on and off according to the second duty cycle, and adjust the output voltage of the power supply circuit according to the capacitance of the load C4 to be measured until the voltage across the load C4 to be measured reaches the first set voltage; control the first switch circuit to be turned off, the second switch circuit to be turned off, the third switch circuit to be turned on, and the fourth switch circuit to be turned off; disconnect the MOS tube Q7, and control the MOS tube Q8 to be turned on and off according to the first duty cycle until the voltage across the load C4 to be measured reaches the set voltage; adjust the duty cycle of the MOS tube Q8 to reduce the output power to achieve rapid and overshoot reaching the set voltage. Among them, the gate voltage waveforms of the MOS tubes Q7 and Q8 are shown as follows: Figure 5 shown.

[0200] When the capacitance of the load C4 to be measured is within the third capacitance range, the load is relatively large, and the switching frequencies of the MOS transistors Q7 and Q8 need to be adjusted simultaneously: the power supply circuit is controlled to output the first voltage, the first switching circuit is controlled to be turned on, the second switching circuit is controlled to be turned on, the third switching circuit is controlled to be turned off, and the fourth switching circuit is controlled to be turned on; the MOS transistors Q7 and Q8 are controlled to be turned on and off according to the second duty cycle, and the output voltage of the power supply circuit is adjusted according to the capacitance of the load C4 to be measured until the voltage across the load C4 to be measured reaches the set voltage. Since the load is relatively large and the voltage rises slowly, only the switching frequencies of the MOS transistors Q7 and Q8 need to be adjusted to achieve the set voltage without overshoot.

[0201] Among them, the gate voltage waveforms of MOS tube Q7 and MOS tube Q8 are as follows: Figure 6 shown.

[0202] The capacitance value of the first capacitance range is lower than that of the second capacitance range, and the capacitance value of the second capacitance range is lower than that of the third capacitance range.

[0203] The first set voltage is 70%-90% of the set voltage.

[0204] The size of the load to be tested can be effectively identified, and the appropriate topology and boost speed can be selected according to the size of the load cell.

[0205] The system further includes: a digital-to-analog converter, a comparator A2 and a fifth switch circuit.

[0206] The digital-to-analog converter is connected to the controller, and the digital-to-analog converter is a DAC chip.

[0207] The comparator A2 has a non-inverting input terminal connected to the digital-to-analog converter, an inverting input terminal connected to the voltage measurement circuit, and an output terminal connected to the fifth switch circuit.

[0208] The fifth switch circuit is connected to the cathodes of the diode D1 and the diode D2 and the load to be measured C4.

[0209] The fifth switch circuit includes an N-type MOS transistor Q9 and a MOS transistor driving circuit 4. The gate of the MOS transistor Q9 is connected to the MOS transistor driving circuit 4. The source of the MOS transistor Q9 is connected to the load C4 to be tested. The drain of the MOS transistor Q9 is connected to the cathodes of the diodes D1 and D2.

[0210] The MOS transistor driving circuit 4 is connected to the output end of the comparator A2.

[0211] The controller is configured to receive the maximum rising voltage of each step set by the user, calculate the maximum value of the next voltage boost based on the current voltage detected by the voltage measurement circuit and the maximum rising voltage, and send it to the digital-to-analog converter; when the voltage at the non-inverting input terminal of the comparator A2 is lower than the voltage at the inverting input terminal, the output terminal of the comparator A2 controls the fifth switch circuit to be disconnected, and stops charging the load C4 to be tested until the controller calculates the maximum value of the next voltage boost.

[0212] The system also includes an anti-overshoot capacitor C3, one end of which is connected to the anodes of diodes D3 and D4, and the other end is connected to the cathodes of diodes D1 and D2 through diode D6. The anode of diode D6 is connected to the cathodes of diodes D1 and D2, and the cathode of diode D6 is connected to the anti-overshoot capacitor C3.

[0213] The system further includes: a first voltage measurement circuit, a comparator A1 and a sixth switch circuit.

[0214] The first voltage measurement circuit (voltage measurement circuit 1 in the figure) is connected between the overshoot prevention capacitor C3 and the cathode of the diode D6;

[0215] Comparator A1, having a non-inverting input terminal connected to the digital-to-analog converter, an inverting input terminal connected to the first voltage measurement circuit, and an output terminal connected to the sixth switch circuit;

[0216] The sixth switch circuit is connected to the resistor R1 and to the anodes of the diodes D3 and D4. The resistor R1 is connected between the diode D6 and the anti-overshoot capacitor C3.

[0217] The first switch circuit is a P-type MOS transistor Q10 , the gate of the MOS transistor Q10 is connected to the output end of the comparator A1 , the source of the MOS transistor Q10 is connected to the anodes of the diodes D3 and D4 , and the drain of the MOS transistor Q10 is connected to the resistor R1 .

[0218] When the voltage at the non-inverting input of comparator A1 is lower than the voltage at the inverting input, the output of comparator A1 controls the sixth switch circuit to turn on, and the energy of the anti-overshoot capacitor C3 is released through the resistor R1. When the voltage at the non-inverting input of comparator A1 is higher than the voltage at the inverting input, the output of comparator A1 controls the sixth switch circuit to turn off.

[0219] The comparator, DAC, and MOS tube drive circuit can effectively control the maximum rising voltage of the load to be measured within the cycle, thereby effectively reducing the overshoot voltage when the output undergoes transient changes.

[0220] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for a person skilled in the art to modify the technical solutions described in the aforementioned embodiments, or to replace some of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions claimed to be protected by the present invention.

Claims

1. A battery cell testing system, characterized in that: The battery cell testing system includes: Power supply circuit; A bus output power modulation circuit includes a MOS transistor driver chip, a MOS transistor Q7, a MOS transistor Q8, a capacitor C1, and a capacitor C2; the gates of the MOS transistors Q7 and Q8 are connected to the MOS transistor driver chip, the source of the MOS transistor Q7 is connected to the drain of the MOS transistor Q8, and the capacitors C1 and C2 connected in series are connected between the drain of the MOS transistor Q7 and the source of the MOS transistor Q8; A transformer, wherein the primary coil of the transformer is connected between the capacitor C1 and the capacitor C2, and between the source of the MOS transistor Q7 and the drain of the MOS transistor Q8; A rectifier bridge includes a diode D1, a diode D2, a diode D3, and a diode D4, wherein the anode of the diode D1 and the cathode of the diode D3, and the anode of the diode D2 and the cathode of the diode D4 are respectively connected to the secondary coil of the transformer; the cathode of the diode D1 and the cathode of the diode D2, and the anode of the diode D3 and the anode of the diode D4 are connected in series via a load to be measured C4 and a resistor R2; A first switch circuit is connected between the power circuit, the drain of the MOS transistor Q7 and the capacitor C1; a second switch circuit connected between the primary coil of the transformer, the capacitor C1 and the capacitor C2; a third switch circuit connected between the power supply circuit, the primary coil of the transformer, and the second switch circuit; a fourth switch circuit connected between the anode of the diode D2 and the cathode of the diode D4; A voltage measuring circuit, used for measuring the voltage of the load C4 to be measured; a current measuring circuit, configured to measure the current flowing through the resistor R2; A controller outputs control signals to the power supply circuit, the MOS transistor driver chip, the first switch circuit, the second switch circuit, and the third switch circuit, and receives signals from the voltage measurement circuit and the current measurement circuit; Controlling the first switch circuit to be disconnected, the second switch circuit to be disconnected, the third switch circuit to be turned on, and the fourth switch circuit to be disconnected; controlling the power supply circuit to output a first voltage, controlling the MOS transistor Q8 to be turned on and off according to a first duty cycle, receiving the current I detected by the current measurement circuit and the voltage V detected by the voltage measurement circuit, and timing t to calculate the capacitance of the load C4 to be measured; Controlling the voltage output by the power supply circuit according to the capacitance of the load C4 to be tested, controlling the on and off of the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit; and controlling the working state of the bus output power modulation circuit until the voltage across the load C4 to be tested reaches a set voltage; After the voltage across the load C4 to be tested reaches a set voltage, the MOS transistor Q7 and the MOS transistor Q8 are controlled to be disconnected, and the load C4 to be tested is in a self-discharge state. When the voltage of the load C4 to be tested measured by the voltage measurement circuit is higher than a second set voltage, the load C4 to be tested is judged to be qualified; otherwise, it is unqualified; The second set voltage is lower than the set voltage.

2. The battery cell testing system according to claim 1, characterized in that: The controller is configured as follows: When the capacitance of the load C4 to be tested is in the first capacitance range, the power supply circuit is controlled to output a first voltage, the first switch circuit is controlled to be disconnected, the second switch circuit is controlled to be disconnected, the third switch circuit is controlled to be connected, and the fourth switch circuit is controlled to be disconnected; and the MOS transistor Q8 is controlled to be turned on and off according to a first duty cycle until the voltage across the load C4 to be tested reaches a set voltage; When the capacitance of the load C4 to be measured is in the second capacitance range, the power supply circuit is controlled to output a first voltage, the first switch circuit is controlled to be turned on, the second switch circuit is controlled to be turned on, the third switch circuit is controlled to be turned off, and the fourth switch circuit is controlled to be turned on; the MOS transistor Q7 and the MOS transistor Q8 are controlled to be turned on and off according to a second duty cycle, and the output voltage of the power supply circuit is adjusted according to the capacitance of the load C4 to be measured until the voltage across the load C4 to be measured reaches a first set voltage; the first switch circuit is controlled to be turned off, the second switch circuit is controlled to be turned off, the third switch circuit is controlled to be turned on, and the fourth switch circuit is controlled to be turned off; and the MOS transistor Q8 is controlled to be turned on and off according to the first duty cycle until the voltage across the load C4 to be measured reaches the set voltage; When the capacitance of the load C4 to be measured is within a third capacitance range, the power supply circuit is controlled to output a first voltage, the first switch circuit is controlled to be turned on, the second switch circuit is controlled to be turned on, the third switch circuit is controlled to be turned off, and the fourth switch circuit is controlled to be turned on; the MOS transistor Q7 and the MOS transistor Q8 are controlled to be turned on and off according to a second duty cycle, and the output voltage of the power supply circuit is adjusted according to the capacitance of the load C4 to be measured until the voltage across the load C4 to be measured reaches a set voltage; The capacitance value of the first capacitance range is lower than that of the second capacitance range, and the capacitance value of the second capacitance range is lower than that of the third capacitance range; Wherein, the first set voltage is lower than the set voltage.

3. The battery cell testing system according to claim 1, characterized in that: The controller is configured according to the formula Calculate C, where C is the capacitance of the load C4 to be measured, and t represents time.

4. The battery cell testing system according to any one of claims 1 to 3, characterized in that: The test system comprises: a digital-to-analog converter, connected to the controller; A comparator A2, having a non-inverting input connected to the digital-to-analog converter, an inverting input connected to the voltage measurement circuit, and an output connected to the fifth switch circuit; a fifth switch circuit connected to the cathodes of the diode D1 and the diode D2 and the load C4 to be measured; an anti-overshoot capacitor C3, one end of which is connected to the anodes of the diodes D3 and D4, and the other end of which is connected to the cathodes of the diodes D1 and D2 via a diode D6, wherein the anode of the diode D6 is connected to the cathodes of the diodes D1 and D2, and the cathode of the diode D6 is connected to the anti-overshoot capacitor C3; The controller is configured to receive the set maximum rising voltage of each step, calculate the maximum value of the next voltage boost based on the current voltage detected by the voltage measurement circuit and the maximum rising voltage, and send it to the digital-to-analog converter; when the voltage at the non-inverting input terminal of the comparator A2 is lower than the voltage at the inverting input terminal, the output terminal of the comparator A2 controls the fifth switch circuit to be disconnected, and stops charging the load C4 to be tested until the controller calculates the maximum value of the next voltage boost.

5. The battery cell testing system according to claim 4, characterized in that: The system comprises: a first voltage measurement circuit connected between the anti-overshoot capacitor C3 and the cathode of the diode D6; A comparator A1, having a non-inverting input connected to the digital-to-analog converter, an inverting input connected to the first voltage measurement circuit, and an output connected to the sixth switch circuit; a sixth switch circuit connected to the resistor R1 and to the anodes of the diodes D3 and D4; the resistor R1 is connected between the diode D6 and the anti-overshoot capacitor C3; When the voltage at the non-inverting input terminal of the comparator A1 is lower than the voltage at the inverting input terminal, the output terminal of the comparator A1 controls the sixth switch circuit to be turned on, and the electric energy of the anti-overshoot capacitor C3 is released through the resistor R1. When the voltage at the non-inverting input terminal of the comparator A1 is higher than the voltage at the inverting input terminal, the output terminal of the comparator A1 controls the sixth switch circuit to be turned off.

6. The battery cell testing system according to claim 5, characterized in that: The controller is configured to send data to the digital-to-analog converter after the test is completed, output a low-voltage analog quantity, and the output end of the comparator A1 controls the sixth switch circuit to turn on, releasing the power of the anti-overshoot capacitor C3 and the load to be tested C4.

7. A multi-stage boost speed control system, characterized in that: The system comprises: Power supply circuit; A bus output power modulation circuit includes a MOS transistor driver chip, a MOS transistor Q7, a MOS transistor Q8, a capacitor C1, and a capacitor C2; the gates of the MOS transistors Q7 and Q8 are connected to the MOS transistor driver chip, the source of the MOS transistor Q7 is connected to the drain of the MOS transistor Q8, and the capacitors C1 and C2 connected in series are connected between the drain of the MOS transistor Q7 and the source of the MOS transistor Q8; A transformer, wherein the primary coil of the transformer is connected between the capacitor C1 and the capacitor C2, and between the source of the MOS transistor Q7 and the drain of the MOS transistor Q8; A rectifier bridge includes a diode D1, a diode D2, a diode D3, and a diode D4, wherein the anode of the diode D1 and the cathode of the diode D3, and the anode of the diode D2 and the cathode of the diode D4 are respectively connected to the secondary coil of the transformer; the cathode of the diode D1 and the cathode of the diode D2, and the anode of the diode D3 and the anode of the diode D4 are connected in series via a load to be measured C4 and a resistor R2; A first switch circuit is connected between the power circuit, the drain of the MOS transistor Q7 and the capacitor C1; a second switch circuit connected between the primary coil of the transformer, the capacitor C1 and the capacitor C2; a third switch circuit connected between the power supply circuit, the primary coil of the transformer, and the second switch circuit; a fourth switch circuit connected between the anode of the diode D2 and the cathode of the diode D4; A voltage measuring circuit, used for measuring the voltage of the load C4 to be measured; a current measuring circuit, configured to measure the current flowing through the resistor R2; A controller outputs control signals to the power supply circuit, the MOS transistor driver chip, the first switch circuit, the second switch circuit, and the third switch circuit, and receives signals from the voltage measurement circuit and the current measurement circuit; The controller is configured to control the first switch circuit to be disconnected, the second switch circuit to be disconnected, the third switch circuit to be turned on, and the fourth switch circuit to be disconnected; control the power supply circuit to output a first voltage, control the MOS transistor Q8 to be turned on and off according to a first duty cycle, receive the current I detected by the current measurement circuit and the voltage V detected by the voltage measurement circuit, and time t to calculate the capacitance of the load C4 to be measured; The voltage output by the power supply circuit is controlled according to the capacitance of the load C4 to be tested, and the on and off of the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit are controlled; and the working state of the bus output power modulation circuit is controlled until the voltage across the load C4 to be tested reaches the set voltage.

8. The multi-stage boost speed control system according to claim 7, characterized in that: The controller is configured as follows: When the capacitance of the load C4 to be tested is in the first capacitance range, the power supply circuit is controlled to output a first voltage, the first switch circuit is controlled to be disconnected, the second switch circuit is controlled to be disconnected, the third switch circuit is controlled to be connected, and the fourth switch circuit is controlled to be disconnected; and the MOS transistor Q8 is controlled to be turned on and off according to a first duty cycle until the voltage across the load C4 to be tested reaches a set voltage; When the capacitance of the load C4 to be measured is in the second capacitance range, the power supply circuit is controlled to output a first voltage, the first switch circuit is controlled to be turned on, the second switch circuit is controlled to be turned on, the third switch circuit is controlled to be turned off, and the fourth switch circuit is controlled to be turned on; the MOS transistor Q7 and the MOS transistor Q8 are controlled to be turned on and off according to a second duty cycle, and the output voltage of the power supply circuit is adjusted according to the capacitance of the load C4 to be measured until the voltage across the load C4 to be measured reaches a first set voltage; the first switch circuit is controlled to be turned off, the second switch circuit is controlled to be turned off, the third switch circuit is controlled to be turned on, and the fourth switch circuit is controlled to be turned off; and the MOS transistor Q8 is controlled to be turned on and off according to the first duty cycle until the voltage across the load C4 to be measured reaches the set voltage; When the capacitance of the load C4 to be measured is within a third capacitance range, the power supply circuit is controlled to output a first voltage, the first switch circuit is controlled to be turned on, the second switch circuit is controlled to be turned on, the third switch circuit is controlled to be turned off, and the fourth switch circuit is controlled to be turned on; the MOS transistor Q7 and the MOS transistor Q8 are controlled to be turned on and off according to a second duty cycle, and the output voltage of the power supply circuit is adjusted according to the capacitance of the load C4 to be measured until the voltage across the load C4 to be measured reaches a set voltage; The capacitance value of the first capacitance range is lower than that of the second capacitance range, and the capacitance value of the second capacitance range is lower than that of the third capacitance range; and the first set voltage is lower than the set voltage.

9. The multi-stage boost speed control system according to any one of claims 7-8, characterized in that: The system comprises: a digital-to-analog converter, connected to the controller; A comparator A2, having a non-inverting input connected to the digital-to-analog converter, an inverting input connected to the voltage measurement circuit, and an output connected to the fifth switch circuit; a fifth switch circuit connected to the cathodes of the diode D1 and the diode D2 and the load C4 to be measured; an anti-overshoot capacitor C3, one end of which is connected to the anodes of the diodes D3 and D4, and the other end of which is connected to the cathodes of the diodes D1 and D2 via a diode D6, wherein the anode of the diode D6 is connected to the cathodes of the diodes D1 and D2, and the cathode of the diode D6 is connected to the anti-overshoot capacitor C3; The controller is configured to receive the set maximum rising voltage of each step, calculate the maximum value of the next voltage boost based on the current voltage detected by the voltage measurement circuit and the maximum rising voltage, and send it to the digital-to-analog converter; when the voltage at the non-inverting input terminal of the comparator A2 is lower than the voltage at the inverting input terminal, the output terminal of the comparator A2 controls the fifth switch circuit to be disconnected, and stops charging the load C4 to be tested until the controller calculates the maximum value of the next voltage boost.

10. The multi-stage boost speed control system according to claim 9, characterized in that: The system comprises: a first voltage measurement circuit connected between the anti-overshoot capacitor C3 and the cathode of the diode D6; A comparator A1, having a non-inverting input connected to the digital-to-analog converter, an inverting input connected to the first voltage measurement circuit, and an output connected to the sixth switch circuit; a sixth switch circuit connected to the resistor R1 and to the anodes of the diodes D3 and D4; the resistor R1 is connected between the diode D6 and the anti-overshoot capacitor C3; When the voltage at the non-inverting input terminal of the comparator A1 is lower than the voltage at the inverting input terminal, the output terminal of the comparator A1 controls the sixth switch circuit to be turned on, and the electric energy of the anti-overshoot capacitor C3 is released through the resistor R1. When the voltage at the non-inverting input terminal of the comparator A1 is higher than the voltage at the inverting input terminal, the output terminal of the comparator A1 controls the sixth switch circuit to be turned off.

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