Photomask design method, semiconductor process and semiconductor structure

Abstract

The invention discloses a photomask design method, a semiconductor process and a semiconductor structure. The photomask design method includes the following steps. A plurality of photomask layout designs are provided, where the plurality of photomask layout designs have a plurality of overall aperture ratios, and each photomask layout design includes a first device region and a first dummy region. The aperture ratio of the first dummy region of the at least one photomask layout design is adjusted to reduce the overall aperture ratio difference between the plurality of photomask layout designs. The photomask design method can prevent the size of the member from deviating.

Description

Technical Field

[0001] The present invention relates to a photomask design method, a semiconductor process, and a semiconductor structure, and more particularly to a photomask design method, a semiconductor process, and a semiconductor structure that can prevent the dimensions of components from deviating. Background Art

[0002] In semiconductor processes, multiple photomasks will have multiple overall aperture ratios. When the difference in the overall aperture ratios between multiple photomasks is too large, it will cause the pattern dimensions of multiple pattern photoresist layers formed by the multiple photomasks to deviate. Therefore, when performing subsequent processes using the multiple above-mentioned pattern photoresist layers, it will cause the dimensions of the components formed by the subsequent processes to deviate. Summary of the Invention

[0003] The present invention provides a photomask design method, a semiconductor process, and a semiconductor structure that can prevent the dimensions of components from deviating.

[0004] The present invention proposes a photomask design method, including the following steps. Provide multiple photomask layout designs, where the multiple photomask layout designs have multiple overall aperture ratios, and each photomask layout design includes a first device region and a first dummy region. Adjust the aperture ratio of the first dummy region of at least one photomask layout design to reduce the difference in the overall aperture ratios between the multiple photomask layout designs (overall aperture ratio difference).

[0005] According to an embodiment of the present invention, in the above-mentioned photomask design method, after adjusting the aperture ratio of the first dummy region of at least one photomask layout design, the difference in the overall aperture ratios between any two photomask layout designs can be in the range of 0% to 20%.

[0006] According to an embodiment of the present invention, in the above-mentioned photomask design method, after adjusting the aperture ratio of the first dummy region of at least one photomask layout design, the difference in the overall aperture ratios between any two photomask layout designs can be in the range of 0% to 15%.

[0007] According to an embodiment of the present invention, in the above-mentioned photomask design method, after adjusting the aperture ratio of the first dummy region of at least one photomask layout design, the difference in the overall aperture ratios between any two photomask layout designs can be in the range of 0% to 10%.

[0008] According to an embodiment of the present invention, in the above-mentioned photomask design method, after adjusting the aperture ratio of the first virtual region of at least one photomask layout design, the overall aperture ratio difference between any two photomask layout designs can be within the range of 0% to 5%.

[0009] According to an embodiment of the present invention, in the above-mentioned photomask design method, the method of adjusting the aperture ratio of the first virtual region of at least one photomask layout design may include increasing the aperture ratio of the first virtual region of at least one photomask layout design.

[0010] According to an embodiment of the present invention, in the above-mentioned photomask design method, the method of adjusting the aperture ratio of the first virtual region of at least one photomask layout design may include decreasing the aperture ratio of the first virtual region of at least one photomask layout design.

[0011] The present invention provides a semiconductor process, including the following steps. Provide a plurality of photomasks formed by the above-mentioned photomask design method. Provide a substrate, where the substrate includes a second device region and a second virtual region, the second device region corresponds to the first device region, the second virtual region corresponds to the first virtual region, the substrate has a fin portion and a dummy fin portion, the fin portion is located in the second device region, and the dummy fin portion is located in the second virtual region. Use a plurality of patterned photoresist layers as masks to perform a plurality of ion implantation processes on the substrate, where the plurality of patterned photoresist layers are formed by performing a plurality of photolithography processes using the plurality of photomasks. After performing the plurality of ion implantation processes, the top-down pattern of the top surface of the dummy fin portion has various widths.

[0012] According to an embodiment of the present invention, in the above-mentioned semiconductor process, at least two ion implantation processes may dope different region ranges of the dummy fin portion. The above different region ranges may have an overlapping region.

[0013] According to an embodiment of the present invention, in the above-mentioned semiconductor process, at least two ion implantation processes may dope different region ranges of the dummy fin portion. The above different region ranges may be separated from each other.

[0014] According to an embodiment of the present invention, in the above-mentioned semiconductor process, the contour of the top-down pattern of the top surface of the dummy fin portion may include an irregular shape.

[0015] According to an embodiment of the present invention, in the above-mentioned semiconductor process, the contour of the top-down pattern of the top surface of the dummy fin portion may include a curve.

[0016] According to an embodiment of the present invention, in the above-mentioned semiconductor process, the contour of the top-down pattern of the top surface of the dummy fin portion may include a wavy shape.

[0017] According to an embodiment of the present invention, in the above semiconductor process, the contour of the top-down pattern of the top surface of the dummy fin may include a tip.

[0018] The present invention provides a semiconductor structure, including a substrate. The substrate includes a device region and a dummy region. The substrate has fins and dummy fins. The fins are located in the device region. The dummy fins are located in the dummy region. The top-down pattern of the top surface of the dummy fins has various widths.

[0019] According to an embodiment of the present invention, in the above semiconductor structure, the contour of the top-down pattern of the top surface of the dummy fin may include an irregular shape.

[0020] According to an embodiment of the present invention, in the above semiconductor structure, the contour of the top-down pattern of the top surface of the dummy fin may include a curve.

[0021] According to an embodiment of the present invention, in the above semiconductor structure, the contour of the top-down pattern of the top surface of the dummy fin may include a wavy shape.

[0022] According to an embodiment of the present invention, in the above semiconductor structure, the contour of the top-down pattern of the top surface of the dummy fin may include a tip.

[0023] According to an embodiment of the present invention, in the above semiconductor structure, the top-down pattern of the top surface of the fin may have a uniform width.

[0024] Based on the above, in the photomask design method and semiconductor process proposed by the present invention, the aperture ratio of the first dummy region of at least one photomask layout design is adjusted, and the overall aperture ratio difference between multiple photomask layout designs is reduced. Therefore, the deviation of the size of components (such as doped regions) formed by subsequent processes (such as ion implantation processes) can be prevented. In addition, after performing the above semiconductor process, the top-down pattern of the top surface of the dummy fins in the semiconductor structure has various widths.

[0025] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are given below and described in detail in conjunction with the accompanying drawings as follows. Description of the Drawings

[0026] Figure 1 It is a flowchart of a photomask design method according to some embodiments of the present invention;

[0027] Figure 2 It is a top view of multiple photomask layout designs according to some embodiments of the present invention;

[0028] Figure 3 It is a top view of multiple photomask layout designs after adjusting the aperture ratio of the dummy region of the photomask layout design;

[0029] Figure 4 Flow chart of semiconductor processes for some embodiments of the present invention;

[0030] Figure 5 Partial top view of multiple photomasks for some embodiments of the present invention;

[0031] Figure 6 Partial top view of a substrate for some embodiments of the present invention;

[0032] Figure 7 Partial top view of a patterned photoresist layer and a substrate for some embodiments of the present invention;

[0033] Figure 8 Partial top view of a patterned photoresist layer and a substrate for some other embodiments of the present invention;

[0034] Figure 9 Partial perspective view of a semiconductor structure for some embodiments of the present invention;

[0035] Figure 10 Partial perspective view of a semiconductor structure for some other embodiments of the present invention;

[0036] Figure 11 Partial perspective view of a semiconductor structure for some other embodiments of the present invention.

[0037] Explanation of reference numerals in the drawings:

[0038] 10: Semiconductor structure

[0039] 100: Substrate

[0040] 102: Semiconductor structure

[0041] C1: Top surface

[0042] F1: Fin

[0043] F2: Virtual fin

[0044] M1, M11, M12, M13: Photomask

[0045] MD1, MD11, MD12, MD13: Photomask layout design

[0046] OP1~OP13: Opening

[0047] PR1, PR11, PR12, PR13: Patterned photoresist layer

[0048] R1, R11, R12, R13, R3, R5: Device region

[0049] R2, R21, R22, R23, R4, R6: Virtual region

[0050] S1, S2: Top surface

[0051] T1: Tip

[0052] S100, S102, S200, S202, S204: Steps Detailed implementation manners

[0053] Examples are listed below and described in detail with reference to the accompanying drawings. However, the provided examples are not intended to limit the scope covered by the present invention. For ease of understanding, the same components will be denoted by the same reference numerals in the following description. In addition, the drawings are for illustrative purposes only and are not drawn to the original scale. Moreover, the features in the top view and the features in the perspective view are not drawn to the same scale. In fact, for the sake of clear discussion, the sizes of various features can be increased or decreased arbitrarily.

[0054] Figure 1 It is a flowchart of a photomask design method according to some embodiments of the present invention. Figure 2 It is a top view of a plurality of photomask layout designs according to some embodiments of the present invention. Figure 3 It is a top view of a plurality of photomask layout designs after adjusting the aperture ratio of the virtual region of the photomask layout design.

[0055] Please refer to Figure 1 , in step S100, a plurality of photomask layout designs are provided, wherein the plurality of photomask layout designs have various overall aperture ratios, and each photomask layout design includes a device region and a virtual region.

[0056] In some embodiments, as Figure 2 shown, the plurality of photomask layout designs MD1 have various overall aperture ratios. Each photomask layout design MD1 includes a device region R1 and a virtual region R2. In some embodiments, the virtual region R2 can surround the device region R1. In some embodiments, the plurality of photomask layout designs MD1 can include a photomask layout design MD11, a photomask layout design MD12, and a photomask layout design MD13. In some embodiments, the overall aperture ratio of the photomask layout design MD12 can be greater than the overall aperture ratio of the photomask layout design MD11, and the overall aperture ratio of the photomask layout design MD13 can be greater than the overall aperture ratio of the photomask layout design MD12. In addition, the number of the photomask layout designs MD1 is not limited to the number in the figure. As long as the number of the photomask layout designs MD1 is plural, it falls within the scope covered by the present invention.

[0057] The photomask layout design MD11 may include a plurality of openings OP1 and a plurality of openings OP2. The plurality of openings OP1 may be located in the device region R11. The plurality of openings OP2 may be located in the dummy region R21. The photomask layout design MD12 may include a plurality of openings OP3 and a plurality of openings OP4. The plurality of openings OP3 may be located in the device region R12. The plurality of openings OP4 may be located in the dummy region R22. The photomask layout design MD13 may include a plurality of openings OP5 and a plurality of openings OP6. The plurality of openings OP5 may be located in the device region R13. The plurality of openings OP6 may be located in the dummy region R23. In some embodiments, the layout designs of the plurality of openings OP1 in the device region R11, the layout designs of the plurality of openings OP3 in the device region R12, and the layout designs of the plurality of openings OP5 in the device region R13 may be different from each other. In some embodiments, the layout designs of the plurality of openings OP2 in the dummy region R21, the layout designs of the plurality of openings OP4 in the dummy region R22, and the layout designs of the plurality of openings OP6 in the dummy region R23 may be the same as or different from each other.

[0058] Please refer to Figure 1 , in step S102, the opening rate of the dummy region of at least one photomask layout design is adjusted, while reducing the overall opening rate difference between the plurality of photomask layout designs. In some embodiments, after adjusting the opening rate of the dummy region of at least one photomask layout design, the overall opening rate difference between any two photomask layout designs may be in the range of 0% to 20%. In some embodiments, after adjusting the opening rate of the dummy region of at least one photomask layout design, the overall opening rate difference between any two photomask layout designs may be in the range of 0% to 15%. In some embodiments, after adjusting the opening rate of the dummy region of at least one photomask layout design, the overall opening rate difference between any two photomask layout designs may be in the range of 0% to 10%. In some embodiments, after adjusting the opening rate of the dummy region of at least one photomask layout design, the overall opening rate difference between any two photomask layout designs may be in the range of 0% to 5%.

[0059] In some embodiments, the method of adjusting the opening rate of the dummy region of at least one photomask layout design may include increasing the opening rate of the dummy region of at least one photomask layout design. For example, as Figure 3 shown, the opening rate of the dummy region R21 of the photomask layout design MD11 may be increased. In some embodiments, the size (e.g., length and / or width) of the opening OP2 in the dummy region R21 may be increased and / or the number of the openings OP2 in the dummy region R21 may be increased to increase the opening rate of the dummy region R21 of the photomask layout design MD11. In this embodiment, the opening rate of the dummy region R21 of the photomask layout design MD11 may be increased by increasing the length of the opening OP2 in the dummy region R21, but the present invention is not limited thereto.

[0060] In some embodiments, a method of adjusting the aperture ratio of a virtual region of at least one photomask layout design may include reducing the aperture ratio of the virtual region of at least one photomask layout design. For example, as Figure 3 shown, the aperture ratio of the virtual region R23 of the photomask layout design MD13 can be reduced. In some embodiments, the size (e.g., length and / or width) of the opening OP6 in the virtual region R23 and / or the number of openings OP6 in the virtual region R23 can be reduced to lower the aperture ratio of the virtual region R23 of the photomask layout design MD13. In this embodiment, the aperture ratio of the virtual region R23 of the photomask layout design MD13 can be reduced by reducing the length of the opening OP6 in the virtual region R23, but the present invention is not limited thereto.

[0061] In some embodiments, by the above method, the aperture ratio of the virtual region R2 of at least one photomask layout design MD1 can be adjusted, thereby reducing the overall aperture ratio difference among multiple photomask layout designs MD1.

[0062] Figure 4 is a flowchart of a semiconductor process according to some embodiments of the present invention. Figure 5 is a partial top view of multiple photomasks according to some embodiments of the present invention. Figure 6 is a partial top view of a substrate according to some embodiments of the present invention. Figure 7 is a partial top view of a patterned photoresist layer and a substrate according to some embodiments of the present invention. Figure 8 is a partial top view of a patterned photoresist layer and a substrate according to some other embodiments of the present invention. Figure 9 is a partial perspective view of a semiconductor structure according to some embodiments of the present invention. Figure 10 is a partial perspective view of a semiconductor structure according to some other embodiments of the present invention. Figure 11 is a partial perspective view of a semiconductor structure according to some other embodiments of the present invention.

[0063] Please refer to Figure 4 and Figure 5 In step S200, provide by Figure 1Multiple photomasks M1 formed by the photomask design method. Each photomask M1 includes a device region R3 and a dummy region R4. The device region R3 of the photomask M1 can correspond to the device region R1 of the photomask layout design MD1. The dummy region R4 of the photomask M1 can correspond to the dummy region R2 of the photomask layout design MD1. In some embodiments, the multiple photomasks M1 can include photomask M11, photomask M12, and photomask M13. In some embodiments, the opening OP7 in the dummy region R4 of the photomask M11 can be larger than the opening OP8 in the dummy region R4 of the photomask M12, and the opening OP8 in the dummy region R4 of the photomask M12 can be larger than the opening OP9 in the dummy region R4 of the photomask M13, but the present invention is not limited thereto. In some embodiments, an opening OP10 can be present in the device region R3 of the photomask M12. Additionally, the number of photomasks M1 is not limited to the number in the figure. As long as the number of photomasks M1 is multiple, it falls within the scope covered by the present invention.

[0064] Please refer to Figure 4 and Figure 6 , in step S202, a substrate 100 is provided, where the substrate 100 includes a device region R5 and a dummy region R6. The device region R5 corresponds to the device region R1, and the dummy region R6 corresponds to the dummy region R2. The substrate has fins F1 and dummy fins F2. The fins F1 are located in the device region R5, and the dummy fins F2 are located in the dummy region R6. In some embodiments, the device region R5 of the substrate 100 can correspond to the device region R3 of the photomask M1, and the dummy region R6 of the substrate 100 can correspond to the dummy region R4 of the photomask M1. In some embodiments, the dummy region R6 can be a region of the substrate 100 that is not used to form semiconductor devices (e.g., active devices or passive devices).

[0065] Please refer to Figure 4 and Figure 7, in step S204, multiple ion implantation processes are performed on the substrate 100 using multiple patterned photoresist layers PR1 as masks, where the multiple patterned photoresist layers PR1 are formed by performing multiple photolithography processes using multiple photomasks M1. Thus, a desired doped region (not shown) can be formed in the substrate 100. In some embodiments, the patterned photoresist layer PR1 may include a patterned photoresist layer PR11, a patterned photoresist layer PR12, and a patterned photoresist layer PR13. In some embodiments, the patterned photoresist layer PR11 may be formed by performing a photolithography process using the photomask M11, the patterned photoresist layer PR12 may be formed by performing a photolithography process using the photomask M12, and the patterned photoresist layer PR13 may be formed by performing a photolithography process using the photomask M13. In some embodiments, the opening OP11 of the patterned photoresist layer PR11 may be larger than the opening OP12 of the patterned photoresist layer PR12, and the opening OP12 of the patterned photoresist layer PR12 may be larger than the opening OP13 of the patterned photoresist layer PR13, but the present invention is not limited thereto. Additionally, the number of the patterned photoresist layers PR1 is not limited to the number in the figure. As long as the number of the patterned photoresist layers PR1 is multiple, it falls within the scope covered by the present invention.

[0066] In some embodiments, multiple ion implantation processes can be performed on the substrate 100 using the patterned photoresist layer PR11, the patterned photoresist layer PR12, and the patterned photoresist layer PR13 as masks. For example, the patterned photoresist layer PR11 can be formed, and then the patterned photoresist layer PR11 can be used as a mask to perform an ion implantation process on the substrate 100. Then, the patterned photoresist layer PR11 can be removed. Next, the patterned photoresist layer PR12 can be formed, and then the patterned photoresist layer PR12 can be used as a mask to perform an ion implantation process on the substrate 100. Subsequently, the patterned photoresist layer PR12 can be removed. Furthermore, the patterned photoresist layer PR13 can be formed, and then the patterned photoresist layer PR13 can be used as a mask to perform an ion implantation process on the substrate 100. Subsequently, the patterned photoresist layer PR13 can be removed.

[0067] In this embodiment, the opening OP11 of the patterned photoresist layer PR11 can expose the dummy fin F2 in the dummy region R6, the opening OP12 of the patterned photoresist layer PR12 can expose the dummy fin F2 in the dummy region R6, and the opening OP13 of the patterned photoresist layer PR13 can partially expose the dummy fin F2 in the dummy region R6, but the present invention is not limited thereto. The area range of the dummy fin F2 exposed by the opening of the patterned photoresist layer PR1 (such as the opening OP11 of the patterned photoresist layer PR11, the opening OP12 of the patterned photoresist layer PR12, or the opening OP13 of the patterned photoresist layer PR13) will vary according to the adjustment method of the opening rate of the dummy region R2 of the photomask layout design MD1. In addition, the opening of the patterned photoresist layer PR1 (such as the opening OP14 of the patterned photoresist layer PR12) can expose the corresponding fin F1 according to product requirements.

[0068] In addition, at least two ion implantation processes can dope different area ranges of the dummy fin F2. In this embodiment, as Figure 7 shown, the above different area ranges (such as the area range of the dummy fin F2 exposed by the opening OP12 and the area range of the dummy fin F2 exposed by the opening 13) can have an overlapping area, but the present invention is not limited thereto. In other embodiments, as Figure 8 shown, the above different area ranges (such as the area range of the dummy fin F2 exposed by the opening OP11, the area range of the dummy fin F2 exposed by the opening OP12, and the area range of the dummy fin F2 exposed by the opening OP13) can be separated from each other.

[0069] In addition, as Figure 9 shown, after multiple ion implantation processes, since the multiple ion implantation processes will damage the dummy fin F2, the top view pattern of the top surface S2 of the dummy fin F2 has various widths. Hereinafter, the semiconductor structure 10 of the above embodiment will be described by Figure 9 . In addition, although the formation method of the semiconductor structure 10 is described by taking the above method as an example, the present invention is not limited thereto.

[0070] Please refer to Figure 9, the semiconductor structure 10 includes a substrate 100. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. The substrate 100 includes a device region R5 and a dummy region R6. The substrate 100 has fins F1 and dummy fins F2. The fin F1 is located in the device region R5. The dummy fin F2 is located in the dummy region R6. The top view pattern of the top surface S2 of the dummy fin F2 has various widths. In some embodiments, the top view pattern of the top surface S1 of the fin F1 may have a uniform width. In some embodiments, the semiconductor structure 10 may further include an isolation structure 102. The isolation structure 102 is located on the substrate 100. The isolation structure 102 may be located on both sides of the fin F1 and both sides of the dummy fin F2. In some embodiments, the isolation structure 102 is, for example, a shallow trench isolation (STI) structure. In some embodiments, the material of the isolation structure 102 is, for example, silicon oxide.

[0071] In this embodiment, the top view pattern of the top surface S2 of the dummy fin F2 is taken as Figure 9 the pattern, but the present invention is not limited thereto. In other embodiments, the top view pattern of the top surface S2 of the dummy fin F2 may be, for example, as Figure 10 or Figure 11 shown in the figure. In some embodiments, as Figures 9 to 11 shown in the figure, the contour of the top view pattern of the top surface S2 of the dummy fin F2 may include an irregular shape. In some embodiments, as Figure 10 shown in the figure, the contour of the top view pattern of the top surface S2 of the dummy fin F2 may include a curve C1. In some embodiments, as Figure 10 shown in the figure, the contour of the top view pattern of the top surface S2 of the dummy fin F2 may include a wavy shape. In some embodiments, as Figure 9 and Figure 11 shown in the figure, the contour of the top view pattern of the top surface S2 of the dummy fin F2 may include a tip T1.

[0072] Based on the above embodiments, in the above photomask design method and semiconductor process, the aperture ratio of the dummy region R2 of at least one photomask layout design MD1 is adjusted, and the overall aperture ratio difference between multiple photomask layout designs MD1 is reduced. Therefore, the deviation of the size of components (such as doped regions) formed by subsequent processes (such as ion implantation processes) can be prevented. In addition, after the semiconductor process, the top view pattern of the top surface S2 of the dummy fin F2 in the semiconductor structure 10 has various widths.

[0073] In summary, in the photomask design method and semiconductor process of the above embodiments, the opening ratio of the virtual region of at least one photomask layout design is adjusted to reduce the overall opening ratio difference between multiple photomask layout designs. Therefore, it is possible to prevent deviations in the dimensions of components (such as doped regions) formed in subsequent processes (such as ion implantation processes). In addition, after performing the semiconductor process, the top-down pattern of the top surface of the virtual fins in the semiconductor structure has various widths.

[0074] Although the present invention has been disclosed as above with embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the claims.

Claims

1. A photomask design method, comprising: Providing a plurality of photomask layout designs, wherein the plurality of photomask layout designs have various overall aperture ratios, and each of the photomask layout designs includes a first device region and a first virtual region; And Adjusting the aperture ratio of the first virtual region of at least one of the photomask layout designs to reduce the overall aperture ratio difference between the plurality of photomask layout designs.

2. The photomask design method according to claim 1, wherein after adjusting the aperture ratio of the first virtual region of at least one of the photomask layout designs, the overall aperture ratio difference between any two of the photomask layout designs is in the range of 0% to 20%.

3. The photomask design method according to claim 1, wherein after adjusting the aperture ratio of the first virtual region of at least one of the photomask layout designs, the overall aperture ratio difference between any two of the photomask layout designs is in the range of 0% to 15%.

4. The photomask design method according to claim 1, wherein after adjusting the aperture ratio of the first virtual region of at least one of the photomask layout designs, the overall aperture ratio difference between any two of the photomask layout designs is in the range of 0% to 10%.

5. The photomask design method according to claim 1, wherein after adjusting the aperture ratio of the first virtual region of at least one of the photomask layout designs, the overall aperture ratio difference between any two of the photomask layout designs is in the range of 0% to 5%.

6. The photomask design method according to claim 1, wherein the method of adjusting the aperture ratio of the first virtual region of at least one of the photomask layout designs includes increasing the aperture ratio of the first virtual region of at least one of the photomask layout designs.

7. The photomask design method according to claim 1, wherein the method of adjusting the aperture ratio of the first virtual region of at least one of the photomask layout designs includes decreasing the aperture ratio of the first virtual region of at least one of the photomask layout designs.

8. A semiconductor process, comprising: Providing a plurality of photomasks formed by the photomask design method according to claim 1; Providing a substrate, wherein the substrate includes a second device region and a second virtual region, the second device region corresponds to the first device region, the second virtual region corresponds to the first virtual region, the substrate has fins and virtual fins, the fins are located in the second device region, and the virtual fins are located in the second virtual region; And Performing a plurality of ion implantation processes on the substrate using a plurality of patterned photoresist layers as masks, wherein The plurality of patterned photoresist layers are formed by performing a plurality of photolithography processes using the plurality of photomasks, and After performing the plurality of ion implantation processes, the top-down pattern of the top surface of the virtual fins has various widths.

9. The semiconductor process according to claim 8, wherein at least two of the ion implantation processes dope different region ranges of the virtual fins, and the different region ranges have an overlapping region.

10. The semiconductor process according to claim 8, wherein at least two of the ion implantation processes dope different area ranges of the dummy fin, and the different area ranges are separated from each other.

11. The semiconductor process according to claim 8, wherein the contour of the top-down pattern of the top surface of the dummy fin includes an irregular shape.

12. The semiconductor process according to claim 8, wherein the contour of the top-down pattern of the top surface of the dummy fin includes a curve.

13. The semiconductor process according to claim 8, wherein the contour of the top-down pattern of the top surface of the dummy fin includes a wavy shape.

14. The semiconductor process according to claim 8, wherein the contour of the top-down pattern of the top surface of the dummy fin includes a tip.

15. A semiconductor structure, comprising: a substrate, wherein the substrate includes a device region and a dummy region, the substrate has fins and dummy fins, the fins are located in the device region, the dummy fins are located in the dummy region, and the top-down pattern of the top surface of the dummy fin has multiple widths.

16. The semiconductor structure according to claim 15, wherein the contour of the top-down pattern of the top surface of the dummy fin includes an irregular shape.

17. The semiconductor structure according to claim 15, wherein the contour of the top-down pattern of the top surface of the dummy fin includes a curve.

18. The semiconductor structure according to claim 15, wherein the contour of the top-down pattern of the top surface of the dummy fin includes a wavy shape.

19. The semiconductor structure according to claim 15, wherein the contour of the top-down pattern of the top surface of the dummy fin includes a tip.

20. The semiconductor structure according to claim 15, wherein the top-down pattern of the top surface of the fin has a uniform width.

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