Method and system for verifying interlocking and locking logic of transformer substation

Abstract

The invention discloses a transformer substation interlocking logic verification method and system, and belongs to the technical field of intelligent transformer substation relay protection and control, and the method comprises the steps: carrying out the automatic recognition of an interlocking logic file of a to-be-verified measurement and control device, and generating an interlocking logic preliminary screening plate; analyzing an SCD model file, and mapping characters in the interlocking logic preliminary screening plate and functional constraint data attributes in the SCD file through a fuzzy matching algorithm to generate an interlocking logic mapping plate; performing multi-source fusion verification on the interlocking logic mapping plate and standardized interlocking logic, and performing logic conflict detection in combination with a preset rule base to generate an interlocking logic verification plate; and importing the interlocking logic verification plate into an automatic detector, performing automatic verification on the interlocking logic of the to-be-verified measurement and control device, and outputting a detection result. According to the invention, on-site interlocking logic verification work can be reduced, and the work accuracy and efficiency of an operation and maintenance team are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of relay protection and control of intelligent substations, and more specifically, relates to a method and system for verifying substation interlocking logic. Background Art

[0002] The interlocking logic of the measurement and control device in the substation usually needs to be confirmed manually during the acceptance stage. During the acceptance, it is necessary to test each condition of each logic according to the design institute's drawings to avoid omissions. This usually consumes a lot of manpower, and the design institute's drawings may also have problems.

[0003] In the operation and maintenance of smart substations, the correctness of the interlocking logic is directly related to the safety and reliability of power grid operations. Traditional verification methods rely on manual comparison of design drawings and measurement and control device logic, simulating operating conditions item by item, and performing status verification. However, with the expansion of substation equipment scale and the increase of logic complexity, manual verification faces problems such as low efficiency and susceptibility to differences between drawings and device versions. In particular, when there is ambiguity in logical expression or ambiguity in symbol recognition in the design drawings, it is easy to cause deviations in on-site verification.

[0004] The prior art document (CN112784697A) discloses a five-defense logic verification scheme in the field of five-defense logic verification technology for substations. The scheme extracts the logic statements in the five-defense simulation operation sheet image and compares them with the specification library. However, the scheme only realizes a simple comparison between the operation interface logic and the specification library. There are problems such as a single verification dimension and an inability to verify the consistency between the device logic and the SCD model. Summary of the invention

[0005] In view of the above problems, the present invention provides a method and system for substation interlocking logic verification, which solves the problem that the existing on-site interlocking logic verification process is complicated and labor-intensive, and further improves the efficiency and accuracy of substation operation and maintenance.

[0006] The present invention adopts the following technical solution.

[0007] A first aspect of the present invention provides a method for verifying substation interlocking logic, comprising the following steps:

[0008] Automatically identify the interlocking logic file of the measurement and control device to be verified and generate a preliminary screening version of the interlocking logic. The automatic identification includes performing text detection and recognition on the logical expressions in the file through an OCR model, and integrating an adversarial training strategy into the training process of the OCR model to generate perturbation samples for the logical operators to optimize the model parameters;

[0009] Parse the SCD model file, map the text in the preliminary screening version of the interlocking logic to the functional constraint data attributes in the SCD file through a fuzzy matching algorithm, and generate a mapped version of the interlocking logic;

[0010] Perform multi-source fusion verification on the mapped version of the interlocking logic and the standardized interlocking logic, detect logical conflicts in combination with a preset rule library, and generate a verified version of the interlocking logic;

[0011] Import the verified version of the interlocking logic into an automated detector to automatically verify the interlocking logic of the control and measurement device to be verified, and output the detection results.

[0012] Optionally, the text detection and recognition of the logical expression in the file by the OCR model includes:

[0013] Perform convolution processing on the input image of the interlocking logic file to extract the convolution feature map;

[0014] Generate anchor points with a fixed width on the output convolution feature map and classify them to distinguish text and non-text regions;

[0015] Adjust its bounding box in the vertical direction based on the selected text anchor points;

[0016] Use a bidirectional long short-term memory network to connect adjacent text anchor points and splice the discrete strings into a complete logical expression in logical order.

[0017] Optionally, integrating an adversarial training strategy in the training process of the OCR model to generate perturbation samples for logical operators to optimize model parameters includes:

[0018] Add geometric and noise perturbations to the input drawing image to generate adversarial samples for simulating the physical deformation and noise interference of the scanned drawing;

[0019] During the model training process, jointly optimize the loss functions of the original samples and the adversarial samples by weighted summation;

[0020] Perform directional deformation enhancement on logical symbols to generate a training data subset covering the diversity of handwritten symbols.

[0021] Optionally, the adding of geometric and noise perturbations to the input drawing image to generate adversarial samples includes:

[0022] The geometric perturbations include rotation, tilt, and perspective transformation, and the noise perturbations include Gaussian noise and blurring;

[0023] The perturbation direction of the adversarial sample is generated based on the model loss gradient direction of the original sample, and the perturbation amplitude is controlled by a preset intensity coefficient.

[0024] Optionally, the loss function for jointly optimizing the original sample and the adversarial sample by weighted summation includes:

[0025] Optimizing the losses of the original sample and the adversarial sample simultaneously in the total loss function:

[0026]

[0027] where α is the weight coefficient for adjusting the contributions of the original sample loss and the adversarial sample loss, β is the focusing coefficient for enhancing the weight of the logical symbol set recognition loss; θ is the model parameter, x is the original sample, y is the true label corresponding to x, and x adv is the adversarial sample, S is the logical symbol set to be optimized; f(s) is the output probability of the model for symbol s; and y s is the true probability of the model for symbol s.

[0028] Optionally, the mapping with the functional constraint data attributes in the SCD file through the fuzzy matching algorithm includes:

[0029] Using the Levenshtein distance algorithm to calculate the edit distance D between the input string a in the preliminary screening version of the interlocking logic and the target string b in the SCD file a,b :

[0030]

[0031] where D i,j is the minimum number of edit operations between the strings a[1..i] and b[1..j]; 1 ai≠bj is the indicator function; a i is the i-th character in the input string a, and b j is the j-th character in the target string b;

[0032] Calculating the similarity based on the edit distance between the input string a and the target string b, and determining a successful match when the similarity is higher than the preset threshold to complete the mapping; otherwise, triggering manual review or marking it as a failed match.

[0033] Optionally, the preset threshold is dynamically adjusted according to the device type, including:

[0034] Dividing the device complexity into levels 1 to 5 based on the device configuration parameters and the complexity of the operation process;

[0035] Calculating the threshold adjustment factor according to the device complexity level and the predefined adjustment coefficient;

[0036] Multiplying the base threshold by the adjustment factor to generate the dynamically adjusted similarity threshold.

[0037] Optionally, the multi-source fusion verification includes:

[0038] When the bus grounding knife switch is detected to be closed, verify whether the associated line switch status meets the off-position condition, and its logical expression is:

[0039]

[0040] Wherein, S_St is the device status function, 1 represents closing, 0 represents opening, and N is the total number of associated lines.

[0041] Optionally, the operations of the automated detector include:

[0042] Convert the logical expression into an MMS control command of the IEC61850 protocol;

[0043] Real-time monitor the change of the GOOSE message status of the measuring and control device, and automatically resend the instruction when no response is received after the timeout.

[0044] The second aspect of the present invention provides a system for verifying the interlocking logic of a substation. Based on the method for verifying the interlocking logic of a substation described in the first aspect of the present invention, the system includes:

[0045] An OCR recognition module, which is used to perform text detection and logical symbol recognition of the interlocking logic file through a deep learning model including adversarial training for generating perturbation samples of logical operators;

[0046] An SCD matching module, which is used to map the OCR recognition result to the functional constraint data attributes in the SCD model based on a fuzzy matching algorithm with a dynamic similarity threshold;

[0047] A multi-source verification module, which is used to compare the mapped logic with the preset standardized logic. This module includes a conflict detection unit and an alarm trigger unit;

[0048] An automated detection module, which is used to send the verified logic instruction to the measuring and control device through a hardware interface, and collect the device response in real time to generate a visual detection report.

[0049] Compared with the prior art, the beneficial effects of the present invention at least include:

[0050] 1. By integrating the OCR recognition technology with adversarial training and the dynamic mapping mechanism of the SCD model, the present invention solves the problems of single verification dimension and inability to verify the consistency between the device logic and the SCD model in the prior art, and improves the accuracy of interlocking logic recognition and system compatibility.

[0051] 2. Through the conflict detection of the multi-source fusion verification mechanism and the preset rule library, the present invention solves the problems of low efficiency and strong experience dependence in manual review, realizes the automatic identification and warning of complex logical conflicts, and effectively improves the intelligent level of substation operation and maintenance.

[0052] 3. Through the IEC61850 protocol conversion and the GOOSE message adaptive retransmission strategy, the present invention solves the problems of response delay and operation uncertainty existing in traditional manual testing, and significantly enhances the real-time performance and operation reliability of the automatic verification of the measurement and control device. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 It is a schematic diagram of the method flow provided according to the embodiments of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0054] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. The described embodiments are only part of the embodiments of the present invention, rather than all embodiments. Based on the spirit of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0055] In Embodiment 1 of the present invention, a method for verifying the interlocking logic of a substation is provided. As Figure 1 shown, it includes the following steps:

[0056] Step 1: Automatically identify the interlocking logic file of the measurement and control device to be verified, and generate a preliminary screening version of the interlocking logic. The automatic identification includes text detection and recognition of the logical expressions in the file through an OCR model. The training process of the OCR model integrates an adversarial training strategy, and the adversarial training strategy includes generating perturbation samples for logical operators to optimize the model parameters.

[0057] Preferably, Step 1 further includes preprocessing the image before recognition, including denoising, binarization, and skew correction.

[0058] Optical Character Recognition (OCR) technology is used to extract text from drawings or electronic documents, which is specifically implemented through the Tesseract engine, and the image preprocessing steps are optimized.

[0059] Further preferably, the OCR model architecture is CTPN (Convolutional Text Proposal Network). CTPN combines a convolutional network and a recurrent network to achieve end-to-end text line detection and recognition.

[0060] Preferably, in the step 1, text detection and recognition of the logical expressions in the document by the OCR model includes:

[0061] Step 1.1, perform convolution processing on the input image of the interlocking logic file to extract a convolutional feature map.

[0062] More preferably, the step 1.1 includes performing multi-layer convolution processing on the input image of the interlocking logic file (such as a scanned drawing) through the VGG16 convolutional neural network in the OCR model to extract a convolutional feature map containing detailed information such as device numbers and logical symbols, providing basic semantic features for subsequent text detection.

[0063] Step 1.2, generate anchor points with a fixed width on the convolutional feature map output in step 1.1 and classify them to distinguish text and non-text regions.

[0064] More preferably, the step 1.2 includes:

[0065] Generate anchor points with a fixed width on the convolutional feature map of the substation drawing, and the classification score formula is:

[0066] P text (i) = σ(W cls ·φ conv (x i ) + b cls )

[0067] where φ conv (x i ) is the feature vector at the i-th position extracted by the VGG16 network (such as the region where the logical symbol "50221 = 0" is located in the drawing); W cls and b cls are classification layer parameters used to distinguish text (such as device numbers) from non-text regions (such as table lines); σ is the Sigmoid function, and the output is the probability that the anchor point is text (for example, the probability of recognizing "50221" as a device number is 0.98).

[0068] Step 1.3, adjust the bounding box of the selected text anchor points in the vertical direction.

[0069] More preferably, the step 1.3 includes:

[0070] For the logical expressions in the substation drawing (such as "50221 = 0 & 50311 = 0"), perform fine-tuning of the anchor points in the vertical direction:

[0071] Δy = t y ·h a

[0072]

[0073] Among them, t y and t h are the offsets predicted by the network, which are used to correct the anchor position (for example, adjusting the initial anchor height from 16 pixels to 20 pixels to completely cover the logical operator "&"); h a is the preset anchor height (matching the height of common characters in the substation drawing).

[0074] Step 1.4: Use a bidirectional long short-term memory network to connect adjacent text anchors and splice the discrete strings into a complete logical expression in logical order.

[0075] Further preferably, the step 1.4 includes:

[0076] Connect adjacent anchors through LSTM to solve the problem of multi-line arrangement of logical expressions in substation drawings:

[0077] h t = LSTM(φ conv (x t ), h t-1 )

[0078] It is used to merge scattered characters (such as "50221 = 0", "50311 = 0") into a complete logical expression "50221 = 0 & 50311 = 0"; preferably, it supports the recognition of inclined text lines (such as italic logical conditions in handwritten annotations in design drawings).

[0079] Preferably, in step 1, integrating adversarial training in the training process of the OCR model to optimize the recognition ability of logical symbols includes:

[0080] For the easily confused operators in substation drawings (such as ∨ (or), ∧ (and)), integrate adversarial training in the training process of the OCR model to optimize the recognition ability of logical symbols;

[0081] Specifically, the integration of adversarial training to optimize the recognition ability of logical symbols includes:

[0082] (1) Adversarial sample generation:

[0083] Add small perturbations to the input drawing image, including geometric and noise perturbations. The geometric perturbations include rotation, inclination, and perspective transformation, and the noise perturbations include Gaussian noise and blurring processing to generate adversarial samples. For example:

[0084]

[0085] Among them, ε is the perturbation intensity, simulating the slight blurring of the scanned drawing; The loss gradient of the model on the original samples is used to generate targeted perturbations (e.g., misidentifying "∧" as "∨").

[0086] (2) Optimize the adversarial loss function

[0087] Optimize the losses of both the original samples and the adversarial samples simultaneously in the total loss function to strengthen the model's attention to key symbols:

[0088]

[0089] Among them, α and β are the weights for balancing ordinary samples and adversarial samples. Exemplarily, they can take values of 0.6 and 0.4 respectively. Specifically, α is the weight coefficient for adjusting the contributions of the losses of the original samples and the adversarial samples, and β is the focusing coefficient for enhancing the loss weight of the logical symbol set recognition; θ is the model parameter, x is the original sample, y is the true label corresponding to x, and x adv is the adversarial sample; S is the set of logical symbols that need to be optimized with emphasis. Exemplarily, S = {∨, ∧}; f(s) is the output probability of the model for symbol s; and y s is the true probability of the model for symbol s.

[0090] (3) Symbol-specific data augmentation

[0091] Design deformation augmentation for logical symbols (such as rotation by ±10°, perspective transformation) to simulate the diversity of handwritten symbols in substation drawings:

[0092] x aug = T(x, λ), λ ~ U(-0.15, 0.15)

[0093] Among them, x aug is the sample data after data augmentation. T(x, λ) is used to perform the data augmentation transformation operation. λ is a random parameter that follows a uniform distribution U(-0.15, 0.15) and is used to control the degree of data augmentation, such as the specific transformation parameters in operations like rotation and perspective transformation.

[0094] It should be noted that the adversarial training optimization strategy for logical symbols is a core component of the OCR model training process. Through adversarial sample generation, targeted loss function design, and symbol-specific data augmentation, this strategy directly optimizes the OCR model's recognition ability for key logical symbols in substation drawings, significantly improving the robustness and practical application effect of the model. This optimization is not limited to theoretical design but is also embedded in the end-to-end training process of the OCR model through specific mathematical formulas and engineering practices.

[0095] Exemplarily, the interlocking logic designed here refers to the interlocking logic for the current substation measurement and control device given by the design institute, and its form includes but is not limited to the form of drawings or electronic documents. The following presents an electronic document of the design institute for the grounding knife interlocking logic of a 500 kV bus, where 0 represents the open state and 1 represents the closed state.

[0096]

[0097] Automatic recognition means converting the designed interlocking logic into a unified format through optical character recognition (OCR) technology, optical mark recognition (OMR) technology, and deep learning-based image processing technology.

[0098] An example of the preliminary screening version of the interlocking logic obtained after automatic recognition is as follows:

[0099] 5117_CTRL:((50221 = 0) & (50311 = 0) & (50411 = 0) & (50511 = 0)).

[0100] Step 2: Parse the SCD model file, map the text in the preliminary screening version of the interlocking logic to the functional constraint data attributes in the SCD file through a fuzzy matching algorithm, and generate a mapped version of the interlocking logic. Among them, the fuzzy matching algorithm dynamically adjusts the similarity matching threshold according to the device type.

[0101] Specifically, text matching means finding the text in the preliminary screening version of the interlocking logic in the SCD file through methods such as exact matching, fuzzy matching based on distance or similarity, string matching, template matching, and deep learning matching, and replacing it with the corresponding FCDA (Functional Constraint Data Attribute) in the SCD file.

[0102] Preferably, in step 2, the mapping to the functional constraint data attributes in the SCD file through the fuzzy matching algorithm includes:

[0103] The algorithm formula for the FCDA matching rule includes:

[0104] (1) Levenshtein distance algorithm

[0105] Calculate the edit distance D between strings a and b a,b :

[0106]

[0107] Among them, D i,jis the minimum number of edit operations for strings a[1..i] and b[1..j]; 1 ai≠bj is the indicator function (1 when the characters are different, otherwise 0); a i is the i-th character in the input string a, b j is the j-th character in the target string b;

[0108] The similarity calculation formula is

[0109]

[0110] Exemplarily, the threshold is set to 90%. When the similarity is greater than or equal to 90%, it is regarded as a successful match.

[0111] Further preferably, the similarity threshold of the fuzzy match is dynamically adjusted according to the device type, and the adjustment formula is:

[0112]

[0113] where, T adj is the adjusted threshold, T base is the basic threshold, exemplarily set to 90%; k is the adjustment coefficient, exemplarily set to 0.1; C eq is the device complexity level. Exemplarily, the complexity can be divided into levels 1 to 5 according to the device configuration parameters and the complexity of the operation process, and level 5 is the highest level.

[0114] According to the above example, after matching the FCDA of the disconnecting switch such as 50221 in the SCD, the following interlocking logic mapping version is obtained:

[0115] 5117_CTRL:((CB5022CTRL / CBCSWI2.Pos.stVal = 0) & (CB5031CTRL / CBCSWI2.Pos.stVal = 0) & (CB5041CTRL / CBCSWI2.Pos.stVal = 0) & (CB5051CTRL / CBCSWI2.Pos.stVal = 0)).

[0116] Step 3, perform multi-source fusion verification on the interlocking logic mapping version and the standardized interlocking logic, detect logical conflicts in combination with the preset rule library, and generate an interlocking logic verification version.

[0117] Preferably, in the said Step 3, the mathematical expression of the multi-source fusion verification logic includes:

[0118] (1) The logical expression of rule R001

[0119] When the bus grounding disconnecting switch is closed, the associated line switch must be in the off position:

[0120]

[0121] Among them, S_St is the device status function (1 = closed, 0 = open), N is the total number of associated lines, and ∧ is the logical "AND" operation, indicating that all lines must meet the conditions.

[0122] (2) State equation of rule R002

[0123] The bus voltage needs to be 0 before operating the device:

[0124]

[0125] Among them, V 母线 is the bus voltage value; A_O is the allowable operation flag (1 = allowed, 0 = prohibited).

[0126] Preferably, the alarm interface in step 3 includes a visual display of the logical conflict path, and uses red highlighting to show the device nodes that violate the standardization rules and their associated links.

[0127] The standardized interlock logic refers to the interlock logic pre-compiled according to experience, which can be used for secondary verification of the logic in the drawing in step 1.

[0128] Multi-source fusion means using the standardized interlock logic to verify the interlock logic mapping version. If the verification fails, an alarm is given through the interface and the current verification is aborted.

[0129] In this example, for the interlock logic of the 500kV bus grounding switch, it is usually required that the switches of the lines connected to the bus are all in the open position. After verification, the logic is correct. There are also some empirical logics that require the condition of no voltage on the bus to be met at the same time. In this case, an alarm will be given on the interface to ask whether to proceed to the next step.

[0130] It should be noted that for the problem of single verification dimension in the prior art, the present invention expands the verification dimension from the single operation interface logic to the quadruple dimensions of device logic, drawing logic, system model, and standardization rule library through the dual mechanisms of associating the logic recognized by OCR with the FCDA in the SCD model and introducing a pre-set standardized logic library for cross-verification. In step 4, import the interlock logic verification version into the automated detector to automatically verify the interlock logic of the to-be-verified measurement and control device and output the detection result.

[0131] Preferably, the operations of the automated detector in step 4 include:

[0132] Convert the logical expression into an MMS control command of the IEC61850 protocol;

[0133] Real-time monitor the GOOSE message status change of the measurement and control device, and automatically resend the instruction when no response is received within the timeout period.

[0134] Specifically, the automated detector refers to a device that can automatically verify the interlocking logic of the measurement and control device according to the interlocking logic file.

[0135] The present invention can improve the on-site work efficiency and improve the accuracy through the secondary verification of the design institute drawings.

[0136] In Embodiment 2 of the present invention, a system for verifying the interlocking logic of a substation is provided. Based on the method for verifying the interlocking logic of a substation described in Embodiment 1, the system includes:

[0137] An OCR recognition module configured to perform text detection and logical symbol recognition of the interlocking logic file through a deep learning model including adversarial training, where the adversarial training includes generating perturbation samples for logical operators;

[0138] An SCD matching module configured to map the OCR recognition result to the FCDA in the SCD model based on a fuzzy matching algorithm with a dynamic similarity threshold;

[0139] A multi-source verification module configured to compare the mapped logic with the preset standard logic, and includes a conflict detection unit and an alarm trigger unit;

[0140] An automated detection module configured to send the verified logic instruction to the measurement and control device through a hardware interface, and collect the device response in real time to generate a visual detection report.

[0141] The present disclosure may be a system, a method, and / or a computer program product. The computer program product may include a computer-readable storage medium having computer-readable program instructions thereon for causing a processor to implement various aspects of the present disclosure.

[0142] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: the specific implementation manners of the present invention can still be modified or equivalently replaced, and any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered by the protection scope of the claims of the present invention.

Claims

1. A method for verifying the interlocking logic of a substation, characterized in that, It includes the following steps: Automatically identify the interlocking logic file of the measurement and control device to be verified, and generate a preliminary version of the interlocking logic. The automatic identification includes text detection and recognition of the logical expressions in the file through an OCR model, and integrating an adversarial training strategy in the training process of the OCR model to generate perturbation samples for logical operators to optimize the model parameters; Parse the SCD model file, map the text in the preliminary version of the interlocking logic to the functional constraint data attributes in the SCD file through a fuzzy matching algorithm, and generate a mapped version of the interlocking logic; Perform multi-source fusion verification on the mapped version of the interlocking logic and the standardized interlocking logic, detect logical conflicts in combination with a preset rule library, and generate a verified version of the interlocking logic; Import the verified version of the interlocking logic into an automated detector to automatically verify the interlocking logic of the measurement and control device to be verified, and output the detection result.

2. The method for verifying the interlocking logic of a substation according to claim 1, wherein: The text detection and recognition of the logical expressions in the file through the OCR model includes: Perform convolution processing on the input interlocking logic file image to extract a convolution feature map; Generate anchor points with a fixed width on the output convolution feature map and classify them to distinguish text and non-text regions; Adjust the bounding box of the selected text anchor points in the vertical direction; Use a bidirectional long short-term memory network to connect adjacent text anchor points, and splice the discrete strings into a complete logical expression in logical order.

3. The method for verifying the interlocking logic of a substation according to claim 2, wherein: Integrating an adversarial training strategy in the training process of the OCR model to generate perturbation samples for logical operators to optimize the model parameters includes: Add geometric and noise perturbations to the input drawing image to generate adversarial samples for simulating the physical deformation and noise interference of the scanned drawing; During the model training process, jointly optimize the loss functions of the original sample and the adversarial sample through a weighted summation method; Perform directional deformation enhancement on logical symbols to generate a training data subset covering the diversity of handwritten symbols.

4. The method for verifying the interlocking logic of a substation according to claim 3, wherein: Adding geometric and noise perturbations to the input drawing image to generate adversarial samples includes: The geometric perturbations include rotation, tilt, and perspective transformation, and the noise perturbations include Gaussian noise and blurring; The perturbation direction of the adversarial sample is generated based on the model loss gradient direction of the original sample, and the perturbation amplitude is controlled by a preset intensity coefficient.

5. The method for verifying the interlocking logic of a substation according to claim 3, wherein: Jointly optimizing the loss functions of the original sample and the adversarial sample through a weighted summation method includes: Simultaneously optimize the losses of the original sample and the adversarial sample in the total loss function: Among them, α is a weight coefficient used to adjust the contributions of the original sample loss and the adversarial sample loss, and β is a focusing coefficient used to enhance the weight of the logical symbol set recognition loss; θ is the model parameter, x is the original sample, y is the true label corresponding to x, and x adv is the adversarial sample, S is the logical symbol set to be optimized; f(s) is the output probability of the model for the symbol s; y s is the true probability of the model for the symbol s.

6. The method for verifying the interlocking logic of a substation according to claim 1, wherein: The mapping to the functional constraint data attributes in the SCD file through a fuzzy matching algorithm includes: Using the Levenshtein distance algorithm, calculate the edit distance D between the input string a in the initial screening version of the interlocking logic and the target string b in the SCD file a,b : Among them, D i,j is the minimum edit distance between the strings a[1..i] and b[1..j]; 1 ai≠bj is an indicator function; a i is the i-th character in the input string a, and b j is the j-th character in the target string b; Calculate the similarity based on the edit distance between the input string a and the target string b. When the similarity is higher than the preset threshold, it is determined that the match is successful and the mapping is completed; otherwise, manual review is triggered or it is marked as a failed match.

7. A method for verifying the interlocking logic of a substation according to claim 6, wherein: The preset threshold is dynamically adjusted according to the device type and includes: Based on the device configuration parameters and the complexity of the operation process, the device complexity is divided into multiple levels; Calculate the threshold adjustment factor according to the device complexity level and the predefined adjustment coefficient; Multiply the base threshold by the adjustment factor to generate a dynamically adjusted similarity threshold.

8. A method for verifying the interlocking logic of a substation according to claim 1, wherein: The multi-source fusion verification includes: When it is detected that the bus earthing switch is closed, verify whether the associated line switch status meets the off-position condition, and its logical expression is: Where S_St is the device status function, 1 represents closing, 0 represents opening, and N is the total number of associated lines.

9. A method for verifying the interlocking logic of a substation according to claim 1, wherein: The operation of the automated detector includes: Convert the logical expression into an MMS control command of the IEC61850 protocol; Real-time monitor the status change of the GOOSE message of the measuring and control device, and automatically resend the instruction when no response is received after a timeout.

10. A system for verifying the interlocking logic of a substation, based on the method for verifying the interlocking logic of a substation according to any one of claims 1-9, characterized in that, The system includes: An OCR recognition module for performing text detection and logical symbol recognition of the interlocking logic file through a deep learning model including adversarial training for generating perturbation samples for logical operators; An SCD matching module for mapping the OCR recognition result to the functional constraint data attributes in the SCD model based on a fuzzy matching algorithm with a dynamic similarity threshold; A multi-source verification module for comparing the mapped logic with the preset standardized logic. This module includes a conflict detection unit and an alarm trigger unit; An automated detection module for sending the verified logical instruction to the measuring and control device through a hardware interface and collecting the device response in real time to generate a visual detection report.

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