Method for realizing synchronous processing of multi-channel ADC data based on FPGA

Abstract

The invention relates to a method for realizing multi-channel ADC (Analog to Digital Converter) data synchronization processing based on an FPGA (Field Programmable Gate Array), which comprises the following steps that: the FPGA receives a clock frequency generated by an external clock generator and takes the clock frequency as a working clock of the FPGA; a plurality of groups of same-frequency clocks and same-phase clocks are generated in the FPGA and are respectively used as working clocks of the ADC chips; the FPGA receives sampling data of each ADC, an enable signal is set, and when the enable signal is effective, digital down-conversion, decimation filtering and FIR filtering are carried out on each sampling data; and after FIR filtering is completed, another enable signal ENend is generated, and data are further stored or transmitted to an upper computer. According to the method and the device for realizing the multi-channel ADC data synchronous processing based on the FPGA, the processor and the computer readable storage medium thereof, synchronous start and stop of the processing flow are controlled through the enable signals ENstart and ENend, synchronous processing of the multi-channel ADC data is ensured, accuracy and effectiveness are improved, and the method and the device have a wide application range.

Description

Technical Field

[0001] The present invention relates to the field of digital signal processing, and particularly to the field of ADC data synchronization processing. Specifically, it refers to a method, device, processor, and computer-readable storage medium for realizing multi-channel ADC data synchronization processing based on FPGA. Background Art

[0002] In a vector network analyzer system, ADC sampling data is crucial. For a multi-port vector network analyzer, which needs to process multi-channel data simultaneously and uses multiple ADC chips, the synchronization of all ADC sampling data is particularly important to ensure the accuracy and effectiveness of the processed data.

[0003] In the existing solution, for multiple ADC chips, a clock generator generates multi-channel clock signals with the same frequency and phase, which are respectively used as the sampling clocks of each chip. In this solution, when the clock frequency is relatively high, due to the limitations of the hardware circuit and others, there will be a phase deviation between the sampling clocks, thus affecting the synchronization between all ADC sampling data. Summary of the Invention

[0004] The object of the present invention is to overcome the above-mentioned disadvantages of the prior art and provide a method, device, processor, and computer-readable storage medium for realizing multi-channel ADC data synchronization processing based on FPGA, which has high accuracy, high effectiveness, and a relatively wide application range.

[0005] In order to achieve the above object, the method, device, processor, and computer-readable storage medium for realizing multi-channel ADC data synchronization processing based on FPGA of the present invention are as follows: The method for realizing multi-channel ADC data synchronization processing based on FPGA is mainly characterized in that the method includes the following steps: (1) The FPGA receives the clock frequency generated by an external clock generator and uses it as the working clock of the FPGA; (2) The FPGA internally generates multiple groups of clocks with the same frequency and the same phase, which are respectively used as the working clocks of each ADC chip; (3) The FPGA receives the sampling data of each ADC, sets an enable signal EN_start, and when the enable signal EN_start is valid, performs digital down-conversion, decimation filtering, and FIR filtering on the sampling data of each channel respectively; (4) After the FIR filtering is completed, the FPGA generates another enable signal EN_end for a single ADC chip to further store the data or transmit it to the host computer.

[0006] Preferably, the step (3) specifically includes the following steps: (3.1) The FPGA receives the sampled data from each ADC, sets an enable signal EN_start, and when the enable signal EN_start is valid, performs digital down-conversion processing on the sampled data of each channel respectively; (3.2) After the digital down-conversion processing is completed, decimation filtering is performed on the data; (3.3) After the decimation filtering is completed, the data is filtered through a FIR filter.

[0007] Preferably, step (4) further includes the following steps: (4.1) After the FIR filtering is completed, the FPGA generates an enable signal EN_end 1, EN_end 2,..., EN_end n-1, EN_end n for each ADC chip respectively, where n is an integer greater than 0, and performs a logical AND operation on the enable signals of all multiple ADC chips to obtain a new enable signal EN; (4.2) If the enable signal EN is valid, the data of each processed ADC chip is stored or transmitted to the host computer in the set order.

[0008] Preferably, the working clock frequencies and phases of the ADC chips of each channel are the same and the phases are consistent, and the sampled data of the ADC chips of each channel are in a synchronous state.

[0009] Preferably, in step (3), the working clock of the ADC chip is consistent with the working clock of the FPGA that processes the sampled data of this ADC chip.

[0010] The device for realizing synchronous processing of multiple ADC data based on FPGA is characterized in that the device includes: A processor configured to execute computer-executable instructions; A memory storing one or more computer-executable instructions, and when the computer-executable instructions are executed by the processor, each step of the method for realizing synchronous processing of multiple ADC data based on FPGA as described above is implemented.

[0011] The processor for realizing synchronous processing of multiple ADC data based on FPGA is characterized in that the processor is configured to execute computer-executable instructions, and when the computer-executable instructions are executed by the processor, each step of the method for realizing synchronous processing of multiple ADC data based on FPGA as described above is implemented.

[0012] The computer-readable storage medium is characterized in that a computer program is stored thereon, and the computer program can be executed by a processor to implement each step of the method for realizing synchronous processing of multiple ADC data based on FPGA as described above.

[0013] The method, device, processor and computer-readable storage medium for realizing synchronous processing of multi-channel ADC data based on FPGA of the present invention use the enable signals EN_start and EN_end to control the synchronous start and stop of the processing flow, ensure the synchronous processing of multi-channel ADC data, improve the accuracy and effectiveness, and have a wide range of applications. Description of the Drawings

[0014] Figure 1 It is a schematic diagram of a common circuit structure for the method of realizing synchronous processing of multi-channel ADC data based on FPGA of the present invention.

[0015] Figure 2 It is a schematic diagram of the main processing flow of the internal signals of FPGA for the method of realizing synchronous processing of multi-channel ADC data based on FPGA of the present invention. Detailed Embodiments

[0016] In order to more clearly describe the technical content of the present invention, the following will be further described in conjunction with specific embodiments.

[0017] The method of realizing synchronous processing of multi-channel ADC data based on FPGA of the present invention includes the following steps: (1) The FPGA receives the clock frequency generated by an external clock generator and uses it as the working clock of the FPGA. (2) The FPGA internally generates multiple groups of co-frequency clocks and in-phase clocks, which are respectively used as the working clocks of each ADC chip. (3) The FPGA receives the sampling data of each ADC, sets an enable signal EN_start, and when the enable signal EN_start is valid, performs digital down-conversion, decimation filtering, and FIR filtering on the sampling data of each channel respectively. (4) After the FIR filtering is completed, the FPGA generates another enable signal EN_end for a single ADC chip to further store the data or transmit it to the host computer.

[0018] As a preferred embodiment of the present invention, step (3) specifically includes the following steps: (3.1) The FPGA receives the sampling data of each ADC, sets an enable signal EN_start, and when the enable signal EN_start is valid, performs digital down-conversion processing on the sampling data of each channel respectively. (3.2) After the digital down-conversion processing is completed, decimation filtering is performed on the data. (3.3) After the decimation filtering is completed, the data is filtered through an FIR filter.

[0019] As a preferred embodiment of the present invention, step (4) further includes the following steps: (4.1) After the FIR filtering is completed, the FPGA generates an enable signal EN_end 1, EN_end 2,..., EN_end n-1, EN_end n for each ADC chip respectively, where n is an integer greater than 0, and performs a logical AND operation on the enable signals of all multiple ADC chips to obtain a new enable signal EN; (4.2) If the enable signal EN is valid, the data of each processed ADC chip is stored or transmitted to the host computer in a set order.

[0020] As a preferred embodiment of the present invention, the operating clock frequencies and phases of all the ADC chips are the same and in phase, and the sampled data of all the ADC chips are in a synchronous state.

[0021] As a preferred embodiment of the present invention, in step (3), the operating clock of the ADC chip is kept consistent with the operating clock of the FPGA that processes the sampled data of this ADC chip.

[0022] The device for realizing synchronous processing of multiple ADC data based on FPGA of the present invention, wherein the device includes: A processor configured to execute computer-executable instructions; A memory storing one or more computer-executable instructions, and when the computer-executable instructions are executed by the processor, each step of the method for realizing synchronous processing of multiple ADC data based on FPGA as described above is implemented.

[0023] The processor for realizing synchronous processing of multiple ADC data based on FPGA of the present invention, wherein the processor is configured to execute computer-executable instructions, and when the computer-executable instructions are executed by the processor, each step of the method for realizing synchronous processing of multiple ADC data based on FPGA as described above is implemented.

[0024] The computer-readable storage medium of the present invention, on which a computer program is stored, and the computer program can be executed by a processor to implement each step of the method for realizing synchronous processing of multiple ADC data based on FPGA as described above.

[0025] In view of the limitations and accuracy of the above existing solutions, the present invention proposes a method for synchronous processing of multiple ADC data based on FPGA, including the following steps: Step 1: An external clock generator generates a stable clock frequency that meets the requirements as the operating clock of the FPGA.

[0026] Step 2: Generate multiple groups of clocks CLK1, CLK2, ……, CLKn-1, CLKn with the same frequency and phase inside the FPGA, and use them as the working clocks for each ADC chip respectively.

[0027] Step 3: Since the working clock frequencies and phases of each ADC chip are exactly the same, the sampled data DATA 1, DATA 2, ……, DATA n-1, DATA n of each ADC are also in a synchronous state. After the FPGA receives the sampled data of each ADC, before processing, set an enable signal EN_start. When the enable signal EN_start is valid, perform digital down-conversion processing on the sampled data of each path respectively. The main purpose of digital down-conversion is to convert high-frequency signals into low-frequency baseband signals, multiply the input signal by the quadrature local oscillator signal generated by the local oscillator (NCO), and filter out the high-frequency components generated by mixing, etc.

[0028] Step 4: After the digital down-conversion processing is completed, continue to perform decimation filtering on the data. Decimation filtering is widely used in digital down-conversion processing systems. It can not only further filter the signal after digital down-conversion, but also reduce the data volume by decimation to achieve the purpose of downsampling.

[0029] Step 5: After the decimation filtering is completed, continue to perform FIR filtering on the data. FIR filtering refers to filtering through an FIR filter. The FIR filter is the abbreviation of a non-recursive filter, also called a finite impulse response filter. An FIR filter with constant coefficients is a type of LTI (linear time-invariant) digital filter. The relationship between the output of an FIR of length N and the input time series x(n) is given in the form of a finite convolution sum, and the specific form is as follows: ; where y(k) is the output signal at the k-th moment, N is the filter order, a(n) is the n-th coefficient of the filter, there are N coefficients in total, and x(k - n) is the input signal at the k - n-th moment, that is, the input signal is delayed by n sampling points.

[0030] It should be particularly noted that the clock used for the above-related operations on the sampled data of each path should be consistent with the working clock of the corresponding ADC chip. The clock used for the above-related operations on the sampled data of each path refers to the multiple groups of clocks CLK1, CLK2, ……, CLKn-1, CLKn with the same frequency and phase generated inside the FPGA in Step 2.

[0031] Step 6: After the FIR filtering is completed, another enable signal EN_end will be generated, indicating the end of the above series of processing processes. The relevant data can be further stored or transmitted to the host computer. The relevant data here includes the amplitude value and phase value after calculation and conversion.

[0032] Step 7: In the above Steps 3 to 6, only a series of operations for single-channel ADC sampled data are described. For multi-channel ADCs, an enable signal EN_end will be generated for each channel.

[0033] (7.1) Before further storing the relevant data or transmitting it to the host computer, perform a logical AND operation on the enable signals EN_end 1, EN_end 2, ……, EN_end n-1, EN_end n of all channels to obtain a new enable signal EN, which is used as the valid enable bit for subsequent operations.

[0034] (7.2) When the enable signal EN is valid, store or transmit the processed data of each channel to the host computer in the set order.

[0035] The FPGA of the present invention internally generates multiple groups of clocks with the same frequency and in the same phase, which are respectively used as the working clocks of each ADC chip. The FPGA internally needs to perform constraint processing on each clock to ensure that the delay paths of each clock are consistent, so that each ADC chip can work simultaneously.

[0036] In the specific implementation manner of the present invention, as Figure 1 shown, an external clock generator generates a stable clock frequency that meets the requirements and connects it to the clock pin of the FPGA as the working clock of the FPGA. Multiple groups of clocks with the same frequency and in the same phase are internally generated by the FPGA and are respectively connected to the clock pins of each ADC chip as the working clocks of each ADC chip. Of course, the power supply circuit, drive circuit, etc. required for the operation of the external clock generator and the FPGA are also essential. Since they are not the focus of this case, they are omitted. After each ADC chip works normally, it outputs the sampled data to the FPGA.

[0037] As Figure 2As shown, the FPGA receives the sampled data from each ADC. Before processing, an enable signal EN_start is set. When the enable signal is valid, subsequent digital down-conversion, decimation filtering, FIR filtering, and other series of processing are performed on the sampled data of each channel. It should be particularly noted that the clock used for performing relevant operations on the sampled data of each channel should be consistent with the working clock of the ADC chip of that channel. After the FIR filtering is completed, the FPGA generates another enable signal EN_end, indicating the end of the above series of processing, and the relevant data can be further stored or transmitted to the host computer. In the above steps, only the series of operations on the sampled data of a single-channel ADC are described. For multiple-channel ADCs, an enable signal EN_end is generated for each channel. Before further storing or transmitting the relevant data to the host computer, a logical AND operation is first performed on the enable signals EN_end1, EN_end 2,..., EN_end n-1, EN_end n generated by all channels to obtain the final enable signal EN, which is used as the enable valid bit for subsequent operations. When the enable is valid, the relevant data is stored or transmitted to the host computer in the set order.

[0038] The FPGA can generate multiple output clocks simultaneously inside, and each clock can be output simultaneously. By setting each output clock to the same frequency and the same phase, the working clocks can be kept consistent. Before outputting each clock to the ADC chips of each channel, constraint processing is performed on each clock inside the FPGA. The purpose is to ensure that the delay paths of each clock are the same, so that each ADC chip can receive the clock signal simultaneously and thus work properly simultaneously. Each ADC chip starts working at the same moment, with the same working frequency, and the output sampled data is in a synchronous state.

[0039] In the specification of this application, the full English name of ADC is Analog to Digital Converter, and the full Chinese name is Analog-to-Digital Converter. The full English name of FIR is Finite Impulse Response, and the full Chinese name is Finite Impulse Response. The full English name of FPGA is Field Programmable Gate Array, and the full Chinese name is Field Programmable Gate Array.

[0040] For the specific implementation solution of this embodiment, reference can be made to the relevant descriptions in the above embodiments, and details are not repeated here.

[0041] It can be understood that the same or similar parts in the above embodiments can be referred to each other, and the content not described in detail in some embodiments can be referred to the same or similar content in other embodiments.

[0042] It should be noted that in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "a plurality of" refers to at least two.

[0043] Any process or method description shown in a flowchart or described otherwise herein can be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a specific logical function or process. The scope of the preferred embodiments of the present invention includes additional implementations, where functions may be executed in a substantially simultaneous manner or in a reverse order according to the involved functions, rather than in the order shown or discussed, which should be understood by those skilled in the art to which the embodiments of the present invention pertain.

[0044] It should be understood that various parts of the present invention can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution device. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0045] Those of ordinary skill in the art of the present technology can understand that all or part of the steps carried by the methods of the above embodiments can be completed by instructing relevant hardware through a program, and the corresponding program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0046] In addition, each functional unit in various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically alone, or two or more units can be integrated into a module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0047] The above-mentioned storage medium can be a read-only memory, a magnetic disk, an optical disk, etc.

[0048] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0049] The method, device, processor, and computer-readable storage medium for implementing multi-channel ADC data synchronous processing based on FPGA of the present invention are adopted. By enabling signals EN_start and EN_end to control the synchronous start and stop of the processing flow, it ensures the synchronous processing of multi-channel ADC data, improves accuracy and effectiveness, and has a wide range of applications.

[0050] In this specification, the present invention has been described with reference to its specific embodiments. However, it is obvious that various modifications and transformations can still be made without departing from the spirit and scope of the present invention. Therefore, the specification and the drawings should be regarded as illustrative rather than restrictive.

Claims

1. A method for realizing multi-channel ADC data synchronous processing based on FPGA, characterized in that The method described above includes the following steps: (1) The FPGA receives the clock frequency generated by an external clock generator and uses it as the working clock of the FPGA; (2) Multiple groups of clocks with the same frequency and in-phase clocks are generated inside the FPGA and used as the working clocks of each ADC chip respectively; (3) The FPGA receives the sampled data of each ADC, sets an enable signal EN_start, and when the enable signal EN_start is valid, performs digital down-conversion, decimation filtering, and FIR filtering on the sampled data of each path respectively; (4) After the FIR filtering is completed, the FPGA generates another enable signal EN_end for a single ADC chip to further store the data or transfer it to the host computer.

2. The method for realizing multi-channel ADC data synchronization processing based on FPGA according to claim 1, wherein The specific steps of step (3) include the following steps: (3.1) The FPGA receives the sampled data of each ADC, sets an enable signal EN_start, and when the enable signal EN_start is valid, performs digital down-conversion on the sampled data of each path respectively; (3.2) After the digital down-conversion is completed, decimation filtering is performed on the data; (3.3) After the decimation filtering is completed, the data is filtered through an FIR filter.

3. The method for realizing multi-channel ADC data synchronization processing based on FPGA according to claim 1, characterized in that The steps of step (4) also include the following steps: (4.1) After the FIR filtering is completed, the FPGA generates an enable signal EN_end 1, EN_end 2,..., EN_end n-1, EN_end n for each ADC chip respectively, where n is an integer greater than 0, and performs a logical AND operation on the enable signals of all multiple ADC chips to obtain a new enable signal EN; (4.2) If the enable signal EN is valid, the data of each ADC chip after processing is stored or transferred to the host computer in the set order.

4. The method for realizing multi-channel ADC data synchronization processing based on FPGA according to claim 1, wherein, The working clock frequencies and phases of each ADC chip are the same and in-phase, and the sampled data of each ADC chip is in a synchronous state.

5. The method for realizing multi-channel ADC data synchronous processing based on FPGA according to claim 1, wherein In step (3), the working clock of the ADC chip is consistent with the working clock of the FPGA that processes the sampled data of this ADC chip.

6. A device for realizing multi-channel ADC data synchronous processing based on FPGA, characterized in that, The device described above includes: A processor configured to execute computer-executable instructions; A memory storing one or more computer-executable instructions, and when the computer-executable instructions are executed by the processor, the various steps of the method for realizing multi-channel ADC data synchronous processing based on FPGA described in any one of claims 1 to 5 are realized.

7. A processor for realizing multi-channel ADC data synchronous processing based on FPGA, characterized in that, The processor is configured to execute computer-executable instructions, and when the computer-executable instructions are executed by the processor, the various steps of the method for realizing multi-channel ADC data synchronous processing based on FPGA described in any one of claims 1 to 5 are realized.

8. A computer-readable storage medium, characterized in that, A computer program is stored thereon, and the computer program can be executed by the processor to realize the various steps of the method for realizing multi-channel ADC data synchronous processing based on FPGA described in any one of claims 1 to 5.

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