System and method for managing memory devices

Abstract

A memory device and a method for managing a memory device are disclosed. The memory device may include a controller, a first non-volatile memory (NVM) device, and a second NVM device. The controller may be configured to: detect a first condition; setting the first NVM device to operate in a first mode of operation and the second NVM device to operate in a second mode of operation based on a first condition; receiving a request from a computing device; and selecting one of a first NVM device and a second NVM device based on the request being one of a first type and a second type, respectively, where the first NVM device is configured to take a first action according to a first mode of operation and the second NVM device is configured to take a second action according to a second mode of operation.

Description

[0001] This application claims priority and the benefit of U.S. Provisional Application No. 63 / 623,627, entitled "METHOD FOR LATENCY REDUCTION IN COMPUTE EXPRESS LINK (CXL) BASED TIERED MEMORY USING DUAL BACK-END SSDS", filed on January 22, 2024, and U.S. Application No. 18 / 630,731, filed on April 9, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] One or more aspects in accordance with embodiments of the present disclosure relate to memory devices, and more particularly, to systems and methods for managing memory devices. Background Art

[0003] Applications running on a host computing device may need to read and write data to memory. As the amount of data read and written to memory increases, the need for storage devices and memory, and for efficiently accessing the storage devices and memory, may also increase.

[0004] The above information disclosed in this background art section is only for enhancing the understanding of the background of the present disclosure, and thus, it may contain information that does not form the prior art. Summary of the Invention

[0005] Embodiments of the present disclosure are directed to an apparatus that includes: a controller, a first non-volatile memory (NVM) device, and a second NVM device. The controller is configured to: detect a first condition; based on the first condition, set the first NVM device to operate in a first operation mode and set the second NVM device to operate in a second operation mode; receive a request from a computing device; and select one of the first NVM device or the second NVM device based on whether the request is of a first type or a second type, wherein the first NVM device is configured to take a first action according to the first operation mode, and the second NVM device is configured to take a second action according to the second operation mode.

[0006] In some embodiments, the first condition includes at least one of expiration of a time period, loss of power, or a command from the computing device.

[0007] In some embodiments, the first type includes write requests, and the second type includes read requests.

[0008] In some embodiments, the apparatus further includes a first memory device and a second memory device, and the controller is further configured to: determine that the request is for writing first data; and based on the request: identify second data in the first memory device; determine that the first NVM device is set to a write operation mode; write the second data to the second memory device and the first NVM device; and store the first data in the first memory device.

[0009] In some embodiments, the controller is further configured to: receive a second request for reading first data; and based on the second request: generate a first command for obtaining the first data from the first memory device and detect a first result; based on the first result, generate a second command for obtaining the first data from the second memory device and detect a second result; determine that the second NVM device is set to a read operation mode; and based on the second result, generate a command for obtaining the first data from the second NVM device.

[0010] In some embodiments, the controller is further configured to: detect a second condition; based on detecting the second condition, the controller is further configured to: determine that the second NVM device is set to a read operation mode; based on the second NVM device being set to the read operation mode, store the second data in the second memory device to the second NVM device; and set the first NVM device to the read operation mode and set the second NVM device to the write operation mode.

[0011] In some embodiments, the apparatus further includes a memory device, wherein the controller is further configured to: detect a second condition; based on detecting the second condition, the controller is further configured to: set the first NVM device and the second NVM device to operate in a first operation mode.

[0012] In some embodiments, the second condition includes a loss of power to the apparatus, and the first operation mode includes a write mode, wherein the controller is further configured to: read the first data and the second data stored in the memory device; and store the first data in the first NVM device and store the second data in the second NVM device.

[0013] In some embodiments, the second condition includes detecting power to the apparatus, and the first operation mode includes a read mode, wherein the controller is further configured to: identify the first data in the first NVM device and the second data in the second NVM device; read the first data and the second data from the first NVM device and the second NVM device, respectively; and store the first data and the second data in the memory device.

[0014] In some embodiments, the process in which the controller is configured to set a first NVM device to operate in a first operation mode and set a second NVM device to operate in a second operation mode further includes: the controller is configured to: set a first value for identifying the first operation mode for the first NVM device and a second value for identifying the second operation mode for the second NVM device in the memory.

[0015] One or more embodiments of the present disclosure also relate to a method, the method including: detecting, by a controller of a storage device, a first condition; based on the first condition, setting, by the controller, a first non-volatile memory (NVM) device to operate in a first operation mode and setting a second NVM device to operate in a second operation mode; receiving, by the controller, a request from a computing device; and selecting, based on whether the request is one of a first type or a second type, one of the first NVM device or the second NVM device, wherein the first NVM device is configured to take a first action according to the first operation mode, and the second NVM device is configured to take a second action according to the second operation mode.

[0016] These and other features, aspects, and advantages of the embodiments of the present disclosure will be more fully understood when considered in connection with the following detailed description, the appended claims, and the drawings. Of course, the actual scope of the invention is defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The non-limiting and non-exhaustive embodiments of the present embodiment are described with reference to the following drawings, in which, unless otherwise specified, the same reference numerals represent the same components throughout the various views.

[0018] Figure 1 A block diagram depicting a computing system according to one or more embodiments.

[0019] Figure 2 A block diagram depicting a memory device according to one or more embodiments.

[0020] Figure 3 A block diagram depicting a storage controller according to one or more embodiments.

[0021] Figure 4 A layout diagram depicting example operation bits stored by a command mode generator according to one or more embodiments.

[0022] Figure 5 A flowchart depicting a process for controlling an operation mode of a non-volatile memory (NVM) and processing a host memory access request based on the operation mode of the NVM according to one or more embodiments.

[0023] Figure 6A flowchart depicting a process for handling memory access requests according to one or more embodiments.

[0024] Figure 7 A flowchart depicting a process for setting an operation mode of one or more non-volatile memories (NVMs) according to one or more embodiments. DETAILED DESCRIPTION

[0025] Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings, in which like reference numerals always denote like elements. However, the present disclosure may be implemented in various different forms and should not be construed as limited to the embodiments shown herein. Instead, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise stated, like reference numerals denote like elements throughout the drawings and the written description, and thus, their description may not be repeated. Further, in the drawings, relative dimensions of elements, layers, and regions may be exaggerated and / or simplified for clarity.

[0026] Embodiments of the present disclosure are described below with reference to block diagrams and flowcharts. Accordingly, it should be understood that each block of the block diagrams and flowcharts can be implemented in the form of a computer program product, a fully hardware embodiment, a combination of hardware and a computer program product, and / or a device, system, computing device, computing entity, etc. that executes instructions, operations, steps, and similar words that can be used interchangeably (e.g., executable instructions, instructions for execution, program code, etc.) on a computer-readable storage medium for execution. For example, the obtaining, loading, and execution of code can be performed sequentially such that one instruction is obtained, loaded, and executed once. In some example embodiments, the obtaining, loading, and / or execution can be performed in parallel such that multiple instructions are obtained, loaded, and / or executed together. Thus, such embodiments can produce a specially configured machine that executes the steps or operations specified in the block diagrams and flowcharts. Accordingly, the block diagrams and flowcharts support various combinations of embodiments for executing the specified instructions, operations, or steps.

[0027] Applications generally require fast, stable, and predictable storage. As the amount of data processed by an application increases, the need for fast data acquisition and storage may also increase. Certain types of memories, such as dynamic random access memory (DRAM), can provide appropriate speed, but their high cost may reduce their use as the sole storage device in a computing system.

[0028] Other types of storage media, such as solid state drives (SSDs), provide a compromise between speed and affordability. However, the performance of an SSD can vary significantly based on the type of workload. For example, an SSD can excel at quickly reading and delivering small files, but their performance can degrade in scenarios that require handling a mix of intensive read and write operations. Unpredictable performance can pose challenges to applications that rely on consistent data access latency. This challenge can become even more pronounced when an SSD is used as a memory tiering device, especially when accessed via a high-speed interface such as Compute Express Link (CXL). Thus, it can be desirable to have a storage solution that provides a balance among affordability, speed, and reliability as applications continue to evolve in complexity and requirements.

[0029] Generally, embodiments of the present disclosure are directed to a storage device that uses multiple types of storage devices for providing memory tiering. In some embodiments, the storage device includes a hybrid of volatile memory (e.g., DRAM) and two or more non-volatile memories (NVMs) (e.g., SSDs). Read requests and write requests to the NVMs can be separated by directing read requests to a first NVM and write requests to a different second NVM. The read requests can be serviced by the first NVM that has a predictable read-only throughput latency. Because the write requests are serviced by a different NVM, additional latency may not be added to the processing of the read requests, which may otherwise be added when the same NVM services both read and write traffic. Thus, even in a mixed traffic scenario, an application may be able to access data from a storage device with predictable performance.

[0030] Figure 1 A block diagram depicting a computing system (or system) in accordance with one or more embodiments. The system includes a host computing device (referred to as the “host”) 100 coupled to one or more endpoints, such as, by way of example, one or more memory devices 102a through 102c (collectively referred to as 102).

[0031] The host 100 includes, without limitation, a processor (e.g., a central processing unit (CPU)) 105, a main memory 104, a memory management unit (MMU 108), and a root complex (RC) interface (or root complex) 112. The processor 105 may include one or more CPU cores 116 configured to execute computer program instructions and process data stored in a cache memory (abbreviated as "memory" or "cache") 118. The cache 118 may be dedicated to one of the CPU cores 116 or shared by each of the CPU cores. It should be understood that although a CPU is used to describe various embodiments, those skilled in the art will recognize that a graphics processing unit (GPU) or other computing unit may be used instead, or in addition to the CPU.

[0032] The cache 118 may be coupled to a memory controller 120, which in turn is coupled to the main memory 104. The main memory 104 may include, for example, a dynamic random access memory (DRAM) that stores computer program instructions and / or other types of data (collectively referred to as data) provided by the memory device 102. To enable a CPU core 116 to execute an instruction or obtain data provided by the memory device 102, the corresponding data may be loaded into the cache memory 118, and the CPU core may consume (e.g., directly) the data from the cache. If the data to be consumed is not yet in the cache, a cache miss may occur, and the memory device 102 may need to be queried to load the data. For example, if the data to be consumed is not in the cache 118, the cache miss logic may query the data from the memory (e.g., the main memory (e.g., DRAM) 104 or the memory device 102) based on the mapped virtual address or physical address.

[0033] In some embodiments, the processor 105 (e.g., an application running on the processor) generates a data access request to the memory device 102. One or more of the data access requests may include a virtual memory address for the location to write or read data. The processor 105 may invoke the MMU 108 to translate the virtual address into a physical address to process the request. The MMU 108 may include a translation table 110 that maps the virtual address to the physical address. The request sent to the memory device 102 to fulfill the data access request may include the physical address corresponding to the virtual address.

[0034] In some embodiments, host 100 exchanges signals or messages with memory device 102 via RC interface 112 and interface connections 106a - 106c (collectively referred to as 106). For example, host 100 may send requests (e.g., load requests or store requests) via RC interface 112 and interface connections 106 to read data from or write data to memory device 102. Messages from memory device 102 to host 100 (such as, for example, in response to a request from the host) may be delivered via interface connections 106 to RC interface 112, which in turn delivers the response to processor 105. Host 100 and memory device 102 may also exchange signals including, for example, specific types of notifications or configuration commands via RC interface 112 and interface connections 106.

[0035] In some embodiments, interface connection 106 (e.g., the connector and its protocol) includes a memory expansion bus (such as, for example, Compute Express Link (CXL)), but the embodiments are not limited thereto. For example, interface connection 106 (e.g., the connector and its protocol) may also include a general - purpose interface (such as, for example, Ethernet, Universal Serial Bus (USB), etc.). In some embodiments, interface connection 106 may include (or conform to) Cache - Coherent Interconnect for Accelerators (CCIX), Dual In - line Memory Module (DIMM) interface, Small Computer System Interface (SCSI), Non - Volatile Memory Express (NVMe), Peripheral Component Interconnect Express (PCIe), Remote Direct Memory Access over Ethernet (RDMA), Serial ATA (SATA), Fibre Channel, Serial Attached SCSI (SAS), NVMe over Fabrics (NVMe - oF), iWARP protocol, InfiniBand protocol, 5G wireless protocol, Wi - Fi protocol, Bluetooth protocol, etc.

[0036] RC interface 112 may be, for example, a PCIe interface configured to implement a root complex for connecting processor 105 and main memory 104 to memory device 102. RC interface 112 may include one or more ports (RPs) 114a - 114c to connect one or more memory devices 102 to the RC. In some embodiments, MMU 108 and / or translation table 110 may be integrated into RC interface 112 to allow address translation to be implemented by the RC interface.

[0037] The memory device 102 may include one or more of volatile computer-readable storage media and / or non-volatile computer-readable storage media. In some embodiments, one or more of the memory devices 102 include memory attached to a CPU or GPU (such as, by way of example, a memory device attached with CXL (including volatile memory devices and persistent memory devices), a memory device attached with RDMA, etc.), but the embodiments are not limited thereto. The memory device attached with CXL (abbreviated as CXL memory) may follow the CXL.mem protocol that "the host 100 can access the memory using commands such as load commands and store commands". In this regard, the host 100 may act as a requester and the CXL memory may act as a subordinate.

[0038] In some embodiments, the memory device 102 is included in a memory system that allows memory tiering to provide an appropriate cost or performance profile. In this regard, different types of storage media may be organized in a memory hierarchy or tier based on the characteristics of the storage media. The characteristic may be access latency. In some embodiments, the hierarchy or level of the memory device increases as the access latency decreases.

[0039] In some embodiments, one or more of the memory devices 102 are the same or different types of memory devices aggregated into a storage pool. For example, the storage pool may include one or more memory devices attached to a CPU or GPU.

[0040] Figure 2 A block diagram depicting the memory device 102 according to one or more embodiments. In some embodiments, the memory device 102 includes a storage controller (or controller) 200, a storage memory (or memory) 202, and two or more non-volatile memories (NVMs) 204a to 204c (NVM1 to NVM n)(collectively referred to as 204). The storage memory 202 can be a high-performance memory of the memory device 102 and can include (or can be) volatile memory (e.g., such as DRAM), but the present disclosure is not limited thereto, and the storage memory 202 can be any suitable type of high-performance volatile or non-volatile memory (such as, by way of example, random access memory (RAM), static random access memory (SRAM), fast page mode dynamic random access memory (FPM DRAM), extended data output dynamic random access memory (EDO DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), double data rate type two synchronous dynamic random access memory (DDR2 SDRAM), double data rate type three synchronous dynamic random access memory (DDR3 SDRAM), Rambus dynamic random access memory (RDRAM), two-transistor RAM (TTRAM), thyristor RAM (T-RAM), zero-capacitor RAM (Z-RAM), Rambus in-line memory module (RIMM), dual in-line memory module (DIMM), single in-line memory module (SIMM), video random access memory (VRAM), cache memory (including various levels), flash memory, register memory, etc.).

[0041] In some embodiments, the storage memory 202 is used and managed as a cache memory. In this regard, the storage memory 202 can store copies of at least some of the data stored in the NVM 204. In some embodiments, the storage memory 202 has a lower access latency than the NVM 204. Thus, in some embodiments, accessing data from the storage memory 202 helps improve overall system performance and responsiveness.

[0042] The NVM 204 can persistently store, for example, data obtained from the host 100. The NVM 204 can take the form of, for example, an SSD, but the present disclosure is not limited thereto, and the NVM 204 can include any suitable type of memory for persistently storing data (such as, by way of example, floppy disks, flexible disks, hard disks, solid state cards (SSC), solid state modules (SSM), enterprise flash drives, magnetic tapes, or any other non-transitory magnetic media, etc.). In some embodiments, one or more of the NVM 204 can include punched cards, paper tapes, optical mark sheets (or any other physical media having a pattern of holes or other optically recognizable marks), compact disc read-only memory (CD-ROM), rewritable compact disc (CD-RW), digital versatile disc (DVD), Blu-ray disc (BD), any other non-transitory optical media, etc.).

[0043] The storage controller 200 can be connected to the NVM 204 and the storage memory 202 through one or more storage interfaces 206a to 206d. The storage controller 200 can receive memory access requests (e.g., load requests or store requests) from the host 100, and send appropriate commands to the NVM 204 and / or the storage memory 202 and receive appropriate commands from the NVM 204 and / or the storage memory 202 to fulfill or service I / O requests. In this regard, the storage controller 200 can include at least one processing component embedded therein for interfacing with the host 100, the storage memory 202, and the NVM 204. The processing component can include, for example, digital circuits (e.g., microcontrollers, microprocessors, digital signal processors, or logic devices (e.g., field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), etc.)) capable of (e.g., via firmware and / or software) executing data access instructions to provide access to data stored in the storage memory 202 or the NVM 204 and access from data stored in the storage memory 202 or the NVM 204.

[0044] In some embodiments, the NVM 204 is configured to operate according to the operation mode to which the NVM is set. The operation mode can be one of a read mode and a write mode. For example, if the NVM 204 (hereinafter referred to as the "read NVM") is set to operate in the read operation mode, the NVM can service (e.g., only service) read requests. If the NVM 204 (hereinafter referred to as the "write NVM") is set to operate in the write operation mode, the NVM can service (e.g., only service) write requests. In this way, a given NVM can service read requests or write requests (but not both) at a given time, thus avoiding read / write conflicts in the given NVM. The NVM 204 can alternate between the read operation mode and the write operation mode based on a predefined policy.

[0045] Figure 3 A block diagram depicting the storage controller 200 according to one or more embodiments. In some embodiments, the storage controller 200 includes a communication endpoint (or endpoints) 300 for interfacing with the host 100. The communication endpoint 300 can include a physical connection and an associated protocol (e.g., CXL) that allows the memory device 102 to exchange data with the host 100.

[0046] In some embodiments, the storage controller 200 further includes a device cache controller (or cache controller) 302, a memory controller 304, a data manager 306, and an NVM controller 308. Although the various controllers 302, 304, 308, and data manager 306 (collectively referred to as control components) are assumed to be separate functional units, those skilled in the art will recognize that, without departing from the spirit and scope of the inventive concept, the functions of the control components may be combined or integrated into a single component, or further subdivided into additional sub-components.

[0047] In some embodiments, the device cache controller 302 is aware of the cache architecture utilized by the storage memory 202 and may use information for managing storing data in and evicting data from the memory. For example, the device cache controller 302 may process a memory access request received from the host 100 via the communication endpoint 300 and generate a cache address for the requested physical address. The device cache controller 302 may also determine whether the request results in a cache hit or a cache miss. Additionally, the device cache controller 302 may monitor the fullness of the storage memory 202 and, if the storage memory 202 has reached a threshold fullness level, identify and evict entries from the memory according to a configured cache algorithm (e.g., a cache replacement policy).

[0048] In some embodiments, the device cache controller 302 passes relevant data to the data manager 306 to service a memory access command from the storage memory 202 or the NVM 204. For example, in the case where the data requested by the host 100 is found in the storage memory 202 (e.g., a cache hit), the device cache controller 302 may pass the cache address to the data manager 306 to access the data from the storage memory 202. In some embodiments, the data manager 306 may communicate with the memory controller 304 to obtain the data from the cache address.

[0049] In the case where the data requested by the host 100 is not located in the storage memory 202 (e.g., a cache miss), the device cache controller 302 may pass to the data manager 306 the address of the NVM 204 from which the data will be obtained. In some embodiments, the data manager 306 communicates with the NVM controller 308 to read the requested data from the NVM 204.

[0050] In some embodiments, the device cache controller 302 identifies entries in the storage memory 202 to be evicted to the NVM 204. Data eviction may be performed when the storage memory 202 has reached a threshold fullness level and data identified in a storage request from the host 100 cannot be saved in the storage memory 202. In such a case, the device cache controller 302 may pass the cache address of the data to be evicted to the data manager 306. The data manager 306 may communicate with the NVM controller 308 to write the data to be evicted to the NVM 204. Depending on the write policy (e.g., write through policy, write back policy, etc.) employed by the device cache controller 302, the data manager 306 may or may not generate an additional write request to the NVM controller 308 for writing the data identified by the storage request.

[0051] In some embodiments, the NVM controller 308 interfaces with the NVM 204 according to a storage access protocol (such as, by way of example, the Non-Volatile Memory Express (NVMe) protocol), but embodiments are not limited thereto. In this regard, the NVM controller 308 may include a command submission controller 310, a first interface 312a for a first NVM (or first NVM device) 204a, and a second interface 312b for a second NVM (or second NVM device) 204b. Of course, if the memory device 102 includes additional NVMs, the NVM controller 308 may include additional interfaces.

[0052] In some embodiments, the command submission controller 310 is configured to generate read commands and write commands (e.g., NVMe read commands and NVMe write commands) based on the information provided by the data manager 306. For example, the generated read command may include the address of the data to be retrieved from the NVM 204 and the address in the storage memory 202 to which the retrieved data is to be returned. The generated write command may include the address of the NVM 204 to which the data is to be written and the address in the storage memory 202 where the data to be written is stored.

[0053] The command submission controller 310 may provide the read commands and write commands to the appropriate interfaces 312a, 312b (collectively referred to as 312) based on the operating mode of the NVM 204. For example, the command submission controller 310 may provide the read command to the first interface 312a for the first NVM 204a when it detects that the first NVM 204a is set to read the NVM, and provide the write command to the second interface 312b for the second NVM 204b when it detects that the second NVM 204b is set to write to the NVM.

[0054] In some embodiments, interface 312 includes one or more queues including, for example, a submission queue, a completion queue, etc. In an example where the first NVM 204a is set to read the NVM, the command submission controller 310 may place a read command in the submission queue of the first interface 312a. The first NVM 204a may obtain the read command from the submission queue and service the read command by obtaining the requested data from the identified memory location of the first NVM 204a and by storing the obtained data in the identified memory location of the storage memory 202.

[0055] In an example where the second NVM 204b is set to write to the NVM, the command submission controller 310 may place a write command in the submission queue of the second interface 312b. The second NVM 204b may obtain the write command from the submission queue and service the write command by obtaining the requested data from the identified memory location of the storage memory 202 and by writing the data to the identified memory location of the second NVM 204b.

[0056] In some embodiments, the storage controller 200 includes a buffer 316 for temporarily storing data that has not yet been submitted to the read NVM (e.g., NVM 204a). In this regard, the data identified in a write request is written to both the buffer 316 and the NVM (e.g., NVM 204b). When a change in the operation mode (e.g., a transition from reading the NVM to writing to the NVM) is detected for the read NVM, all or a portion of the data stored in the buffer 316 is stored to the read NVM. That is, the buffer 316 may be flushed to a set level. In this way, when the NVM is in a read operation mode, the two NVMs may store at least some of the same data and service read requests for that data.

[0057] In some embodiments, the data stored in the buffer 316 is marked to indicate whether the data is written to one NVM or two. When the data is written to two NVMs, the memory location storing the data may be released to make room for new data.

[0058] In some embodiments, if the requested data is temporarily stored in the buffer, the host read request is serviced from the buffer 316. If the buffer does not contain the requested data, the request may be serviced from the read NVM.

[0059] In some embodiments, the operating mode of the NVM 204 is set by the command mode generator 314. The command mode generator 314 may use one or more policies to set the operating mode. One policy may be a time-based policy. Under the time-based policy, the command mode generator 314 may initially set one or more NVMs to the read operating mode and set one or more other NVMs to the write operating mode. In some embodiments, all NVMs are set to one operating mode. For example, all NVMs may be set to the read operating mode upon power-up. In some embodiments, the NVM alternates between the read operating mode and the write operating mode at a given time interval. For example, every 100 ms, the read NVM (e.g., NVM 204a) may switch to the write operating mode, and the write NVM (e.g., NVM 204b) may switch to the read operating mode.

[0060] In some embodiments, the policy may use the state of the memory device 102 to trigger a transition of the memory device 102 from one operating mode to another. For example, the fullness of the buffer 316 may trigger a switch to allow flushing the buffer into the read NVM. In this regard, the policy may set a threshold fullness of the buffer 316 that is to be met before the switch is triggered.

[0061] In some embodiments, the state of the memory device 102 may be a loss (or expected loss) of power or a restoration of power to the memory device 102. For example, in a persistent memory operation, the policy may trigger all of a portion of the NVM 204 to be set in the write operating mode in response to determining a loss of power or an expected loss of power. The multiple NVMs 204 in the write operating mode may allow data stored in the storage memory 202 to be moved to the NVM at an increased write bandwidth before an actual loss of power. When power is restored to the memory device 102, the policy may trigger all or a portion of the NVM 204 to be set in the read operating mode. The multiple NVMs 204 in the read operating mode may allow the storage memory 202 to be populated at an increased read bandwidth.

[0062] In some embodiments, the switching of the operation mode of the NVM 204 is controlled or suggested by the host 100. In this regard, the host may store a policy for determining when the switching should occur. For example, the policy may be based on the state of an application that issues read requests and write requests to the memory device 102, the number of NVMs 204, etc. The policy may indicate a threshold ratio of read requests to write requests, and the threshold ratio may cause the operation mode of one or more NVMs 204 to switch from a write operation mode to a read operation mode, or vice versa. As an example, the policy may stipulate that if the read traffic is twice as much as the write traffic, then the operation mode of one or more NVMs 204 should be switched from the write operation mode to the read operation mode to increase the read bandwidth. The host 100 may send commands to the memory device 102 in the recommended operation mode. In some embodiments, the command mode generator 308 implements the recommended operation mode if, for example, there is no conflict with the local policy.

[0063] Figure 4 Depicts a layout diagram of an example operation bit 400 stored by the command mode generator 314 according to one or more embodiments. The command mode generator 314 may set the operation bit 400 to determine the operation mode of the NVM 204. In Figure 4 the example, the first bits 402a to 402c are set for the first NVM 204a, and the second bits 404a to 404c are set for the second NVM 204b. For example, a bit value of "0" may indicate that the NVM will be in the read mode (R) 406, and a bit value of "1" may indicate that the NVM will be in the write mode (W) 408. The NVM 204 may alternately operate in the operation mode periodically (e.g., on a regular or irregular basis). In some embodiments, the two NVMs 204 may be set to operate in the same operation mode (e.g., both in the read mode 410 as indicated by the associated operation bits 402a and 404a or both in the write mode 412 as indicated by the associated operation bits 402c and 404c).

[0064] Figure 5 Depicts a flowchart of a process for controlling the operation mode of the NVM and processing host memory access requests based on the operation mode. The process begins, and in operation 500, the storage controller 200 (e.g., the command mode generator 314) detects a first condition for setting or switching (collectively referred to as setting) the operation mode of one or more NVMs 204. The first condition may be identified in a policy followed by the command mode generator 314 to set the operation mode. The first condition may be, for example, the expiration of a time period, the detection of a threshold fullness of the buffer 316, the loss of power, the restoration of power, a command from the host, etc.

[0065] In operation 502, the operation mode of one or more NVM devices 204 is set based on the detected first condition. For example, the command mode generator 314 may set one or more operation bits 400 of the first NVM device and one or more operation bits 400 of the second NVM device based on the detected condition. In this regard, the first NVM device may be set to a first operation mode, and the second NVM device may be set to a second operation mode. The operation mode of the NVM device may be changed based on the detection of a second condition.

[0066] In operation 504, the memory controller 200 receives a memory access request from a computing device (e.g., host 100). The memory access request may be a request to read or write data.

[0067] In the case where the device cache controller 302 determines that access to the NVM 204 is needed to service the request (e.g., in the case of a cache miss), the data manager 306 sends a read command or a write command to the NVM controller 308. In operation 506, the NVM controller 308 selects one of the first NVM device or the second NVM device to service the memory access command from the host 100. In this regard, the command submission controller 310 may identify the operation mode of the first NVM device based on the operation mode set by the command mode generator 314, and select the first NVM device based on the memory access request having a first type (e.g., a write request). The first NVM device may be configured to respond to the memory access request according to the first operation mode (e.g., take a first action).

[0068] The command submission controller 310 may also identify the operation mode of the second NVM device based on the operation mode set by the command mode generator 314, and select the second NVM device based on the memory access request having a second type (e.g., a read request). The second NVM device may be configured to respond to the memory access request according to the second operation mode (e.g., take a second action).

[0069] Figure 6 A flowchart depicting a process for handling memory access requests according to one or more embodiments. For Figure 6 the purposes of the example, assume that: the request has been processed by the device cache controller 302 and the data manager 306, and when it is determined that the memory access request will be serviced by the NVM 204, a read command or a write command has been sent to the NVM controller 308.

[0070] Processing begins, and in operation 600, the NVM controller 308 determines whether it has received a write command. The write command may be the result of evicting data from the storage memory 202 to make room for new data to be written by the host. The data to be written to the NVM may be the evicted data. In some embodiments, in addition to being saved in the storage memory 202, the new data is also written to the NVM. In this embodiment, a second write command may be generated for the new data to be written by the host.

[0071] If the NVM controller 308 has received a write command, then in operation 602, the NVM controller 308 identifies the NVM (e.g., NVM 204a) that has been set to the write operation mode. The NVM may be identified based on the operation bits 400 set by the command mode generator 314.

[0072] In operation 604, the NVM controller 308 (e.g., the command submission controller 310) submits the write command (e.g., an NVMe write command) to the interface (e.g., interface 312a) associated with the identified write NVM (e.g., NVM 204a). The write NVM obtains the write command from the interface and continues to write the data associated with the command to the memory location of the write NVM. A copy of the data is also stored in the buffer 316.

[0073] Referring again to operation 600, if the command is not a write command, then in operation 606, a determination is made as to whether the command is a read command. If the answer is yes, then in operation 608, a determination is made as to whether the requested data is in the buffer 316. If the answer is yes, then in operation 610, the data is retrieved from the buffer, stored in the storage memory 202, and returned to the host 100.

[0074] If the data is not in the buffer, then in operation 612, the NVM controller 308 identifies the NVM (e.g., NVM 204b) that has been set to the read operation mode. The NVM may be identified based on the operation bits 400 set by the command mode generator 314.

[0075] In operation 614, the NVM controller 308 (e.g., the command submission controller 310) submits the read command (e.g., an NVMe read command) to the interface (e.g., interface 312b) associated with the identified read NVM (e.g., NVM 204b). The read NVM obtains the read command from the interface and continues to obtain the data associated with the command from the memory location of the read NVM. The retrieved data is stored in the storage memory 202 and returned to the host 100.

[0076] Figure 7A flowchart depicting a process for setting an operation mode of one or more NVMs 204 according to one or more embodiments. The process begins, and in operation 700, a command mode generator 314 detects a condition for setting an operation mode of one or more NVMs 204. The condition can be identified in a policy followed by the command mode generator 314 to set the operation mode. The condition can be, for example, expiration of a time period, detection of a threshold fullness of a buffer 316, loss of power, restoration of power, a command from a host (e.g., to detect power to the memory device 102), etc.

[0077] In operation 702, the command mode generator 314 identifies a new operation mode to which one or more NVMs will switch. In some embodiments, an NVM in a read operation mode switches to a write operation mode, and an NVM in a write operation mode switches to a read operation mode. In some embodiments, during, for example, power-on, power loss, etc., all or at least a portion of the NVMs switch to the same operation mode (e.g., all in a read operation mode or in a write operation mode).

[0078] In operation 704, write data collected in the buffer 316 is flushed to one or more NVMs transitioning from a read operation mode to a write operation mode. The data can be flushed to a set flush level. The data in the buffer 316 can also be marked to indicate the NVM 204 to which they have been written. Data written to all NVMs 204 can be released to make room for new write data.

[0079] In operation 706, the command mode generator 314 sets operation bits 400 of one or more NVMs to reflect the transitioned operation mode.

[0080] As would be understood by one of ordinary skill in the art, various embodiments of the present disclosure allow for predictable performance of an application even under mixed read workloads and write workloads. The separation of read workloads from write workloads and the specialization of one or more NVMs to handle each workload individually enhances the performance of read operations in a cost-effective manner.

[0081] One or more embodiments of the present disclosure may be implemented in one or more processors. The term "processor" may refer to one or more processors and / or one or more processing cores. One or more processors may be hosted in a single device or distributed across multiple devices (e.g., in a cloud system). The processor may include, for example, an application specific integrated circuit (ASIC), a general or special purpose central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), and programmable logic devices (such as a field programmable gate array (FPGA)). In a processor, as used herein, each function is performed by hardware configured (i.e., hardwired) to perform the function, or by more general hardware (such as a CPU) configured to execute instructions stored in a non-transitory storage medium (e.g., memory). The processor may be fabricated on a single printed circuit board (PCB) or distributed across multiple interconnected PCBs. The processor may include other processing circuitry; for example, the processing circuitry may include two processing circuits, an FPGA and a CPU, interconnected on a PCB.

[0082] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, first component, first region, first layer, or first section discussed herein may be referred to as a second element, second component, second region, second layer, or second section without departing from the spirit and scope of the inventive concept.

[0083] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the inventive concept. Furthermore, unless explicitly stated, the embodiments described herein are not mutually exclusive. Aspects of the embodiments described herein may be combined in some implementations.

[0084] As used herein, unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. It will also be understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of...," when following a list of elements, modify the entire list of elements and not individual elements in the list. Further, the use of "may" when describing embodiments of the inventive concept means "one or more embodiments of the present disclosure." Additionally, the term "exemplary" is intended to mean an example or illustration. As used herein, the term "use" and its variations may be considered synonymous with the term "utilize" and its variations.

[0085] Although exemplary embodiments of systems and methods for managing a memory device have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Accordingly, it will be understood that systems and methods for managing a memory device constructed in accordance with the principles of the present disclosure may be embodied in a manner different from that specifically described herein. The disclosure is also defined in the appended claims and their equivalents.

[0086] The system and method for processing a storage transaction may include one or more combinations of the features set forth in the following statements.

[0087] Statement 1. A memory device, comprising: a controller; a first non-volatile memory (NVM) device; and a second NVM device, wherein the controller is configured to: detect a first condition; based on the first condition, set the first NVM device to operate in a first operation mode and set the second NVM device to operate in a second operation mode; receive a request from a computing device; and select one of the first NVM device and the second NVM device based on whether the request is of a first type or a second type, wherein the first NVM device is configured to take a first action according to the first operation mode, and the second NVM device is configured to take a second action according to the second operation mode.

[0088] Statement 2. The memory device according to Statement 1, wherein the first condition includes at least one of expiration of a time period, loss of power, restoration of power, and a command from a computing device.

[0089] Statement 3. The device according to Statement 1, wherein the first type includes a write request, and the second type includes a read request.

[0090] Statement 4. The memory device according to Statement 1 further includes a first memory and a second memory, wherein the controller is further configured to: determine that the request is for writing first data; and based on the request: identify second data in the first memory; determine that the first NVM device is set to a write operation mode; write the second data to the second memory and the first NVM device; and store the first data in the first memory.

[0091] Statement 5. The memory device according to Statement 4, wherein the controller is further configured to: receive a second request for reading the first data; and based on the second request: generate a first command for obtaining the first data from the first memory and detect a first result of the first command; based on the first result, generate a second command for obtaining the first data from the second memory and detect a second result of the second command; determine that the second NVM device is set to a read operation mode; and based on the second result, generate a command for obtaining the first data from the second NVM device.

[0092] Statement 6. The memory device according to Statement 4, wherein the controller is further configured to: detect a second condition; and based on detecting the second condition, the controller is further configured to: determine that the second NVM device is set to a read operation mode; based on the second NVM device being set to the read operation mode, store the second data in the second memory to the second NVM device; and set the first NVM device to a read operation mode and set the second NVM device to a write operation mode.

[0093] Statement 7. The memory device according to Statement 1 further includes: a memory, wherein the controller is further configured to: detect a second condition; based on detecting the second condition, the controller is further configured to: set the first NVM device and the second NVM device to operate in a first operation mode.

[0094] Statement 8. The memory device according to Statement 7, wherein the second condition includes a loss of power to the memory device, and the first operation mode includes a write mode, wherein the controller is further configured to: read the first data and the second data stored in the memory; and store the first data in the first NVM device and store the second data in the second NVM device.

[0095] Statement 9. The memory device according to Statement 7, wherein the second condition includes detecting power to the memory device, and the first operation mode includes a read mode, wherein the controller is further configured to: identify the first data in the first NVM device and the second data in the second NVM device; read the first data from the first NVM device and read the second data from the second NVM device; and store the first data and the second data in the memory.

[0096] Statement 10. The memory device according to any one of Statements 1 to 9, wherein the process of the controller being configured to set the first NVM device to operate in a first operation mode and set the second NVM device to operate in a second operation mode further includes: the controller being configured to: set in the memory of the memory device a first value for identifying the first operation mode for the first NVM device and a second value for identifying the second operation mode for the second NVM device.

[0097] Statement 11. A method for managing a memory device, comprising: detecting, by a controller of the memory device, a first condition; based on the first condition, setting, by the controller, a first non-volatile memory (NVM) device to operate in a first operation mode and setting a second NVM device to operate in a second operation mode; receiving, by the controller, a request from a computing device; and selecting, based on the request being one of a first type and a second type, one of the first NVM device and the second NVM device, wherein the first NVM device is configured to take a first action according to the first operation mode, and the second NVM device is configured to take a second action according to the second operation mode.

[0098] Statement 12. The method according to Statement 11, wherein the first condition includes at least one of expiration of a time period, loss of power, restoration of power, and a command from a computing device.

[0099] Statement 13. The method according to Statement 11, wherein the first type includes a write request, and the second type includes a read request.

[0100] Statement 14. The method according to Statement 11, further comprising: determining, by the controller, that the request is for writing first data; and based on the request: identifying, by the controller, second data in a first memory; determining, by the controller, that the first NVM device is set to a write operation mode; writing, by the controller, the second data to a second memory and the first NVM device; and storing, by the controller, the first data in the first memory.

[0101] Statement 15. The method according to Statement 14, further comprising: receiving, by the controller, a second request for reading the first data; and based on the second request: generating, by the controller, a first command for obtaining the first data from the first memory and detecting a first result of the first command; based on the first result, generating, by the controller, a second command for obtaining the first data from the second memory and detecting a second result of the second command; determining that the second NVM device is set to a read operation mode; and based on the second result, generating a command for obtaining the first data from the second NVM device.

[0102] Statement 16. The method according to Statement 14 further includes: detecting, by a controller, a second condition; and based on detecting the second condition: determining, by the controller, that a second NVM device is set to a read operation mode; storing, by the controller, second data in the second memory into the second NVM device based on the second NVM device being set to the read operation mode; and setting the first NVM device to the read operation mode and setting the second NVM device to the write operation mode.

[0103] Statement 17. The method according to Statement 11 further includes: detecting a second condition; and based on detecting the second condition: setting, by the controller, the first NVM device and the second NVM device to operate in a first operation mode.

[0104] Statement 18. The method according to Statement 17, wherein the second condition includes a loss of power to the memory device, and the first operation mode includes a write mode, and wherein the method further includes: reading first data and second data stored in the memory; and storing the first data in the first NVM device and storing the second data in the second NVM device.

[0105] Statement 19. The method according to Statement 17, wherein the second condition includes detecting power to the memory device, and the first operation mode includes a read mode, and wherein the method further includes: identifying first data in the first NVM device and second data in the second NVM device; reading the first data from the first NVM device and reading the second data from the second NVM device; and storing the first data and the second data in the memory.

[0106] Statement 20. The method according to any one of Statements 11 to 19, wherein the step of setting the first NVM device to operate in the first operation mode and setting the second NVM device to operate in the second operation mode further includes: setting, in the memory of the memory device, a first value for identifying the first operation mode for the first NVM device and a second value for identifying the second operation mode for the second NVM device.

Claims

1. A memory device, comprising: A controller; A first non-volatile memory device; And A second non-volatile memory device, Wherein the controller is configured to: Detect a first condition; Based on the first condition, set the first non-volatile memory device to operate in a first operation mode and set the second non-volatile memory device to operate in a second operation mode; Receive a request from a computing device; and Based on the request being one of a first type and a second type, select one of the first non-volatile memory device and the second non-volatile memory device, wherein the first non-volatile memory device is configured to take a first action according to the first operation mode, and the second non-volatile memory device is configured to take a second action according to the second operation mode.

2. The memory device according to claim 1, wherein, The first condition includes at least one of expiration of a time period, loss of power, restoration of power, and a command from the computing device.

3. The memory device according to claim 1, wherein, The first type includes a write request, and the second type includes a read request.

4. The memory device according to claim 1 further includes a first memory and a second memory, wherein, The controller is further configured to: Determine that the request is for writing first data; and Based on the request: Identify second data in a first memory; Determine that the first non-volatile memory device is set to a write operation mode; Write the second data to a second memory and the first non-volatile memory device; And Store the first data in the first memory.

5. The memory device according to claim 4, wherein, The controller is further configured to: Receive a second request for reading the first data; and Based on the second request: Generate a first command for obtaining the first data from the first memory and detect a first result of the first command; Based on the first result, generate a second command for obtaining the first data from the second memory and detect a second result of the second command; Determine that the second non-volatile memory device is set to a read operation mode; And Based on the second result, generate a command for obtaining the first data from the second non-volatile memory device.

6. The memory device according to claim 4, wherein, The controller is further configured to: Detect a second condition; and Based on detecting the second condition, the controller is further configured to: Determine that the second non-volatile memory device is set to a read operation mode; Based on the second non-volatile memory device being set to the read operation mode: Store the second data in the second memory into the second non-volatile memory device; And Set the first non-volatile memory device to the read operation mode and set the second non-volatile memory device to the write operation mode.

7. The memory device according to claim 1, further comprising a memory, wherein the controller is further configured to: Detect a second condition; Based on detecting the second condition, the controller is further configured to: Set the first non-volatile memory device and the second non-volatile memory device to operate in a first operation mode.

8. The memory device according to claim 7, wherein, The second condition includes loss of power to the memory device, and the first operation mode includes a write mode, wherein the controller is further configured to: Read the first data and the second data stored in the memory; and Store the first data into the first non-volatile memory device and store the second data into the second non-volatile memory device.

9. The memory device according to claim 7, wherein, The second condition includes detecting power to the memory device, and the first operation mode includes a read mode, wherein the controller is further configured to: Identify first data in a first non-volatile memory device and second data in a second non-volatile memory device; Read the first data from the first non-volatile memory device and read the second data from the second non-volatile memory device; and Store the first data and the second data in the memory.

10. The memory device according to any one of claims 1 to 9, wherein, The process by which the controller is configured to set the first non-volatile memory device to operate in the first operation mode and set the second non-volatile memory device to operate in the second operation mode further includes: The controller is configured to: set a first value for identifying the first operation mode for the first non-volatile memory device and a second value for identifying the second operation mode for the second non-volatile memory device in the memory of the memory device.

11. A method for managing a memory device, including: Detecting a first condition by a controller of the memory device; Based on the first condition, setting a first non-volatile memory device to operate in a first operation mode and setting a second non-volatile memory device to operate in a second operation mode by the controller; Receiving a request by the controller from a computing device; And Based on the request being one of a first type and a second type, selecting one of the first non-volatile memory device and the second non-volatile memory device, wherein the first non-volatile memory device is configured to take a first action according to the first operation mode, and the second non-volatile memory device is configured to take a second action according to the second operation mode.

12. The method according to claim 11, wherein, The first condition includes at least one of expiration of a time period, loss of power, restoration of power, and a command from a computing device.

13. The method according to claim 11, wherein, The first type includes a write request, and the second type includes a read request.

14. The method according to claim 11, further including: Determining by the controller that the request is for writing first data; And Based on the request: Identifying second data in a first memory by the controller; Determining by the controller that the first non-volatile memory device is set to a write operation mode; Writing the second data to a second memory and the first non-volatile memory device by the controller; And Storing the first data in the first memory by the controller.

15. The method according to claim 14, further including: Receiving by the controller a second request for reading the first data; And Based on the second request: Generating by the controller a first command for obtaining the first data from the first memory and detecting a first result of the first command; Based on the first result, generating by the controller a second command for obtaining the first data from the second memory and detecting a second result of the second command; Determining that the second non-volatile memory device is set to a read operation mode; And Based on the second result, generating a command for obtaining the first data from the second non-volatile memory device.

16. The method according to claim 14, further including: Detecting a second condition by the controller; And Based on detecting the second condition: The controller determines that the second non-volatile memory device is set to the read operation mode; Based on the second non-volatile memory device being set to the read operation mode, the controller stores the second data in the second memory into the second non-volatile memory device; And Set the first non-volatile memory device to the read operation mode and set the second non-volatile memory device to the write operation mode.

17. The method according to claim 11, further comprising: Detect a second condition; Based on detecting the second condition: The controller sets the first non-volatile memory device and the second non-volatile memory device to operate in a first operation mode.

18. The method according to claim 17, wherein The second condition includes a loss of power to the memory device, and the first operation mode includes a write mode, wherein the method further comprises: Read the first data and the second data stored in the memory; and Store the first data in the first non-volatile memory device and store the second data in the second non-volatile memory device.

19. The method according to claim 17, wherein, The second condition includes detecting the power to the memory device, and the first operation mode includes a read mode, wherein the method further comprises: Identify the first data in the first non-volatile memory device and the second data in the second non-volatile memory device; Read the first data from the first non-volatile memory device and read the second data from the second non-volatile memory device; and Store the first data and the second data in the memory.

20. The method according to any one of claims 11 to 19, wherein The step of setting the first non-volatile memory device to operate in a first operation mode and setting the second non-volatile memory device to operate in a second operation mode further comprises: Set a first value for identifying the first operation mode for the first non-volatile memory device and a second value for identifying the second operation mode for the second non-volatile memory device in the memory of the memory device.

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