Flash device access system and method

Abstract

The application discloses a Flash device access system and method, and relates to the technical field of chip design. The system comprises an interface control module and a protocol conversion module. The interface control module is used for selecting a corresponding access mode according to the type of a received access request and generating an access command. The access request is divided into a data transmission request for data transmission and a configuration request for system configuration, and the access mode comprises a direct access mode and an indirect access mode. The protocol conversion module is used for determining relevant access parameters according to the access command, selecting a protocol stage from a plurality of preset protocol stages according to the parameters, and generating a protocol command sequence to complete data transmission with a target Flash device. The application solves the problems of single access mode and fixed protocol flow in the prior art, and can adopt different access modes according to the type of a request and selectively organize protocol stages according to a command.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip design technical field, and particularly relates to a Flash device access system and method. BACKGROUND

[0002] In the existing Flash device access system, a single fixed access mode is usually adopted to process all types of access requests, whether it is a data transmission request or a system configuration request. This way lacks pertinence when dealing with different types of requests. In addition, the protocol process followed by the system when communicating with the Flash device is also usually fixed, containing multiple preset protocol stages. Even if some access commands do not require all stages, the entire sequence must be executed completely, which causes redundant steps in the communication process.

[0003] Therefore, there is an urgent need for a Flash device access system that can select different access modes according to the type of access request and selectively combine multiple protocol stages according to the access command. SUMMARY

[0004] The present application provides a Flash device access system and method to solve the problems caused by the single access mode and fixed protocol process in the prior art.

[0005] The present application provides a Flash device access system, which comprises:

[0006] An interface control module is configured to select a corresponding access mode according to the request type of the received access request, and generate an access command according to the request type and the corresponding access mode; the access request comprises a data transmission request for data transmission to a target Flash device and a configuration request for configuration of the access system; the access mode comprises a direct access mode and an indirect access mode;

[0007] A protocol conversion module is configured to determine access parameters according to the access command, select from a plurality of preset protocol stages according to the access parameters, and generate a protocol command sequence for data transmission to the target Flash device.

[0008] The present application also provides a Flash device access method, which is applied to any one of the above-mentioned Flash device access systems, and the method comprises:

[0009] According to the request type of the received access request, a corresponding access mode in the interface control module is selected; the access request comprises a data transmission request for data transmission to a target Flash device and a configuration request for configuration of the access system; the access mode comprises a direct access mode and an indirect access mode;

[0010] generating an access command according to the request type and the corresponding access mode;

[0011] determining access parameters according to the access command;

[0012] generating a protocol command sequence from a plurality of preset protocol stages according to the access parameters, to perform data transmission with the target Flash device.

[0013] The application further provides an electronic device, comprising a memory for storing a computer program, and a processor for executing the computer program to implement the steps of any of the Flash device access methods.

[0014] The application further provides a computer readable storage medium, which stores a computer program, wherein the computer program is executed by a processor to implement the steps of any of the Flash device access methods.

[0015] The application solves the problems of the prior art that the processing mode lacks pertinence due to the single access mode, and the communication sequence contains redundant steps due to the fixed protocol flow. Specifically, the application sets an interface control module, which can identify whether the access request is a request for data transmission or a request for system configuration, and accordingly selects a direct access mode or an indirect access mode. This enables the system to have the ability to distribute different tasks to different processing paths, thereby providing respective matching operation modes for the two access tasks that differ in function, and realizing the correspondence between the tasks and the processing modes. Meanwhile, the application further uses a protocol conversion module to selectively combine a plurality of preset protocol stages according to a specific access command to generate a protocol command sequence, instead of forcibly executing all stages. The finally generated protocol command sequence can be constructed to contain only the necessary steps for the current command, so that the construction of the protocol sequence can accurately reflect the actual demand of the command itself, and avoid unnecessary communication flow. BRIEF DESCRIPTION OF DRAWINGS

[0016] To more clearly illustrate the application, the following will briefly introduce the drawings needed in the embodiments. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0017] Figure 1 A system structure schematic diagram of a Flash device access system provided by the embodiment of the application;

[0018] Figure 2 A structure schematic diagram of a Flash controller provided by the embodiment of the application;

[0019] Figure 3 The state conversion schematic diagram of the AHB bus provided by the embodiment of the present application is shown in FIG. 1;

[0020] Figure 4 The protocol conversion schematic diagram provided by the embodiment of the present application is shown in FIG. 2;

[0021] Figure 5 The working flow schematic diagram of the Flash controller provided by the embodiment of the present application is shown in FIG. 3;

[0022] Figure 6 The structure schematic diagram of the computer device provided by the embodiment of the present application is shown in FIG. 4. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0024] It should be noted that, in the description of the present application, the terms “include”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0025] In order for those skilled in the art to better understand the technical solutions of the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0026] Firstly, the terms involved in the present application are introduced.

[0027] QSPI: Quad Serial Peripheral Interface, four-way serial peripheral interface; AHB: Advanced High Performance Bus, high-level high-performance bus; APB: Advanced Peripheral Bus, high-performance peripheral bus; XIP: eXecute In Place, on-chip execution; PCB: Printed Circuit Board, printed circuit board.

[0028] In the design of modern system on chip (SoC), external flash memory plays a crucial role as both the source of system boot code and the storage medium for a large amount of application data. To access flash efficiently, a dedicated controller such as a QSPI (quad serial peripheral interface) controller is usually integrated inside the SoC. However, with the continuous improvement of SoC performance and the increasing complexity of application scenarios, existing flash access technologies face multiple challenges. First, there is a problem of balancing performance and flexibility in interface design. Some controllers use low-speed buses such as APB for control, which is flexible in configuration but has a bandwidth bottleneck when handling large data read / write (such as on-chip execution XIP of code); while other controllers use high-speed buses such as AHB, which can provide high throughput but are too cumbersome for simple configuration or status query commands, resulting in low control efficiency. How to simultaneously meet the requirements of high-performance data transmission and convenient and flexible control in a controller is a difficult point in current design.

[0029] In addition, at the communication protocol level, although the standard QSPI protocol process is normative, its fixed multi-stage (instruction, address, idle cycle, data, etc.) sequence is redundant in many scenarios. For example, a simple command to read a status register does not require an address or idle cycle stage, but the traditional controller still needs to perform the complete process step by step, which undoubtedly increases communication overhead and delay, reducing protocol execution efficiency. At the same time, with the continuous improvement of QSPI working frequency, the phase offset problem between clock and data signals caused by PCB wiring delay, flash chip processing delay and other physical factors becomes more prominent. This signal integrity problem can cause the SoC to sample the returned data at the wrong time point, causing data read errors, which severely limits the highest working frequency and data transmission reliability that the system can achieve. Existing phase adjustment schemes are often complex or dependent on specific hardware platforms, lacking a simple, general and easy-to-implement solution.

[0030] Therefore, how to design a flash access controller that can balance interface versatility, protocol execution efficiency and high-frequency communication reliability is a technical problem that needs to be solved by those skilled in the art.

[0031] Embodiments of the present application provide a flash device access system, the structure of the system is as shown in Figure 1 The system includes the following modules:

[0032] An interface control module is configured to select a corresponding access mode according to the request type of the received access request, and generate an access command according to the request type and the corresponding access mode.

[0033] Specifically, the module first receives an access request from outside, analyzes the request type of the request, and judges the purpose of the request. According to the judged request type, a mode corresponding to the request type is selected from the preset access modes. Finally, an internal access command is generated based on the request type and the selected mode, and the command is handed over to the next module for processing. The access request refers to an instruction or signal from the outside of the system (such as a CPU) to request the system to operate the Flash device. The access mode refers to several different working modes or processing flows preset in the system. The module will switch to the most suitable working mode according to the task. The access command is a standardized internal instruction generated by the interface control module after processing the external request, which is used by other parts of the system.

[0034] The access request includes a data transmission request for data transmission to the target Flash device and a configuration request for configuration of the access system. The requests from the outside are mainly divided into two categories: data transmission request, which is to read or write data from the Flash device. The configuration request is not for data transmission, but for setting or parameter modification of the Flash device access system itself.

[0035] The target Flash device refers to the external storage chip to be accessed by the system, which is the final object of operation. Data transmission refers to the movement of user data between the system and the Flash device, such as reading files and saving data. Configuration refers to the setting of the working parameters of the access system itself, such as setting the working speed and function switch.

[0036] The above-mentioned access mode includes a direct access mode and an indirect access mode.

[0037] The protocol conversion module is used to determine the access parameters according to the access command, select from the preset multiple protocol stages according to the access parameters, generate a protocol command sequence, and perform data transmission with the target Flash device.

[0038] Specifically, the access command generated by the interface control module is received, and the access parameters are extracted from the access command. The module internally stores a plurality of standard communication steps, i.e. protocol stages. According to the access parameters obtained in the previous step, only a few stages necessary for the current task are selected from the preset stages. The selection is critical, meaning that not all stages are used every time. The sequence generation is to combine the selected protocol stages to form a final executable instruction sequence, called protocol command sequence. Finally, the generated sequence is used to perform actual communication and data transmission with the external Flash device.

[0039] The access parameters above are specific information parsed from the access command, such as the address to be accessed, the data length to be read / written, the specific instruction code, etc. The protocol phase is a series of fixed steps specified by the standard protocol when communicating with the Flash device, such as sending an instruction, sending an address, and waiting, which are different phases. The protocol command sequence is a complete operation instruction that can be directly sent to the Flash device for execution, which is composed of one or more protocol phases in a specific order.

[0040] The Flash device access system of the embodiments of the present application solves the problems in the prior art that the processing mode lacks pertinence due to the single access mode, and the communication sequence contains redundant steps due to the fixed protocol flow. Specifically, the present application sets an interface control module, which can identify whether the access request is a request for data transmission or a request for system configuration, and accordingly selects the direct access mode or the indirect access mode. This enables the system to have the ability to distribute different tasks to different processing paths, thereby providing respective matching operation modes for the two access tasks that differ in function, and realizing the correspondence between the tasks and the processing modes. Meanwhile, the present application also uses a protocol conversion module to selectively combine a plurality of preset protocol phases to generate a protocol command sequence according to the specific access command, instead of executing all the phases. The finally generated protocol command sequence can be composed of only the necessary steps for the current command, so that the composition of the protocol sequence can accurately reflect the actual needs of the command itself, avoiding unnecessary communication processes.

[0041] In an optional embodiment, the interface control module is specifically used for:

[0042] When receiving a data transmission request for data transmission to the target Flash device, the direct access mode is selected; and when receiving a configuration request for configuring the access system, the indirect access mode is selected.

[0043] Mapping the specific request type to the specific access mode brings the effect that the system behavior is deterministic and predictable. Through this explicit binding, it is ensured that the data transmission task with higher performance requirement is always processed by the direct access mode, while the control and configuration type task is processed by the indirect access mode, so that the selection of the mode is no longer ambiguous or random, but follows a fixed and function-optimized logical rule.

[0044] The interface control module includes a first interface and a second interface; wherein the first interface is used to receive a data transmission request for data transmission to the target Flash device; and the second interface is used to receive a configuration request for configuring the access system.

[0045] By setting two independent interfaces, the system distinguishes the two requests on the physical link, lays a hardware foundation for subsequent use of different processing logic (direct / indirect mode), and enables the identification and shunting of requests to be completed at the interface level.

[0046] The first interface is an advanced high-performance bus interface for communicating with an advanced high-performance bus, and is configured to receive a data transmission request for data transmission to a target Flash device; and the second interface is a high-performance peripheral bus interface for communicating with a high-performance peripheral bus, and is configured to receive a configuration request for configuration of an access system.

[0047] The data transmission request is associated with an advanced high-performance bus (AHB) to take advantage of its high bandwidth characteristics, and the configuration request is associated with a control bus (APB) to take advantage of its simple structure. This design not only enables seamless integration into existing SoC architectures, but also enables each request type to take advantage of the corresponding bus.

[0048] In an optional embodiment, the direct access mode includes: mapping the target Flash device as a memory address space of the access system; and reading and writing the memory address space to complete data transmission. The indirect access mode includes: configuring a register of the access system to build an access task for the target Flash device, so that the access system performs data transmission to the target Flash device according to the access task.

[0049] In an optional embodiment, the protocol conversion module is specifically configured to:

[0050] According to the access command, determine the access parameter; according to the access parameter, select from a plurality of preset protocol stages to obtain a target protocol stage; according to the obtained target protocol stage, build a protocol command sequence; and perform data transmission to the target Flash device through the protocol command sequence.

[0051] The problem of how to dynamically build a protocol sequence is solved, bringing the effect of clear logic and step-by-step generation process. This process clearly defines the internal logic of protocol conversion, so that the generation of the protocol sequence is based on the analysis and judgment of the command parameters, rather than a fixed template, ensuring the certainty and flexibility of the generation process.

[0052] The plurality of preset protocol stages includes at least two of a chip select active stage, an instruction stage, and an address stage; wherein the chip select active stage is configured to activate a chip select signal; the instruction stage is configured to send an instruction code; and the address stage is configured to send an address.

[0053] The access parameters include at least one of an instruction code, an address value, and a data length.

[0054] The access parameters further include control parameters for controlling the protocol flow, the control parameters including at least one of address length information and a number of null instruction cycles; the address length information is used to determine whether to skip the address stage; and the number of null instruction cycles is used to determine the number of null instruction cycles inserted between the address stage and the data stage.

[0055] Through the parameters, the system can actively and explicitly omit some stages unnecessary for some commands (for example, a read status register command can skip the address stage).

[0056] In an optional embodiment, the system further includes:

[0057] a phase adjustment module configured to adjust a sampling phase for collecting data returned by the target Flash device; the sampling phase is a relative phase between a sampling clock and the returned data.

[0058] By introducing a module specially configured to adjust the relative phase between the sampling clock and the returned data, the system acquires the ability to actively compensate for physical delay, and ensures that the data sampling point falls in the most stable interval of the signal, thereby ensuring the correctness of data reception at a high clock frequency.

[0059] The phase adjustment module is specifically configured to:

[0060] adjust the sampling phase by phase-shifting the sampling clock according to a preset delay value.

[0061] The determination of the delay value includes:

[0062] write calibration data to the target Flash device at a first rate; switch to a second rate and traverse a plurality of delay values to read back the calibration data until the read-back data matches the calibration data; the second rate is higher than the first rate.

[0063] In addition, the protocol conversion module includes a state jump control register; the protocol conversion module configures the state jump control register according to the access command; each bit in the state jump control register corresponds to a preset protocol stage, and is used to enable or disable execution of the protocol stage, thereby selecting among a plurality of preset protocol stages to achieve skipping of the protocol stage.

[0064] The process of traversing multiple delay values to read back the calibration data specifically includes: starting from an initial delay value, incrementally changing the delay value and reading back until a continuous delay value interval with a length not less than a preset window threshold is found, all delay values in the interval can make the read back data match the calibration data; and selecting a middle value or a preset offset value of the continuous delay value interval as the finally determined delay value.

[0065] The system further comprises a data buffering module; when the system works in the direct access mode, the data buffering module is configured in a stream mode to allow direct transmission of data between the first interface and the protocol conversion module to minimize delay; when the system works in the indirect access mode, the data buffering module is configured in a block mode to allow unified processing of data by the protocol conversion module after the data is written into or read out of the data buffering unit.

[0066] To sum up, the Flash device access system provided by the application solves the comprehensive problems of the Flash access system in the prior art in terms of interface versatility, protocol execution efficiency and high-frequency communication reliability, and the overall beneficial effects are embodied in the construction of a comprehensive Flash device access solution with high performance, high flexibility and high stability. Specifically, first, by setting the first interface (AHB) and the second interface (APB), the data transmission request and the configuration request are separated at the physical level, which lays a hardware foundation for subsequent adoption of different processing strategies. Based on this, the system can clearly direct the data transmission task to the direct access mode implemented through memory mapping, fully utilizing the bandwidth advantage of the high-performance bus; at the same time, the configuration task is directed to the indirect access mode implemented through register programming, realizing fine control. This cooperative working mechanism of the dual mode and the dual interface makes the system realize the compromise between performance and flexibility at the top-level architecture. Regardless of which mode generates the access command, the command will enter the protocol conversion module. According to the specific parameters (such as instruction code, address value) in the command, the module can not only selectively combine standard protocol stages (such as instruction, address stage), but more importantly, can actively skip unnecessary protocol stages through control parameters (such as address length information). This feature enables the advantages of the two aforementioned access modes to be fully utilized, and the high-performance data flow in the direct mode can further reduce overhead through an optimized protocol sequence, while the control command in the indirect mode can be executed more quickly. Finally, in order to ensure that the entire system is not limited by physical limitations when pursuing high performance, the scheme introduces a phase adjustment module. Through a calibration process, the module can automatically determine an optimal delay value and use the value to accurately offset the sampling clock phase. This mechanism provides reliability guarantee for all the high-performance operations mentioned above, ensuring that even at high-speed data transmission, the data returned from the Flash can be accurately and correctly collected.

[0067] Based on the Flash device access system of the above embodiment, the embodiment of the application also provides a Flash controller which integrates AHB bus and APB bus into the Flash controller, uses different bus data paths in different transmission modes, supports flexible SPI / QSPI protocol conversion, and is convenient for adapting to various Flash devices.

[0068] The structure of the Flash controller is shown in Figure 2 The Flash controller is a controller for accessing a Flash device through a QSPI interface, that is, a QSPI controller in Figure 2 The controller comprises an AHB control unit, an APB control unit, a command generation unit, a sending-receiving buffer unit, a QSPI protocol conversion unit and a QSPI interface unit.

[0069] The AHB control unit is responsible for data read and write in direct mode, and the APB control unit is responsible for register configuration and data read and write in indirect mode. Regardless of which mode is used, the command generation unit is required to convert the command format into a format recognizable by an external Flash device, enter the buffer unit and the QSPI protocol conversion unit, realize serial-parallel / parallel-serial conversion, and complete communication with the external Flash device through the QSPI interface unit.

[0070] Specifically, the AHB control unit is mainly used for communication between the QSPI controller and an external AHB bus, and mainly comprises an AHB interface and a direct mode control unit. The AHB interface is used for communication with the external AHB bus. The direct mode control unit is used for managing state conversion of the AHB bus, as shown in Figure 3 .

[0071] The idle state is waiting for a reset signal or an AHB bus request. The read state is processing a read request of the AHB bus. The write state is processing a write request of the AHB bus. The error state is processing an error condition of the AHB bus.

[0072] The APB control unit is mainly used for communication between the QSPI controller and an external APB interface, and mainly comprises register read and write, mode switching and an indirect mode control unit. The APB control unit internally comprises an APB interface, a register unit, a mode controller and an indirect mode control unit.

[0073] The APB interface is used for communication with the external APB bus. The register unit is used for read and write of configuration information of the QSPI controller. The mode controller is used for controlling the working mode of the QSPI.

[0074] Direct mode is data transmission through AHB interface, in which the external flash device is mapped as a part of memory, and data read and write can be directly performed through address. Indirect mode is data transmission through APB interface, and all operations are performed by programming QSPI control register. It allows software to directly access sending and receiving buffer.

[0075] Figure 2 The controller in the application further comprises chip select switching, which is configured to generate chip select signals for managing the external flash device according to commands of the register unit, and the controller supports two chip select signals. Clock management, which is configured to generate clock signals for managing the external flash device according to commands of the register unit. Command generation unit, which is configured to convert requests in the direct mode or the indirect mode into a byte sequence through a command generator, and generate control command data buffer unit of the flash device, which is configured to temporarily store data to be sent and received data.

[0076] The QSPI protocol conversion of the controller is configured to send the byte sequence from the command generation unit to the QSPI interface unit after phase-by-phase parallel-serial conversion, and convert the signal from the QSPI interface unit into a receiving signal after sampling signal adjustment, and then transmit the receiving signal to the receiving buffer. The QSPI protocol conversion comprises a phase adjustment unit and a protocol conversion unit.

[0077] The phase adjustment unit is configured to finely adjust the phase of the receiving signal and the clock according to the register configuration, and can be adjusted according to the period of the system clock (APB / AHB bus clock) to ensure the correctness of the receiving data sampling.

[0078] The protocol conversion unit, as shown in Figure 4 comprises the following states:

[0079] Idle state, waiting for a reset signal or a QSPI command.

[0080] Chip select state, activating the QSPI chip select signal.

[0081] Instruction phase, sending a QSPI instruction.

[0082] Address phase, sending a QSPI address.

[0083] Alternation phase, processing the alternation function of the QSPI.

[0084] Data transmission phase, performing data transmission.

[0085] Sending phase, sending data.

[0086] Sending holding phase, maintaining the sending state.

[0087] Receiving phase, receiving data.

[0088] Receive hold phase, hold the receive state.

[0089] Chip select hold phase, hold the chip select signal.

[0090] Finally, the QSPI interface unit, for communication with the external Flash device.

[0091] The specific workflow of the Flash controller is shown in Figure 5 , including the following processes:

[0092] First, before using the QSPI controller, initialization configuration is needed, including configuring QSPI clock, buffer depth, working mode and Flash device working mode, etc.

[0093] Configuring QSPI clock includes setting the clock prescaler of the QSPI controller to determine the QSPI clock frequency. For example, set the frequency division coefficient to 1, which means the QSPI clock frequency is half of the system clock frequency.

[0094] Configuring QSPI buffer depth includes setting the receive and transmit buffer depth of the QSPI controller.

[0095] Configuring QSPI working mode includes setting the working mode of the QSPI controller, including clock mode, operation mode (direct mode or indirect mode) and selection of chip select signal, etc.

[0096] Configuring Flash device working mode includes setting the working mode of the Flash device, such as command mode of read ID, write enable, erase, etc.

[0097] Next, the QSPI controller receives read and write instructions from the system through the APB interface or the AHB interface. These instructions include read data, write data, erase sector, etc.

[0098] Read instruction is to read the register of QSPI controller through APB interface to get the current instruction information.

[0099] Write instruction is to write instruction to the register of QSPI controller through AHB interface to set the working mode and operation parameters of QSPI controller.

[0100] Subsequently, the command generation unit of QSPI controller generates the corresponding standard format command according to the received instruction. The command generated by the command generation unit includes five stages of instruction, address, alternate byte, null instruction cycle and data.

[0101] Among them, the instruction stage: generate the instruction part of QSPI command, such as read command, write command, etc.

[0102] Address phase: generate the address part of the QSPI command, specify the address of the operation.

[0103] Alternating byte phase: generate the alternating byte part of the QSPI command, used to control the operation mode.

[0104] Idle cycle phase: generate the idle cycle part of the QSPI command, used to leave time for the Flash device to prepare data.

[0105] Data phase: generate the data part of the QSPI command, used to read or write data.

[0106] The generated command enters the data buffer and waits to be sent. The QSPI controller converts the command into the standard QSPI protocol format through the protocol conversion unit, as shown in the above Figure 4 . Then the serial signal is sent to the external Flash device through the QSPI interface.

[0107] As can be seen, the QSPI protocol usually only has the above-mentioned 5 phases, but the above-mentioned Figure 4 After the 5 phases are disassembled, 11 states are formed. And each state can be selected to be retained or closed, but one of the above-mentioned 5 states must be retained. Based on the above settings, the application also supports the XIP mode in direct mode. And all states can jump to any subsequent state, which speeds up the data conversion speed in different states.

[0108] Subsequently, the external Flash device feeds back data through the QSPI interface. The phase adjustment unit of the QSPI controller selects the appropriate data sampling position, and then converts the received serial data into parallel data through the protocol conversion unit, and then stores the data into the receiving buffer.

[0109] Serial-parallel conversion refers to the protocol conversion unit of the QSPI controller converting the received serial data into parallel data for subsequent processing. Data buffering refers to storing the received data into the receiving buffer of the QSPI controller for further processing.

[0110] Collecting feedback data requires the coordination of the phase adjustment unit. The phase adjustment unit is mainly used to adjust the relative phase of the clock and data line when the QSPI receives messages from the Flash device. Due to the PCB wiring and the delay of the Flash device itself, the QSPI may not be able to correctly sample the clock when receiving data. Providing a phase adjustment unit can adjust the data sampling position backward according to the system clock period, ensuring that the QSPI sampling point can sample the data center position. Ensuring the stability of QSPI communication and improving communication quality.

[0111] In the phase adjustment unit, a lower rate QSPI operating frequency is configured first to ensure normal reading and writing of the Flash device; specific calibration data is written to the Flash device at a specified address; the QSPI is improved to the design required frequency for Flash device data reading, and the sampling control register is traversed, and when the correct data is read, the appropriate phase adjustment value is determined. The delay sampling value positioned by the above method can run the QSPI at a higher frequency.

[0112] Finally, the QSPI controller can send data in the buffer to other parts of the system through the APB or AHB interface.

[0113] In summary, the Flash controller provided by the embodiments of the present application realizes the universality of the practical application of the QSPI controller by simultaneously integrating the AHB and APB interfaces. The more QSPI application modes are supported by using the protocol conversion state machine with finer granularity and flexibility. The working frequency of the QSPI is improved by using the phase adjustment technology.

[0114] Based on the Flash device access system according to the above embodiments, the present example also provides a Flash device access method for execution of the system, and the method includes the following processes:

[0115] According to the request type of the received access request, the corresponding access mode in the interface control module is selected;

[0116] According to the request type and the corresponding access mode, an access command is generated;

[0117] According to the access command, an access parameter is determined;

[0118] According to the access parameter, a protocol command sequence is generated by selecting from a plurality of preset protocol stages to perform data transmission with the target Flash device.

[0119] In the above steps, according to the access parameter, a protocol command sequence is generated by selecting from a plurality of preset protocol stages to perform data transmission with the target Flash device, which specifically includes:

[0120] According to the access parameter, a target protocol stage is selected from a plurality of preset protocol stages;

[0121] According to the obtained target protocol stage, a protocol command sequence is constructed;

[0122] Data transmission is performed with the target Flash device through the protocol command sequence.

[0123] The embodiments of the present application also provide an electronic device, such as Figure 6As shown, the device includes a memory 14 and a processor 20, the memory 10 stores a computer program, and the processor 20 is configured to run the computer program to perform the steps in any of the above-mentioned Flash device access method embodiments.

[0124] Embodiments of the present application also provide a computer readable storage medium, which stores a computer program, wherein the computer program is configured to perform the steps in any of the above-mentioned Flash device access method embodiments when executed.

[0125] In an exemplary embodiment, the above-mentioned computer readable storage medium can include, but is not limited to, a U disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0126] Embodiments of the present application also provide a computer program product, which includes a computer program, and the computer program is executed by a processor to implement the steps in any of the above-mentioned Flash device access method embodiments.

[0127] Embodiments of the present application also provide another computer program product, which includes a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps in any of the above-mentioned Flash device access method embodiments.

[0128] The skilled person can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in general terms in the above description. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0129] The above introduces in detail a Flash device access system, method, device, storage medium and program product provided by the present application. The principles and implementation manners of the present application are described by applying specific examples, and the above example is only used to help understand the method of the present application and its core idea. It should be pointed out that, for ordinary skilled persons in the technical field, some improvements and modifications can be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A Flash device access system, characterized in that, The system includes: The interface control module is used to select the corresponding access mode according to the request type of the received access request, and generate an access command according to the request type and the corresponding access mode; the access request includes a data transmission request for transmitting data to the target Flash device and a configuration request for configuring the access system; the access mode includes a direct access mode and an indirect access mode. The protocol conversion module is used to determine access parameters according to the access command, and select from multiple preset protocol stages according to the access parameters to generate a protocol command sequence for data transmission with the target Flash device; Specifically, the interface control module is used for: When a data transfer request to the target Flash device is received, the direct access mode is selected; When a configuration request to configure the access system is received, the indirect access mode is selected; The protocol conversion module includes a state transition control register. The protocol conversion module configures the state transition control register according to the access command. Each bit in the state transition control register corresponds to a preset protocol stage, which is used to enable or disable the execution of the preset protocol stage, thereby selecting from multiple preset protocol stages to achieve skipping of protocol stages. The interface control module includes a first interface and a second interface; The first interface is an Advanced High Performance Bus (AHS) interface that communicates with an AHS bus and is used to receive data transmission requests to transmit data to the target Flash device. The second interface is a high-performance peripheral bus interface that communicates with a high-performance peripheral bus and is used to receive configuration requests for configuring the access system. The access parameters also include control parameters, which are used to control the protocol flow. The control parameters include at least one of address length information and the number of empty instruction cycles. The address length information is used to determine whether to skip the address phase; the number of empty instruction cycles is used to determine the empty instruction cycles inserted between the address phase and the data phase. The system also includes: A phase adjustment module is used to adjust the sampling phase in order to acquire data returned by the target Flash device; the sampling phase is the relative phase between the sampling clock and the returned data. The system also includes a data buffer module; when the system operates in direct access mode, the data buffer module is configured in streaming mode, allowing data to be transmitted directly between the first interface and the protocol conversion module to minimize latency; when the system operates in indirect access mode, the data buffer module is configured in block mode, allowing data to be written to or read from the data buffer unit before being processed uniformly by the protocol conversion module.

2. The system according to claim 1, characterized in that, The direct access mode includes: Map the target Flash device to the memory address space of the access system; The memory address space is read from and written to complete the data transfer.

3. The system according to claim 2, characterized in that, The indirect access mode includes: The registers of the access system are configured to construct an access task for the target Flash device, so that the access system performs data transmission on the target Flash device according to the access task.

4. The system according to claim 3, characterized in that, The protocol conversion module is specifically used for: Determine the access parameters based on the access command; Based on the access parameters, a target protocol stage is obtained by selecting from multiple preset protocol stages. Based on the obtained target protocol phase, construct the protocol command sequence; Data is transmitted to the target Flash device via the protocol command sequence.

5. The system according to claim 4, characterized in that, The plurality of preset protocol phases include at least two of the following: chip select valid phase, instruction phase, and address phase; The chip select enable phase is used to activate the chip select signal; the instruction phase is used to send instruction codes; and the address phase is used to send addresses.

6. The system according to claim 5, characterized in that, The access parameters include at least one of the following: instruction code, address value, and data length; The instruction code is used to determine the content of the instruction stage; the address value is used to determine the content of the address stage; and the data length is used to determine the content of the data transmission stage.

7. The system according to claim 1, characterized in that, The phase adjustment module is specifically used for: The sampling clock is phase-shifted according to a preset delay value to adjust the sampling phase.

8. The system according to claim 7, characterized in that, The determination of the delay value includes: Write calibration data to the target Flash device at a first rate; Switch to the second rate and iterate through multiple delay values ​​to read back the calibration data until the read-back data matches the calibration data; the second rate is higher than the first rate.

9. A method for accessing a Flash device, characterized in that, The method is applied to the Flash device access system as described in any one of claims 1 to 8, and the method includes: Based on the type of the received access request, the corresponding access mode in the interface control module is selected; the access request includes a data transmission request for transmitting data to the target Flash device and a configuration request for configuring the access system; the access mode includes a direct access mode and an indirect access mode. Generate access commands based on the request type and corresponding access mode; Determine the access parameters based on the access command; Based on the access parameters, a sequence of protocol commands is generated from multiple preset protocol stages to transmit data with the target Flash device. The step of selecting the corresponding access mode in the interface control module based on the request type of the received access request includes: When a data transfer request to the target Flash device is received, the direct access mode is selected; When a configuration request to configure the access system is received, the indirect access mode is selected; The protocol conversion module includes a state transition control register. The protocol conversion module configures the state transition control register according to the access command. Each bit in the state transition control register corresponds to a preset protocol stage, which is used to enable or disable the execution of the preset protocol stage, thereby selecting from multiple preset protocol stages to achieve skipping of protocol stages. The interface control module includes a first interface and a second interface; the first interface is an Advanced High Performance Bus (AHS) interface that communicates with an AHS bus and is used to receive data transmission requests for data transmission to the target Flash device; the second interface is a High Performance Peripheral Bus (HSP) interface that communicates with a High Performance Peripheral Bus (HSP) and is used to receive configuration requests for configuring the access system. The access parameters also include control parameters, which are used to control the protocol flow. The control parameters include at least one of address length information and the number of empty instruction cycles. The address length information is used to determine whether to skip the address phase. The number of empty instruction cycles is used to determine the number of empty instruction cycles inserted between the address phase and the data phase. The method further includes: The sampling phase is adjusted by a phase adjustment module to acquire data returned by the target Flash device; the sampling phase is the relative phase between the sampling clock and the returned data. The method further includes: when the system operates in direct access mode, the data buffer module is configured in streaming mode, allowing data to be transmitted directly between the first interface and the protocol conversion module to minimize latency; when the system operates in indirect access mode, the data buffer module is configured in block mode, allowing data to be written to or read from the data buffer unit and then processed uniformly by the protocol conversion module.

10. The method according to claim 9, characterized in that, The step of selecting from a preset plurality of protocol stages based on the access parameters to generate a protocol command sequence for data transmission with the target Flash device includes: Based on the access parameters, a target protocol stage is obtained by selecting from multiple preset protocol stages. Based on the obtained target protocol phase, construct the protocol command sequence; Data is transmitted to the target Flash device via the protocol command sequence.

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