FPGA online program upgrading method based on QSPI Flash

Abstract

The invention discloses an FPGA (Field Programmable Gate Array) online program upgrading method based on QSPI (Quantitative Serial Peripheral Interface) Flash. The FPGA online program upgrading method comprises the following steps: S1, loading a boot program after an FPGA is powered up; s2, accessing a software online upgrading flag bit within power-on preset time; s3, if the online upgrading flag bit is 1, resetting the online upgrading flag bit, and caching the current state at the same time; if the online upgrading flag bit is 0, returning to the step S2; s4, the online upgrading flag bit is accessed again after a preset period is delayed, if the online upgrading flag bit is inconsistent with the online upgrading flag bit in the step S3, the step S2 is executed, and if the online upgrading flag bit is consistent with the online upgrading flag bit in the step S3 and is 1, online program upgrading is conducted. The method has a very good effect on remote software updating of the infrared imaging product.

Description

Technical Field

[0001] The present invention belongs to the technical field of application of infrared imaging product components and software development, and particularly relates to an FPGA online program upgrade method based on QSPI Flash. Background Art

[0002] Currently, 7-series FPGAs are often used in infrared imaging products for preprocessing functions of image algorithms. Due to changes in system requirements, the update and optimization of FPGAs have become a trend. The traditional FPGA update method is completed through the JTAG interface. For products assembled as a whole, disassembly is often required, and the upgrade process is complex and inefficient. Summary of the Invention

[0003] The technical problem solved by the present invention is: overcoming the deficiencies of the prior art, providing an FPGA online program upgrade method based on QSPI Flash, which has very good effects in realizing software remote update of infrared imaging products.

[0004] The object of the present invention is achieved through the following technical solutions: an FPGA online program upgrade method based on QSPI Flash, including: Step S1: After the FPGA is powered on, load the boot program; Step S2: Access the software online upgrade flag bit within a preset power-on time; Step S3: If the online upgrade flag bit is 1, reset the online upgrade flag bit and cache the current state at the same time; if the online upgrade flag bit is 0, return to Step S2; Step S4: After a preset period of delay, access the online upgrade flag bit again. If it is inconsistent with the online upgrade flag bit in Step S3, return to Step S2. If they are consistent and the value is 1, perform online program upgrade.

[0005] In the above FPGA online program upgrade method based on QSPI Flash, the online program upgrade includes: Step S5: After the host computer decomposes the program file to be burned, send the write instruction and the decomposed program file to the FPGA through the AXI UART; the FPGA sends the decomposed program file to the QSPI Flash through the AXIQuad SPI module by means of the loaded boot area configuration bitstream; after sending is completed, send the write instruction feedback to the host computer through the AXI UART; Step S6: After the host computer receives the write instruction feedback, send the read instruction request to the FPGA through the AXI UART. The FPGA reads back the file in the QSPI Flash through the AXIQuad SPI module and sends the read-back file to the host computer through the AXI UART; Step S7: The host computer compares the read-back file with the decomposed program file. If the comparison results are consistent, repeat Steps S5 to S6 until all the program files to be burned are sent.

[0006] In the above FPGA online program upgrade method based on QSPI Flash, 3 program areas are divided inside the Flash. The 3 program areas are the boot area, i.e., the program boot area, the M area, i.e., the program update area, and the G area, i.e., the program backup area.

[0007] In the above FPGA online program upgrade method based on QSPI Flash, after the FPGA is powered on, the boot program is loaded. When no online upgrade instruction is received 1.5 s after the program in the boot area is loaded, it will automatically jump to load the configuration bitstream in the M area. If the M configuration bitstream fails to be loaded, the G area configuration bitstream will be loaded.

[0008] In the above FPGA online program upgrade method based on QSPI Flash, after the host computer issues a write instruction and receives the write instruction report, it will initiate a second write instruction request.

[0009] In the above FPGA online program upgrade method based on QSPI Flash, the online upgrade flag bit is accessed again after a 10 ms delay.

[0010] In the above FPGA online program upgrade method based on QSPI Flash, during the software upgrade process, the host computer will divide the programming file, divide the file according to the size of the Flash page, and fill 0 for the data less than the page size.

[0011] In the above FPGA online program upgrade method based on QSPI Flash, the size of the page is 256 byte.

[0012] In the above FPGA online program upgrade method based on QSPI Flash, during the software upgrade process, after the host computer sends a write Flash instruction, it waits for the write instruction report and then initiates a read instruction request. The received read-back file is compared with the decomposed program file. If they are inconsistent, the write Flash request for this page will be initiated again. If an error is reported after three requests, the program upgrade will be stopped and the inconsistent position information will be reported.

[0013] A computer-readable storage medium, on which a computer program is stored. When the computer program is run by a processor, it implements the FPGA online program upgrade method based on QSPI Flash.

[0014] The present invention has the following beneficial effects compared with the prior art:

[0015] (1) Through steps S2, S3, and S4 of the present invention, by repeatedly judging the online flag bit, it can effectively prevent the FPGA from executing an incorrect program after being powered on and receiving an incorrect instruction;

[0016] (2) By partitioning the program areas of the boot area, G area, and M area of the Flash in the present invention, it is possible to prevent the program upgrade from failing midway, resulting in the FPGA being unable to work properly.

[0017] (3) By comparing the received read-back file with the decomposed program file in the present invention, it is possible to prevent error codes from occurring in the transmission link due to electromagnetic interference, which may cause the Flash to solidify an incorrect program file, resulting in the FPGA loading an incorrect file and being unable to work properly. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention. Moreover, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0019] Figure 1 is a schematic diagram of the FPGA online program upgrade process based on QSPI Flash provided by an embodiment of the present invention;

[0020] Figure 2 is a schematic diagram of the QSPI Flash cache address provided by an embodiment of the present invention;

[0021] Figure 3 is a schematic diagram of the boot program framework provided by an embodiment of the present invention;

[0022] Figure 4 is a schematic diagram of the FPGA reading and writing process to the Flash provided by an embodiment of the present invention;

[0023] Figure 5 is a schematic diagram of the write operation provided by an embodiment of the present invention;

[0024] Figure 6 is a schematic diagram of the read operation provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be completely conveyed to those skilled in the art. It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other. Hereinafter, the present invention will be described in detail with reference to the drawings and in combination with the embodiments.

[0026] Figure 1It is a schematic diagram of the FPGA online program upgrade process based on QSPI Flash provided by an embodiment of the present invention. As Figure 1 shown, the FPGA online program upgrade method based on QSPI Flash includes:

[0027] Step S1: After the FPGA is powered on, load the boot program;

[0028] Step S2: Access the software online upgrade flag bit within a preset time after power-on;

[0029] Step S3: If the online upgrade flag bit is 1, reset the online upgrade flag bit and cache the current state at the same time; if the online upgrade flag bit is 0, return to Step S2;

[0030] Step S4: After a preset period of delay, access the online upgrade flag bit again. If it is inconsistent with the online upgrade flag bit in Step S3, return to Step S2. If they are consistent and the flag bit is 1, perform the online program upgrade.

[0031] The online program upgrade includes:

[0032] Step S5: After the host computer decomposes the program file to be burned, send the write instruction and the decomposed program file to the FPGA through the AXI UART; the FPGA sends the decomposed program file to the QSPI Flash through the AXIQuad SPI module by using the loaded boot area configuration bitstream; after the sending is completed, send the write instruction feedback to the host computer through the AXI UART;

[0033] Step S6: After the host computer receives the write instruction feedback, send a read instruction request to the FPGA through the AXI UART. The FPGA reads back the file in the QSPI Flash through the AXIQuad SPI module and sends the read-back file to the host computer through the AXI UART;

[0034] Step S7: The host computer compares the read-back file with the decomposed program file. If the comparison results are consistent, repeat Step S5 to Step S6 until all the program files to be burned are sent.

[0035] Specifically, the method includes the following steps:

[0036] Step 1: After the product is powered on, load the boot program.

[0037] Step 2: Access the software online upgrade flag bit (1 for upgrade, 0 for no upgrade) within 1.5 s after power-on;

[0038] When a device such as a host computer initiates a software online upgrade request, a variable is declared to represent the software upgrade request status. After receiving this variable, the FPGA sets the online upgrade flag bit to 1.

[0039] The variable being 0x0000 indicates idle, 0XAAxx indicates an online upgrade instruction, 0XAAAA indicates a read Flash instruction, 0xAA55 indicates a write Flash instruction, and 0X55xx indicates a completed online upgrade instruction. When the host computer performs read / write operations on the Flash, it needs to first initiate a write request and then initiate a read request after receiving the write acknowledgment.

[0040] Step 3: If the status flag bit is 1, reset this flag bit and cache the current status simultaneously. If the status flag bit is 0, return to Step 2.

[0041] Step 4: After a 10 ms cycle delay, access the online upgrade flag bit again. If it is inconsistent with the cached flag bit in Step 3, return to Step 2. If they are consistent and the flag bit is 1, perform an online program upgrade.

[0042] Step 5: Perform an online program upgrade.

[0043] Step 6: End the online program upgrade.

[0044] The Flash is internally divided into 3 program areas: the boot area (program boot area), the M area (program update area), and the G area (program backup area). After the product is powered on, the boot program is loaded. If no online upgrade instruction is received 1.5 s after the boot area program is loaded, it will automatically jump to load the M configuration bitstream. If the M configuration bitstream fails to load, the G configuration bitstream will be loaded, ensuring the loading time while providing program backup to prevent the system from crashing.

[0045] The host computer will initiate a second write instruction request only after initiating a write instruction and receiving the write instruction acknowledgment, preventing data stream blockage during Flash programming, which may cause the online upgrade to fail.

[0046] After resetting the status flag bit, access the status flag bit again after a 10 ms cycle delay. This is to prevent misjudgment of instructions caused by incorrect instructions from the host computer or external electromagnetic interference.

[0047] During the software upgrade process, the host computer will divide the programming file and divide the file according to the size of the Flash page (256 bytes). Data less than 256 bytes is padded with 0s, ensuring that the bitstream in the boot area does not occupy too many resources.

[0048] During the software upgrade process, after the host computer sends a write Flash instruction, it waits for the write instruction feedback and then initiates a read instruction request. It compares the received read data. If they are inconsistent, it will initiate a write Flash request for the same page again. If it reports an error after three requests, the program upgrade will stop and the inconsistent position information will be reported.

[0049] As Figure 1 shown, the present invention provides an FPGA online program upgrade method based on QSPI Flash. After the product is powered on, it loads the boot program. The boot program accesses the software online upgrade flag bit (1 for upgrade, 0 for no upgrade) within 1.5 s after startup. If no online upgrade instruction is received after 1.5 s, it loads the M configuration bitstream. If the M configuration bitstream fails to load, it loads the G configuration bitstream. When the status flag bit is 1, it resets the flag bit and caches the current status. After a 10 ms cycle delay, it accesses the online upgrade flag bit again. If the cached status is consistent and is 1, it performs an online program upgrade.

[0050] As Figure 2 shown, after the product is powered on, the FPGA will perform a loading operation according to the expected settings. Usually, the FPGA will actively read the configuration bitstream in the Flash. Specifically, the FPGA directly starts reading from address 0 of the Flash, first loads the configuration bitstream in the boot area, and then loads the starting address and IPROG command of the G area configuration bitstream after watchdog timing processing. After the FPGA reads the IPROG command, it skips the subsequent data and starts loading the M area configuration bitstream from the set address. When the M area configuration bitstream fails to load, it executes the G area configuration bitstream.

[0051] As Figure 3 shown, the program in the boot area includes an embedded soft-core Microblaze processor, a general serial interface AXI UART, and a general QSPI interface AXIQuad SPI.

[0052] As Figure 4 shown, the host computer divides the program to be burned into packages, usually according to the page size of the flash, and packs and reorganizes the burn instruction, burn address, and burn data, and sends them to the Microbalze through the serial port. The Microblaze processor reads and writes data to the Flash through the AXIQuad SPI.

[0053] As Figure 5 shown, the process of sending a write data packet needs to first send a write enable instruction, then an erase instruction, and then wait for the erase to end before sending a write enable instruction and a write data instruction to complete the writing to the Flash. After the write data is completed, a write feedback instruction is sent through the serial port AXI UART.

[0054] As Figure 6 shown, the process of sending read data requires sending a read enable instruction first, then reading the data, and sending the read data to the host computer through the serial port AXI UART.

[0055] The host computer compares the read data with the written data. If they are inconsistent, it will initiate a write Flash request for this page again. If an error occurs after three requests, the program upgrade will be stopped, and the inconsistent position information will be reported. If they are consistent, the write operation for the next packet of data will be performed until all data is written and verified successfully.

[0056] This embodiment also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is run by a processor, it implements the FPGA online program upgrade method based on QSPI Flash.

[0057] This embodiment has a good effect in realizing the software remote update of the infrared imaging product. Through steps S2, S3, and S4 of this embodiment, by repeatedly judging the online flag bit, it can effectively prevent the FPGA from executing an incorrect program after being powered on and receiving an incorrect instruction; through the program area division of the boot area, G area, and M area of the Flash in this embodiment, it can prevent the program upgrade from failing halfway, resulting in the FPGA being unable to work properly; through comparing the received read-back file with the decomposed program file in this embodiment, it can prevent bit errors in the transmission link caused by electromagnetic interference, so that the Flash solidifies an incorrect program file, resulting in the FPGA loading an incorrect file and being unable to work properly.

[0058] Although the present invention has been disclosed above with preferred embodiments, it is not used to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the disclosed methods and technical contents without departing from the spirit and scope of the present invention. Therefore, any simple modification, equivalent change, and modification made to the above embodiments according to the technical essence of the present invention without departing from the technical solution of the present invention all belong to the protection scope of the technical solution of the present invention.

Claims

1. An FPGA online program upgrade method based on QSPI Flash, characterized in that Including: Step S1: After the FPGA is powered on, load the boot program; Step S2: Access the software online upgrade flag bit within a preset power-on time; Step S3: If the online upgrade flag bit is 1, reset the online upgrade flag bit and cache the current state simultaneously; if the online upgrade flag bit is 0, return to Step S2; Step S4: After a preset period of delay, access the online upgrade flag bit again. If it is inconsistent with the online upgrade flag bit in Step S3, return to Step S2. If it is consistent and is 1, perform an online program upgrade.

2. The FPGA online program upgrade method based on QSPI Flash according to claim 1, characterized in that: The online program upgrade includes: Step S5: After the host computer decomposes the program file to be burned, send the write instruction and the decomposed program file to the FPGA through the AXI UART; the FPGA sends the decomposed program file to the QSPI Flash through the AXI QuadSPI module by means of the loaded boot area configuration bitstream; after sending is completed, send the write instruction feedback to the host computer through the AXI UART; Step S6: After the host computer receives the write instruction feedback, send a read instruction request to the FPGA through the AXI UART. The FPGA reads back the file in the QSPI Flash through the AXI QuadSPI module and sends the read-back file to the host computer through the AXI UART; Step S7: The host computer compares the read-back file with the decomposed program file. If the comparison results are consistent, repeat Steps S5 to S6 until all the program files to be burned are sent.

3. The method for online program upgrade of FPGA based on QSPI Flash according to claim 1, wherein: The Flash is internally divided into 3 program areas, namely the boot area (i.e., the program boot area), the M area (i.e., the program update area), and the G area (i.e., the program backup area).

4. The FPGA online program upgrade method based on QSPI Flash according to claim 3, characterized in that: After the FPGA is powered on and loads the boot program, if no online upgrade instruction is received 1.5 s after the boot area program is loaded, it will automatically jump to load the M area configuration bitstream. If the M configuration bitstream loading fails, then load the G area configuration bitstream.

5. The FPGA online program upgrade method based on QSPI Flash according to claim 2, characterized in that: The host computer will initiate a second write instruction request only after initiating a write instruction and receiving the write instruction feedback.

6. The FPGA online program upgrade method based on QSPI Flash according to claim 1, characterized in that: Access the online upgrade flag bit again after a 10 ms delay.

7. The method for online program upgrade of FPGA based on QSPI Flash according to claim 2, wherein: During the software upgrade process, the host computer will divide the burned file, divide the file according to the size of the Flash page, and fill 0 for the data less than the page size.

8. The method for online program upgrading of FPGA based on QSPI Flash according to claim 7, wherein: The size of the page is 256 byte.

9. The method for online program upgrade of FPGA based on QSPI Flash according to claim 2, characterized in that: During the software upgrade process, after the host computer sends a write Flash instruction, it waits for the write instruction feedback and then initiates a read instruction request, compares the received read-back file with the decomposed program file. If they are inconsistent, it will initiate a write Flash request for this page again. If an error occurs after three requests, stop the program upgrade and report the inconsistent position information.

10. A computer-readable storage medium, characterized in that, A computer program is stored thereon, and when the computer program is run by a processor, the method described in any one of claims 1 to 9 is implemented.

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