Startup system, method, device, electronic device, medium and product

Abstract

The present application discloses a startup system, method, device, electronic device, medium and product, and relates to the field of server technology. Through the present application, a second processor is set to record first debugging information generated in the boot phase and generate a log, and the first processor can obtain the log. The complete log is collected and reported through the one-click log collection of the first processor, thereby avoiding the problem of loss of the first debugging information due to incomplete loading of the file system in the boot phase, thereby improving the integrity of the log.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to startup systems, methods, devices, electronic devices, media, and products. Background Art

[0002] During operation, the server generates various debugging messages that reflect the server's operating status, including normal and abnormal conditions. Logs are generated based on these debugging messages and stored in the file system, allowing maintenance personnel to use them to perform server maintenance.

[0003] In practice, multiple debugging messages include debugging information from the startup process, which includes mounting the file system. After the file system is mounted, the server can use the file system to store data. Debug information generated before the file system is mounted during the startup process cannot be effectively stored, resulting in incomplete logs. Summary of the Invention

[0004] The present application provides a startup system, method, device, electronic device, medium and product to at least solve the problem of incomplete logs in the related art.

[0005] The present application provides a startup system, comprising: a first processor, a second processor, a first memory, and a first controller; wherein the first processor is connected to the first memory, the first processor is used to execute a boot loader to enter a boot phase, the boot phase generates first debugging information, the first processor is further used to obtain the first debugging information from the first memory after completing the startup of an operating system and generate a log based on the first debugging information, the first memory is used to store the first debugging information; the first controller is used to associate the serial port of the first processor with the serial port of the second processor, the first controller is used to control the first processor to send the first debugging information to the second processor during the boot phase; the second processor is also connected to the first memory, and the second processor is used to write the first debugging information into the first memory.

[0006] The present application also provides a startup method, including: executing a boot loader through a first processor to enter a boot phase, wherein the boot phase generates first debugging information; associating the serial port of the first processor with the serial port of the second processor through a first controller, so that the second processor receives the first debugging information and writes the first debugging information into a first memory; receiving the heartbeat information of the first processor through the first controller, switching the access control right of the first memory through the first controller, and opening or closing the serial port connection between the first processor and the second processor and setting a flag; executing operating system startup through the first processor, reading the flag set by the first controller after completing the operating system startup, obtaining the first debugging information from the first memory to generate a log, and storing the log in the log directory of the first processor.

[0007] The present application also provides a startup device, including: a recording module, used to execute a boot loader through a first processor to enter a boot phase, and the boot phase generates first debugging information; a sending module, used to associate the serial port of the first processor with the serial port of the second processor through a first controller, so that the second processor receives the first debugging information and writes the first debugging information into a first memory; the sending module is also used to receive the heartbeat information of the first processor through the first controller, switch the access control right of the first memory through the first controller, and open or close the serial port connection between the first processor and the second processor and set a flag; a generation module, used to execute operating system startup through the first processor, read the flag set by the first controller after completing the operating system startup, obtain the first debugging information from the first memory to generate a log, and store the log in the log directory of the first processor.

[0008] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned startup methods when executing the computer program.

[0009] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned startup methods are implemented.

[0010] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned startup methods when executed by a processor.

[0011] Through this application, a second processor is set to record the first debugging information generated during the boot phase and generate a log, and the first processor can obtain the log. The complete log is collected and reported through the one-click log collection of the first processor, thereby avoiding the problem of the first debugging information being lost due to incomplete loading of the file system during the boot phase, thereby improving the integrity of the log. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0013] Figure 1 A schematic diagram of an application scenario of a startup system provided in an embodiment of the present application;

[0014] Figure 2 A schematic diagram of the structure of a startup system provided in an embodiment of the present application;

[0015] Figure 3 A schematic diagram of the structure of the startup system provided in an embodiment of the present application;

[0016] Figure 4 A schematic diagram of the structure of the startup system provided in an embodiment of the present application;

[0017] Figure 5 A schematic diagram of the structure of the startup system provided in an embodiment of the present application;

[0018] Figure 6 A schematic diagram of the structure of the startup system provided in an embodiment of the present application;

[0019] Figure 7 A schematic diagram of a startup method provided in an embodiment of the present application;

[0020] Figure 8 A schematic diagram of a startup method provided in an embodiment of the present application;

[0021] Figure 9 A schematic diagram of the startup sequence provided in an embodiment of the present application;

[0022] Figure 10 A schematic structural diagram of a starting device provided in an embodiment of the present application;

[0023] Figure 11 A schematic structural diagram of a starting device provided in an embodiment of the present application;

[0024] Figure 12 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0026] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0027] It should be noted that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like, indicating positions or relationships, are based on the positions or relationships shown in the accompanying drawings and are intended solely for ease of description and simplification of the present application. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting the present application. The terms "mounted," "connected," and "connected" should be interpreted broadly, and may include, for example, fixed, removable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; and internal communication between two components. The terms "parallel," "perpendicular," and "equal" encompass the described conditions and conditions similar to the described conditions, provided that the range of the similar conditions is within an acceptable range of deviation, as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes both absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism may be, for example, within 5°; "perpendicular" includes both absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity may also be, for example, within 5°. "Equal" includes both absolute equality and approximate equality, where the acceptable deviation range for approximate equality may be, for example, that the difference between the two is less than or equal to 5% of either. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0028] For example, debugging information is data generated by a program or system during operation for diagnosing problems. It can include error messages, logs, stack traces, variable status, and more. Operations and maintenance personnel can use this debugging information to accurately locate the location and type of the fault, thereby effectively resolving the problem. Debugging information is recorded in logs. The more complete the debugging information in the logs, the more accurately maintenance personnel can perform their work. Therefore, log integrity is crucial. This debugging information includes debugging information during the startup process.

[0029] Exemplarily, the startup process of a first processor of a server's baseboard management controller (BMC) may include a boot phase and an initialization phase. The boot phase includes: the server is powered on, the first processor loads a boot loader from flash memory, and the first processor initializes the boot loader. The initialization phase includes: the first processor loads an operating system kernel using the boot loader, the first processor runs the operating system kernel, and the first processor mounts a file system. After the boot phase and initialization phase are complete, the first processor can operate normally.

[0030] In related technologies, during the boot phase of the first processor, the debug information generated cannot be effectively stored because the file system is not mounted. If the first processor fails to boot, the loss of debug information makes it difficult for maintenance personnel to locate the fault. Retesting by connecting a serial line and analyzing the serial printout after the fault is reproduced leads to high maintenance costs.

[0031] In this application, the second processor pre-mounts the file system and stores the debugging information of the first processor during the boot phase through the second processor. Even if the first processor fails during the boot phase, the debugging information can still be effectively stored, thereby reducing the information accuracy in the log and improving the integrity of the log.

[0032] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0033] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the startup system depends, the specific application environment architecture or specific hardware architecture is described here. Figure 1 , Figure 1 This is a schematic diagram of an application scenario of a startup system. The startup system includes a processor and a memory. The memory is used to execute startup and record logs. The memory is used to store logs. The stored logs can be extracted for maintenance of the startup system.

[0034] In practice, if the log contains complete debugging information, maintenance personnel can accurately locate faults based on the log. If the log does not contain the debugging information required by maintenance personnel, they must retest the serial line to locate the fault, which is inefficient. Therefore, improving log integrity is key to improving maintenance efficiency.

[0035] Figure 2 A schematic diagram of the structure of a startup system provided in an embodiment of the present application is shown in FIG. Figure 2As shown, an embodiment of the present application provides a startup system, comprising: a first processor, a second processor, a first memory, and a first controller; wherein,

[0036] The first processor is connected to the first memory, the first processor is used to execute the boot loader to enter the boot phase, the boot phase generates first debugging information, the first processor is further used to obtain the first debugging information from the first memory after completing the startup of the operating system and generate a log based on the first debugging information, and the first memory is used to store the first debugging information;

[0037] The first controller is used to associate the serial port of the first processor with the serial port of the second processor, and the first controller is used to control the first processor to send first debugging information to the second processor during the boot phase;

[0038] The second processor is also connected to the first memory, and is used to write the first debugging information into the first memory.

[0039] Exemplarily, the first processor is configured to execute a startup process, which may include a boot phase and an initialization phase. The second processor is configured to store first debug information generated during the boot phase of the first processor in a first memory in real time to prevent loss of the first debug information. The first controller is configured to connect the first processor and the second processor while the first processor is executing the boot phase, so that the first debug information can be sent from the first processor to the second processor.

[0040] Exemplarily, the second processor is configured to store the first debugging information instead of the first processor when the first processor executes the boot phase, thereby improving the integrity of the log.

[0041] In conjunction with a scenario example, when the first processor executes the boot phase, the first processor does not mount the file system and cannot store the first debugging information. The first controller connects the first processor and the second processor. The debugging information generated by the first processor is sent by the first processor to the second processor, and the second processor stores the first debugging information in the first memory. After the first processor completes the boot phase, the first processor can store the debugging information. At this time, the second processor is not required to replace the storage of the debugging information. The first controller controls the first processor and the second processor to disconnect. After the first processor completes the startup, the first processor obtains the first debugging information from the first memory and completes the log with the first debugging information.

[0042] Optionally, the first controller may be a complex programmable logic device (CPLD).

[0043] Optionally, the first processor reads a boot loader from the first memory and runs the boot loader to start up.

[0044] A feasible implementation method is Figure 3 A schematic diagram of the structure of the startup system provided in the embodiment of the present application is shown in FIG. Figure 3 As shown, the startup system also includes: a first transmitter and a second transmitter; wherein the first controller is used to control the connection and disconnection between the first transmitter and the second transmitter, the first transmitter is used to transmit the first debugging information during the boot phase, and the second transmitter is used to transmit the first debugging information to the second processor.

[0045] Exemplarily, the first transmitter and the second transmitter are configured to transmit the first debugging information in real time, that is, when the first processor generates the first debugging information, the first debugging information is transmitted to the second processor in real time.

[0046] Optionally, the first transmitter and the second transmitter are Universal Asynchronous Receiver / Transmitter (UART). A UART is a serial communication interface used to transmit data between devices asynchronously (without a unified clock signal). It converts parallel data from the transmitter into a serial bit stream, or converts serial data from the receiver into parallel data. UART achieves synchronization using a pre-agreed bit rate. Requiring only two signal lines and a ground line, UART has the advantage of simple hardware requirements and can enable communication with simple debugging.

[0047] Exemplarily, when the first processor executes the booting phase, the first controller controls the communication between the first transmitter and the second transmitter, thereby transmitting the first debugging information.

[0048] In this feasible implementation, the first debugging information can be transmitted in real time through the first transmitter and the second transmitter, thereby avoiding information loss and improving the integrity of the log.

[0049] A feasible implementation method is Figure 4 A schematic diagram of the structure of the startup system provided in the embodiment of the present application is shown in FIG. Figure 4 As shown, the startup system also includes a switch; wherein the switch is connected to the first controller, the first transmitter, and the second transmitter; the first controller is used to disconnect the connection between the first transmitter and the second transmitter through the switch when receiving the heartbeat information of the first processor sent by the first transmitter; the first controller is used to connect the connection between the first transmitter and the second transmitter through the switch when no heartbeat information is received within a preset time.

[0050] Exemplarily, the first controller is connected to the switch, and the first controller controls the switch to be turned on and off, so as to control the connection between the first transmitter and the second transmitter to be turned on and off.

[0051] Optionally, in a default state, the switch is in a connected state, in which case the first transmitter and the second transmitter are connected, so that when the system is powered on, the first transmitter can transmit the first debugging information to the second transmitter without switching the switch connection state. After the first processor completes startup, the first processor sends a heartbeat message to the first controller, causing the first controller to control the switch to disconnect.

[0052] In combination with the scenario example, after the first processor is started, the first processor can store the first debugging information normally without the need for the second processor. The first controller determines through the heartbeat information that the first processor has started, and then controls the switch to disconnect to stop the second processor from storing debugging information.

[0053] For example, if the first controller does not receive heartbeat information within a preset period of time, it means that the first processor has been shut down or is abnormal. By controlling the switch to be connected, the first processor can transmit the first debugging information to the second processor for storage when it is started next time.

[0054] Optionally, the first processor transmits heartbeat information to the second processor. If the second processor receives the heartbeat information, it stops storing the first debugging information in the first memory to avoid conflict between the first processor and the second processor in storing the first debugging information.

[0055] In this feasible implementation, the first controller can accurately determine the startup state of the first processor through the heartbeat information, thereby accurately controlling the switch to improve the accuracy of the log.

[0056] In a feasible implementation method, the startup system also includes a startup controller; the second processor is a coprocessor or a single-chip microcomputer; wherein, the first processor inside the startup controller is connected to the coprocessor, and the first processor is used to send a wake-up instruction to the coprocessor to enable the coprocessor to run; or, the single-chip microcomputer outside the startup controller is connected to the first processor inside the startup controller, and the single-chip microcomputer is used to start after the first processor starts according to the power-on sequence.

[0057] Exemplarily, if the second processor is a coprocessor, the first processor and the second processor are both located inside the startup controller, and there is a communication connection between the first processor and the second processor, so that instructions can be sent.

[0058] Exemplarily, after powering on, the first processor sends a wake-up command to the second processor to start the second processor. The second processor runs a real-time operating system (RTOS). Compared to the first processor, the second processor takes less time to start up and can quickly complete startup. Thus, while the first processor is in the booting phase, the second processor has already completed startup and can store the first debugging information.

[0059] Optionally, if the second processor is a single-chip microcomputer outside the boot controller, the second processor can be started by controlling the power-on sequence. Specifically, the first processor is controlled to power on a preset time later than the second processor so that the second processor has completed startup when the first processor is in the boot phase.

[0060] In this feasible implementation, by controlling the startup of the second processor, the second processor can be started when the first processor is in the boot phase, so that the second processor can effectively store the first debugging information of the first processor, thereby improving the integrity of the log.

[0061] For example, in a boot controller such as a BMC, some BMCs include a first processor and a coprocessor, and the coprocessor can be used as a second processor to store the first debugging information. In other BMCs, the first processor is not included in the coprocessor, and a microcontroller external to the BMC is used as a second processor to store the first debugging information.

[0062] For example, if the second processor is a coprocessor, the first memory is located inside the boot controller and is used by devices inside the boot controller. If the second processor is a single-chip microcomputer, the first memory is located outside the boot controller and can be shared by devices inside and outside the boot controller.

[0063] For a BMC with a coprocessor, the coprocessor runs a real-time operating system (RTOS). The first processor uses the first transmitter, the coprocessor uses the second transmitter, and the first and coprocessors time-share the first memory. When the server is powered on, Core 0 of the first processor loads the Boot Read-Only Memory (BootROM) and loads the top Universal Boot Loader (Uboot) code from the first memory into the internal Random Access Memory (RAM). The internal RAM runs the Secondary Program Loader (SPL) code. The SPL wakes Core 1 to load the RTOS, and the RTOS on the coprocessor begins running. Core 0 initializes the Double Data Rate Synchronous Dynamic Random-Access Memory (DDR) using the SPL and loads the remaining Uboot code into the DDR. Uboot begins running, initializes the serial port, and debug information begins to be output to the serial port, booting the first processor system. The first controller begins operation upon power-up and connects the first and second transmitters by default. After Uboot completes serial port initialization, the first debug information on the first processor is output from the first transmitter. The coprocessor's real-time operating system receives the first debug information from the second transmitter and writes it to a designated area in the first memory. When the first processor completes system startup, it periodically sends heartbeat information to the first controller. After receiving the heartbeat information from the first device, the first controller disconnects the first and second transmitters. After receiving a disconnection indicator from the first controller, the first processor reads the first debug information from the designated area in the first memory and saves it to a log file in its own file system. The first controller continuously monitors the first processor's heartbeat information, and the coprocessor's real-time operating system continuously monitors the second transmitter. If the first controller fails to detect the first processor's heartbeat information, it reconnects the first and second transmitters. The coprocessor's real-time operating system then receives debug information from the second transmitter and writes it to the first memory. This allows operations personnel to access operation logs for all time periods, including logs from the startup process.

[0064] For a BMC without a coprocessor, a real-time operating system is run through a single-chip microcomputer. The first processor uses the first transmitter, and the single-chip microcomputer uses the second transmitter. The first processor and the single-chip microcomputer time-share the first memory through a multiplexer, and the first controller controls the multiplexer. The second memory is exclusive to the first processor. When the server is powered on, the first processor is powered on a preset time later than the single-chip microcomputer. The first processor loads the BootROM and runs, imports the top Uboot code from the second processor into the internal RAM, and the internal RAM runs the SPL code. The SPL initializes the DDR and imports the remaining Uboot code into the DDR. U-Boot starts running, initializes the serial port, and the first debugging information begins to be output from the serial port, guiding the first processor's operating system to start. The single-chip microcomputer runs the real-time operating system. The first controller starts running when powered on, and by default, connects the first transmitter to the second transmitter and connects the first memory to the single-chip microcomputer. After the first processor's Uboot completes serial port initialization, the first debug information for the first device is output from the first processor's first transmitter. The second processor's real-time operating system receives the first debug information from the second processor's second transmitter and writes it to a designated area in the first memory. Because the microcontroller is powered on first and operates as a real-time operating system, booting takes only seconds. Therefore, while the first processor's first debug information is output from the first transmitter, the microcontroller can receive the first debug information from the second transmitter. After the first processor's system boot is complete, the first processor periodically sends heartbeat information to the first controller. Upon receiving the heartbeat information from the first device, the first controller disconnects the first and second transmitters and switches the first memory to the first processor. After receiving the disconnection flag from the first controller, the first processor reads the first debug information from the designated area in the first memory and saves it to a log file in its own file system. The first controller continuously monitors the first processor's heartbeat information, while the microcontroller's real-time operation monitors the second transmitter's serial port. If the first controller fails to detect the first processor's heartbeat information, it reconnects the first and second transmitters and connects the first memory to the microcontroller. The MCU's real-time operating system receives the debugging information from the second transmitter and writes it into the first memory. Therefore, the operation and maintenance personnel can obtain the BMC's operation logs for all time periods, including the startup process logs.

[0065] In this feasible implementation, the function of the second processor is realized by different devices, which can adapt to different application scenarios, thereby improving the versatility of the log generation solution.

[0066] In a feasible implementation, the second processor is a coprocessor, and the first processor obtains the boot loader from the first memory.

[0067] Exemplarily, in a scenario where the second processor is a coprocessor, the first processor and the second processor share a first memory, and the boot loader is stored in the first memory.

[0068] In this feasible implementation, the cost of starting the system can be reduced by sharing the first memory.

[0069] In a feasible implementation, the second processor is a single chip microcomputer, the first processor is connected to a second memory, the second memory is located outside the startup controller, and the first processor obtains the boot loader from the second memory.

[0070] Figure 5 A schematic diagram of the structure of the startup system provided in the embodiment of the present application is shown in FIG. Figure 5 As shown, for the scenario where the second processor is a single-chip microcomputer, the boot loader is stored in the second memory, and the first processor obtains the boot loader from the second memory.

[0071] Exemplarily, the second memory is a memory dedicated to the first processor.

[0072] Combined with the scenario example, taking the second processor as a single-chip microcomputer as an example, the first memory is located outside the boot controller, and devices outside the boot controller can share the first memory. At this time, the boot loader is stored in the second memory dedicated to the first processor to improve the security of the boot loader.

[0073] In this feasible implementation, the boot loader is stored in a memory dedicated to the first processor, which can improve the security of the boot loader and thus improve the reliability of the startup system.

[0074] A feasible implementation method is Figure 6 A schematic diagram of the structure of the startup system provided in the embodiment of the present application is shown in FIG. Figure 6 As shown, the startup system further includes a multiplexer; wherein the multiplexer is connected to the first processor, the second processor, and the first memory, and the multiplexer is used to switch the processor connected to the first memory according to the instruction of the first controller.

[0075] Exemplarily, the multiplexer switches the access of the first processor or the second processor to the first memory according to the control information, and at the same time, only one processor can access the first memory.

[0076] Optionally, the first controller sends control information to the multiplexer based on the received heartbeat information to control the multiplexer's connection mode. If the first controller receives the heartbeat information, the first controller sends control information to control the connection between the first processor and the first memory. If the first controller does not receive the heartbeat information within a preset time period, the first controller sends control information to control the connection between the second processor and the first memory.

[0077] Optionally, the multiplexer receives heartbeat information of the first processor, and switches the connection between the first processor or the second processor and the first memory according to the received heartbeat information.

[0078] In this feasible implementation, by switching the connection through the multiplexer, access conflicts between the first processor and the second processor can be avoided, thereby avoiding repeated storage of debugging information, thereby improving the accuracy of the log.

[0079] Figure 7 A schematic diagram of the startup method provided in the embodiment of the present application is shown in FIG. Figure 7 As shown, the embodiment of the present application provides a startup method, which is described in detail as follows:

[0080] S701: Execute a boot loader through a first processor to enter a boot phase, and generate first debugging information in the boot phase.

[0081] Exemplarily, the first processor generates debugging information in real time during operation, and the debugging information is used to generate a log, including debugging information during the startup process. The startup process of the operating system of the first processor may include a boot phase and an initialization phase, and the first debugging information is debugging information during the boot phase.

[0082] S702 . Associate the serial port of the first processor with the serial port of the second processor through the first controller, so that the second processor receives the first debugging information and writes the first debugging information into the first memory.

[0083] For example, during the booting phase, the first processor does not mount the file system, and the first processor cannot effectively store the first debugging information in the first processor. If the boot fails, the first debugging information will be lost, resulting in an incomplete log.

[0084] For example, the second processor runs a real-time operating system, which has the advantage of fast startup. While the first processor is booting the operating system, the second processor has already completed the booting of the operating system and mounted the file system, enabling the storage of debug information. During the boot phase, the first processor sends the first debug information to the second processor in real time as it is generated. This allows the second processor to store the first debug information in the first memory in real time, thereby preventing the loss of debug information.

[0085] Optionally, the first processor and the second processor transmit information to coordinate which processor currently uses the first memory, so as to implement time-sharing multiplexing of the first memory and avoid conflicts in data storage between the first processor and the second processor.

[0086] S703: Receive heartbeat information of the first processor through the first controller, switch access control rights of the first memory through the first controller, open or close the serial port connection between the first processor and the second processor and set a flag.

[0087] Illustratively, after receiving the heartbeat information, the first controller controls the first memory to have access control rights to the first memory, so that after the first processor completes booting of the operating system, the first processor obtains the first debugging information from the first memory.

[0088] S704: Execute operating system startup through the first processor, read the flag set by the first controller after the operating system startup is completed, obtain first debugging information from the first memory to generate a log, and store the log in the log directory of the first processor.

[0089] Exemplarily, after the operating system is started, the first processor can store debugging information and generate logs normally, and the second processor no longer stores the debugging information of the first processor. The first processor obtains the first debugging information stored by the second processor from the first memory and generates a log of the first debugging information.

[0090] Optionally, the log is stored in a log file of the first processor, so that operation and maintenance personnel can obtain a complete log including the first debugging information.

[0091] The startup method provided by the embodiment of the present application includes: executing a boot loader through a first processor to enter the boot phase, and generating first debugging information in the boot phase; associating the serial port of the first processor with the serial port of the second processor through a first controller, so that the second processor receives the first debugging information and writes the first debugging information into the first memory; receiving the heartbeat information of the first processor through the first controller, switching the access control right of the first memory through the first controller, and opening or closing the serial port connection between the first processor and the second processor and setting a flag; executing the operating system startup through the first processor, reading the flag set by the first controller after completing the operating system startup, obtaining the first debugging information from the first memory to generate a log, and storing the log in the log directory of the first processor. The above scheme, by setting the second processor to record the first debugging information generated in the boot phase and generate a log, and the first processor can obtain the log, and the complete log is collected and reported through the one-key log of the first processor, thereby avoiding the problem of the first debugging information being lost due to the incomplete loading of the file system in the boot phase, thereby improving the integrity of the log.

[0092] Based on any of the above embodiments, Figure 8 , describes the detailed process of the startup method.

[0093] Figure 8 This is a flow chart of a startup method provided in an embodiment of the present application. Figure 8 As shown, the method includes:

[0094] S801: Execute a boot loader through a first processor to enter a boot phase, and generate first debugging information in the boot phase.

[0095] It should be noted that the execution process of S801 refers to S701 and will not be repeated here.

[0096] S802: Send first debugging information to the first transmitter, so that the first transmitter transmits the first debugging information to the second processor through the second transmitter.

[0097] Exemplarily, the first transmitter and the second transmitter are UARTs, and after the first processor generates the first debugging information, the debugging information is transmitted to the second processor in real time through the first transmitter and the second transmitter.

[0098] S803: Send heartbeat information to the first controller via the first processor at preset intervals.

[0099] Exemplarily, the heartbeat information is sent after the first processor completes the startup of the operating system. After receiving the heartbeat information, the first controller can clearly know that the first processor has completed the startup of the operating system.

[0100] Exemplarily, the first controller determines whether the operating system of the first processor is in a running state according to a preset time length.

[0101] In this example scenario, the first controller sets a timer with a preset duration. If the first controller receives a heartbeat message before the timer expires, the first processor is considered to be in operation and the timer is reset. If no heartbeat message is received before the timer expires, the first processor has stopped operating or has experienced a fault.

[0102] Optionally, the preset duration may be dynamically adjusted according to the working state of the first processor, and after the preset duration is adjusted, it is synchronized to the first controller in real time.

[0103] Based on the above implementation manner, by setting a preset duration, the frequency at which the first processor sends heartbeat information can be controlled to reduce the energy consumption of the first processor.

[0104] S804: If the first controller receives the heartbeat information, the first controller disconnects the first transmitter and the second transmitter, and sends a disconnection signal to the first processor through the first controller.

[0105] For example, when the first controller receives heartbeat information, it indicates that the operating system of the first processor has completed startup. In this case, the second processor does not need to store the debugging information of the first processor, and the first processor does not need to send debugging information to the second processor. The connection between the first transmitter and the second transmitter can be disconnected to stop the first processor from sending debugging information to the second processor.

[0106] Exemplarily, the disconnection information is used to enable the first processor to clearly know that the connection between the first transmitter and the second transmitter has been disconnected, that is, the debugging information of the first processor is no longer transmitted to the second processor.

[0107] In a feasible implementation, a switch is included between the first transmitter and the second transmitter; the connection between the first transmitter and the second transmitter can be disconnected by the following method, including: controlling the switch to disconnect by the first controller to disconnect the connection between the first transmitter and the second transmitter.

[0108] Exemplarily, the switch quickly responds to the received electrical signal and controls the connection or disconnection.

[0109] In this example scenario, a switch connects a first transmitter to a second transmitter. If the switch is connected, information can be transmitted between the first transmitter and the second transmitter. If the switch is disconnected, information cannot be transmitted between the first transmitter and the second transmitter.

[0110] In this feasible implementation, the connection or disconnection can be quickly controlled by the instantly responding switch, avoiding a conflict between the first processor and the second processor accessing the first memory due to delayed triggering, thereby improving the accuracy of the log.

[0111] S805: The first processor obtains first debugging information from the first memory through the first processor according to the disconnection signal.

[0112] For example, when the first processor receives the disconnect signal, it indicates that the first controller has disconnected the first processor from the second processor. The second processor no longer receives debug information sent by the first processor and can no longer store debug information in the first memory. In other words, the second processor stops accessing the first memory. Based on this, the first processor's access to the first memory does not conflict with the second processor.

[0113] In combination with a scenario example, if the first processor and the second processor access the first memory at the same time, the first processor may obtain information from the first memory and then the second processor may store information into the first memory, resulting in inaccurate information obtained by the first processor.

[0114] Optionally, before accessing the first memory, the first processor sends an instruction to the second processor to instruct the second processor to stop accessing the first memory, thereby avoiding access conflict.

[0115] Based on the above implementation, the disconnect signal is used to avoid conflicts between the first processor and the second processor in accessing the first memory, thereby preventing the first processor from obtaining incorrect debugging information, thereby improving the accuracy of the log.

[0116] In a feasible implementation, the startup method further includes: if the first controller does not receive the heartbeat information within a preset time period, connecting the first transmitter and the second transmitter via the first controller.

[0117] Exemplarily, according to a preset strategy, the first processor sends heartbeat information once every preset time period, and the preset time period is synchronized between the first processor and the first controller.

[0118] In combination with the scenario example, the first processor strictly executes the preset policy. When the first processor fails or the operating system of the first processor is shut down, the first processor cannot execute the preset policy normally. The first controller makes a judgment based on the preset policy. If the first controller does not receive the heartbeat information within the preset time, it means that the first processor cannot execute the preset policy normally, and it can be judged that the first processor fails or the operating system of the first processor is shut down. By connecting the first transmitter and the second transmitter, the first debugging information of the first processor can be sent to the second processor in time after the first processor is restarted.

[0119] In this feasible implementation method, by setting a preset duration and synchronizing the preset duration between the first processor and the first controller, the first controller can accurately determine the timing of connecting the first transmitter and the second transmitter based on the preset duration and heartbeat information, thereby avoiding the problem of missing first debugging information after the first processor is restarted, thereby improving the integrity of the log.

[0120] A feasible implementation method is that the startup method also includes: if the first controller receives heartbeat information, the first controller controls the multiplexer to connect the first memory and the first processor; if the first controller does not receive heartbeat information within a preset time, the first controller controls the multiplexer to connect the first memory and the second processor.

[0121] Exemplarily, a multiplexer is used to control only one processor to be connected to the first memory at any one time, so as to avoid conflicts when the processors use the first memory.

[0122] Optionally, the processor to which the first memory is connected is controlled through coordination between the first processor and the second processor. For example, the first processor sends an instruction to the second processor to instruct the second processor to connect to the first memory, and the second processor sends an instruction to the multiplexer to establish a connection between the second processor and the first memory.

[0123] For example, if the first controller receives a heartbeat message, it indicates that the operating system of the first processor has completed startup and the first processor can store debugging information and generate logs. The multiplexer is controlled to connect the first memory and the first processor to enable the first processor to access the first memory. If the first controller does not receive a heartbeat message within a preset time, it indicates that the operating system of the first processor has not completed startup and the first processor cannot store debugging information and generate logs. The multiplexer is controlled to connect the first memory and the second processor to enable the second processor to access the first memory and store the first debugging information.

[0124] In this feasible implementation, the multiplexer can avoid conflicts between the first processor and the second processor in accessing the first memory, thereby improving the integrity of the log.

[0125] In a feasible implementation, the startup method further includes: sending usage instructions between the first processor and the second processor to achieve time-sharing multiplexing of the first memory by the first processor and the second processor.

[0126] Exemplarily, the use instruction is used to indicate that the first processor or the second processor currently uses the first memory, and coordination between the first processor and the second processor is achieved by using the use instruction.

[0127] In combination with a scenario example, by using instructions, the first processor is coordinated to use the first memory in the first time period and the second processor to use the first memory in the second time period, and the first time period and the second time period do not overlap, thereby avoiding conflicts between the first processor and the second processor in accessing the first memory.

[0128] In this feasible implementation, by sending data between the first processor and the second processor, the use of the first memory by the first processor and the second processor can be effectively coordinated, avoiding access conflicts between the first processor and the second processor to the first memory, thereby improving the accuracy of the log.

[0129] In a feasible implementation, the startup method also includes: receiving a power-on signal, executing a boot loader through the first processor to enter the boot phase, the boot phase including an initial boot phase and a main boot phase; in the initial boot phase, sending a wake-up instruction to the second processor through the first processor to enable the second processor to run.

[0130] Exemplarily, the initial boot phase includes: powering on the server and initializing the DDR. The main boot phase includes: loading the boot loader into the DDR and running the boot loader. During both the initial boot phase and the main boot phase, the first processor does not mount the file system.

[0131] In combination with the scenario example, sending a wake-up instruction to the second processor through the first processor in the initial boot phase can enable the second processor to start up early, so that the second processor can effectively store the first debugging information of the first processor during the boot phase of the first processor.

[0132] Next, combine Figure 9 The startup sequence is explained.

[0133] Figure 9 This is a schematic diagram of the startup sequence provided in the embodiment of the present application. Figure 9 As shown, during the initial boot phase, the first processor sends a wake-up instruction to the second processor to start the second processor. After the second processor completes the startup, it monitors the first debugging information of the first processor. When the first processor starts and finishes running the application, it sends a heartbeat message to the first controller. The first controller disconnects the transmitter based on the heartbeat message to disconnect the first processor and the second processor, and continues to monitor the heartbeat message. The first controller obtains the connection status of the transmitter and sends the transmitter connection status to the first processor. After the first processor determines that the transmitter has been disconnected based on the transmitter connection status, it obtains the first debugging information from the first memory and generates a log based on the first debugging information.

[0134] In this feasible implementation, sending a wake-up instruction to the second processor in the initial boot phase can enable the second processor to start early and store the first debugging information of the first processor, thereby reducing omissions of debugging information and improving the integrity of the log.

[0135] In a feasible implementation, the startup method further includes: receiving a power-on signal, and controlling the second processor and the first processor to start in sequence according to a preset interval through a power-on sequence, wherein the second processor starts first.

[0136] Exemplarily, in the power-on sequence, the second processor starts first, and then the first processor starts after a preset interval, so that when the first processor is in the initial boot phase, the second processor has already completed startup and can store the first debugging information.

[0137] Optionally, the preset interval is greater than or equal to the startup time of the second processor.

[0138] In combination with the scenario example, if the second processor is started later and the first processor has already started and generated part of the first debugging information, part of the first debugging information of the first processor may be missed, affecting the integrity of the log.

[0139] In this feasible implementation, the power-on sequence allows the second processor to start up before the first processor and store the first debugging information of the first processor, thereby reducing omissions of debugging information and improving the integrity of the log.

[0140] In a feasible implementation, the startup method further includes: obtaining a boot loader from the first memory or the second memory by the first processor.

[0141] Exemplarily, taking the second processor as a coprocessor as an example, the first memory is located inside the boot controller, and the boot loader can be stored in the first memory or the second memory.

[0142] For example, taking the second processor as a single-chip microcomputer, the first memory is located outside the boot controller, and devices outside the boot controller can share the first memory. At this time, the boot loader is stored in the second memory inside the boot controller to improve the security of the boot loader.

[0143] In this feasible implementation, the boot loader is stored in a memory inside the boot controller, which can improve the security of the boot loader and thus improve the reliability of the boot system.

[0144] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0145] Figure 10 This is a schematic diagram of the structure of the starting device provided in the embodiment of the present application. Figure 10 As shown, the embodiment of the present application further provides a starting device, the starting device 100 may include: a recording module 101, a sending module 102, and a generating module 103, wherein:

[0146] The recording module 101 is configured to execute a boot loader through a first processor to enter a boot phase, and generate first debugging information in the boot phase.

[0147] The sending module 102 is configured to associate the serial port of the first processor with the serial port of the second processor through the first controller, so that the second processor receives the first debugging information and writes the first debugging information into the first memory.

[0148] The sending module 102 is further used to receive the heartbeat information of the first processor through the first controller, switch the access control right of the first memory through the first controller, and open or close the serial port connection between the first processor and the second processor and set a flag

[0149] The generating module 103 is configured to execute operating system startup through the first processor, read the flag set by the first controller after the operating system startup is completed, obtain the first debugging information from the first memory to generate a log, and store the log in the log directory of the first processor.

[0150] It should be noted that the starting device shown in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.

[0151] In a possible implementation, the sending module 102 is specifically configured to send the first debugging information to the first transmitter, so that the first transmitter transmits the first debugging information to the second processor through the second transmitter.

[0152] Figure 11 This is a schematic diagram of the structure of a starting device provided in an embodiment of the present application. Figure 10 Based on the embodiment shown, Figure 11 As shown, the starting device 100 further includes: an acquisition module 104, a connection module 105, a multiplexing module 106, a coordination module 107, a wake-up module 108, a starting module 109, and a guiding module 1010, wherein:

[0153] The acquisition module 104 is used to:

[0154] Sending heartbeat information to the first controller via the first processor at preset intervals;

[0155] If the first controller receives the heartbeat information, disconnecting the first transmitter from the second transmitter through the first controller, and sending a disconnect signal to the first processor through the first controller;

[0156] The first processor obtains the first debugging information from the first memory through the first processor according to the disconnection signal.

[0157] In a possible implementation, a switch is included between the first transmitter and the second transmitter; the acquisition module 104 is specifically configured to:

[0158] The first controller controls the switch to be opened, so as to disconnect the connection between the first transmitter and the second transmitter.

[0159] The connection module 105 is used to:

[0160] If the first controller does not receive the heartbeat information within the preset time period, the connection between the first transmitter and the second transmitter is connected through the first controller.

[0161] The multiplexing module 106 is used to:

[0162] If the first controller receives the heartbeat information, the first controller controls the multiplexer to connect the first memory and the first processor;

[0163] If the first controller does not receive the heartbeat information within a preset time period, the first controller controls the multiplexer to connect the first memory and the second processor.

[0164] The coordination module 107 is configured to:

[0165] The first processor and the second processor send usage instructions to each other, so that the first processor and the second processor can time-share multiplex the first memory.

[0166] The wake-up module 108 is configured to:

[0167] Receiving a power-on signal, executing a boot loader through the first processor to enter a boot phase, the boot phase including an initial boot phase and a main boot phase;

[0168] During the initial booting phase, a wake-up instruction is sent to the second processor via the first processor to enable the second processor to operate.

[0169] The startup module 109 is used to:

[0170] A power-on signal is received, and the second processor and the first processor are started in sequence according to a preset interval through power-on sequence control, wherein the second processor is started first.

[0171] The guidance module 1010 is configured to:

[0172] The boot loader is retrieved from the first memory or the second memory by the first processor.

[0173] For the description of the features in the embodiment corresponding to the starting device, please refer to the relevant description of the embodiment corresponding to the starting method, and no further details will be given here.

[0174] Figure 12 This is a schematic diagram of the structure of the electronic device provided in this application. Figure 12As shown, the electronic device 120 provided in this embodiment includes: at least one processor 1201 and a memory 1202. Optionally, the electronic device 120 further includes a communication component 1203. The processor 1201, the memory 1202 and the communication component 1203 are connected via a bus.

[0175] During the specific implementation process, at least one processor 1201 executes the computer-executable instructions stored in the memory 1202, so that the at least one processor 1201 executes the above-mentioned startup method embodiment.

[0176] The specific implementation process of the processor 1201 can be found in the above method embodiment. Its implementation principle and technical effects are similar and will not be repeated here in this embodiment.

[0177] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the application may be directly executed by a hardware processor or by a combination of hardware and software modules within the processor.

[0178] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage.

[0179] A bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be categorized as address buses, data buses, and control buses. For ease of illustration, the buses in the drawings of this application are not limited to just one bus or just one type of bus.

[0180] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above-mentioned startup method embodiments when running.

[0181] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0182] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned startup method embodiments are implemented.

[0183] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned startup method embodiments are implemented.

[0184] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0185] The above is a detailed introduction to a startup system, method, device, electronic device, medium and product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A starting system, characterized in that: include: A first processor, a second processor, a first memory, and a first controller; wherein, The first processor is connected to the first memory, the first processor is used to execute a boot loader to enter a boot phase, the boot phase generates first debugging information, the first processor is further used to obtain the first debugging information from the first memory after completing the startup of the operating system and generate a log based on the first debugging information, the first memory is used to store the first debugging information; The first controller is used to associate the serial port of the first processor with the serial port of the second processor, and the first controller is used to control the first processor to send the first debugging information to the second processor during a boot phase; The second processor is also connected to the first memory, and the second processor is used to write the first debugging information into the first memory.

2. The starting system according to claim 1, characterized in that: The startup system further includes: a first transmitter and a second transmitter; wherein, The first controller is used to control the connection and disconnection between the first transmitter and the second transmitter. The first transmitter is used to transmit the first debugging information in the boot phase, and the second transmitter is used to transmit the first debugging information to the second processor.

3. The starting system according to claim 2, characterized in that: The starting system further includes a switch; wherein, The switch is connected to the first controller, the first transmitter, and the second transmitter; The first controller is configured to disconnect the first transmitter and the second transmitter through the switch when receiving the heartbeat information of the first processor sent by the first transmitter; The first controller is configured to connect the first transmitter and the second transmitter via the switch when the heartbeat information is not received within a preset period of time.

4. The starting system according to any one of claims 1 to 3, characterized in that: The startup system further includes a startup controller; the second processor is a coprocessor or a single chip microcomputer; wherein, The first processor in the startup controller is connected to the coprocessor, and the first processor is used to send a wake-up instruction to the coprocessor to enable the coprocessor to run; or The single chip microcomputer outside the startup controller is connected to the first processor inside the startup controller, and the single chip microcomputer is used to start after the first processor starts according to a power-on sequence.

5. The starting system according to claim 4, characterized in that: The second processor is a coprocessor, and the first processor obtains the boot loader from the first memory.

6. The starting system according to claim 4, characterized in that: The second processor is a single chip microcomputer, the first processor is connected to a second memory, the second memory is located outside the startup controller, and the first processor obtains the boot loader from the second memory.

7. The starting system according to claim 1, characterized in that: The startup system further includes: a multiplexer; wherein, The multiplexer is connected to the first processor, the second processor, and the first memory, and is configured to switch the processor connected to the first memory according to an instruction of the first controller.

8. A startup method, characterized in that: Applied to the starting system according to any one of claims 1 to 7, the method comprises: Entering a boot phase by executing a boot loader through the first processor, wherein the boot phase generates first debugging information; Associating the serial port of the first processor with the serial port of the second processor through the first controller, so that the second processor receives the first debugging information and writes the first debugging information into the first memory; receiving heartbeat information of the first processor through the first controller, switching access control rights of the first memory through the first controller, and opening or closing a serial port connection between the first processor and the second processor and setting a flag; The operating system is started up by the first processor, and after the operating system is started up, a flag set by the first controller is read, the first debugging information is obtained from the first memory to generate a log, and the log is stored in a log directory of the first processor.

9. The startup method according to claim 8, characterized in that: The method further comprises: The first debugging information is sent to a first transmitter, so that the first transmitter transmits the first debugging information to the second processor through a second transmitter.

10. The startup method according to claim 9, characterized in that: Acquiring the first debugging information from the first memory includes: Sending heartbeat information to the first controller via the first processor at preset intervals; If the first controller receives the heartbeat information, disconnecting the first transmitter and the second transmitter through the first controller, and sending a disconnect signal to the first processor through the first controller; The first processor obtains the first debugging information from the first memory through the first processor according to the disconnect signal.

11. The startup method according to claim 10, characterized in that: A switch is provided between the first transmitter and the second transmitter; and disconnecting the first transmitter and the second transmitter by the first controller comprises: The first controller controls the switch to be opened, so as to disconnect the connection between the first transmitter and the second transmitter.

12. The startup method according to claim 11, characterized in that: The method further comprises: If the first controller does not receive the heartbeat information within a preset time period, the connection between the first transmitter and the second transmitter is established through the first controller.

13. The startup method according to claim 12, characterized in that: The method further comprises: If the first controller receives the heartbeat information, controlling the multiplexer to connect the first memory and the first processor through the first controller; If the first controller does not receive the heartbeat information within a preset time period, the first controller controls the multiplexer to connect the first memory and the second processor.

14. The startup method according to claim 8, characterized in that: The method further comprises: The first processor and the second processor send usage instructions to each other, so that the first processor and the second processor can time-share multiplex the first memory.

15. The startup method according to claim 8, characterized in that: The method further comprises: receiving a power-on signal, and executing a boot loader by the first processor to enter the boot phase, wherein the boot phase includes an initial boot phase and a main boot phase; During the initial booting phase, a wake-up instruction is sent to the second processor via the first processor to enable the second processor to operate.

16. The startup method according to claim 8, characterized in that: The method further comprises: A power-on signal is received, and the second processor and the first processor are started in sequence according to a preset interval through power-on sequence control, wherein the second processor is started first.

17. The startup method according to claim 8, characterized in that: The method further comprises: The boot loader is obtained from the first memory or the second memory by the first processor.

18. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the startup method according to any one of claims 8 to 17 when executing the computer program.

19. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the startup method according to any one of claims 8 to 17 are implemented.

20. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the startup method according to any one of claims 8 to 17 are implemented.

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