Data processing method and device for solid state disk

Abstract

The invention discloses a data processing method and device for a solid state disk, and relates to the technical field of computers, and the method comprises the steps: analyzing the performance demand information of target data in a processing process, selecting an error correction method which can meet the performance demand information as much as possible from a plurality of first error correction methods as a target error correction method, different data processing scenes can correspond to different performance demand information, and a proper error correction method can be switched to carry out error correction processing on the target data according to different data processing scenes, so that the performance demand of the target data in the processing process is met as far as possible, and the processing efficiency is improved. The technical problem that the accuracy of the error correction result in some scenes is low due to the fact that the data error correction technology cannot meet different data processing requirements is solved, and the technical effects of being suitable for different data processing scenes and improving the accuracy of the error correction result are achieved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and particularly to a data processing method and device for a solid-state drive. Background Art

[0002] A Redundant Array of Independent Disks (RAID) card improves the performance and reliability of data storage by combining multiple physical disks. During data transmission, errors may be caused by noise, interference, or hardware failures, so it is crucial to adopt effective error correction techniques.

[0003] Currently, data error correction techniques are usually targeted at specific data processing scenarios and cannot be applied to different data processing requirements, resulting in low accuracy of error correction results in some scenarios. Summary of the Invention

[0004] This application provides a data processing method and device for a solid-state drive to at least solve the problem that in the related art, the data error correction technique cannot be applied to different data processing requirements, resulting in low accuracy of error correction results in some scenarios.

[0005] This application provides a data processing method for a solid-state drive, where the solid-state drive is used to store target data, and the method includes:

[0006] Obtain the hardware resources of the solid-state drive;

[0007] When the hardware resources meet the resource usage requirements in the target data processing process, obtain the performance requirement information of the target data during the processing process;

[0008] Compare the performance requirement information with a preset performance requirement threshold to obtain a first comparison result;

[0009] Based on the first comparison result and the performance characteristics of each of the first error correction methods, determine at least one of the target error correction methods from multiple first error correction methods;

[0010] Perform error correction processing on the target data through at least one of the target error correction methods.

[0011] This application also provides a data processing device for a solid-state drive, where the solid-state drive is used to store target data, and the device includes:

[0012] A first acquisition module, configured to acquire the hardware resources of the solid-state drive;

[0013] A second acquisition module is used to acquire performance requirement information of the target data during the processing process when the hardware resources meet the resource usage requirements of the target data during the processing process;

[0014] A first processing module, used for comparing the performance requirement information with a preset performance requirement threshold to obtain a first comparison result;

[0015] A second processing module, configured to determine at least one target error correction method from a plurality of the first error correction methods based on the first comparison result and performance characteristics of each of the first error correction methods;

[0016] The third processing module is used to perform error correction processing on the target data by using at least one of the target error correction methods.

[0017] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned solid state hard disk data processing methods when executing the computer program.

[0018] The present application also provides a computer-readable storage medium, in which a computer program is stored, wherein when the computer program is executed by a processor, the steps of any of the above-mentioned methods for processing data of a solid-state hard disk are implemented.

[0019] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned solid-state hard disk data processing methods when executed by a processor.

[0020] Through the present application, the performance requirement information of the target data during the processing is analyzed, and an error correction method that can meet the performance requirement information as much as possible is selected from multiple first error correction methods. As the target error correction method, different data processing scenarios can correspond to different performance requirement information. According to different data processing scenarios, the appropriate error correction method can be switched to perform error correction processing on the target data, so that the performance requirements of the target data during the processing are met as much as possible. Therefore, the technical problem that the data error correction technology cannot be applied to different data processing requirements, resulting in low accuracy of the error correction results in some scenarios, can be solved, and the technical effect of being applicable to different data processing scenarios and improving the accuracy of the error correction results can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 One of the flow diagrams of a data processing method for a solid - state drive provided by an embodiment of the present application;

[0023] Figure 2 A schematic diagram of power consumption area division provided by an embodiment of the present application;

[0024] Figure 3 Another flow diagram of a data processing method for a solid - state drive provided by an embodiment of the present application;

[0025] Figure 4 A schematic structural diagram of a data processing device for a solid - state drive provided by an embodiment of the present application. Detailed implementation manners

[0026] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0027] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variation thereof are intended to cover a non - exclusive inclusion, such that a process, method, article or device including a series of elements includes not only those elements but also other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0028] To enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0029] Combined with the specific application environment architecture or specific hardware architecture on which the execution of the data processing method of the solid - state drive depends, the specific application environment architecture or specific hardware architecture will be described herein.

[0030] Embodiments of the present application provide a data processing method for a solid - state drive. The method will be described in detail in combination with the execution process of the data processing method of the solid - state drive.

[0031] The solid - state drive provided by the embodiments of the present application is used to store target data.

[0032] Among them, the solid-state drive is a hard disk made of a solid-state electronic storage chip array. Multiple solid-state drives can form a Redundant Array of Independent Disks (RAID) to form a RAID card, and the server is equipped with a RAID card as a storage controller.

[0033] The target data is the data stored in the solid-state drive. During the transmission of the target data, the transmission link may have errors due to noise, interference, or hardware failures.

[0034] The data processing method for the solid-state drive provided by the embodiments of the present application is used to correct errors in the target data in the solid-state drive.

[0035] Specifically, Figure 1 FIG. is a flowchart of a data processing method for a solid-state drive according to an embodiment of the present application.

[0036] As Figure 1 shown, the data processing method for the solid-state drive includes the following steps:

[0037] Step S101, obtain the hardware resources of the solid-state drive.

[0038] Among them, the hardware resources can be physically available storage capacity, read and write speed, etc., which can characterize the ability to process and store data. The resource usage requirement is the minimum standard of the hardware resources required to complete the task of processing the target data.

[0039] Step S102, when the hardware resources meet the resource usage requirements in the process of processing the target data, obtain the performance requirement information in the process of processing the target data.

[0040] In this embodiment, the fact that the hardware resources meet the resource usage requirements in the process of processing the target data indicates that the current hardware configuration can efficiently support the data processing task.

[0041] In this embodiment, the performance requirement information is the information corresponding to the requirements for the performance indicators of the target data transmission and processing in the corresponding application scenario or data processing task. When the requirements corresponding to the performance requirement information are met, the solid-state drive can efficiently and stably complete the data processing task.

[0042] In this step, the corresponding performance requirement information can be analyzed and obtained according to the processing scenario corresponding to the target data. It can be understood that different data processing scenarios correspond to different performance requirement information.

[0043] Step S103, compare the performance requirement information with a preset performance requirement threshold to obtain a first comparison result.

[0044] Step S104: Based on the first comparison result and the performance characteristics of each first error correction method, determine at least one target error correction method from multiple first error correction methods. Herein, the first error correction method is a method that can perform error correction processing on target data, and the error correction processing is a process of detecting and correcting errors in the target data. The target error correction method is an error correction method selected from multiple first error correction methods that can satisfy the performance requirement information as much as possible.

[0045] In this step, according to the performance requirement information, analyze the requirements for the performance indicators of the data during the process of transmitting and processing the target data, and select an error correction method from multiple first error correction methods that can satisfy the performance requirement information as much as possible as the target error correction method. It can be understood that one target error correction method can be determined from multiple first error correction methods, or multiple target error correction methods can be determined.

[0046] In this embodiment, the preset performance requirement threshold is a preset performance standard used to divide the performance requirement level corresponding to the performance requirement information.

[0047] The first comparison result is used to represent the performance requirement level corresponding to the performance requirement information. For example, the first comparison result can be that the requirement for a certain performance is high or low, etc.

[0048] For example, the performance requirement information can be compared with the preset performance requirement threshold. When the performance requirement corresponding to the performance requirement information is greater than the preset performance requirement threshold, it is determined that the first comparison result is that the requirement for the corresponding performance is higher. When the performance requirement corresponding to the performance requirement information is less than the preset performance requirement threshold, it is determined that the first comparison result is that the requirement for the corresponding performance is lower.

[0049] In this embodiment, the performance characteristic of the first error correction method is a characteristic that can evaluate and measure the implementation effect of the error correction method. The performance advantages of different first error correction methods can be different, and the indicators corresponding to the performance characteristics of the first error correction method correspond to the indicators corresponding to the performance requirement information.

[0050] In this embodiment, according to the first comparison result, determine the requirement level for the corresponding performance. According to the performance characteristics of each first error correction method, select an error correction method whose implementation effect can meet the performance requirements from multiple first error correction methods as the target error correction method.

[0051] In this embodiment, by combining the requirements of the data processing scenario with the performance characteristics of the first error correction method, the target error correction method selected from the first error correction methods is more suitable for the corresponding data processing scenario, can satisfy the requirements of the corresponding data processing scenario as much as possible, and improve the accuracy of the error correction result.

[0052] Step S105: Perform error correction processing on the target data through at least one target error correction method.

[0053] In this step, after the target error correction method is selected, the target data may be corrected using the target error correction method to improve the accuracy of the target data.

[0054] In the related art, data error correction technology is usually targeted at specific data processing scenarios and cannot be applied to different data processing requirements, resulting in low accuracy of error correction results in some scenarios.

[0055] According to the data processing method for a solid-state hard disk provided in an embodiment of the present application, by analyzing the performance requirement information of the target data during the processing, an error correction method that can meet the performance requirement information as much as possible is selected from multiple first error correction methods. As the target error correction method, different data processing scenarios may correspond to different performance requirement information. According to different data processing scenarios, the appropriate error correction method can be switched to perform error correction processing on the target data, so that the performance requirements of the target data during the processing are met as much as possible. This method can be applicable to different data processing scenarios and improve the accuracy of the error correction results.

[0056] In some embodiments, the performance requirement information includes at least one of a bit error rate requirement, a delay tolerance requirement, a bandwidth requirement, a reliability requirement, and a computing resource requirement.

[0057] Among them, bit error rate, delay tolerance, bandwidth, reliability and computing resources are performance indicators of target data during processing.

[0058] The bit error rate is the ratio of the number of erroneously received bits to the total number of transmitted bits during data transmission, and is used to measure the accuracy of data transmission.

[0059] Delay tolerance is the maximum delay time that the system can accept during data transmission or processing. Exceeding this time may cause system performance to degrade.

[0060] Bandwidth is the maximum amount of data that a communication channel can transmit per unit time and is used to characterize the speed of data transmission.

[0061] Reliability is the ability of data to maintain integrity and accuracy during transmission, storage, and processing.

[0062] The amount of computing resources is the total amount of various computing resources required to complete the data processing task.

[0063] In this embodiment, the bit error rate requirement is the requirement proposed for the bit error rate of target data transmission and processing, the latency tolerance requirement is the requirement proposed for the latency tolerance of target data transmission and processing, the bandwidth requirement is the requirement proposed for the bandwidth of target data transmission and processing, the reliability requirement is the requirement proposed for the reliability of target data transmission and processing, and the computing resource quantity requirement is the requirement proposed for the computing resource quantity of target data transmission and processing.

[0064] In this embodiment, the performance requirement information includes one or more of the bit error rate requirement, the latency tolerance requirement, the bandwidth requirement, the reliability requirement, and the computing resource quantity requirement.

[0065] In this embodiment, by comprehensively considering various requirement information in different data processing scenarios, various first error correction methods can be more comprehensively compared, and the selected target error correction method is more suitable for the corresponding data processing scenario, thereby improving the accuracy of the error correction result.

[0066] In some embodiments, the first error correction method includes at least two of the forward error correction method, the error correction code method, and the cyclic redundancy check method.

[0067] Among them, the forward error correction (FEC) method is an error correction method that attaches additional information when sending data, so that the receiving end can detect and correct errors in transmission without requesting retransmission. The forward error correction method is suitable for high-speed data transmission links such as PCIe and SAS, and scenarios sensitive to latency.

[0068] The error correction code (ECC) method is an error correction method that encodes the original data by adding redundant information, so as to perform error detection and correction during data transmission or storage. The error correction code method is suitable for scenarios with high requirements for data reliability and allowing a certain amount of overhead, such as enterprise-level storage systems.

[0069] The cyclic redundancy check (CRC) method is an error correction method that calculates the check value of the data and attaches it to the data. The receiving party verifies the integrity of the data by recalculating the check value. The cyclic redundancy check method is suitable for scenarios with a low error rate and requiring efficient error detection, such as network communication scenarios.

[0070] In this embodiment, a target error correction method can be selected from the forward error correction method, the error correction code method, and the cyclic redundancy check method.

[0071] In some embodiments, the forward error correction method is based on sparse matrix optimization. A simple iterative algorithm is embedded in the forward error correction method. The complexity of the polynomial of the cyclic redundancy check method is less than the first complexity threshold, and / or the polynomial in the cyclic redundancy check method is an approximate polynomial.

[0072] Wherein, the sparse matrix is a matrix with most elements being zero. The simple iterative algorithm is an algorithm that gradually approaches the solution of the equation system by means of step-by-step approximation. The first complexity threshold is a preset complexity. The approximate polynomial is a polynomial expression that approximately represents a certain function or data set.

[0073] In this embodiment, in the forward error correction method, a sparse matrix can be used to construct an encoding matrix, reducing the number of non-zero elements to be processed during the encoding process, thereby reducing the computational complexity. At the receiving end, since most elements in the sparse matrix are zero, only non-zero elements need to be concerned during the decoding process, which can reduce the amount of calculation.

[0074] Embedding a simple iterative algorithm in the forward error correction method means that in the decoding process of the forward error correction method, the simple iterative method is used to gradually approach the correct decoding result, which can improve the system efficiency.

[0075] The complexity of the polynomial of the cyclic redundancy check method can be represented by the order of the polynomial. Selecting a polynomial with a complexity lower than the first complexity threshold, that is, selecting a lower-order polynomial, to implement the encoding and decoding process of the cyclic redundancy check method can improve the computational efficiency and reduce resource consumption.

[0076] In the cyclic redundancy check method, using an approximate polynomial for generating and verifying the check code can improve the computational efficiency and simplify the implementation complexity.

[0077] In this embodiment, the parameters of each error correction method can also be optimized according to different data processing scenarios to reduce redundant calculations.

[0078] In this embodiment, the first error correction method is optimized, and the target error correction method is selected from the first error correction method to perform error correction processing on the target data, which can improve the computational efficiency and reduce the system resource consumption.

[0079] In some embodiments, the performance requirement information includes bit error rate requirement, latency tolerance requirement, and bandwidth requirement. The first error correction methods include forward error correction method, error correction code method, and cyclic redundancy check method. Based on the first comparison result and the performance characteristics of each first error correction method, determining at least one target error correction method from multiple first error correction methods includes:

[0080] When the bandwidth requirement is greater than the bandwidth requirement threshold, determining the cyclic redundancy check method as the target error correction method;

[0081] Alternatively, when the bandwidth requirement is less than or equal to the bandwidth requirement threshold, based on the bit error rate requirement, the latency tolerance requirement, and the performance characteristics of the forward error correction method, the error correction code method, and the cyclic redundancy check method, determine the target error correction method.

[0082] The bandwidth requirement threshold is a preset value and can be determined based on the bandwidth resources of the solid-state drive.

[0083] That the bandwidth requirement is greater than the bandwidth requirement threshold indicates that the current bandwidth resources are insufficient, that is, the bandwidth resources are limited. Determining the cyclic redundancy check method as the target error correction method reduces the use of bandwidth resources in the error correction process; that the bandwidth requirement is less than or equal to the bandwidth requirement threshold indicates that the current bandwidth resources are sufficient, and the target error correction method can be determined according to the bit error rate requirement and the latency tolerance requirement.

[0084] In this embodiment, preferentially determining the target error correction method based on the bandwidth requirement can achieve higher bandwidth utilization and lower system complexity in resource-constrained scenarios.

[0085] In some embodiments, before obtaining the performance requirement information of the target data during the processing based on the performance requirement information, the method further includes:

[0086] When the hardware resources do not meet the resource usage requirements during the processing of the target data, perform hardware acceleration processing on the solid-state drive so that the hardware resources meet the resource usage requirements.

[0087] The hardware resources may be physically available storage capacity, read and write speed, etc., which can characterize the ability to process and store data. The resource usage requirement is the minimum standard of the hardware resources required to complete the task of processing the target data.

[0088] In this embodiment, that the hardware resources do not meet the resource usage requirements during the processing of the target data indicates that the current hardware configuration cannot efficiently support the data processing task, which may slow down the processing speed. In this case, before implementing the error correction task through the target error correction method, perform hardware acceleration processing on the solid-state drive, that is, improve the read and write speed and response performance of the solid-state drive by upgrading the hardware, optimizing the software algorithm, or using the built-in hardware acceleration technology, etc.

[0089] In this embodiment, performing hardware acceleration processing on the solid-state drive before correcting the target data through the target error correction method can improve the error correction efficiency and reliability.

[0090] In some embodiments, performing hardware acceleration processing on the solid-state drive includes:

[0091] Optimize the architecture of the solid-state drive, reduce the power consumption of the solid-state drive, and / or optimize the target data in the solid-state drive.

[0092] In this embodiment, optimizing the architecture of the solid-state drive can be to improve the computing efficiency by improving the internal design and component layout of the solid-state drive. Reducing the power consumption of the solid-state drive can be to adopt certain technologies and methods to reduce the electrical energy consumed by the solid-state drive during operation. Optimizing the target data in the solid-state drive is to improve the storage efficiency and access speed of the target data through certain technologies and methods.

[0093] In this embodiment, hardware acceleration processing of the solid-state drive is one of the means to achieve at least one of optimizing the architecture of the solid-state drive, reducing the power consumption of the solid-state drive, and optimizing the target data in the solid-state drive.

[0094] In this embodiment, various ways of hardware acceleration processing of the solid-state drive can be applied to different hardware acceleration scenarios, more comprehensively improving the speed of the solid-state drive to process target data, thereby improving the error correction efficiency.

[0095] In some embodiments, optimizing the architecture of the solid-state drive includes:

[0096] Setting dedicated computing units corresponding to each first error correction method in the solid-state drive, setting a multi-channel architecture corresponding to multiple first error correction methods in the solid-state drive, and / or setting a reconfigurable architecture in the solid-state drive.

[0097] Among them, the dedicated computing unit is to design and configure an independent computing unit for each first error correction method. The dedicated computing unit is used to execute a specific first error correction method. The multi-channel architecture is to integrate multiple independent data channels into the solid-state drive, which can process multiple data streams in parallel. The reconfigurable architecture is an architecture that allows the hardware resources of the solid-state drive to be dynamically adjusted and optimized according to different application requirements.

[0098] In this embodiment, setting dedicated computing units in the solid-state drive, for example, a customized FEC engine or CRC calculation module, is optimized for a specific first error correction method.

[0099] In the application-specific integrated circuit (ASIC) of the solid-state drive, use hard IP, such as a dedicated FEC module, to replace the soft core implementation. As shown in Table 1, the comparison of resource occupancy, power consumption, and maximum frequency between the soft core and the hard core can be seen. Using the hard core can reduce the logic resource occupancy and power consumption.

[0100] Table 1

[0101] IP Type Resource Occupancy (GE) Power Consumption (mW / Gbps) Maximum Frequency (GHz) Soft Core 15,000 3.2 0.8 Hard Core 4,500 0.9 2.5

[0102] In this embodiment, a parallel processing architecture is implemented in the field programmable gate array (FPGA) or ASIC of the solid state drive.

[0103] For example, in combination with data chunking (block size = 256B) and pipeline cascading (P = 8), the data stream is chunked, CRC or FEC is calculated in parallel, a multi-channel architecture is used to process multiple data streams simultaneously, and the processing delay is reduced through parallelization while optimizing power consumption.

[0104] In this embodiment, a dynamic reconfigurable architecture is implemented in the FPGA of the solid state drive, the error correction algorithm is dynamically switched according to the data processing scenario, multiple error correction engines are integrated in the ASIC, and specific modules are dynamically enabled or disabled through a low-power switch. As shown in Table 2, it is the operating state corresponding to the reconfigurable architecture.

[0105] Table 2

[0106] Status Wake-up Time Power Consumption Retention Register ACTIVE - 100％ No IDLE 10ns 30％ Yes OFF 100ns 0.1％ No

[0107] In some embodiments, power consumption reduction processing is performed on the solid state drive, including:

[0108] Implementing clock gating and power gating in the solid state drive, implementing dynamic voltage and frequency scaling in the solid state drive, and / or partitioning multiple power consumption areas in the solid state drive to independently manage the power consumption of each power consumption area.

[0109] Among them, clock gating is a technology for reducing the power consumption of digital circuits by controlling the distribution of clock signals, power gating is a technology for reducing power consumption by cutting off the power supply to inactive circuit parts, and dynamic voltage and frequency scaling (DVFS) is a technology for optimizing power consumption and performance by dynamically adjusting the operating voltage and frequency of the processor, so as to reduce power consumption as much as possible while meeting performance requirements.

[0110] In this embodiment, clock gating and power gating are implemented in the FPGA or ASIC, the clock of unused computing units is turned off during idle periods, and the power supply of some modules is turned off under low load.

[0111] In this embodiment, dynamic voltage and frequency scaling is implemented in the solid state drive, the operating voltage and frequency are adjusted according to the real-time load, the performance is improved under high load, and the power consumption is reduced under low load.

[0112] In this embodiment, an FPGA or an ASIC is divided into multiple power consumption regions, and the power consumption of each power consumption region is managed independently. The high-priority region maintains high performance, and the low-priority region enters the low-power mode.

[0113] For example, as Figure 2 shown, a solid-state drive can be divided into two major power consumption regions: a power management unit and a processing core cluster. Multiple power consumption regions can be further divided in the power management unit, including a dynamic voltage and frequency adjustment controller, a temperature sensor, a workload monitor, a voltage regulator, a clock generator, a clock gating control logic, and a power switch matrix. Multiple power consumption regions can also be divided in the processing core cluster, including CPU cores, a digital signal processing engine, and accelerators.

[0114] In some embodiments, the target data in the solid-state drive is optimized, including:

[0115] Compressing the target data, and / or performing chunking processing on the target data to obtain multiple target data chunks;

[0116] In the case of performing chunking processing on the target data, error correction processing is performed on the target data through at least one target error correction method, including:

[0117] Performing error correction processing on each target data chunk through at least one target error correction method.

[0118] Among them, data compression is a process of reducing the data size, which can save data storage space and reduce data transmission time. Chunking processing is a process of splitting large data into smaller and more manageable data chunks. A target data chunk is a data chunk obtained after performing chunking processing on the target data.

[0119] In this embodiment, before performing error correction processing on the target data chunks, the target data is compressed. The compression processing can be implemented through a lightweight compression algorithm, such as Run-Length Encoding (RLE), which can reduce the computational amount and transmission bandwidth. The target data is chunked, and error correction processing is independently performed on each target data chunk, which can reduce the single computational amount and lower the peak power consumption.

[0120] The following introduces a specific embodiment of a data processing method for a solid-state drive.

[0121] The first error correction method includes CRC, FEC, ECC, and end-to-end data protection. Among them, ECC is suitable for scenarios with high requirements for data reliability and allowing a certain amount of overhead, such as enterprise-level storage systems, etc. FEC is suitable for high-speed data transmission links and scenarios sensitive to latency. CRC is suitable for scenarios with a low error rate and requiring efficient error detection, such as network communication, etc. End-to-end data protection is suitable for complex storage systems where data needs to be highly reliable throughout the entire transmission path.

[0122] First, determine the target error correction method based on the bit error rate requirement. Compare the bit error rate requirement with the preset bit error rate requirement threshold. Set the preset bit error rate requirement thresholds to 1e5 and 1e-8. When the bit error rate requirement is greater than 1e5, determine that the first comparison result is a lower requirement for the bit error rate, and preferentially select FEC as the target error correction method to correct errors in real time. At the same time, detect hardware resources such as cache resources. If the hardware resources are sufficient, ECC can be superimposed for dual protection. When the bit error rate requirement is less than 1e-8, determine that the first comparison result is a higher requirement for the bit error rate, and select CRC as the target error correction method to only detect errors and retransmit if there is a bit error.

[0123] Second, determine the target error correction method based on the delay tolerance requirement. When the delay tolerance is low, perform real-time processing. Real-time processing depends on the data stream. The technology that CRC depends on retransmission will cause a relatively high delay, so disable the CRC error correction method. FEC or lightweight ECC can be used as the target error correction method. When the delay tolerance is high, perform background processing and data backup, etc., which can maximize the reliability of the target data. ECC or end-to-end protection can be used to maximize the integrity and reliability of the target data.

[0124] Third, determine the target error correction method based on the bandwidth requirement. When the bandwidth resources are sufficient, preferentially select error correction methods with high data integrity, namely ECC or end-to-end methods.

[0125] When the bandwidth resources are limited, do not select FEC that occupies bandwidth with redundant data, and preferentially select CRC or lightweight ECC as the target error correction method.

[0126] Fourth, determine the target error correction method based on the computing resource requirement. When the cache (hardware) resources are sufficient, the corresponding error correction method can be selected according to the corresponding requirements. When the cache resources are insufficient, preferentially select CRC as the target error correction method. CRC has simple calculations and requires less cache. If the data reliability requirements of the application scenario are relatively high, dedicated chip acceleration functions can be selected, such as using FPGA or ASIC to achieve low-power real-time error correction, or sacrificing some bandwidth in exchange for real-time error correction capabilities.

[0127] In this embodiment, by combining the performance requirement information with the performance characteristics of the first error correction method, the optimal first error correction method is intelligently selected as the target error correction method in different application scenarios, achieving a balance among performance, reliability, and resource overhead.

[0128] The following introduces a specific embodiment of a data processing method for another solid-state drive.

[0129] As Figure 3 shown, Step 1: Determine whether the hardware resources of the solid-state drive are sufficient to meet the resource usage requirements in the target data processing process, that is, whether it can accelerate the current data processing scenario. If it is satisfied, proceed to Step 3; if not, proceed to Step 2.

[0130] Step 2: Perform hardware acceleration processing on the solid-state drive. First, optimize the hardware architecture, design a dedicated computing unit, use a parallel processing structure to split the data flow, and at the same time set a dynamic switching error correction engine to achieve a dynamically reconfigurable architecture.

[0131] Secondly, optimize the error correction algorithm by means of lightweight error correction algorithms, adaptive error correction, approximate computing, etc., and further optimize the error correction process.

[0132] And combine clock gating, power gating, and DVFS to achieve fine-grained power consumption control, improving performance under high load and reducing power consumption under low load.

[0133] Step 3: Determine whether the bandwidth resources are sufficient. If the bandwidth resources are limited, use CRC or lightweight ECC as the target error correction method; if the bandwidth resources are sufficient, proceed to Step 4.

[0134] Step 4: Determine the requirements of the application scenario for the bit error rate and latency, and process the dependent data stream in real time. In the case of low latency and high bit error rate, preferentially select FEC superposable ECC as the target error correction method; in the case of high latency and high bit error rate, select FEC as the target error correction method; in the case of high latency and low bit error rate, select lightweight ECC as the target error correction method; in the case of low latency and low bit error rate, select CRC as the target error correction method.

[0135] Among them, high latency means high requirements for real-time performance, that is, low latency tolerance; low latency means low requirements for real-time performance, that is, high latency tolerance; low bit error rate means high requirements for the bit error rate, that is, low bit error rate; high bit error rate means low requirements for the bit error rate, that is, high bit error rate.

[0136] In this embodiment, through dedicated hardware acceleration, customized computing units, and parallel architectures, performance can be improved and power consumption can be reduced. Through adaptive error correction, the error correction algorithm and intensity are dynamically adjusted according to the real-time bit error rate and data stream characteristics for power consumption management. Combining clock gating, power gating, and DVFS, fine-grained power control is achieved. And lightweight algorithms are used to reduce the computational complexity through approximate computing and sparse matrix optimization.

[0137] The data processing method of the solid-state drive provided by the embodiment of the present application can improve the error correction efficiency and reliability by optimizing the architecture of the solid-state drive, quickly detect and correct errors in real-time data streams, reduce the latency caused by retransmission, reduce the power consumption of the solid-state drive, and reduce the power consumption during idle or low load. Based on the parallel architecture, high throughput and low latency processing are supported. Through dynamic reconfigurable hardware FPGA or adaptive algorithms, the strategy is dynamically adjusted according to the bit error rate, bandwidth, and cache resources, flexibly adapting to diverse scenarios, and showing significant advantages in dimensions such as performance, power consumption, cost, and adaptability, especially suitable for scenarios with strict requirements for real-time performance and energy efficiency ratio.

[0138] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0139] The embodiment of the present application also provides a data processing device for a solid-state drive.

[0140] The embodiment of the present application also provides a data processing device for a solid-state drive, and the solid-state drive is used to store target data.

[0141] As Figure 4 shown, the data processing device of the solid-state drive includes:

[0142] A first acquisition module 410, configured to acquire the hardware resources of the solid-state drive;

[0143] A second acquisition module 420, configured to acquire the performance requirement information during the processing of the target data when the hardware resources meet the resource usage requirements during the processing of the target data;

[0144] A first processing module 430, configured to compare the performance requirement information with a preset performance requirement threshold to obtain a first comparison result;

[0145] A second processing module 440, configured to determine at least one target error correction method from multiple first error correction methods based on the first comparison result and the performance characteristics of each first error correction method;

[0146] The third processing module 450 is used to perform error correction processing on the target data by using at least one target error correction method.

[0147] According to the data processing device of the solid-state hard disk provided in the embodiment of the present application, by analyzing the performance requirement information of the target data during the processing, an error correction method that can meet the performance requirement information as much as possible is selected from multiple first error correction methods. As the target error correction method, different data processing scenarios can correspond to different performance requirement information. According to different data processing scenarios, the appropriate error correction method can be switched to perform error correction processing on the target data, so that the performance requirements of the target data during the processing process are met as much as possible. It can be applicable to different data processing scenarios and improve the accuracy of the error correction results.

[0148] In some embodiments, the performance requirement information includes at least one of a bit error rate requirement, a delay tolerance requirement, a bandwidth requirement, a reliability requirement, and a computing resource requirement.

[0149] In some embodiments, the first error correction method includes at least two of a forward error correction method, an error correction code method, and a cyclic redundancy check method.

[0150] In some embodiments, the forward error correction method is based on sparse matrix optimization, a simple iterative algorithm is embedded in the forward error correction method, the complexity of the polynomial of the cyclic redundancy check method is less than a first complexity threshold, and / or the polynomial in the cyclic redundancy check method is an approximate polynomial.

[0151] In some embodiments, the performance requirement information includes a bit error rate requirement, a delay tolerance requirement, and a bandwidth requirement, the first error correction method includes a forward error correction method, an error correction code method, and a cyclic redundancy check method, and the second processing module 440 is used to determine the cyclic redundancy check method as the target error correction method when the bandwidth requirement is greater than the bandwidth requirement threshold;

[0152] Alternatively, when the bandwidth requirement is less than or equal to the bandwidth requirement threshold, the target error correction method is determined based on the bit error rate requirement and the delay tolerance requirement, as well as the performance characteristics of the forward error correction method, the error correction code method, and the cyclic redundancy check method. In some embodiments, the first processing module 430 is also used to

[0153] When the hardware resources do not meet the resource usage requirements during the target data processing, the solid-state hard disk is subjected to hardware acceleration processing so that the hardware resources meet the resource usage requirements.

[0154] In some embodiments, the first processing module 430 is further used to optimize the architecture of the solid state drive, reduce the power consumption of the solid state drive, and / or optimize the target data in the solid state drive.

[0155] In some embodiments, the first processing module 430 is further configured to set dedicated computing units corresponding to respective first error correction methods in the solid-state drive, set a multi-channel architecture corresponding to multiple first error correction methods in the solid-state drive, and / or set a reconfigurable architecture in the solid-state drive.

[0156] In some embodiments, the first processing module 430 is further configured to implement clock gating and power gating in the solid-state drive, implement dynamic voltage and frequency scaling in the solid-state drive, and / or divide the solid-state drive into multiple power consumption regions and independently manage the power consumption of each power consumption region.

[0157] In some embodiments, the first processing module 430 is further configured to perform compression processing on target data, and / or perform chunking processing on target data to obtain multiple target data chunks;

[0158] In the case of performing chunking processing on target data, error correction processing is performed on the target data by at least one target error correction method, including:

[0159] Performing error correction processing on each target data chunk by at least one target error correction method.

[0160] For the description of the features in the corresponding embodiments of the data processing device of the solid-state drive, reference may be made to the relevant description in the corresponding embodiments of the data processing method of the solid-state drive, which will not be elaborated herein one by one.

[0161] An embodiment of the present application further provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any of the above embodiments of the data processing method of the solid-state drive.

[0162] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above embodiments of the data processing method of the solid-state drive when running.

[0163] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: various media such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disc that can store a computer program.

[0164] An embodiment of the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the steps in any of the above embodiments of the data processing method of the solid-state drive are implemented.

[0165] Embodiments of the present application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, where the computer program, when executed by a processor, implements the steps in any of the above embodiments of the data processing method for a solid-state drive.

[0166] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0167] The above has introduced in detail a data processing method and apparatus for a solid-state drive provided by the present application. Specific examples are used herein to illustrate the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A data processing method for a solid-state drive, characterized in that, The solid-state drive is used to store target data, and the method includes: Obtain the hardware resources of the solid-state drive; When the hardware resources meet the resource usage requirements in the processing of the target data, obtain the performance requirement information of the target data during the processing; Compare the performance requirement information with a preset performance requirement threshold to obtain a first comparison result; Based on the first comparison result and the performance characteristics of each first error correction method, determine at least one target error correction method from multiple first error correction methods; Perform error correction processing on the target data through at least one of the target error correction methods.

2. The data processing method of the solid-state drive according to claim 1, characterized in that, The performance requirement information includes at least one of a bit error rate requirement, a latency tolerance requirement, a bandwidth requirement, a reliability requirement, and a computing resource amount requirement.

3. The data processing method of the solid-state drive according to claim 1, wherein The first error correction methods include at least two of a forward error correction method, an error correction code method, and a cyclic redundancy check method.

4. The data processing method of the solid state drive according to any one of claims 1-3, characterized in that, The performance requirement information includes a bit error rate requirement, a latency tolerance requirement, and a bandwidth requirement, and the first error correction methods include a forward error correction method, an error correction code method, and a cyclic redundancy check method. The determining at least one of the target error correction methods from multiple first error correction methods based on the first comparison result and the performance characteristics of each of the first error correction methods includes: When the bandwidth requirement is greater than the bandwidth requirement threshold, determine the cyclic redundancy check method as the target error correction method; Alternatively, when the bandwidth requirement is less than or equal to the bandwidth requirement threshold, determine the target error correction method based on the bit error rate requirement, the latency tolerance requirement, and the performance characteristics of the forward error correction method, the error correction code method, and the cyclic redundancy check method.

5. The data processing method of the solid-state drive according to any one of claims 1-3, characterized in that, Before obtaining the performance requirement information of the target data during the processing, the method further includes: When the hardware resources do not meet the resource usage requirements in the processing of the target data, perform hardware acceleration processing on the solid-state drive so that the hardware resources meet the resource usage requirements.

6. The data processing method of the solid state drive according to claim 5, wherein The performing hardware acceleration processing on the solid-state drive includes: Performing optimization processing on the architecture of the solid-state drive, performing power consumption reduction processing on the solid-state drive, and / or performing optimization processing on the target data in the solid-state drive.

7. The data processing method of the solid-state drive according to claim 6, wherein The performing optimization processing on the architecture of the solid-state drive includes: Setting dedicated computing units corresponding to each of the first error correction methods in the solid-state drive, setting a multi-channel architecture corresponding to multiple first error correction methods in the solid-state drive, and / or setting a reconfigurable architecture in the solid-state drive.

8. The data processing method of the solid-state drive according to claim 6, wherein, The performing power consumption reduction processing on the solid-state drive includes: Implementing clock gating and power gating in the solid-state drive, implementing dynamic voltage and frequency scaling in the solid-state drive, and / or dividing the solid-state drive into multiple power consumption areas and independently managing the power consumption of each power consumption area.

9. The data processing method of the solid-state drive according to claim 6, wherein The performing optimization processing on the target data in the solid-state drive includes: Performing compression processing on the target data, and / or performing block processing on the target data to obtain multiple target data blocks; In the case of performing chunking processing on the target data, performing error correction processing on the target data by at least one of the target error correction methods includes: Performing error correction processing on each of the target data chunks respectively by at least one of the target error correction methods.

10. A data processing device for a solid state drive, characterized in that, The solid state drive is used to store target data, and the device includes: A first acquisition module, configured to acquire the hardware resources of the solid state drive; A second acquisition module, configured to acquire the performance requirement information during the processing of the target data when the hardware resources meet the resource usage requirements during the processing of the target data; A first processing module, configured to compare the performance requirement information with a preset performance requirement threshold to obtain a first comparison result; A second processing module, configured to determine at least one target error correction method from multiple first error correction methods based on the first comparison result and the performance characteristics of each first error correction method; A third processing module, configured to perform error correction processing on the target data by at least one of the target error correction methods.

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