Hard disk control circuit, method, device, medium and program product

Abstract

The present application discloses a hard disk control circuit, method, device, medium and program product in the field of computer technology. In the hard disk control circuit provided by the present application, the first port of the processor is connected to the first upstream port of the communication bridge, and the first downstream port corresponding to the first upstream port in the communication bridge is connected to the hard disk; the second port of the processor is connected to the second upstream port of the communication bridge through the main logic control device, and the second downstream port corresponding to the second upstream port in the communication bridge is connected to the hard disk through the slave logic control device. According to this circuit connection method, the main logic control device can perform related operations such as processor port status identification, and there is no need to use a longer communication link with the help of the backplane CPLD to identify the processor port status, saving the transmission time of the port status, thereby improving the recognition efficiency of the processor port status, eliminating the traditional transmission of a longer communication link, converting the multi-module joint debugging problem into a single-node diagnosis problem, and reducing the error rate.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a hard disk control circuit, method, device, medium and program product. Background Art

[0002] Typically, during the POST (Power-On Self-Test) phase of a server system, before the processor has completed PCIe (Peripheral Component Interconnect Express) device enumeration, it issues an uncalibrated, invalid hard drive light-on command. Once the processor completes PCIe device enumeration, it issues a valid, normal hard drive light-on command. To verify the validity of the hard drive light-on command, the BIOS (Basic Input Output System) reports the processor port status to the Baseboard Management Controller (BMC) via the Enhanced Serial Peripheral Interface (eSPI) bus. The BMC then sends this information to the backplane Complex Programmable Logic Device (CPLD) via the Inter-Integrated Circuit (I2C) bus. The backplane CPLD then performs operations such as processor port status verification. This long communication link slows down these operations.

[0003] Therefore, how to improve the processing efficiency of related operations performed by the backplane CPLD is a problem that those skilled in the art need to solve. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a hard disk control circuit, method, device, medium and program product to improve the processing efficiency of related operations performed by the backplane CPLD.

[0005] In the first aspect, the present application provides a hard disk control circuit, comprising: a processor, a master logic control device, a communication bridge, a slave logic control device and a hard disk; wherein, the first port of the processor is connected to the first upstream port of the communication bridge, and the first downstream port corresponding to the first upstream port in the communication bridge is connected to the hard disk; the second port of the processor is connected to the second upstream port of the communication bridge through the master logic control device, and the second downstream port corresponding to the second upstream port in the communication bridge is connected to the hard disk through the slave logic control device.

[0006] In the second aspect, the present application provides a hard disk control method, including: a processor generates a hard disk light-on instruction, and transmits the hard disk light-on instruction to a main logic control device connected to the processor through a target processor port; after the main logic control device detects that the volume management device corresponding to the target processor port is enabled, the hard disk light-on instruction is split into multiple sub-instructions, and the multiple sub-instructions are transmitted to a communication bridge connected to the main logic control device; the communication bridge transmits the multiple sub-instructions to a slave logic control device connected to the communication bridge; the slave logic control device executes the hard disk light-on operation according to the multiple sub-instructions.

[0007] In a third aspect, the present application provides an electronic device comprising: a hard disk control circuit according to any one of the aforementioned items.

[0008] In a fourth aspect, the present application provides an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the aforementioned disclosed hard disk control method.

[0009] In a fifth aspect, the present application provides a non-volatile storage medium for storing a computer program, wherein the computer program implements the aforementioned disclosed hard disk control method when executed by a processor.

[0010] In a sixth aspect, the present application provides a computer program product, comprising a computer program / instruction, which implements the steps of the aforementioned disclosed hard disk control method when executed by a processor.

[0011] It can be seen from the above scheme that the present application provides a hard disk control circuit, including: a processor, a master logic control device, a communication bridge, a slave logic control device and a hard disk; wherein, the first port of the processor is connected to the first upstream port of the communication bridge, and the first downstream port corresponding to the first upstream port in the communication bridge is connected to the hard disk; the second port of the processor is connected to the second upstream port of the communication bridge through the master logic control device, and the second downstream port corresponding to the second upstream port in the communication bridge is connected to the hard disk through the slave logic control device.

[0012] It can be seen that the beneficial effects of the present application are as follows: the hard disk control circuit includes: a processor, a main logic control device, a communication bridge, a slave logic control device and a hard disk, and the first port of the processor is connected to the first upstream port of the communication bridge, and the first downstream port corresponding to the first upstream port in the communication bridge is connected to the hard disk; the second port of the processor is connected to the second upstream port of the communication bridge through the main logic control device, and the second downstream port corresponding to the second upstream port in the communication bridge is connected to the hard disk through the slave logic control device. According to this circuit connection method, the main logic control device can perform related operations such as processor port status identification, and there is no need to use a longer communication link with the backplane CPLD to identify the processor port status, saving the transmission time of the port status, thereby improving the efficiency of processor port status identification, eliminating the traditional transmission of a longer communication link, converting the multi-module joint debugging problem into a single-node diagnosis problem, and reducing the error rate.

[0013] Correspondingly, the hard disk control device, medium and program product provided by this application also have the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0015] Figure 1 This is a schematic diagram of a hard disk control circuit disclosed in this application;

[0016] Figure 2 A schematic diagram of a communication bridge disclosed in this application;

[0017] Figure 3 This is a schematic diagram of the second communication bridge disclosed in this application;

[0018] Figure 4 This is a flow chart of a hard disk control method disclosed in this application;

[0019] Figure 5 This is a schematic diagram of the second hard disk control circuit disclosed in this application;

[0020] Figure 6 This is a schematic diagram of the third hard disk control circuit disclosed in this application;

[0021] Figure 7 This is a flow chart of the second hard disk control method disclosed in this application;

[0022] Figure 8 A server structure diagram provided for this application;

[0023] Figure 9 This is a terminal structure diagram provided for this application. DETAILED DESCRIPTION

[0024] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0025] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0026] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0027] With the rapid development of big data processing, cloud computing, and artificial intelligence technologies, server storage systems face multiple challenges: high concurrency, low latency, and high bandwidth. Traditional SAS / SATA interface hard drives, limited by protocol stack efficiency and physical bandwidth, face significant performance bottlenecks in multi-queue access scenarios. Against this backdrop, all-flash technology based on the PCIe bus and NVMe protocol has rapidly emerged. Current mainstream NVMe hard drives support the PCIe 6.0 interface, increasing theoretical transfer rates to 64GT / s (bidirectional bandwidth up to 256Gbps), and achieving single-drive sequential read and write performance exceeding 14GB / s, significantly improving the throughput of data center storage systems. However, hardware management and status monitoring in server multi-drive backplane designs remain technical bottlenecks. For example, traditional solutions for drive status indication (lighting management) have the following drawbacks: 1) The traditional polling mechanism relies on CPU interrupt service routines. When 24 NVMe drives are mounted, the monitoring thread utilization reaches 12.7%, and the standard deviation of event response latency reaches 47ms, failing to meet the 100ms real-time response required by the UEFI specification. 2) The dual-master control architecture (such as BMC+CPU) lacks a unified interface standard and requires the backplane CPLD to determine the upstream host, significantly increasing the risk of misjudgment in operation and maintenance.

[0028] At present, during the POST stage of the server system, when the processor has not yet completed the enumeration of the PCIe device, an uncalibrated and invalid hard disk light-up instruction will be issued. After the processor completes the enumeration of the PCIe device, a normal and valid hard disk light-up instruction will be issued. In order to identify the validity of the hard disk light-up instruction, the BIOS needs to report the processor port status to the BMC through the eSPI bus, and then the BMC sends it to the backplane CPLD through the I2C bus. The backplane CPLD performs operations such as processor port status identification. The long communication link causes the related operations to be executed slowly. To this end, the present application provides a hard disk control solution that can convert multi-module joint debugging problems into single-node diagnosis problems, reduce the error rate, and improve the execution efficiency of operations such as processor port status identification.

[0029] See also Figure 1 As shown, an embodiment of the present application discloses a hard disk control circuit, including: a processor, a master logic control device, a communication bridge, a slave logic control device and a hard disk.

[0030] The first port of the processor is connected to the first upstream port of the communication bridge, and the first downstream port corresponding to the first upstream port in the communication bridge is connected to the hard disk; the second port of the processor is connected to the second upstream port of the communication bridge through the master logic control device, and the second downstream port corresponding to the second upstream port in the communication bridge is connected to the hard disk through the slave logic control device. Specifically, the slave logic control device is connected to the hard disk and the corresponding hard disk indicator light through the hard disk connector. Multiple hard disk connectors can be connected downstream of the slave logic control device, and one hard disk connector can be plugged into one hard disk. The hard disk can be an NVME disk or other type.

[0031] based on Figure 1 The circuit shown, the corresponding hard disk light-on process may include: the processor generates a hard disk light-on instruction, and transmits the hard disk light-on instruction to a main logic control device connected to the processor through a target processor port (such as the second port); after the main logic control device detects that the volume management device corresponding to the target processor port is enabled, the hard disk light-on instruction is split into multiple sub-instructions, and the multiple sub-instructions are transmitted to a communication bridge connected to the main logic control device; the communication bridge transmits the multiple sub-instructions to a slave logic control device connected to the communication bridge; the slave logic control device executes the hard disk light-on operation according to the multiple sub-instructions.

[0032] In one embodiment, the third port of the processor is connected to the main logic control device through the management controller. That is, the third port of the processor is connected to the management controller, and the management controller is also connected to the main logic control device. For details, see Figure 5 or Figure 6The third port of the processor is connected to the BMC used as a management controller, and the management controller is also connected to the CPLD used as the main logic control device. In addition, a level conversion module Levelshit can be connected between the second port and the main logic control device to achieve voltage adjustment.

[0033] See Figure 2 The communication bridge includes: an equal number of interconnected upstream connectors and downstream connectors; a first upstream port and a second upstream port provided on the upstream connector; and a first downstream port and a second downstream port provided on the downstream connector. The connection method between the upstream connector and the downstream connector can refer to the common circuit connection of the corresponding connectors, and both the upstream connector and the downstream connector can be MCIO connectors.

[0034] In one embodiment, the processor, master logic control device, management controller, and upstream connector are located on the mainboard, and the slave logic control device, hard disk, and downstream connector are located on the backplane. The mainboard can be connected to multiple backplanes.

[0035] See Figure 3 , the communication bridge includes: an upstream connector, a switching device and a downstream connector connected in sequence; the first upstream port and the second upstream port are provided on the upstream connector; the first downstream port and the second downstream port are provided on the downstream connector. Accordingly, the switching device includes: a first connector, a switching module and a second connector connected in sequence; the first connector is connected to the upstream connector, and the number is equal to that of the upstream connectors; the second connector is connected to the downstream connector, and the number is equal to that of the downstream connectors; the first connector is also connected to the second connector through a bridge controller; the number of the first connector and the second connector is equal. The number of sub-instructions received by the bridge controller is directly proportional to the number of its downstream channels. Accordingly, the master logic control device is used to: synchronize the status of the target processor port to the slave logic control device and / or the bridge controller.

[0036] It should be noted that the connection path from the processor to the hard drive includes: the processor port (such as the second port, the first port), the master logic control device, the communication bridge, the slave logic control device, and the hard drive. Based on this, the master logic control device can automatically construct and record the physical topology relationship between the processor port and the hard drive upon power-up. Therefore, if the processor, master logic control device, management controller, and upstream connector are located on the motherboard, and the slave logic control device, hard drive, and downstream connector are located on the backplane, and the motherboard is connected to multiple backplanes, the master logic control device can clearly determine the connection path (i.e., the physical topology relationship) from any processor port to any hard drive.

[0037] In this embodiment, the hard disk control circuit includes: a processor, a master logic control device, a communication bridge, a slave logic control device, and a hard disk. The first port of the processor is connected to the first upstream port of the communication bridge, and the first downstream port corresponding to the first upstream port in the communication bridge is connected to the hard disk. The second port of the processor is connected to the second upstream port of the communication bridge through the master logic control device, and the second downstream port corresponding to the second upstream port in the communication bridge is connected to the hard disk through the slave logic control device. According to this circuit connection method, the master logic control device can perform related operations such as processor port status identification, eliminating the need to use a longer communication link to identify the processor port status with the backplane CPLD, saving port status transmission time, thereby improving the efficiency of processor port status identification, eliminating the traditional longer communication link transmission, and converting multi-module joint debugging problems into single-node diagnosis problems, reducing error rates.

[0038] See also Figure 4 As shown, the embodiment of the present application discloses a hard disk control method, which is applied to the hard disk control circuit described in other embodiments, including:

[0039] S401: The processor generates a hard disk light-on instruction and transmits the hard disk light-on instruction to a main logic control device connected to the processor through a target processor port.

[0040] S402: After detecting that the volume management device corresponding to the target processor port is enabled, the main logic control device splits the hard disk light-on instruction into multiple sub-instructions, and transmits the multiple sub-instructions to a communication bridge connected to the main logic control device.

[0041] Before transmitting the multiple sub-commands to the communication bridge, the downlink channel corresponding to the target processor port is activated. After detecting that the volume management device corresponding to the target processor port is not enabled, the hard disk light-on command is discarded.

[0042] S403: The communication bridge transmits the multiple sub-instructions to the slave logic control device connected to the communication bridge.

[0043] S404: The slave logic control device executes a hard disk lighting operation according to the multiple sub-instructions.

[0044] Specifically, the slave logic control device is used to detect whether the corresponding hard disk is in place according to multiple sub-instructions, and perform a hard disk lighting operation on the hard disk in place.

[0045] In this embodiment, the master logic control device and the slave logic control device can be CPLD or other devices. The master logic control device is set on the server mainboard, and the slave logic control device is set on the backplane.

[0046] In one embodiment, the hard disk control circuit further includes a management controller (e.g., a BMC) connected to both the processor and the main logic control device. Accordingly, the main logic control device is configured to capture interaction signals between the processor and the management controller and, based on the interaction signals, detect whether the volume management device corresponding to the target processor port is enabled. Specifically, the main logic control device is configured to: determine that the volume management device corresponding to the target processor port is enabled when the interaction signals determine that the state of the target processor port is a first target value; and determine that the volume management device corresponding to the target processor port is disabled when the interaction signals determine that the state of the target processor port is a second target value.

[0047] In one example, the main logic control device is configured to: upon receiving a hard drive light-on instruction from a management controller, block the hard drive light-on instruction transmitted by the processor. Accordingly, the main logic control device is configured to: set the bus receiving port corresponding to the processor to a high-impedance state to block the hard drive light-on instruction transmitted by the processor. Accordingly, the main logic control device is configured to: upon receiving a light-on control authority relinquishing instruction or a restart instruction from the management controller, set the bus receiving port corresponding to the management controller to a high-impedance state to block the hard drive light-on instruction transmitted by the management controller; and set the bus receiving port corresponding to the processor to a low-impedance state to receive the hard drive light-on instruction transmitted by the processor.

[0048] In this embodiment, the slave logic control device is configured to report the detected hard disk status to the master logic control device. Correspondingly, the master logic control device is configured to report the received hard disk status to the processor.

[0049] In one embodiment, the master logic control device is configured to automatically establish a mapping relationship between processor ports and connector ports within the communication bridge upon power-up based on the connector status within the communication bridge and the hard drive presence signal detected by the slave logic control device. Based on this mapping relationship, the master logic control device determines the corresponding downstream channel for a received hard drive light-on command, specifically, the connection path from the processor to the hard drive.

[0050] In this embodiment, the main logic control device directly connected to the processor can detect whether the volume management device corresponding to the processor port is enabled (i.e., detect the processor port status) nearby, thereby eliminating the need to use a longer communication link with the help of the backplane CPLD to identify the processor port status, saving the transmission time of the port status, thereby improving the efficiency of identifying the processor port status, eliminating the traditional transmission of longer communication links, and converting the multi-module joint debugging problem into a single-node diagnosis problem, reducing the error rate; in addition, the main logic control device can split the hard disk light-up instruction into multiple sub-instructions, and transmit the multiple sub-instructions to the downstream communication bridge and the slave logic control device, so that the connector in the communication bridge has more free pins, which is conducive to the expanded monitoring of other types of data such as temperature.

[0051] It should be noted that a dual-master control architecture can be used to dynamically switch the control of the lighting signal between the CPU and the BMC. Figure 5 The mainboard houses the CPU, BMC, mainboard CPLD, and an MCIO connector; the backplane houses the backplane CPLD, MCIO connector, and numerous hard drive connectors. The mainboard MCIO connector and the backplane MCIO connector form a communication bridge. When the CPU is used as the master controller, a system-wide hard drive on-disk command is issued via the SCL / SDA bus matrix of the VPP (VMD Port Physical) protocol. The mainboard CPLD (the master logic control device) receives the CPU's hard drive on-disk command via the VPP bus and parses the command to identify the CPU port number (PORT_ID) and the corresponding on-disk status code. The command is one bit long, and the on-disk status code occupies two bits. When the VMD_ENABLE state of the corresponding CPU port is enabled, the global on-disk command is split into MCIO port sub-commands based on a pre-stored truth table (which records the hardware connection between the CPU port number and the mainboard MCIO connector). The sub-commands are then transmitted via the SMBus (System Management Bus) through the downstream MCIO connector (the MCIO connector on the backplane) to the backplane CPLD (the slave logic control device) for execution. When the system switches to BMC control mode, the BMC obtains control over the lights and then turns on the lights. VMD (Volume Management Device) is the volume management device.

[0052] In this example, each x8 MCIO port is assigned two sets of 8-bit lighting data. The address bits of each set are fixed at 0x40. This unified address ensures decoupling of the backplane CPLD code. Furthermore, when the motherboard CPLD lacks I / O pin resources, an I2C switch chip (such as the PCA9546) can be used to expand a single SMBus channel into multiple independent channels through address decoding. Specifically, an I2C switch chip is placed between the motherboard CPLD and the motherboard MCIO connector to expand the single SMBus channel into multiple independent channels.

[0053] and Figure 5In the process, the motherboard CPLD establishes a communication link with the CPU via the eSPI bus, capturing the interaction signals (CPU port status) between the CPU and BMC in real time and parsing the VMD enable status packets transmitted by eSPI from the CPU port. If VMD_STATUS = 1 on a CPU port, the corresponding MCIO downlink channel is activated and the light-on command is sent to the target backplane CPLD. If VMD_STATUS = 0, all pending light-on commands for that port are discarded.

[0054] When the mainboard CPLD receives a light-on command from the BMC via the SMBus, it immediately sets the CPU's VPP bus receiving port to a high-impedance state, blocking the light-on command from the CPU until it receives a light-on control relinquishment command from the BMC or the system is restarted and restored to the default settings.

[0055] The backplane's upstream MCIO ports correspond one-to-one with the I2C bus. Each MCIO port corresponds to a set of I2C buses, containing the lighting information for two hard drives. The backplane's CPLD parses the lighting information sent from the I2C bus and checks the hard drive's presence. If a hard drive is present, the lighting command is executed; if not, the lighting command is disabled.

[0056] Each set of indicator light information corresponds to 8 bits of data. In this example, the hard drive indicator light command only uses bits 0 and 1, which control the illumination of the same indicator light in different colors. A red light indicates an error, a blue light indicates the hard drive is in place, and a pink light indicates a rebuild and recovery. Unused bits 2-7 can be redefined, for example, Bit 4 indicates the hard drive is in place (PRSNT), Bit 5 controls independent hard drive power-on (POWEREN), and Bit 6 triggers hard drive power-saving mode (PWRDIS). Through custom functions, the backplane CPLD responds to motherboard status queries and returns status information such as the current location and power supply.

[0057] The I2C bus signal pins between the motherboard CPLD and the backplane CPLD are configured in open-drain (OD) mode, with integrated 1kΩ pull-up resistors on the backplane and 100kΩ pull-down resistors on the motherboard. During the boot process, the motherboard CPLD switches the downstream I2C SDA / SCL pins to input mode and detects their voltage levels. If the SDA / SCL pins on the I2C bus are detected to be consistently low, the corresponding MCIO port is determined to be disconnected from the backplane. If they are consistently high or exhibit high-level pulses, the MCIO port is considered connected to the backplane and recorded as a valid topological node. A dynamic truth table is constructed based on the MCIO port connection status and the hard drive presence signal (PRSNT) returned by the backplane CPLD, automatically mapping the physical topology from CPU to MCIO connector to backplane to hard drive. If an MCIO port is detected to be connected but no hard drive is present, it is marked as pending expansion, and the operating system blocks the port's lighting command.

[0058] See Figure 6 The motherboard houses the CPU, BMC, motherboard CPLD, and an MCIO connector; the backplane houses the backplane CPLD, MCIO connector, and numerous hard drive connectors; the PCIE switch board (i.e., the switch device) houses the MCIO X8 connector (i.e., the first connector), the PCIE switch (i.e., the switch module), and another MCIO X8 connector (i.e., the second connector). The motherboard MCIO connector, the backplane MCIO connector, the PCIE switch board MCIO X8 connector, the PCIE switch (bridge controller), and another MCIO X8 connector form a communication bridge. When the motherboard CPLD detects that the CPU port corresponding to an MCIO X8 interface sends a light-on command exceeding two sets of data, it triggers the downlink link type determination mechanism, determining that the downlink is connected to the backplane via the PCIE switch board. In this case, if the VMD corresponding to that CPU port is in the ENABLE state, the motherboard CPLD transparently transmits the light-on data corresponding to that CPU port to the lower-level CPLD. Taking the PCI ESWITCH board (SW board) as an example, the amount of light-on data received by the SW board's CPLD is directly proportional to the number of MCIO ports expanded on the SW board. For example, if the SW board has one MCIO X8 connector on the upstream side and four MCIO X8 connectors on the downstream side, the SW board's CPLD will receive eight sets of light-on data and distribute the data to each downstream port based on the hardware connection topology. Through layered transparent transmission and topology adaptation mechanisms, the backplane achieves hardware compatibility with both the motherboard upstream and the switch board upstream, ensuring consistency in backplane design.

[0059] See Figure 7 , a hard disk control method includes:

[0060] ① When the server is powered on, the mainboard CPLD receives the system-wide lighting information from the CPU and binds the lighting command corresponding to the CPUPORT to the corresponding MCIO X8 interface based on the truth table.

[0061] ② The mainboard CPLD traverses each set of lighting information and determines whether the CPU port corresponding to each set of lighting information is in VMDENABLE state. If VMD ENABLE = 1, the lighting information is distributed / transparently transmitted to the downstream board; if VMD ENABLE = 0, the lighting information corresponding to the CPU port is shielded to avoid invalid signal transmission.

[0062] ③ The motherboard CPLD checks the amount of LED data associated with each MCIO x8 port. If the current port corresponds to two sets of LED information, the downstream is determined to be directly connected to the hard drive backplane. The two sets of LED information corresponding to the CPU port are repackaged, the address bits are unified to 0x40, and then sent to the backplane CPLD via the MCIO port. If the current port corresponds to more than two sets of LED information, it is determined that the downstream link is transferred through the PCIe switch board, and the original LED data is directly transmitted to the switch board CPLD.

[0063] ④ For the SW board, the SW board CPLD distributes data to the I2C bus corresponding to each downstream MCIO port based on the hardware connection relationship. The data content format is consistent with the lighting command format issued by the mainboard CPLD in the scenario where the mainboard is directly connected to the backplane.

[0064] ⑤ For the backplane, parse each set of lighting data in the I2C bus (each set contains 2 instructions) to detect whether the target hard disk is in place: if the hard disk is in place, drive the corresponding LED to perform the lighting / extinguishing operation; if the hard disk is not in place, discard the set of instructions and record the abnormal status.

[0065] In this embodiment, a CPLD-level state determination and data transparent transmission mechanism enables plug-and-play compatibility between the same backplane and heterogeneous motherboard platforms, eliminating adaptation issues caused by different VPP / CPU ADDRs across different platforms. The MCIO connector pinout strategy has been optimized: the VPP / CPU ADDR signals previously occupied seven pins, but now only require two pins to achieve equivalent functionality. The five pins saved can be used to configure functional expansion interfaces (such as temperature sensors), improving hardware resource utilization and system scalability. The motherboard CPLD integrates topology state self-awareness, enabling real-time analysis of CPU-issued power-up commands and VMD enable status, and synchronously mapping them to downstream devices (such as the backplane or switch). Furthermore, key status information (such as power-up command dispatch counts and hard drive presence status) is exposed through CPLD registers. Direct register reads are supported to locate the cause of anomalies (such as VMD disabled or link down), transforming traditional multi-module joint debugging issues into single-node diagnostic issues, reducing debugging workload.

[0066] The following describes an electronic device provided in an embodiment of the present application. The electronic device described below can be cross-referenced with other embodiments described herein. The electronic device in this embodiment can be any of the devices mentioned in the previous embodiments, such as a processor, a master logic control device, a communication bridge, and a slave logic control device.

[0067] An embodiment of the present application discloses an electronic device, which may include: the hard disk control circuit described in other embodiments.

[0068] An embodiment of the present application discloses an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the method disclosed in any of the above embodiments.

[0069] In one example, an electronic device includes at least one hard disk control circuit according to any of the preceding embodiments. The hard disk control circuit includes a processor, a master logic control device, a communication bridge, and a slave logic control device. Multiple hard disk connectors are connected downstream of the slave logic control device, each of which can accommodate a single hard disk. The hard disks can be NVME drives or other types. In this electronic device, the master logic control device, directly connected to the processor, can locally detect whether the volume management device corresponding to the processor port is enabled (i.e., detect the processor port status). This eliminates the need for a backplane CPLD to identify the processor port status via a longer communication link, saving port status transmission time and improving processor port status identification efficiency. This eliminates the need for traditional longer communication link transmission, transforming multi-module joint debugging issues into single-node diagnostic issues and reducing error rates. Furthermore, the master logic control device can split the hard disk light-on command into multiple sub-commands and transmit these sub-commands to the downstream communication bridge and slave logic control device. This allows for more unused pins on the connector within the communication bridge, facilitating the expanded monitoring of other data types, such as temperature.

[0070] The processor is used to generate a hard disk light-on instruction and transmit the hard disk light-on instruction to a main logic control device connected to the processor through a target processor port.

[0071] The main logic control device is configured to, upon detecting that the volume management device corresponding to the target processor port is enabled, split the hard disk light-on command into multiple sub-commands and transmit the multiple sub-commands to a communication bridge connected to the main logic control device. Prior to transmitting the multiple sub-commands to the communication bridge, the downlink channel corresponding to the target processor port is activated. Upon detecting that the volume management device corresponding to the target processor port is not enabled, the hard disk light-on command is discarded.

[0072] The communication bridge is used for transmitting a plurality of sub-commands to a slave logic control device connected to the communication bridge.

[0073] The slave logic control device is used to execute the hard disk lighting operation according to multiple sub-instructions. Specifically, the slave logic control device is used to: detect whether the corresponding hard disk is in place according to the multiple sub-instructions, and execute the hard disk lighting operation for the hard disk in place.

[0074] In one embodiment, the hard disk control circuit further includes a management controller (e.g., a BMC) connected to both the processor and the main logic control device. Accordingly, the main logic control device is configured to capture interaction signals between the processor and the management controller and, based on the interaction signals, detect whether the volume management device corresponding to the target processor port is enabled. Specifically, the main logic control device is configured to: determine that the volume management device corresponding to the target processor port is enabled when the interaction signals determine that the state of the target processor port is a first target value; and determine that the volume management device corresponding to the target processor port is disabled when the interaction signals determine that the state of the target processor port is a second target value.

[0075] In one example, the main logic control device is configured to: upon receiving a hard drive light-on instruction from a management controller, block the hard drive light-on instruction transmitted by the processor. Accordingly, the main logic control device is configured to: set the bus receiving port corresponding to the processor to a high-impedance state to block the hard drive light-on instruction transmitted by the processor. Accordingly, the main logic control device is configured to: upon receiving a light-on control authority relinquishing instruction or a restart instruction from the management controller, set the bus receiving port corresponding to the management controller to a high-impedance state to block the hard drive light-on instruction transmitted by the management controller; and set the bus receiving port corresponding to the processor to a low-impedance state to receive the hard drive light-on instruction transmitted by the processor.

[0076] In this embodiment, the slave logic control device is configured to report the detected hard disk status to the master logic control device. Correspondingly, the master logic control device is configured to report the received hard disk status to the processor.

[0077] In one embodiment, the master logic control device is configured to automatically establish a mapping relationship between processor ports and connector ports within the communication bridge upon power-up based on the connector status within the communication bridge and the hard drive presence signal detected by the slave logic control device. Based on this mapping relationship, the master logic control device determines the corresponding downstream channel for a received hard drive light-on command.

[0078] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: after detecting that the volume management device corresponding to the target processor port of the processor is enabled, the hard disk light-on instruction sent by the processor is split into multiple sub-instructions; the multiple sub-instructions are transmitted to the slave logic control device through the communication bridge, so that the slave logic control device performs the hard disk light-on operation according to the multiple sub-instructions.

[0079] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: after detecting that the volume management device corresponding to the target processor port is not enabled, discarding the hard disk light-on instruction.

[0080] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: capturing interaction signals between the processor and the management controller, and detecting whether the volume management device corresponding to the target processor port is enabled through the interaction signals.

[0081] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: when it is determined through the interactive signal that the state of the target processor port is a first target value, it is determined that the volume management device corresponding to the target processor port is enabled; when it is determined through the interactive signal that the state of the target processor port is a second target value, it is determined that the volume management device corresponding to the target processor port is not enabled.

[0082] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: if a hard disk light-on instruction sent by the management controller is received, the hard disk light-on instruction transmitted by the processor is shielded.

[0083] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: setting the bus receiving port corresponding to the processor to a high impedance state to shield the hard disk light-on instruction transmitted by the processor.

[0084] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: if a light-on control abandonment instruction or a restart instruction is received from the management controller, the bus receiving port corresponding to the management controller is set to a high-impedance state to shield the hard disk light-on instruction transmitted by the management controller; the bus receiving port corresponding to the processor is set to a low-impedance state to receive the hard disk light-on instruction transmitted by the processor.

[0085] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: before transmitting the multiple sub-instructions to the communication bridge, activating the downlink channel corresponding to the target processor port.

[0086] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: detecting whether the corresponding hard disk is in place according to multiple sub-instructions, and performing a hard disk lighting operation on the hard disk in place.

[0087] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: synchronizing the state of the target processor port to the slave logic control device and / or the bridge controller.

[0088] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: reporting the detected hard disk status to the main logic control device.

[0089] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: reporting the received hard disk status to the processor.

[0090] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: when powered on, based on the connector status in the communication bridge and the hard disk presence signal detected from the logic control device, automatically build a mapping relationship between the processor port and the connector port in the communication bridge.

[0091] Furthermore, the embodiment of the present application also provides an electronic device. The electronic device can be Figure 8 The server shown can also be Figure 9 The terminal shown. Figure 8 and Figure 9 Each of the diagrams is a structural diagram of an electronic device according to an exemplary embodiment, and the contents in the diagrams cannot be considered as any limitation on the scope of use of the present application.

[0092] Figure 8 This is a schematic diagram of the structure of a server provided in an embodiment of the present application. The server may specifically include: at least one processor, at least one memory, a power supply, a communication interface, an input / output interface, and a communication bus. The memory is used to store a computer program, which is loaded and executed by the processor to implement the relevant steps of hard disk control disclosed in any of the aforementioned embodiments.

[0093] In this embodiment, the power supply is used to provide operating voltage for each hardware device on the server; the communication interface can create a data transmission channel between the server and external devices. The communication protocol it follows is any communication protocol that can be applied to the technical solution of this application and is not specifically limited here; the input and output interface is used to obtain external input data or output data to the outside world. The specific interface type can be selected according to specific application needs and is not specifically limited here.

[0094] In addition, the memory as a carrier for resource storage can be a read-only memory, random access memory, disk or CD, etc. The resources stored thereon include operating system, computer programs and data, etc. The storage method can be temporary storage or permanent storage.

[0095] The operating system is used to manage and control the hardware devices and computer programs on the server, enabling the processor to operate and process data in the memory. It can be Windows Server, NetWare, Unix, Linux, etc. In addition to computer programs capable of implementing the hard disk control method disclosed in any of the aforementioned embodiments, computer programs can also include computer programs capable of performing other specific tasks. Data can include data such as application update information and information about the application developer.

[0096] Figure 9 This is a schematic diagram of the structure of a terminal provided in an embodiment of the present application. The terminal may specifically include but is not limited to a smartphone, tablet computer, laptop computer or desktop computer.

[0097] Generally, the terminal in this embodiment includes: a processor and a memory.

[0098] The processor may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor may be implemented in at least one of the following hardware forms: a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), or a PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is used to process data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing content required to be displayed on the display. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0099] The memory may include one or more computer non-volatile storage media, which may be non-transitory. The memory may also include high-speed random access memory, and non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory is at least used to store the following computer program, wherein, after the computer program is loaded and executed by the processor, it can implement the relevant steps in the hard disk control method performed by the terminal side disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory may also include an operating system and data, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include but is not limited to update information of the application.

[0100] In some embodiments, the terminal may further include a display screen, an input and output interface, a communication interface, a sensor, a power supply, and a communication bus.

[0101] Those skilled in the art will understand that Figure 9 The structure shown in the figure does not constitute a limitation to the terminal, and may include more or fewer components than shown in the figure.

[0102] A non-volatile storage medium provided in an embodiment of the present application is introduced below. The non-volatile storage medium described below can be referenced with other embodiments described herein.

[0103] A non-volatile storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the hard disk control method disclosed in the aforementioned embodiment. The non-volatile storage medium is a computer-readable non-volatile storage medium that, as a carrier for resource storage, can be a read-only memory, random access memory, magnetic disk, or optical disk. The resources stored thereon include an operating system, computer program, and data, and the storage method can be either temporary or permanent.

[0104] In this embodiment, when the processor executes a computer program stored in a non-volatile storage medium, the following steps can be specifically implemented: after detecting that the volume management device corresponding to the target processor port of the processor is enabled, the hard disk light-on instruction sent by the processor is split into multiple sub-instructions; the multiple sub-instructions are transmitted to the slave logic control device through the communication bridge, so that the slave logic control device performs the hard disk light-on operation according to the multiple sub-instructions.

[0105] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: after detecting that the volume management device corresponding to the target processor port is not enabled, discarding the hard disk light-on instruction.

[0106] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: capturing the interaction signal between the processor and the management controller, and detecting whether the volume management device corresponding to the target processor port is enabled through the interaction signal.

[0107] In this embodiment, when the processor executes a computer program stored in a non-volatile storage medium, the following steps may be specifically implemented: when it is determined through an interactive signal that the state of the target processor port is a first target value, it is determined that the volume management device corresponding to the target processor port is enabled; when it is determined through an interactive signal that the state of the target processor port is a second target value, it is determined that the volume management device corresponding to the target processor port is not enabled.

[0108] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: if a hard disk light-on instruction is received from the management controller, the hard disk light-on instruction transmitted by the processor is shielded.

[0109] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: the bus receiving port corresponding to the processor is set to a high impedance state to shield the hard disk light-on instruction transmitted by the processor.

[0110] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: if a light-on control abandonment instruction or restart instruction is received from the management controller, the bus receiving port corresponding to the management controller is set to a high-impedance state to shield the hard disk light-on instruction transmitted by the management controller; the bus receiving port corresponding to the processor is set to a low-impedance state to receive the hard disk light-on instruction transmitted by the processor.

[0111] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: before transmitting the multiple sub-instructions to the communication bridge, activating the downlink channel corresponding to the target processor port.

[0112] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, it can specifically implement the following steps: detecting whether the corresponding hard disk is in place according to multiple sub-instructions, and performing a hard disk lighting operation on the hard disk in place.

[0113] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: synchronizing the state of the target processor port to the slave logic control device and / or the bridge controller.

[0114] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: reporting the detected hard disk status to the main logic control device.

[0115] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: reporting the received hard disk status to the processor.

[0116] In this embodiment, when the processor executes a computer program stored in a non-volatile storage medium, the following steps can be specifically implemented: when powered on, a mapping relationship between the processor port and the connector port in the communication bridge is automatically established based on the connector status in the communication bridge and the hard disk presence signal detected from the logic control device.

[0117] A computer program product provided in an embodiment of the present application is introduced below. The computer program product described below can be referenced with other embodiments described herein.

[0118] A computer program product includes a computer program / instruction, which implements the steps of the hard disk control method disclosed above when executed by a processor.

[0119] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium is used to store a computer program, and when the computer program is executed by a processor, the steps in any of the above embodiments are implemented.

[0120] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0121] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of non-volatile storage medium known in the art.

[0122] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A hard disk control circuit, characterized in that: include: Processor, master logic control device, communication bridge, slave logic control device and hard disk; The first port of the processor is connected to the first uplink port of the communication bridge, and the first downlink port corresponding to the first uplink port in the communication bridge is connected to the hard disk; The second port of the processor is connected to the second uplink port of the communication bridge through the master logic control device, and the second downlink port corresponding to the second uplink port in the communication bridge is connected to the hard disk through the slave logic control device; The third port of the processor is connected to the main logic control device through the management controller; The processor generates a hard disk light-on instruction, and transmits the hard disk light-on instruction to the main logic control device through the second port; After detecting that the volume management device corresponding to the second port is enabled, the main logic control device splits the hard disk light-on instruction into multiple sub-instructions and transmits the multiple sub-instructions to the communication bridge; The communication bridge transmits the plurality of sub-commands to the slave logic control device; The slave logic control device executes the hard disk lighting operation according to the multiple sub-instructions; The hard disk control circuit also includes: a management controller connected to both the processor and the main logic control device; accordingly, the main logic control device captures the interaction signal between the processor and the management controller, and detects whether the volume management device corresponding to the second port is enabled through the interaction signal; when it is determined through the interaction signal that the state of the second port is a first target value, it is determined that the volume management device corresponding to the second port is enabled; when it is determined through the interaction signal that the state of the second port is a second target value, it is determined that the volume management device corresponding to the second port is not enabled.

2. The hard disk control circuit according to claim 1, wherein: The communication bridge includes: an uplink connector and a downlink connector that are connected to each other and are equal in number; the first uplink port and the second uplink port are arranged on the uplink connector; the first downlink port and the second downlink port are arranged on the downlink connector.

3. The hard disk control circuit according to claim 2, wherein: The processor, the master logic control device, the management controller and the upstream connector are arranged on a mainboard; the slave logic control device, the hard disk and the downstream connector are arranged on a backplane.

4. The hard disk control circuit according to claim 3, wherein: The main board is connected to a plurality of back boards.

5. The hard disk control circuit according to claim 1, wherein: A level conversion module is connected between the second port and the main logic control device.

6. The hard disk control circuit according to claim 1, wherein: The communication bridge includes: an uplink connector, a switching device, and a downlink connector connected in sequence; the first uplink port and the second uplink port are provided on the uplink connector; the first downlink port and the second downlink port are provided on the downlink connector.

7. The hard disk control circuit according to claim 6, wherein: The switching device includes: a first connector, a switching module, and a second connector connected in sequence; the first connector is connected to the upstream connector and the number of the first connector is equal to the number of the upstream connector; the second connector is connected to the downstream connector and the number of the second connector is equal to the number of the downstream connector; the first connector is also connected to the second connector through a bridge controller; the number of the first connector and the second connector is equal.

8. The hard disk control circuit according to any one of claims 1 to 7, characterized in that: The main logic control device is used to automatically construct and record the physical topology relationship between the processor port and the hard disk when powered on.

9. A hard disk control method, characterized in that: The hard disk control circuit according to any one of claims 1 to 8, comprising: a processor, a master logic control device, a communication bridge, a slave logic control device, and a hard disk, including: The processor generates a hard disk light-on instruction, and transmits the hard disk light-on instruction to the main logic control device connected to the processor through the target processor port; After detecting that the volume management device corresponding to the target processor port is enabled, the main logic control device splits the hard disk light-on instruction into multiple sub-instructions, and transmits the multiple sub-instructions to the communication bridge connected to the main logic control device; The communication bridge transmits the plurality of sub-commands to the slave logic control device connected to the communication bridge; The slave logic control device executes the hard disk lighting operation according to the multiple sub-instructions; The hard disk control circuit also includes: a management controller connected to both the processor and the main logic control device; accordingly, the main logic control device captures the interaction signal between the processor and the management controller, and detects whether the volume management device corresponding to the target processor port is enabled through the interaction signal; when it is determined through the interaction signal that the state of the target processor port is a first target value, it is determined that the volume management device corresponding to the target processor port is enabled; when it is determined through the interaction signal that the state of the target processor port is a second target value, it is determined that the volume management device corresponding to the target processor port is not enabled.

10. The hard disk control method according to claim 9, wherein: The main logic control device discards the hard disk light-on instruction after detecting that the volume management device corresponding to the target processor port is not enabled.

11. The hard disk control method according to claim 9, wherein: If the main logic control device receives the hard disk light-on instruction sent by the management controller, it sets the bus receiving port corresponding to the processor to a high-impedance state to shield the hard disk light-on instruction transmitted by the processor.

12. The hard disk control method according to claim 11, wherein: If the main logic control device receives a command to abandon the lighting control right or a restart command sent by the management controller, it sets the bus receiving port corresponding to the management controller to a high-impedance state to shield the hard disk lighting command transmitted by the management controller; and sets the bus receiving port corresponding to the processor to a low-impedance state to receive the hard disk lighting command transmitted by the processor; The slave logic control device detects whether the corresponding hard disk is in place according to the multiple sub-instructions, and performs a hard disk lighting operation on the hard disk in place.

13. The hard disk control method according to any one of claims 9 to 12, characterized in that: The communication bridge includes: an equal number of interconnected upstream connectors and downstream connectors; the upstream connector is connected to the master logic control device and the processor, and the downstream connector is connected to the slave logic control device; Alternatively, the communication bridge includes: an upstream connector, a switching device and a downstream connector connected in sequence; the upstream connector connects the master logic control device and the processor, and the downstream connector connects the slave logic control device; the switching device includes: a first connector, a switching module and a second connector connected in sequence; the first connector is connected to the upstream connector and the number is equal to the upstream connector; the second connector is connected to the downstream connector and the number is equal to the downstream connector; the first connector is also connected to the second connector through a bridge controller; the number of the first connector and the second connector is equal; the number of sub-instructions received by the bridge controller is directly proportional to the number of its downstream channels.

14. The hard disk control method according to claim 13, wherein: The master logic control device synchronizes the state of the target processor port to the slave logic control device and / or the bridge controller; The slave logic control device reports the detected hard disk status to the master logic control device; correspondingly, the master logic control device reports the received hard disk status to the processor; When the master logic control device is powered on, the master logic control device automatically constructs and records the physical topology relationship between the processor port and the hard disk according to the connector status in the communication bridge and the hard disk presence signal detected by the slave logic control device.

15. An electronic device, characterized in that: include: The hard disk control circuit according to any one of claims 1 to 8.

16. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to execute the computer program to implement the hard disk control method according to any one of claims 9 to 14.

17. A non-volatile storage medium, characterized in that: Used to store a computer program, wherein when the computer program is executed by a processor, the hard disk control method according to any one of claims 9 to 14 is implemented.

18. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the hard disk control method according to any one of claims 9 to 14 is implemented.

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