Multi-link automatic matching device, control method and electronic equipment

Abstract

The invention discloses a multi-link automatic matching device, a control method and electronic equipment, and relates to the technical field of electronic equipment, the multi-link automatic matching device comprises a high-speed signal processing module, a capacitor, a plurality of signal operation management linkers and a self-adaptive matcher, the capacitor identifies the voltage type of an output signal of the high-speed signal processing module, and the self-adaptive matcher carries out self-adaptive matching on the signal operation management linkers; the self-adaptive matcher can distribute the output signal of the high-speed signal processing module to the signal operation management linker with the rated voltage matched with the voltage type of the high-speed signal processing module, so that the technical problem that the same PCB cannot be compatible with two or more link topologies is solved; the technical effect of automatically matching the corresponding signal operation management linker according to the voltage of the output signal of the high-speed signal processing module is achieved.

Description

Technical Field

[0001] This application relates to the technical field of electronic devices, and particularly to multi-link automatic matching devices, control methods, and electronic devices. Background Art

[0002] With the rapid development of artificial intelligence fields such as robots, speech recognition, image recognition, natural language processing, expert systems, machine learning, and computer vision, users have higher and higher requirements for data transmission and data processing. With the increase in data transmission rate, users also have higher and higher requirements for signal quality.

[0003] However, the link topologies of linkers produced by different manufacturers are different. Limited by the number of pins of the output signal on the Retimer chip, which is a group of X16 PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) signals, different link topologies cannot be applied in the same PCB (Printed Circuit Board). If users need to be compatible with two link topologies simultaneously, they need to design two circuit boards, consuming a large amount of manpower and material resources. Summary of the Invention

[0004] This application provides a multi-link automatic matching device, including: a high-speed signal processing module, a plurality of signal operation management linkers, and an adaptive matcher. Among them, the rated voltages of the plurality of signal operation management linkers are different; the adaptive matcher is configured to receive the output signal of the high-speed signal processing module and distribute the output signal to the corresponding signal operation management linker according to the voltage of the output signal of the high-speed signal processing module. To at least solve the problem of compatible different link topology linkers in the same PCB board in the related art.

[0005] This application also provides an automatic control method for an adaptive matcher, which is applied to the above multi-link automatic matching device, including: identifying the voltage of the output signal of the high-speed signal processing module; distributing the output signal to the corresponding signal operation management linker according to the identified voltage.

[0006] This application provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of the above automatic control method of the adaptive matcher when executing the computer program.

[0007] With this application, since an adaptive matcher is provided at the output end of the high-speed signal processing module, the adaptive matcher can distribute the output signal of the high-speed signal processing module to the signal operation management linker whose rated voltage matches its voltage type according to the voltage type of the output signal of the high-speed signal processing module. Therefore, the technical problem that the same PCB cannot be compatible with two or more link topologies can be solved, and the technical effect of automatically matching the corresponding signal operation management linker according to the voltage of the output signal of the high-speed signal processing module can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0009] Figure 1 Schematic diagram of the internal connection of a multi-link automatic matching device provided by an embodiment of the present application; Figure 2 Schematic diagram of the relative position relationship between the preset points of an adaptive matching pin and the output end of the adaptive matcher provided by an embodiment of the present application; Figure 3 Schematic diagram of the package structure of an adaptive matcher provided by an embodiment of the present application; Figure 4 Schematic diagram of the arrangement of the input end and the output end in the package structure of an adaptive matcher provided by an embodiment of the present application; Figure 5 Schematic diagram of the steps of an automatic control method for an adaptive matcher provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0010] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0011] It should be noted that in the description of this application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0012] In order to enable those skilled in the art of this technology to better understand the solution of this application, the following further details this application in conjunction with the drawings and specific embodiments.

[0013] Figure 1 For the internal connection schematic diagram of a multi-link automatic matching device provided by an embodiment of this application, please refer to Figure 1 , this application provides a multi-link automatic matching device 100, including: a high-speed signal processing module 10, a plurality of signal operation management linkers 30, and an adaptive matcher 20, wherein the rated voltages of the plurality of signal operation management linkers 30 are different; the adaptive matcher 20 is configured to receive the output signal of the high-speed signal processing module 10 and distribute the output signal to the corresponding signal operation management linker 30 according to the voltage of the output signal of the high-speed signal processing module 10. It should be noted that Figure 1 only the case where the multi-link automatic matching device 100 includes 3 signal operation management linkers 30 is schematically shown. It can be understood that the number of signal operation management linkers 30 can be greater than 3, and this application does not limit this.

[0014] In an alternative embodiment provided by this application, please refer to Figure 1, the multi-link automatic matching device 100 includes a high-speed signal processing module 10. Exemplarily, the high-speed signal processing module 10 includes a Retimer chip and other processors with high-speed signal processing functions, and the present disclosure does not limit this. A Retimer chip is an integrated circuit chip for high-speed signal transmission. Through the internal clock data recovery (CDR) circuit, it extracts clock information from the input signal, re-samples and shapes the signal, and eliminates jitter, attenuation, and distortion introduced during transmission. The Retimer chip re-times the signal according to the recovered clock signal to ensure accurate signal timing, thereby extending the signal transmission distance and improving transmission quality. Its core function is to regenerate, shape, and re-time the signal to ensure the integrity and stability of the signal in a long-distance or complex transmission environment, and can solve the signal attenuation problem after long-distance transmission or complex circuit board wiring; secondly, the Retimer chip can extend the signal transmission distance, enabling reliable data interaction between devices at a greater distance. For example, in USB or PCIE interfaces, the Retimer chip can overcome the limitation of signal transmission distance to extend the transmission distance; the Retimer chip can repair signal distortion caused by problems such as impedance mismatch, reflection, and crosstalk, ensuring accurate data transmission and improving signal integrity; the Retimer chip supports high-speed data transmission by optimizing signal timing and quality, meeting application scenarios with high requirements for bandwidth and rate such as 4K video transmission and high-speed data storage; the Retimer chip can act as an intermediate bridge to adapt and convert signals between devices of different specifications, enabling data interaction between devices with different transmission standards.

[0015] The multi-link automatic matching device 100 further includes a plurality of signal operation and management linkers 30. Exemplarily, the signal operation and management linker 30 includes linkers with operation management and maintenance functions such as OAM (Operations, Administration, and Maintenance) linkers. OAM mainly refers to Ethernet OAM at the link level. It is a set of tools and protocols for Ethernet link operation, management, and maintenance. Ethernet OAM detects network connectivity by sending detection messages periodically or manually, providing functions similar to Ping and Traceroute in IP networks to confirm and locate Ethernet faults. When a connectivity fault is detected, OAM can also cooperate with the protection switching protocol to trigger protection switching to achieve the operation-level reliability goal of network service interruption less than or equal to 50 milliseconds. The core function of the OAM linker is to ensure stable link operation, achieve rapid fault location, and performance monitoring.

[0016] The multi-link automatic matching device 100 further includes an adaptive matcher 20. The input end of the adaptive matcher 20 is connected to the output end of the high-speed signal processing module 10 for receiving the output signal of the high-speed signal processing module 10. The output end of the adaptive matcher 20 is connected to the signal operation management linker 30. Since the rated voltages of different OAM linkers are different, the adaptive matcher 20 is used to distribute the output signal to the corresponding signal operation management linker 30 according to the voltage of the output signal of the high-speed signal processing module 10.

[0017] Through this application, since the adaptive matcher 20 is provided at the output end of the high-speed signal processing module 10, the adaptive matcher 20 can distribute the output signal of the high-speed signal processing module 10 to the corresponding signal operation management linker 30 according to the voltage of the output signal of the high-speed signal processing module 10, and the rated voltage of the signal operation management linker 30 matches the voltage of the output signal of the high-speed signal processing module 10. Therefore, the technical problem that a single PCB board cannot be compatible with two or more link topologies of linkers can be solved, and the technical effect of automatically matching the corresponding signal operation management linker 30 according to the voltage of the output signal of the high-speed signal processing module 10 can be achieved.

[0018] Please continue to refer to Figure 1, this application provides a multi-link automatic matching device 100, including: A capacitor 40 is also provided on the connection line between the high-speed signal processing module 10 and the adaptive matcher 20. The first pole 41 of the capacitor 40 is electrically connected to the output end of the high-speed signal processing module 10, and the second pole 42 of the capacitor 40 is electrically connected to the input end of the adaptive matcher 20. The high-speed signals (such as differential signals, single-ended signals) output by the high-speed signal processing module 10 are essentially electromagnetic waves whose voltage or current changes with time. The transmission quality of high-speed signals highly depends on resistance. When the high-speed signal processing module 10 is, for example, a Retimer chip, the Retimer chip is used in a high-speed serial communication link to receive input signals, recover its clock and data, and then re-transmit the data with a new and clean clock to re-time the signals, which can eliminate the jitter and noise accumulated in long-distance transmission or multi-stage interconnection and improve signal integrity. A capacitor 40 is an electronic component that can store charge and is composed of two conductors (called plates) close to each other and the insulating medium (called dielectric) between them. When a voltage is applied to the two plates of the capacitor 40, positive charges will accumulate on one plate, and negative charges will accumulate on the other plate, thus forming an electric field inside the capacitor 40, and the capacitor 40 stores electrical energy. The capacitor 40 can store electrical energy and release it when needed. The capacitor 40 has the characteristic of blocking direct current and passing alternating current, that is, it allows alternating current signals to pass through while blocking direct current signals. This is because the voltage of the alternating current signal changes with time, causing the capacitor to continuously charge and discharge, forming a current; while the voltage of the direct current signal is constant, and there is no current passing through the capacitor 40 after charging is completed. Connecting the capacitor 40 to the output end of the Retimer chip, since high-speed differential signals (such as PCIe, Ethernet, etc.) are usually alternating current signals and do not contain direct current components. The capacitor is connected in series on the differential output pair of the Retimer to block the direct current voltage difference. To ensure that the direct current bias voltages between the transmitter and the receiver do not interfere with each other, while allowing high-speed alternating current data signals to pass through. It can simplify the interconnection design between different power domains, eliminate common-mode noise, and protect the chip from damage caused by direct current voltage mismatch. The adaptive matcher 20 works closely with the Retimer chip to optimize the integrity of the output signals of the Retimer chip on different transmission channels. The characteristic impedance of the transmission line (such as 50 ohms or 100 ohm differential) must match the impedance of the transmitter and the receiver to avoid signal reflection, which may cause signal distortion. The adaptive matcher 20 is designed to dynamically adjust the matching.

[0019] Please refer to Figure 1, in an optional embodiment provided by the present application, the multi-link automatic matching device 100 includes a high-speed signal processing module 10, a capacitor 40, an adaptive matcher 20, and a plurality of signal operation management linkers 30. Among them, the output end of the high-speed signal processing module 10 is electrically connected to the first pole 41 of the capacitor 40. The adaptive matcher 20 includes an input end and an output end. The second pole 42 of the capacitor 40 is electrically connected to the input end of the adaptive matcher 20. The output end of the adaptive matcher 20 is electrically connected to the input end of the signal operation management linker 30. The adaptive matcher 20 is configured to distribute the output signal of the high-speed signal processing module 10 to the corresponding signal operation management linker 30 according to the voltage of the output signal of the high-speed signal processing module 10 recognized by the capacitor 40.

[0020] The output signal of the high-speed signal processing module 10 is a high-speed and high-quality digital signal. When the capacitor 40 is connected to the output end of the high-speed signal processing module 10, for example, if the output signal of the high-speed signal processing module 10 received by the capacitor 40 is 20Ω, the capacitor 40 will recognize the output signal of the high-speed signal processing module 10 as a low-voltage signal, and the capacitor 40 will transmit the low-voltage signal to the adaptive matcher 20; if the output signal of the high-speed signal processing module 10 received by the capacitor 40 is 20 - 50Ω, the capacitor 40 will recognize the output signal of the high-speed signal processing module 10 as a medium-voltage signal, and the capacitor 40 will transmit the medium-voltage signal to the adaptive matcher 20. Of course, the capacitor 40 can also recognize the output signal of the high-speed signal processing module 10 as a high-voltage signal according to the resistance value carried by the output signal of the high-speed signal processing module 10... and so on. The above are only examples, and the present application does not limit the ranges and classifications of the low-voltage signal, medium-voltage signal, and high-voltage signal recognized by the capacitor 40.

[0021] The circuit inside the adaptive matcher 20 evaluates the voltage range and link status of the output signal by analyzing the signal characteristics (such as signal attenuation degree, reflection situation, eye diagram quality, etc.) output from the capacitor 40. In this process, the capacitor 40, as part of the signal path, its characteristics are one of the considerations. According to the evaluation results, the adaptive matcher 20 adjusts its own output drive strength (swing), pre-emphasis, de-emphasis and other parameters to match the input requirements of different signal operation management linkers 30 and channel losses. For example, if a large link loss is recognized (i.e., corresponding to a lower effective voltage range), the adaptive matcher 20 may increase the drive swing or pre-emphasis. If there are multiple different signal operation management linkers 30, they may support different data rates or communication protocols. The adaptive matcher 20 participates in link training and negotiation, and adjusts the output signal to a rate and protocol compatible with the target signal operation management linker 30. So that the high-speed signal processing module 10 can be seamlessly connected to various signal operation management linkers 30 of different types, different electrical characteristics or different protocols. It can greatly improve the compatibility and flexibility of the system without manually configuring or replacing hardware to match different signal operation management linkers 30. By dynamically adjusting the characteristics of the output signal, the adaptive matcher 20 can compensate for channel losses, minimize reflections and crosstalk, ensure that the signal still maintains high quality when reaching the signal operation management linker 30, thereby reducing the bit error rate and improving the reliability of data transmission. Especially in the face of long-distance, high-attenuation or complex connection scenarios, this adaptive ability is particularly important. The multi-link automatic matching device 100 provided in this application can automatically identify the characteristics of the connected signal operation management linker 30 and automatically adjust the matching parameters, thus realizing a certain degree of plug-and-play function and simplifying the deployment and maintenance of the system.

[0022] The adaptive matcher 20 dynamically adjusts its own output parameters by analyzing the quality of the output signal passing through the capacitor 40 (such as amplitude, waveform integrity, etc.) and evaluating the characteristics of the connected OAM linker. This adjustment enables the signal to be "distributed" (adapted and transmitted) to different signal operation and management linkers 30 in an optimal state, thereby achieving excellent interoperability, signal integrity, reliability, and system performance flexibility. In this way, by setting the capacitor 40 on the connection line between the high-speed signal processing module 10 and the adaptive matcher 20, the voltage type of the output signal of the high-speed signal processing module 10 can be identified by the capacitor 40, and the identification result can be transmitted to the adaptive matcher 20. The adaptive matcher 20 can select the signal operation and management linker 30 with a rated voltage matching this voltage type according to the voltage type output by the capacitor 40. The setting of the capacitor 40 can simplify the voltage identification path of the output signal of the high-speed signal processing module 10 by the adaptive matcher 20, reduce the number of components, and simplify the circuit design. The capacitor 40 is small in volume and low in cost, and is suitable for compact devices or high-density integration scenarios.

[0023] It should be noted that the specific capacitance value of the capacitor 40 can be set according to customer requirements and actual process needs, and this application does not limit it.

[0024] Figure 2 This is a diagram showing the relative position relationship between the preset point positions of an adaptive matching pin provided in an embodiment of this application and the output end of the adaptive matcher. Please refer to Figure 1 and Figure 2 , this application provides a multi-link automatic matching device 100, including: the adaptive matcher 20 at least includes a group of adaptive matching pins 22, and the adaptive matching pins 22 are configured to automatically move to the output end of the adaptive matcher 20 according to the voltage of the output signal of the high-speed signal processing module 10, so as to establish an electrical connection with the signal operation and management linker 30 through the adaptive matching pins 22.

[0025] In an alternative embodiment provided by the present disclosure, as described above, when the input end of the adaptive matcher 20 receives the output signal of the high-speed signal processing module 10 identified by the capacitor 40 as a low-voltage signal, the adaptive matcher 20 receives this low-voltage signal, and based on this low-voltage signal, controls the adaptive matching pin 22 to move to the first position 241 corresponding to the output end of the adaptive matcher 20 and electrically connect to the corresponding signal operation management linker 30, and the rated voltage of the corresponding signal operation management linker 30 matches the low voltage of the output signal of the high-speed signal processing module 10. Similarly, when the output signal of the high-speed signal processing module 10 identified by the capacitor 40 is a medium-voltage signal, the adaptive matcher 20 controls the adaptive matching pin 22 to move to the second position 251 corresponding to the output end of the adaptive matcher 20 and electrically connect to the signal operation management linker 30, and the rated voltage of the corresponding signal operation management linker 30 matches the medium voltage of the output signal of the high-speed signal processing module 10. Similarly, when the output signal of the high-speed signal processing module 10 identified by the capacitor 40 is a high-voltage signal, the adaptive matcher 20 controls the adaptive matching pin 22 to move to the third position 261 corresponding to the output end of the adaptive matcher 20 and electrically connect to the signal operation management linker 30, and the rated voltage of the corresponding signal operation management linker 30 matches the high voltage of the output signal of the high-speed signal processing module 10.

[0026] The setting of the adaptive matching pin 22 allows the multi-link automatic matching device 100 to adapt to multiple interface types at the physical level. Traditional electronic matching mainly adjusts the electrical parameters of signals, while the technical solution in this application can directly physically select different signal paths or connection points. That is, an adaptive matcher 20 can serve multiple signal operation management linkers 30 with different physical sizes or pin layouts without additional adapter boards or complex wiring. By selecting the most suitable physical path, signal loss and reflection on the transmission path can be minimized to reduce the bit error rate and improve the reliability and performance of data transmission. When different signal operation management linkers 30 are inserted, the system can automatically detect and adjust the physical connection without manual intervention. This can greatly simplify the internal device deployment, maintenance, and upgrade processes of the multi-link automatic matching device 100, especially in scenarios where different modules need to be frequently replaced or tested. Although the setting of the adaptive matching pin 22 increases the structural complexity, it can eliminate a large number of complex electronic switching matrices, multiplexers, or expensive custom connectors, thereby reducing the overall system cost or simplifying the circuit board design in specific applications. For highly integrated optical communication systems or test platforms, it can provide higher flexibility. The adaptive matching pin 22 provided in the embodiment of this application provides strong scalability for future support of more types and updated standards of signal operation management linkers 30, only by updating the firmware and movement algorithm of the adaptive matcher 20 without redesigning the entire hardware connection part.

[0027] The adaptive matching pins 22 physically move according to the output signal voltage and establish an electrical connection, which can extend the signal adaptation at the traditional electronic level to the physical connection level, improving the connection flexibility and interoperability with the linkers. The adaptive matcher 20 can automatically select and establish the optimal physical signal path, thus greatly optimizing signal integrity and enhancing reliability, especially suitable for complex high-speed communication systems that need to be compatible with multiple interface types or perform automated tests. In this way, the adaptive matcher 20 can control the movement of the adaptive matching pins 22 according to the voltage type of the output signal of the high-speed signal processing module 10 received and connect with the corresponding signal operation and management linker 30. The rated voltage of the signal operation and management linker 30 electrically connected to the adaptive matching pins 22 can match the voltage type received by the adaptive matcher 20. Different rated voltage signal operation and management linkers 30 can be compatible on the same multi-link automatic matching device 100, meeting the diverse needs of users, improving the adaptation rate, and reducing the labor cost and time cost of repeated research and development.

[0028] Please continue to refer to Figure 1 and Figure 2 This application provides a multi-link automatic matching device 100. A set of adaptive matching pins 22 includes at least 8 pairs of differential signal electrical connection points. Differential Signal is a signal transmission method that transmits information through two complementary signal lines (usually marked as V + and V - ). Its core principle is to judge the logical state of the signal by detecting the voltage difference (V diff =V + -V - ) between these two lines, rather than relying on the absolute voltage of a single line to the ground. This design gives it significant advantages in anti-interference, high-speed transmission, and signal integrity. Differential signals have strong anti-interference ability. External noise (such as electromagnetic interference) will act on both signal lines simultaneously, causing the same amplitude of voltage change in V + and V - . The differential signal electrical connection points can transmit differential signal pairs with the same amplitude and opposite phases, which are used to form the transmission channel of the differential signal. In this embodiment, by designing the adaptive matching pins 22 into a set of 8 pairs of differential signal electrical connection points, the transmission requirements of most Ethernet protocols can be met without adding extra pairs, avoiding resource waste.

[0029] Please continue to refer to Figure 1 and Figure 2 This application provides a multi-link automatic matching device 100. The number of output terminals of the adaptive matcher 20 is n, where n is an integer greater than or equal to 3.

[0030] In an alternative embodiment provided by the present application, the adaptive matcher 20 may include one input terminal and three output terminals. Alternatively, the adaptive matcher 20 may include one input terminal and four output terminals. Alternatively, the adaptive matcher 20 may include one input terminal and five output terminals... and so on. Without listing them all here, it only needs to satisfy that the number of output terminals of the adaptive matcher 20 is greater than or equal to three. In this way, by setting multiple output terminals, each output terminal can match signal operation management linkers 30 with different rated voltages, improving the compatibility and adaptability of the multi-link automatic matching device 100. When the multi-link automatic matching device 100 needs to connect multiple high-speed channels, having a multi-output adaptive matcher can replace multiple single-output or dual-output matching chips, directly reducing the number of chips on the PCB board, thereby reducing the board size and complexity. Fewer chips mean less wiring and smaller PCB area requirements, making the entire design more compact and concise, and can be effectively applied to limited spaces. In addition, multiple output terminals can be configured to adapt to different types of downstream signal operation management linkers 30, which may have different electrical characteristics, transmission rates, or protocol standards. The adaptive matcher 20 can independently adapt and equalize for each output channel, improving versatility. The adaptive matcher 20 has more than three output terminals, enabling higher integration, greater bandwidth, stronger flexibility and reliability, and can more effectively manage and optimize multiple high-speed communication links, thus meeting the stringent requirements of modern high-speed data transmission systems for performance, density, and scalability.

[0031] Please continue to refer to Figure 1 and Figure 2 , the present application provides a multi-link automatic matching device 100. The output terminals of the adaptive matcher 20 include differential signal channels, and the number of differential signal channels in one output terminal of the adaptive matcher 20 is equal to the number of a group of adaptive matching pins 22. Exemplarily, when a group of adaptive matching pins 22 includes eight pairs of differential signal electrical connection points, one output terminal of the adaptive matcher 20 correspondingly includes eight pairs of differential signal channels, that is, the number of differential signal electrical connection points is equal to the number of differential signal channels. Specifically, a group of adaptive matching pins 22 moves to the corresponding output terminal of the adaptive matcher 20, and the eight pairs of differential signal electrical connection points in the adaptive matching pins 22 are electrically connected to the differential signal channels in one output terminal of the adaptive matcher 20 one by one to achieve signal transmission. In this way, when the adaptive matching pins 22 move to the corresponding output terminal of the adaptive matcher 20, since the number of differential signal electrical connection points in the adaptive matching pins 22 is equal to the number of differential signal channels in any one output terminal of the adaptive matcher 20, the integrity and transmission quality of signal transmission can be ensured. In applications that require flexible configuration or expansion of differential signal channels, it can also support flexible configuration and expansion and can adapt to different application requirements.

[0032] Figure 3 Schematic diagram of the encapsulation structure of an adaptive matcher provided by an embodiment of the present application Figure 4 Schematic diagram of the arrangement of the input end and the output end in the encapsulation structure of an adaptive matcher provided by an embodiment of the present application. Please refer to Figures 2 to 4 The present application provides a multi-link automatic matching device 100. The output end of the adaptive matcher 20 includes a first output end 24, a second output end 25, and a third output end 26. Please refer to Figure 2 In the adaptive matcher 20, the preset positions of the adaptive matching pins 22 are a first position 241, a second position 251, and a third position 261. Among them, the first position 241 corresponds to the position of the first output end 24 of the adaptive matcher 20, the second position 251 corresponds to the position of the second output end 25 of the adaptive matcher 20, and the third position 261 corresponds to the position of the third output end 26 of the adaptive matcher 20. The adaptive matcher 20 further includes a driving component 21, and the driving component 21 is configured to receive the output signal of the capacitor 40 and control the movement of the adaptive matching pins 22 to the first position 241 or the second position 251 or the third position 261 according to the output signal of the capacitor 40.

[0033] In an optional embodiment provided by the present application, exemplarily, the position of the first output end 24 corresponds to the signal operation management linker 30 that matches the low-voltage signal. When the capacitor 40 determines that the output signal of the high-speed signal processing module 10 is a low-voltage signal, the driving component 21 in the adaptive matcher 20 receives the low-voltage signal and drives the adaptive matching pins 22 to move to the first position 241 corresponding to the first output end 24 of the adaptive matcher 20. The position of the second output end 25 corresponds to the signal operation management linker 30 that matches the medium-voltage signal. When the capacitor 40 determines that the output signal of the high-speed signal processing module 10 is a medium-voltage signal, the driving component 21 in the adaptive matcher 20 receives the medium-voltage signal and drives the adaptive matching pins 22 to move to the second position 251 corresponding to the second output end 25 of the adaptive matcher 20. The position of the third output end 26 corresponds to the signal operation management linker 30 that matches the high-voltage signal. When the capacitor 40 determines that the output signal of the high-speed signal processing module 10 is a high-voltage signal, the driving component 21 in the adaptive matcher 20 receives the high-voltage signal and drives the adaptive matching pins 22 to move to the third position 261 corresponding to the third output end 26 of the adaptive matcher 20. In this way, the driving component can control the movement of the adaptive matching pins 22 to the preset positions corresponding to different types of voltages according to the received voltage type, and electrically connect to the signal operation management linker 30 that matches the voltage type through the output end of the adaptive matcher 20 at the preset position to realize the transmission of signals.

[0034] Please refer to Figure 3 andFigure 4 , this application provides a multi-link automatic matching device 100, with the input end and the output end located on the same plane.

[0035] In an optional embodiment provided by this application, the adaptive matcher 20 further includes a packaging structure 50. The packaging structure 50 can be a structure with flat planes such as a cube or a cuboid. Of course, it can also be other types of packaging structures 50. Figure 3 Taking the packaging structure 50 as a cuboid for illustration only, this application does not limit this, and it can be specifically designed and adjusted according to the actual process. It can be understood that the packaging structure 50 is used to package the devices inside the adaptive matcher 20, and the input end and the output end of the adaptive matcher 20 are set on only one plane on the surface of the packaging structure 50. Exemplarily, the packaging structure 50 includes a first surface 51, and the first surface 51 is one of the six surfaces of the packaging structure. Figure 3 Taking the first surface 51 as the side surface of the packaging structure 50 for illustration only.

[0036] Please refer to Figure 4 , the input end 23 and the output end 27 of the adaptive matcher 20 include at least one row of differential signal channels, and each row of differential signal channels includes at least one group of X8 PCIE signal channels. PCIE is used to connect external devices on the computer motherboard, such as graphics cards, sound cards, network cards, solid-state drive controllers, etc., to provide faster and more stable connections for various external devices. Optionally, the input end 23 and the output end 27 of the adaptive matcher 20 are arranged in parallel in the same plane of the packaging structure 50. For example, both the input end 23 and the output end 27 are located on the first surface 51 of the packaging structure 50. Optionally, when there are multiple output ends 27, the distance between the input end 23 and the adjacent output end 27 and the distance between each output end 27 can be equal or not equal, and this application does not limit this. In this way, by packaging the adaptive matcher 20, the packaging structure 50 can physically protect the internal devices of the adaptive matcher 20 from external damage; only the input end 23 and the output end 27 of the adaptive matcher 20 are left on the surface of the packaging structure 50, facilitating the access and connection of external devices. Setting the input end 23 and the output end 27 on the same plane, the coplanar design can reduce the volume of the adaptive matcher 20, be suitable for portable or high-density integration scenarios, shorten the signal path, and reduce the risks of electromagnetic interference and crosstalk; reduce costs, simplify the manufacturing process, and meet the requirements of high frequency, high-density integration and user experience.

[0037] Please continue to refer to Figure 1 and Figure 4 , this application provides a multi-link automatic matching device 100. The number of output ends 27 of the adaptive matcher 20 is the first number, and the number of signal operation management linkers 30 is the second number, and the first number is equal to the second number.

[0038] Understandably, the number of output terminals 27 of the adaptive matcher 20 is greater than or equal to 3. When the adaptive matcher includes 3 output terminals 27, the multi-link automatic matching device 100 includes 3 signal operation management linkers 30 with different rated voltages; when the adaptive matcher includes 4 output terminals 27, the multi-link automatic matching device 100 includes 4 signal operation management linkers 30 with different rated voltages; when the adaptive matcher includes 5 output terminals 27, the multi-link automatic matching device 100 includes 5 signal operation management linkers 30 with different rated voltages... and so on, which will not be listed one by one here. Figure 1 Taking the multi-link automatic matching device 100 including 3 output terminals 27 and 3 signal operation management linkers 30 as an example for illustration, the present application is not limited thereto. In this way, the number of output terminals 27 of the adaptive matcher 20 is equal to the number of signal operation management linkers 30. Then, any output terminal 27 of the adaptive matcher 20 has a signal operation management linker 30 that can be connected to it. That is, according to the user's needs and the number of signal operation management linkers 30 that need to be compatible, the number of output terminals 27 of the adaptive matcher 20 can be flexibly set, reducing the waste of interfaces caused by setting too many output terminals 27 of the adaptive matcher 20 and reducing the shortage of interface numbers caused by setting too few output terminals 27 of the adaptive matcher 20.

[0039] Figure 5 Please refer to Figure 1 and Figure 5 , the present application provides an automatic control method for an adaptive matcher 20, which is applied to the multi-link automatic matching device 100 provided in the present application, including: Step S1: Identify the voltage of the output signal of the high-speed signal processing module 10; Step S2: Distribute the output signal of the high-speed signal processing module 10 to the corresponding signal operation management linker 30 according to the identified voltage.

[0040] In Step S1, since the voltages of the output signals of the high-speed signal processing module 10 are different, the corresponding signal operation management linkers 30 to be connected are different. The automatic control method provided in the embodiment of the present application identifies the voltage types of the output signals of the high-speed signal processing module 10. In Step S2, according to the identified voltage types of the output signals of the high-speed signal processing module 10, a signal operation management linker 30 with a matching voltage can be selected for connection. On this basis, the adaptive matcher 20 provided in the present application can be compatible with multiple signal operation management linkers 30 in the same PCB board by setting multiple different output terminals, improving the intensiveness and adaptability of the device.

[0041] Please refer to Figure 1, in step S1, the voltage of the output signal of the high-speed signal processing module 10 is identified, including: identifying the voltage of the output signal of the high-speed signal processing module 10 by identifying the voltage signal at the output end of the capacitor 40. The multi-link automatic matching device 100 provided in the present application determines whether the output signal of the high-speed signal processing module 10 belongs to a low-voltage signal, a medium-voltage signal, or a high-voltage signal by setting the capacitor 40 in the connection line between the high-speed signal processing module 10 and the adaptive matcher 20 and identifying the resistance carried by the output signal of the high-speed signal processing module 10 through the capacitor 40. In this way, the efficient identification of the voltage type of the output signal of the high-speed signal processing module 10 is realized by installing the capacitor, which facilitates the adaptive matcher 20 to select a suitable output end to connect with the signal operation management linker 30.

[0042] In an alternative embodiment provided by the present application, please refer to Figure 1 and Figure 5 , the adaptive matcher 20 includes multiple output ends, and the positions of the multiple output ends correspond to the multiple signal operation management linkers 30 one by one. In step S2, distributing the output signal of the high-speed signal processing module 10 to the corresponding signal operation management linker 30 according to the identified voltage includes: the adaptive matcher 20 distributes the output signal of the high-speed signal processing module 10 to one of the output ends of the adaptive matcher 20 according to the identified voltage, and the signal operation management linker 30 receives the output signal from the output end of the adaptive matcher corresponding to its position.

[0043] In an alternative embodiment provided by the present application, please refer to Figure 1 and Figure 5 , the adaptive matcher 20 further includes an adaptive matching pin 22. In step S2, distributing the output signal of the high-speed signal processing module 10 to the corresponding signal operation management linker 30 according to the identified voltage includes: the adaptive matcher 20 controls the adaptive matching pin 22 to move to a preset position corresponding to one of the output ends of the adaptive matcher 20 according to the identified voltage type of the output signal of the high-speed signal processing module 10, and engages with the signal operation management linker 30 corresponding to the position of the output end of the adaptive matcher 20 to establish an electrical connection, and the rated voltage of the signal operation management linker 30 engaged with the adaptive matching pin 22 matches the voltage signal received by the driving component 21.

[0044] The present application provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of the automatic control method of the adaptive matcher 20 provided by the present application when executing the computer program.

[0045] The above has introduced in detail a multi-link automatic matching device, a control method and an electronic device provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A multi-link automatic matching device, characterized in that, Comprising: A high-speed signal processing module, a plurality of signal operation management linkers, and an adaptive matcher, wherein the rated voltages of the plurality of signal operation management linkers are different; The adaptive matcher is configured to receive the output signal of the high-speed signal processing module and distribute the output signal of the high-speed signal processing module to the corresponding signal operation management linker according to the voltage of the output signal of the high-speed signal processing module.

2. The multi-link automatic matching device according to claim 1, wherein Comprising: A capacitor is further provided on the connection line between the high-speed signal processing module and the adaptive matcher. The first pole of the capacitor is electrically connected to the output end of the high-speed signal processing module, and the second pole of the capacitor is electrically connected to the input end of the adaptive matcher.

3. The multi-link automatic matching device according to claim 2, characterized in that, The adaptive matcher includes an input end and an output end. The input end of the adaptive matcher is electrically connected to the capacitor, and the output end of the adaptive matcher is connected to the signal operation management linker.

4. The multi-link automatic matching device according to claim 3, characterized in that Comprising: The adaptive matcher includes at least one set of adaptive matching pins, and the adaptive matching pins are configured to automatically move to the output end of the adaptive matcher according to the voltage of the output signal of the high-speed signal processing module, so as to establish an electrical connection with the signal operation management linker through the adaptive matching pins.

5. The multi-link automatic matching device according to claim 4, characterized in that One set of the adaptive matching pins includes at least 8 pairs of differential signal electrical connection points.

6. The multi-link automatic matching device according to claim 5, characterized in that, The number of output ends of the adaptive matcher is n, and n is an integer greater than or equal to 3.

7. The multi-link automatic matching device according to claim 4, characterized in that, The output end of the adaptive matcher includes differential signal channels, and the number of differential signal channels in one output end of the adaptive matcher is equal to the number of one set of adaptive matching pins.

8. The multi-link automatic matching device according to claim 5, characterized in that The output end of the adaptive matcher includes a first output end, a second output end, and a third output end. The preset positions of the adaptive matching pins in the adaptive matcher are a first position, a second position, and a third position, wherein the first position corresponds to the position of the first output end, the second position corresponds to the position of the second output end, and the third position corresponds to the position of the third output end; The adaptive matcher further includes a driving component, and the driving component is configured to receive the output signal of the capacitor and control the adaptive matching pins to move to the first position or the second position or the third position according to the output signal of the capacitor.

9. The multi-link automatic matching device according to claim 3, characterized in that, The input end and the output end are located on the same plane.

10. The multi-link automatic matching device according to claim 3, characterized in that, The number of output ends of the adaptive matcher is a first number, and the number of signal operation management linkers is a second number, and the first number is equal to the second number.

11. An automatic control method for an adaptive matcher, characterized in that, Applied in the multi-link automatic matching device according to any one of claims 1-10, including: Identifying the voltage of the output signal of the high-speed signal processing module; Distributing the output signal to the corresponding signal operation management linker according to the identified voltage.

12. The automatic control method of the adaptive matcher according to claim 11, characterized in that, A capacitor is included between the high-speed signal processing module and the adaptive matcher, The identifying the voltage of the output signal of the high-speed signal processing module includes: identifying the voltage of the output signal of the high-speed signal processing module by identifying the voltage signal at the output end of the capacitor.

13. The automatic control method of the adaptive matcher according to claim 11, characterized in that, The adaptive matcher includes a plurality of output terminals, and the positions of the plurality of output terminals respectively correspond to the plurality of signal operation management linkers one by one; The distributing the output signal to the corresponding signal operation management linker according to the recognized voltage includes: The adaptive matcher distributes the output signal to an output terminal of one of the adaptive matchers according to the recognized voltage, and the signal operation management linker receives the output signal of the output terminal of the adaptive matcher corresponding to its position.

14. The automatic control method of the adaptive matcher according to claim 11, characterized in that, The adaptive matcher further includes an adaptive matching pin, The distributing the output signal of the high-speed signal processing module to the corresponding signal operation management linker according to the recognized voltage signal includes: The adaptive matcher controls the adaptive matching pin to move to an output terminal of one of the adaptive matchers according to the recognized voltage, and engages with the signal operation management linker corresponding to the position of the output terminal of the adaptive matcher to establish an electrical connection.

15. An electronic device, characterized in that, including: a memory for storing a computer program; a processor for implementing the steps of the automatic control method according to any one of claims 11-14 when executing the computer program.

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