PCB design method, device, equipment and storage medium

Abstract

The present application proposes a PCB design method, apparatus, device, and storage medium, wherein the method includes: determining a target stackup in the inner layer of an original PCB; wherein the target stackup is the other wiring layers in the inner layer of the original PCB except for the high-density wiring layer, the ground layer, and the power layer; generating a first stackup for the first daughter card in a new PCB based on the top layer, the power layer, and the target stackup of the original PCB; generating a second stackup for the second daughter card in the new PCB based on the bottom layer and the high-density wiring layer of the original PCB; generating a dummy layer in the new PCB; and generating the new PCB based on the first stackup, the second stackup, and the dummy layer. The technical solution of the present application can reduce the space required for wiring and improve connector compatibility.

Description

Technical Field

[0001] The present application relates to the field of PCB design technology, and in particular to a PCB design method, apparatus, device, and storage medium. Background Art

[0002] In related technologies, the design of staggered placement of high-density press-fit connectors on the bottom layer of the PCB and SMT (Surface Mount Technology) connectors on the top layer is relatively simple, but it will limit wiring space and connector selection. Changing the placement of the above connectors requires redesigning the PCB. Summary of the Invention

[0003] The present application aims to solve one of the technical problems in the related art at least to a certain extent.

[0004] In a first aspect, the present application proposes a PCB design method, the method comprising: determining a target stackup in an inner layer of an original PCB; wherein the target stackup is other wiring layers in the inner layer of the original PCB except a high-density wiring layer, a ground layer, and a power layer; generating a first stackup of a first daughter card in a new PCB based on a top layer, a power layer, and the target stackup of the original PCB; generating a second stackup of a second daughter card in the new PCB based on a bottom layer and a high-density wiring layer of the original PCB; generating a dummy layer in the new PCB; and generating the new PCB based on the first stackup, the second stackup, and the dummy layer.

[0005] In one implementation, generating the first stack of the first daughter card in the new PCB based on the top layer, the power layer, and the target stack of the original PCB includes: generating a first inner layer of the first stack based on the power layer in the original PCB; generating corresponding second inner layers on both sides of the first inner layer based on the target stack; generating a first outer layer of the first stack based on the top layer of the original PCB; wherein the first outer layer includes a first signal layer, and the first signal layer is used to arrange the long wires and metal layer of the top layer of the original PCB.

[0006] In one implementation, generating the second stack of the second daughter card in the new PCB based on the bottom layer and high-density wiring layer of the original PCB includes: generating a third inner layer of the second stack; generating a fourth inner layer corresponding to the high-density wiring layer in the second daughter card on both sides of the third inner layer; generating a second outer layer of the second stack based on the bottom layer of the original PCB; wherein the second outer layer includes a second signal layer and a third signal layer, the second signal layer is used to arrange short lines of the bottom layer of the original PCB, and the third signal layer is used to arrange long lines of the bottom layer of the original PCB.

[0007] In an optional implementation, the method further includes: obtaining a first high-density pin pair number and design requirements of the high-density connector in the original PCB, and device information of the available high-density connector of the new PCB; selecting a candidate high-density connector from the available high-density connectors based on the design requirements and the device information; selecting a target high-density connector from the candidate high-density connectors based on the first high-density pin pair number; obtaining a second high-density pin pair number of the target high-density connector; in response to the first high-density pin pair number being less than the second high-density pin pair number, obtaining a first differential signal pair number in the first high-density pin pair number and a second differential signal pair number in the second high-density pin pair number, and generating a fifth inner layer on both sides of the third inner layer based on the difference between the first differential signal pair number and the second differential signal pair number.

[0008] In one implementation, the total thickness of the first daughter card is less than a preset first thickness threshold; wherein the first thickness threshold is determined according to the length of the non-plated hole corresponding to the hard disk connector of the original PCB.

[0009] In one implementation, the total thickness of the second daughter card is less than a preset second thickness threshold; wherein the second thickness threshold is determined according to the pin length of the high-density connector on the bottom layer of the original PCB.

[0010] In a second aspect, the present application proposes a PCB design device, which includes: a first processing module for determining a target stack in an inner layer of an original PCB; wherein the target stack is other wiring layers in the inner layer of the original PCB except a high-density wiring layer, a ground layer and a power layer; a second processing module for generating a first stack of a first daughter card in a new PCB based on the top layer, the power layer and the target stack of the original PCB; a third processing module for generating a second stack of a second daughter card in the new PCB based on the bottom layer and the high-density wiring layer of the original PCB; a fourth processing module for generating a dummy layer in the new PCB; and a fifth processing module for generating the new PCB based on the first stack, the second stack and the dummy layer.

[0011] In one implementation, the second processing module is used to: generate a first inner layer of the first stack based on the power layer in the original PCB; generate corresponding second inner layers on both sides of the first inner layer based on the target stack; generate a first outer layer of the first stack based on the top layer of the original PCB; wherein the first outer layer includes a first signal layer, and the first signal layer is used to arrange the long wires and metal layer of the top layer of the original PCB.

[0012] In one implementation, the third processing module is used to: generate a third inner layer of the second stack; generate a fourth inner layer in the second daughter card corresponding to the high-density wiring layer on both sides of the third inner layer; generate a second outer layer of the second stack based on the bottom layer of the original PCB; wherein the second outer layer includes a second signal layer and a third signal layer, the second signal layer is used to arrange short lines of the bottom layer of the original PCB, and the third signal layer is used to arrange long lines of the bottom layer of the original PCB.

[0013] In an optional implementation, the third processing module is also used to: obtain the first high-density pin pair number and design requirements of the high-density connector in the original PCB, and the device information of the available high-density connector of the new PCB; select a candidate high-density connector from the available high-density connectors based on the design requirements and the device information; select a target high-density connector from the candidate high-density connectors based on the first high-density pin pair number; obtain the second high-density pin pair number of the target high-density connector; in response to the first high-density pin pair number being less than the second high-density pin pair number, obtain the first differential signal pair number in the first high-density pin pair number and the second differential signal pair number in the second high-density pin pair number, and generate a fifth inner layer on both sides of the third inner layer based on the difference between the first differential signal pair number and the second differential signal pair number.

[0014] In one implementation, the total thickness of the first daughter card is less than a preset first thickness threshold; wherein the first thickness threshold is determined according to the length of the non-plated hole corresponding to the hard disk connector of the original PCB.

[0015] In one implementation, the total thickness of the second daughter card is less than a preset second thickness threshold; wherein the second thickness threshold is determined according to the pin length of the high-density connector on the bottom layer of the original PCB.

[0016] In a third aspect, the present application proposes an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the PCB design method as described in the first aspect.

[0017] In a fourth aspect, the present application proposes a computer-readable storage medium for storing instructions, which, when executed, enables the method described in the first aspect to be implemented.

[0018] In a fifth aspect, the present application proposes a computer program product, comprising a computer program, which, when executed by a processor, implements the steps of the PCB design method as described in the first aspect.

[0019] The PCB design method, apparatus, device, and storage medium provided in this application can generate new stacks corresponding to the first and second daughter cards in a new PCB based on the stacks in the original PCB, thereby obtaining a new PCB that can support the overlapping placement of high-density connectors on the bottom layer and hard drive connectors on the top layer. This can reduce the space required for wiring and improve connector compatibility.

[0020] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0022] Figure 1 This is a flow chart of a PCB design method provided in an embodiment of the present application;

[0023] Figure 2 This is a flow chart of another PCB design method provided in an embodiment of the present application;

[0024] Figure 3 This is a flow chart of another PCB design method provided in an embodiment of the present application;

[0025] Figure 4 This is an example diagram of connector library information provided by an embodiment of the present application;

[0026] Figure 5 This is an example diagram of a PCB design solution provided in an embodiment of the present application;

[0027] Figure 6 This is an example diagram of pin parameters provided in an embodiment of the present application;

[0028] Figure 7 This is a schematic structural diagram of a PCB design device provided in an embodiment of the present application;

[0029] Figure 8 It is a structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0031] In high-density storage backplane design, the conventional approach is to arrange high-density press-fit connectors for connecting to the control board on the bottom layer (Bottom layer), and surface-mount connectors for connecting to the hard drives on the top layer (Top layer). Because the design needs to avoid vertical overlap and interference between the press-fit connector vias and the surface-mount connector pads, the two types of connectors are usually arranged in a staggered manner. While this layout prevents vertical overlap between the connector pins on both sides, simplifying the PCB design process, it also compresses the space available for backplane layout and wiring, increasing wiring difficulty, and limiting the area of ​​the backplane's heat dissipation openings, which is not conducive to heat dissipation. It also restricts the selection of connectors, affecting design flexibility and performance expansion.

[0032] The following describes the PCB design method and device according to the embodiments of the present application with reference to the accompanying drawings.

[0033] See Figure 1 , Figure 1 This is a flow chart of a PCB design method provided by an embodiment of the present application. Figure 1 As shown, the method may include but is not limited to the following steps:

[0034] Step S101: Determine a target stackup in an inner layer of an original PCB.

[0035] In an embodiment of the present application, the original PCB may be a PCB with a multi-layer mixed-pressure stacked structure.

[0036] The target stack is the other wiring layers in the original PCB inner layer except the high-density wiring layer, the ground layer and the power layer.

[0037] Exemplarily, the routing conditions of high-density areas of all routing layers (ie, non-GND layers and non-power layers) in the original PCB are obtained, and the routing layers without routing in the high-density areas are determined as target stacking layers.

[0038] Step S102: generating a first stackup of a first daughter card in a new PCB based on a top layer, a power layer, and a target stackup of the original PCB.

[0039] It can be understood that the first stack of the first daughter card includes multiple stacks.

[0040] Exemplarily, the top layer, power layer and target layer of the original stack are retained, the conductive structure of the top layer is transferred to the newly created signal layer, and the corresponding ground layer is generated according to the design specifications to generate the first layer of the first daughter card in the new PCB.

[0041] Step S103: generating a second stack of the second daughter card in the new PCB based on the bottom layer and the high-density wiring layer of the original PCB.

[0042] It can be understood that the second stack of the second daughter card includes multiple stacks.

[0043] Exemplarily, the bottom layer and high-density wiring layer of the original PCB are retained, and the bottom conductive structure is transferred to the newly created signal layer, and the corresponding ground layer is generated according to the design specification to generate the second stack of the second daughter card.

[0044] Step S104: Generate a dummy layer in the new PCB.

[0045] In the embodiment of the present application, the dummy layer is a stacked layer used to adjust the thickness and impedance of the new PCB and has no circuit functions such as signal transmission.

[0046] For example, a dummy layer in a new PCB may be generated according to actual design requirements.

[0047] Exemplarily, there is at least one dummy layer.

[0048] Exemplarily, a dummy layer is generated between the first daughter card and the second daughter card, and a low-fluidity prepreg is used to prevent glue from flowing into the hole when the first daughter card and the second daughter card are pressed together.

[0049] Step S105: Generate a new PCB based on the first stack, the second stack and the dummy layer.

[0050] Exemplarily, the first stack of the first daughter card, the second stack of the second daughter card, and the dummy layer are integrated to obtain a new PCB, the starting layer and the ending layer of the high-density connector pins are set as the bottom layer of the new PCB, and the starting layer and the ending layer of the hard disk connector NPTH (Non-Plated Through Hole) pins are set as the top layer of the new PCB. The stacks are renamed according to their actual arrangement, and the correspondence between the original PCB stacks and the new PCB stacks is recorded. The traces and copper foils are exported from the original PCB layer by layer, and the exported documents are edited to modify the layer where each element is located, and then imported into the new PCB layer by layer.

[0051] In an optional implementation, a prohibited routing area may be established within a preset range (eg, 40 mils) based on the pins of the crimp connector.

[0052] In an optional implementation, a limit may be set for the minimum distance between a through hole and a blind hole, for example, 30 mil.

[0053] In an optional implementation, the non-compliant routing and vias may be modified based on the violation coordinate positions marked in the design rule check report to optimize the new PCB.

[0054] It should be noted that the new PCB obtained by using any embodiment of the present application can support the overlapping placement of high-density connectors on the bottom layer and hard disk connectors on the top layer.

[0055] By implementing the embodiments of the present application, new stacks corresponding to the first daughter card and the second daughter card in the new PCB can be generated based on the stacks in the original PCB, thereby obtaining a new PCB that can support the overlapping placement of high-density connectors on the bottom layer and hard disk connectors on the top layer, thereby reducing the space required for wiring and improving compatibility with connectors.

[0056] In some embodiments, a new stackup corresponding to the top layer, power layer, and target stackup of the original PCB can be generated respectively, thereby obtaining a first stackup corresponding to the first daughter card. As an example, see Figure 2 , Figure 2 This is a flow chart of another PCB design method provided by the embodiment of the present application. Figure 2 As shown, the method may include but is not limited to the following steps:

[0057] Step S201: Determine a target stackup in an inner layer of an original PCB.

[0058] In the embodiment of the present application, step S201 can be implemented by any of the methods in the embodiments of the present application. The embodiments of the present application do not limit this and will not be described in detail.

[0059] Step S202: generating a first inner layer of a first stack based on a power layer in an original PCB.

[0060] In the embodiment of the present application, the first inner layer may be a middle layer of the first daughter card.

[0061] Exemplarily, based on the number of power supply layers in the original PCB, a corresponding number of power supply layers are generated as middle layers in the first stack of the first daughter card.

[0062] Step S203: Generate corresponding second inner layers on both sides of the first inner layer based on the target stack.

[0063] Exemplarily, the first inner layer is used as an intermediate layer, and second inner layers corresponding to the target stacking are generated on both sides of the first inner layer.

[0064] It should be noted that the second inner layer may include a signal layer corresponding to the target stack and a ground layer corresponding to the signal layer.

[0065] Step S204: generating a first outer layer of a first stack based on the top layer of the original PCB.

[0066] The first outer layer includes a first signal layer, and the first signal layer is used to arrange the long wires and the metal layer of the top layer of the original PCB.

[0067] Exemplarily, in the first stack, the top layer of the original PCB corresponds to the new top layer, and a new first signal layer is generated. The first signal layer is used to arrange the long lines and metal layer of the top layer of the original PCB. The new top layer and the first signal layer constitute the outer layer of the first stack.

[0068] Step S205: generating a second stack of the second daughter card in the new PCB based on the bottom layer and the high-density wiring layer of the original PCB.

[0069] In the embodiment of the present application, step S205 can be implemented by any of the methods in the embodiments of the present application. The embodiments of the present application do not limit this and will not be described in detail.

[0070] Step S206: Generate a dummy layer in the new PCB.

[0071] In the embodiment of the present application, step S206 can be implemented by any of the methods in the embodiments of the present application. The embodiments of the present application do not limit this and will not be described in detail.

[0072] Step S207: Generate a new PCB based on the first stack, the second stack and the dummy layer.

[0073] In the embodiment of the present application, step S207 can be implemented by any of the methods in the embodiments of the present application. The embodiments of the present application do not limit this and will not be described in detail.

[0074] By implementing the embodiments of the present application, new stacks corresponding to the top layer, power layer, and target stack of the original PCB can be generated, thereby obtaining a first stack corresponding to the first daughter card. This stack is then combined with the new stack corresponding to the second daughter card to obtain a new PCB that can support the overlapping placement of high-density connectors on the bottom layer and hard disk connectors on the top layer. This can reduce the space required for wiring and improve connector compatibility.

[0075] In one implementation, new stacks corresponding to the bottom layer and high-density wiring layer of the original PCB can be generated separately as the second stack of the second daughter card. Figure 3 , Figure 3 This is a flow chart of another PCB design method provided by the embodiment of the present application. Figure 3 As shown, the method may include but is not limited to the following steps:

[0076] Step S301: Determine a target stackup in an inner layer of an original PCB.

[0077] In the embodiment of the present application, step S301 can be implemented in any of the ways in the embodiments of the present application. The embodiments of the present application do not limit this and will not be described in detail.

[0078] Step S302: generating a first stackup of a first daughter card in a new PCB based on a top layer, a power layer, and a target stackup of the original PCB.

[0079] In the embodiment of the present application, step S302 can be implemented by any of the methods in the embodiments of the present application. The embodiments of the present application do not limit this and will not be described in detail.

[0080] Step S303: generating a third inner layer of the second stack.

[0081] Illustratively, the third inner layer may be a middle layer of the second daughter card.

[0082] Exemplarily, at least one ground layer is generated as a middle layer of the second stack.

[0083] Step S304: generating a fourth inner layer corresponding to the high-density wiring layer in the second daughter card on both sides of the third inner layer.

[0084] Exemplarily, the third inner layer is used as an intermediate layer, and fourth inner layers corresponding to the high-density wiring layers are generated on both sides of the third inner layer.

[0085] It should be noted that the fourth inner layer may include a signal layer corresponding to the high-density wiring layer, and a ground layer corresponding to the signal layer.

[0086] Step S305: generating a second outer layer of a second stack based on the bottom layer of the original PCB.

[0087] In an embodiment of the present application, the second outer layer includes a second signal layer and a third signal layer. The second signal layer is used to arrange the short lines of the bottom layer of the original PCB, and the third signal layer is used to arrange the long lines of the bottom layer of the original PCB.

[0088] Exemplarily, the bottom layer of the original PCB is split into a second signal layer and a third signal layer, the second signal layer is used to arrange short lines on the bottom layer of the original PCB, and the third signal layer is used to arrange long lines on the bottom layer of the original PCB.

[0089] Step S306: Generate a dummy layer in the new PCB.

[0090] In the embodiment of the present application, step S306 can be implemented by any of the methods in the embodiments of the present application. The embodiments of the present application do not limit this and will not be described in detail.

[0091] Step S307: Generate a new PCB based on the first stack, the second stack and the dummy layer.

[0092] In the embodiment of the present application, step S307 can be implemented by any of the methods in the embodiments of the present application. The embodiments of the present application do not limit this and will not be described in detail.

[0093] By implementing the embodiments of the present application, new stacks corresponding to the bottom layer and high-density wiring layer of the original PCB can be generated separately to serve as the second stack of the second daughter card. The second daughter card can then be combined with the first daughter card to create a new PCB that can support the overlapping placement of high-density connectors on the bottom layer and hard drive connectors on the top layer. This can reduce the space required for wiring and improve connector compatibility.

[0094] In one implementation, the above method may further include the following steps:

[0095] Step A1: Obtain the first high-density pin pair number and design requirements of the high-density connector in the original PCB, as well as device information of available high-density connectors of the new PCB.

[0096] In the embodiments of the present application, the above-mentioned design requirements may include but are not limited to data transmission rate.

[0097] For example, after obtaining design requirements and reading the original PCB design file, the model and corresponding quantity of all high-density connectors in the underlying layer are retrieved and output, and the device information of the currently available high-density connectors is obtained. The device information may include but is not limited to the model, available quantity, data transmission rate, and number of pin pairs.

[0098] In some embodiments, device information of high-density connectors stored in a device library may be obtained as device information of available high-density connectors.

[0099] For example, see Figure 4 , Figure 4 This is an example diagram of connector library information provided by the embodiment of the present application. Figure 4 As shown, the available high-density connector material number, pin length, signal rate, number of pin pairs, hard disk connector material number and corresponding NPTH pin length can be stored in different columns of the table. This table can be connected to the device library to perform real-time update and maintenance based on the status of the connector in the device library, ensuring the accuracy and comprehensiveness of the connector library information and improving the design efficiency of new PCBs.

[0100] Step A2: Based on the design requirements and device information, a candidate high-density connector is selected from available high-density connectors.

[0101] For example, taking the case where the design requirements include a data transmission rate requirement, based on the data transmission rates supported by the available high-density connectors, a candidate high-density connector that meets the data transmission rate requirement is selected from the available high-density connectors.

[0102] Step A3: Selecting a target high-density connector from candidate high-density connectors based on the first high-density pin pair number.

[0103] For example, a high-density connector with the same number of differential pairs as the first high-density pin pairs is preferably selected as the target high-density connector; if the high-density connector has the same number of differential pair rows as the first high-density pin pairs, then the high-density connector with the same number of differential pairs as the first high-density pin pairs is selected as the target high-density connector; again, a high-density connector with a smaller number of differential pairs than the first high-density pin pairs is selected as the target high-density connector to improve the utilization rate of high-density devices.

[0104] Step A4: Obtain the number of second high-density pin pairs of the target high-density connector.

[0105] For example, according to the material number of the target high-density connector, Figure 4 Search in the table shown to obtain the second highest density pin pair number of the target high-density connector.

[0106] In some embodiments, the number of signals required to be routed on all high-density connectors in the original PCB can be obtained, and the number of signals can be divided by the second high-density pin pair number to obtain the number of high-density connectors in the new PCB.

[0107] Step A5: In response to the first differential signal pair number in the first high-density pin pair number being smaller than the second differential signal pair number in the second high-density pin pair number, generating a fifth inner layer on both sides of the third inner layer based on the difference between the first differential signal pair number and the second differential signal pair number.

[0108] Exemplarily, in response to the first differential signal pair number in the first high-density pin pair number being smaller than the second differential signal pair number in the second high-density pin pair number, the same number of signal layers as the above difference and the same number of ground layers as the above difference are generated on both sides of the middle layer of the second daughter card.

[0109] By implementing the embodiments of the present application, high-density connectors can be reselected based on PCB design requirements and available connector device information, and the new PCB can be adjusted based on the selection results. This makes the new PCB more in line with actual production requirements and improves the usability of the new PCB in industrial production.

[0110] In one implementation, the total thickness of the first daughter card is less than a preset first thickness threshold; wherein the first thickness threshold is determined according to the length of the non-plated hole corresponding to the hard disk connector of the original PCB.

[0111] Exemplarily, the thickness of each stack of the first daughter card may be adjusted so that the total thickness of the first daughter card is less than a preset first thickness threshold.

[0112] Exemplarily, the first thickness threshold may be 1.1 times the length of the non-plated hole corresponding to the hard disk connector of the original PCB.

[0113] For example, according to the material number of the hard disk connector, Figure 4 Search in the table shown to obtain the NPTH pin length corresponding to the part number.

[0114] In some embodiments, the total thickness of the second daughter card is less than a preset second thickness threshold; wherein the second thickness threshold is determined according to the pin length of the high-density connector on the bottom layer of the original PCB.

[0115] Exemplarily, the thickness of each stack of the second daughter card may be adjusted so that the total thickness of the second daughter card is less than a preset second thickness threshold.

[0116] Exemplarily, the second thickness threshold may be 1.1 times the length of the pins of the high-density connector on the bottom layer of the original PCB.

[0117] For example, according to the material number of the high-density connector, Figure 4 Search in the table shown to obtain the pin length corresponding to the part number.

[0118] The following is an exemplary description of the PCB design method provided by this application in conjunction with specific embodiments:

[0119] As an example, see Figure 5 , Figure 5 This is an example diagram of a PCB design solution provided by the embodiment of this application. Figure 5 As shown, taking the 14-layer stack commonly used in storage devices as an example, the original PCB stack is divided into two daughter cards (i.e., the first daughter card and the second daughter card mentioned above). The upper daughter card uses the power layer of the original PCB stack as the middle layer, retains the top layer of the original PCB stack, and adds Ly6_Signal (sixth layer_signal layer) for arranging the long lines and metal layers in the top layer of the original PCB. The routing conditions of all routing layers (i.e., non-GND, non-power layers) in high-density areas are counted, and the routing layers without routing in the high-density area are symmetrically added on both sides of Ly3_Pwr (third layer_power layer) and Ly4_Pwr (fourth layer_power layer). It is confirmed whether additional routing layers are needed based on the routing requirements. If all routing layers have wiring in the high-density area, the upper daughter card will maintain Figure 5 The 6-layer board shown.

[0120] Adjust the trace layers with traces in the high-density area in the original PCB (taking Ly3_signal (the third layer_signal layer), Ly5_signal (the fifth layer_signal layer), Ly10_signal (the tenth layer_signal layer), and Ly12_signal (the twelfth layer_signal layer) as examples) to the lower daughter card. At the same time, split the bottom layer of the original PCB stack into Ly7_Signal (the seventh layer_signal layer) and Ly18_Signal layer (the eighteenth layer_signal layer) of the new PCB, which are used to route the short traces and long traces of the bottom layer of the original stack respectively;

[0121] Record the number of pinpairs of the high-density connector on the original PCB as X1*Y1 (indicating that this high-density connector has Y1 columns, and each column can route X1 pairs of differential signals), and the number of pinpairs of the high-density connector on the new PCB as X2*Y2; if X1 < X2, symmetrically add X1 - X2 signal layers and X1 - X2 GND layers on both sides of Ly12_Gnd and Ly13_Gnd. Add a dummy layer between the upper daughter card and the lower daughter card, and use a low-flow prepreg to prevent resin from flowing into the holes when the upper and lower daughter cards are laminated.

[0122] After that, modify the device packaging. Exemplarily, please refer to Figure 6 , Figure 6 which is an example diagram of pin parameters provided by an embodiment of the present application. As Figure 6 shown, after selecting the pins to be modified, enter the parameter configuration interface. If the pins to be modified are top-layer NPTH pins, set the parameter options of all layers below the Ly6_signal layer (the sixth layer_signal layer) to None; if the pins to be modified are bottom-layer high-density device pins, set the parameter options of all layers from the top layer to the Ly6_signal layer (including the Ly6_signal layer) to None.

[0123] Please refer to Figure 7 , Figure 7 which is a schematic structural diagram of a PCB design device provided by an embodiment of the present application. As Figure 7 shown, the device 700 includes: a first processing module 701, configured to determine a target stack in the inner layer of the original PCB; wherein, the target stack is other wiring layers in the inner layer of the original PCB except for the high-density wiring layer, the ground layer, and the power layer; a second processing module 702, configured to generate a first stack of the first daughter card in the new PCB based on the top layer, the power layer, and the target stack of the original PCB; a third processing module 703, configured to generate a second stack of the second daughter card in the new PCB based on the bottom layer and the high-density wiring layer of the original PCB; a fourth processing module 704, configured to generate a dummy layer in the new PCB; a fifth processing module 705, configured to generate a new PCB based on the first stack, the second stack, and the dummy layer.

[0124] In one implementation, the second processing module 702 is used to: generate a first inner layer of the first stack based on the power layer in the original PCB; generate corresponding second inner layers on both sides of the first inner layer based on the target stack; generate a first outer layer of the first stack based on the top layer of the original PCB; wherein the first outer layer includes a first signal layer, and the first signal layer is used to arrange the long wires and metal layer of the top layer of the original PCB.

[0125] In one implementation, the third processing module 703 is used to: generate a third inner layer of the second stack; generate a fourth inner layer corresponding to the high-density wiring layer in the second daughter card on both sides of the third inner layer; generate a second outer layer of the second stack based on the bottom layer of the original PCB; wherein the second outer layer includes a second signal layer and a third signal layer, the second signal layer is used to arrange short lines of the bottom layer of the original PCB, and the third signal layer is used to arrange long lines of the bottom layer of the original PCB.

[0126] In an optional implementation, the third processing module 703 is also used to: obtain the first high-density pin pair number and design requirements of the high-density connector in the original PCB, and the device information of the available high-density connector of the new PCB; select a candidate high-density connector from the available high-density connectors based on the design requirements and device information; select a target high-density connector from the candidate high-density connectors based on the first high-density pin pair number; obtain the second high-density pin pair number of the target high-density connector; in response to the first high-density pin pair number being less than the second high-density pin pair number, obtain the first differential signal pair number in the first high-density pin pair number and the second differential signal pair number in the second high-density pin pair number, and generate a fifth inner layer on both sides of the third inner layer based on the difference between the first differential signal pair number and the second differential signal pair number.

[0127] In one implementation, the total thickness of the first daughter card is less than a preset first thickness threshold; wherein the first thickness threshold is determined according to the length of the non-plated hole corresponding to the hard disk connector of the original PCB.

[0128] In one implementation, the total thickness of the second daughter card is less than a preset second thickness threshold; wherein the second thickness threshold is determined according to the pin length of the high-density connector on the bottom layer of the original PCB.

[0129] The apparatus of the present invention can generate new stacks corresponding to the first and second daughter cards in a new PCB based on the stacks in the original PCB, thereby obtaining a new PCB that can support overlapping placement of high-density connectors on the bottom layer and hard drive connectors on the top layer. This can reduce the space required for wiring and improve connector compatibility.

[0130] It should be noted that the aforementioned explanation of the PCB design method embodiment is also applicable to the PCB design device of this embodiment and will not be repeated here.

[0131] In order to implement the above embodiment, the present application also proposes an electronic device. Figure 8 , Figure 8 Schematic diagram of the structure of the electronic device provided in the embodiment of the present application. Figure 8 As shown, the electronic device 800 includes: a processor 801, and a memory 802 communicatively connected to the processor 801; the memory 802 stores computer-executable instructions; the processor 801 executes the computer-executable instructions stored in the memory to implement the method provided in the aforementioned embodiment.

[0132] In order to implement the above embodiments, the present application also proposes a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the methods provided in the above embodiments.

[0133] In order to implement the above embodiments, the present application also proposes a computer program product, including a computer program, which implements the methods provided by the above embodiments when executed by a processor.

[0134] In the description of this application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a way to describe the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0135] In the descriptions of the foregoing embodiments, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are mutually inconsistent.

[0136] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0137] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0138] The logic and / or steps represented in a flowchart or otherwise described herein, for example, can be considered a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" is any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (not exhaustive) of computer-readable media include: an electrical connection with one or more wires (electronic devices), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and a portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or otherwise processing it in a suitable manner if necessary, and then storing it in a computer memory.

[0139] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used: a discrete logic circuit having logic gate circuits for implementing logical functions on data signals, an application-specific integrated circuit having suitable combinational logic gate circuits, a programmable gate array (PGA), a field-programmable gate array (FPGA), etc.

[0140] Those skilled in the art will appreciate that all or part of the steps in the method for implementing the above-mentioned embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0141] In addition, the functional units in the various embodiments of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into a module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0142] The storage medium mentioned above may be a read-only memory, a magnetic disk, or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application. Persons skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A PCB design method, characterized in that: include: Determining a target stackup in an inner layer of an original PCB; wherein the target stackup is other wiring layers in the inner layer of the original PCB except a high-density wiring layer, a ground layer, and a power layer; generating a first stackup of a first daughter card in a new PCB based on the top layer, the power layer, and the target stackup of the original PCB; wherein the first stackup includes a newly created first signal layer, a newly created top layer, the power layer, the target stackup, and a ground layer; the first signal layer includes the conductive structure of the top layer; and the newly created top layer includes the remaining portion of the top layer excluding the conductive structure of the top layer; Generating a second stack of the second daughter card in the new PCB based on the bottom layer and the high-density wiring layer of the original PCB; wherein the second stack includes a newly created third signal layer, a newly created bottom layer, the high-density wiring layer, and a ground layer; the third signal layer includes the conductive structure of the bottom layer; and the newly created bottom layer includes the remaining portion of the bottom layer excluding the conductive structure of the bottom layer; Generating a dummy layer in the new PCB; wherein the dummy layer is located between the first daughter card and the second daughter card; The new PCB is generated based on the first stack, the second stack, and the dummy layer.

2. The method according to claim 1, characterized in that The step of generating a first stackup of a first daughter card in a new PCB based on the top layer, the power layer, and the target stackup of the original PCB includes: generating a first inner layer of the first stack based on a power layer in the original PCB; generating corresponding second inner layers on both sides of the first inner layer based on the target stack; The first outer layer of the first stack is generated based on the top layer of the original PCB; wherein the first outer layer includes a first signal layer, and the first signal layer is used to arrange the long wires and metal layer of the top layer of the original PCB.

3. The method according to claim 1, characterized in that Generating a second stack of the second daughter card in the new PCB based on the bottom layer and the high-density wiring layer of the original PCB includes: generating a third inner layer of the second laminate; generating a fourth inner layer corresponding to the high-density wiring layer in the second daughter card on both sides of the third inner layer; A second outer layer of the second stack is generated based on the bottom layer of the original PCB; wherein the second outer layer includes a second signal layer and a third signal layer, the second signal layer is used to arrange the short lines of the bottom layer of the original PCB, and the third signal layer is used to arrange the long lines of the bottom layer of the original PCB.

4. The method according to claim 3, characterized in that The method further comprises: Obtaining a first high-density pin pair number and design requirements of the high-density connector in the original PCB, and device information of an available high-density connector in the new PCB; Selecting a candidate high-density connector from the available high-density connectors based on design requirements and the device information; Selecting a target high-density connector from the candidate high-density connectors based on the first high-density pin pair number; Obtaining the second high-density pin pair number of the target high-density connector; In response to the first high-density pin pair number being less than the second high-density pin pair number, the first differential signal pair number in the first high-density pin pair number and the second differential signal pair number in the second high-density pin pair number are obtained, and based on the difference between the first differential signal pair number and the second differential signal pair number, a fifth inner layer is generated on both sides of the third inner layer.

5. The method according to claim 1, characterized in that The total thickness of the first daughter card is less than a preset first thickness threshold; wherein the first thickness threshold is determined according to the length of the non-plated hole corresponding to the hard disk connector of the original PCB.

6. The method according to claim 1, characterized in that The total thickness of the second daughter card is less than a preset second thickness threshold; wherein the second thickness threshold is determined according to the pin length of the high-density connector on the bottom layer of the original PCB.

7. A PCB design device, characterized in that: include: A first processing module is configured to determine a target stack in an inner layer of an original PCB; wherein the target stack is other wiring layers in the inner layer of the original PCB except a high-density wiring layer, a ground layer, and a power layer; a second processing module, configured to generate a first stackup of a first daughter card in a new PCB based on the top layer, the power layer, and the target stackup of the original PCB; wherein the first stackup includes a newly created first signal layer, a newly created top layer, the power layer, the target stackup, and a ground layer; the first signal layer includes the conductive structure of the top layer; and the newly created top layer includes the remaining portion of the top layer excluding the conductive structure of the top layer; a third processing module, configured to generate a second stack of layers for the second daughter card in the new PCB based on the bottom layer and the high-density wiring layer of the original PCB; wherein the second stack includes a newly created third signal layer, a newly created bottom layer, the high-density wiring layer, and a ground layer; the third signal layer includes the conductive structure of the bottom layer, and the newly created bottom layer includes the remaining portion of the bottom layer excluding the conductive structure of the bottom layer; a fourth processing module, configured to generate a dummy layer in the new PCB; wherein the dummy layer is located between the first daughter card and the second daughter card; A fifth processing module is configured to generate the new PCB based on the first stack, the second stack, and the dummy layer.

8. An electronic device, characterized in that: include: a processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method according to any one of claims 1 to 6.

10. A computer program product, characterized in that The method comprises a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 6.

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