Quantum processor, method, and related device for computing a grid vector bidim

Abstract

The invention discloses a quantum processor, method and related device for calculating two norms of a lattice vector, and relates to the technical field of quantum computation.The quantum processor for calculating the two norms of the lattice vector comprises a square arithmetic unit, a division arithmetic unit, a first register and a second register; the first register is used for storing a quantum state corresponding to each component of the lattice vector; the square arithmetic unit and the division arithmetic unit alternately act on the second register, and after the square arithmetic unit superposes the square operation result of any component of the lattice vector stored in the first register to the second register, the division arithmetic unit circularly exchanges the quantum bits of the second register in # imgabs0 # sub-quantum states according to the sequence from the high order to the low order; the square operation result of each component of the lattice vector is superposed to the second register to generate a two-norm of the lattice vector, and p is the maximum value in each component of the lattice vector. Calculation of a lattice vector two-norm can be realized by using a quantum computer.

Description

Technical Field

[0001] This application belongs to the field of quantum computing technology, and particularly relates to a quantum processor, method, and related device for calculating the two-norm of lattice vectors. Background Art

[0002] A quantum computer is a physical device that follows the laws of quantum mechanics to perform high-speed mathematical and logical operations, store, and process quantum information. When a device processes and calculates quantum information and runs quantum algorithms, it is a quantum computer. Due to its relatively more efficient ability to process mathematical problems compared to ordinary computers, for example, it can accelerate the time to crack RSA keys from hundreds of years to a few hours, quantum computers have become a key technology under research.

[0003] The shortest vector problem (SVP) is one of the fundamental difficult problems on lattices and is the basis for the security of lattice cryptosystems. The SVP solving algorithm is a key technology for evaluating the security of lattice cryptography algorithms. The time complexity of classical algorithms for solving SVP is O(N), while the time complexity of the Grover quantum search algorithm is only Therefore, the quantum Grover search algorithm can be used for acceleration. The prerequisite for accelerating with the quantum Grover search algorithm is to use a quantum computer to implement the solution of the two-norm of lattice vectors. Summary of the Invention

[0004] The purpose of this application is to provide a quantum processor, method, and related device for calculating the two-norm of lattice vectors, aiming to use a quantum computer to solve the two-norm of lattice vectors.

[0005] To achieve the above purpose, in the first aspect of the embodiments of this application, a quantum processor for calculating the two-norm of lattice vectors is provided. The quantum processor includes a square operation unit, a division operation unit, a first register, and a second register;

[0006] The first register is used to store the quantum states corresponding to the components of the lattice vector;

[0007] The square operation unit and the division operation unit act on the second register alternately. After the square operation unit superimposes the square operation result of any component of the lattice vector stored in the first register onto the second register, the division operation unit cyclically exchanges the quantum states of the qubits in the second register in the order from the highest bit to the lowest bit times of quantum states until the square operation results of each component of the lattice vector are superimposed onto the second register to generate the two-norm of the lattice vector, where p is the maximum value among the components of the lattice vector.

[0008] In a possible implementation, the squaring operator includes an adder and a multiplier;

[0009] The adder acts on the first register and the second register, and sequentially superimposes the quantum states corresponding to each component of the lattice vector onto the second register in the order from the highest bit to the lowest bit according to the bit positions;

[0010] After the adder superimposes the quantum state of any bit corresponding to each component onto the second register, the multiplier acts on the second register to perform a double multiplication operation on the superimposed result stored in the second register.

[0011] In a possible implementation, the adder is a controlled adder, the quantum processor includes a first auxiliary qubit, and the squaring operator includes a first CNOT gate;

[0012] For each component of the lattice vector, the control bit positions of the first CNOT gate are sequentially each bit from the highest bit to the lowest bit of the quantum state corresponding to this component, and the target bit position includes the first auxiliary qubit; the initial quantum state of the first auxiliary qubit is |0>;

[0013] The controlled adder is used to superimpose the quantum state of the control bit position of the first CNOT gate onto the second register after the first CNOT gate acts and when the quantum state of the first auxiliary qubit is the target quantum state.

[0014] In a possible implementation, the squaring operator further includes a second CNOT gate;

[0015] After the controlled adder superimposes the quantum state of the control bit position of the first CNOT gate onto the second register, the second CNOT gate uses the control bit position of the first CNOT gate as the control bit position and the first auxiliary qubit as the target bit to restore the quantum state of the first auxiliary qubit to the initial quantum state.

[0016] In a possible implementation, the quantum processor includes a second auxiliary qubit, the multiplier includes a SWAP gate, and the SWAP gate acts on the qubits of the second register and the second auxiliary qubit to cyclically exchange the quantum states of each bit in the order from the lowest bit to the highest bit.

[0017] In the second aspect of the embodiments of the present application, a method for calculating the two-norm of a lattice vector is provided, and the method includes:

[0018] Construct a quantum processor as described in any one of the first aspect;

[0019] Encode the lattice vector to be calculated into the first register of the quantum processor and run the quantum processor;

[0020] Determine the two-norm of the lattice vector to be calculated according to the quantum state of the second register of the quantum processor.

[0021] In a third aspect of the embodiments of the present application, there is provided a device for calculating the two-norm of a lattice vector, the device including:

[0022] A construction module for constructing the quantum processor according to any one of the first aspects;

[0023] An operation module for encoding the lattice vector to be calculated into the first register of the quantum processor and running the quantum processor;

[0024] A determination module for determining the two-norm of the lattice vector to be calculated according to the quantum state of the second register of the quantum processor.

[0025] In a fourth aspect of the embodiments of the present application, there is provided a storage medium in which a computer program is stored, wherein the computer program is set to execute the steps of the method according to any one of the second aspects when running.

[0026] In a fifth aspect of the embodiments of the present application, there is provided an electronic device including a memory and a processor, wherein a computer program is stored in the memory, and the processor is set to run the computer program to execute the steps of the method according to any one of the second aspects.

[0027] In a sixth aspect of the embodiments of the present application, there is provided a quantum computer operating system, and the quantum computer operating system realizes the calculation of the two-norm of the lattice vector according to the method described in the second aspect.

[0028] Based on the above technical solutions, the present application provides a quantum processor for calculating the two-norm of a lattice vector. The quantum processor includes a square operator, a division operator, a first register, and a second register. The first register is used to store the quantum states corresponding to the components of the lattice vector. The square operator and the division operator act on the second register alternately. After the square operator superimposes the square operation result of any component of the lattice vector stored in the first register on the second register, the division operator cyclically exchanges the quantum bits of the second register in the order from high to low. Sub - quantum states, until the square operation results of each component of the lattice vector are superimposed on the second register to generate the two - norm of the lattice vector, where p is the maximum value among the components of the lattice vector. In this application, through the quantum states corresponding to each component of the lattice vector stored in the first register, the square operation unit and the division operation unit act on the second register alternately, so that the square operation results of each component of the lattice vector are superimposed on the second register, realizing the solution of the two - norm of the lattice vector using a quantum computer. Description of the Drawings

[0029] Figure 1 is a network block diagram of a system for calculating the two - norm of a lattice vector shown according to an exemplary embodiment.

[0030] Figure 2 is a quantum circuit diagram of a quantum processor for calculating the two - norm of a lattice vector shown according to an exemplary embodiment.

[0031] Figure 3 is a quantum circuit diagram of a square operation unit shown according to an exemplary embodiment.

[0032] Figure 4 is a quantum circuit diagram of a multiplier shown according to an exemplary embodiment.

[0033] Figure 5 is a flowchart of a method for calculating the two - norm of a lattice vector shown according to an exemplary embodiment

[0034] Figure 6 is a block diagram of a device for calculating the two - norm of a lattice vector shown according to an exemplary embodiment.

[0035] Figure 7 is a block diagram of a computer device shown according to an exemplary embodiment. Detailed Embodiments

[0036] The embodiments described below by referring to the drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application.

[0037] Figure 1 is a network block diagram of a system for calculating the two - norm of a lattice vector provided by an embodiment of the present application. The system for calculating the two - norm of a lattice vector may include a network 110, a server 120, a wireless device 130, a client 140, a storage 150, a classical computing unit 160, a quantum computing unit 170, and may also include additional memories, classical processors, quantum processors, and other devices not shown.

[0038] Network 110 is a medium for providing communication links between various devices and computers interconnected within a system for calculating the two-norm of a lattice vector, including but not limited to the Internet, intranet, local area network, mobile communication network, and combinations thereof. The connection can be made using wired, wireless communication links, fiber optic cables, etc.

[0039] Server 120, wireless device 130, and client 140 are conventional data processing systems that can contain data and have application programs or software tools for performing conventional computing processes. Client 140 can be a personal computer or a network computer, and thus the data can also be provided by server 120. Wireless device 130 can be a smart phone, tablet, laptop, smart wearable device, etc. Storage unit 150 can include database 151, which can be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, quantum programs, etc.

[0040] Classical computing unit 160 (quantum computing unit 170) can include classical processor 161 (quantum processor 171) for processing classical data (quantum data) and memory 162 (memory 172) for storing classical data (quantum data). The classical data (quantum data) can be a boot file, an operating system image, and application program 163 (application program 173). Application program 163 (application program 173) can be used to implement a quantum algorithm compiled according to the method for calculating the two-norm of a lattice vector provided in the embodiments of the present application.

[0041] Any data or information stored or generated in classical computing unit 160 (quantum computing unit 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner. Similarly, any application program executed by it can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0042] It should be noted that a real quantum computer has a hybrid structure and at least includes Figure 1 two major parts: classical computing unit 160, responsible for performing classical computing and control; quantum computing unit 170, responsible for running quantum programs to achieve quantum computing.

[0043] The above-mentioned classical computing unit 160 and quantum computing unit 170 can be integrated into one device or distributed among two different devices. For example, the first device including the classical computing unit 160 runs a classical computer operating system, on which quantum application development tools and services are provided, as well as the storage and network services required for quantum applications. Users develop quantum programs through the quantum application development tools and services thereon, and send the quantum programs to the second device including the quantum computing unit 170 through the network services thereon. The second device runs a quantum computer operating system, and parses and compiles the code of the quantum program into instructions that can be recognized and executed by the quantum processor 170 through the quantum computer operating system. The quantum processor 170 implements the quantum algorithm corresponding to the quantum program according to the instructions.

[0044] The computing unit of the classical processor 161 in the classical computing unit 160 is based on CMOS transistors of a silicon chip. This computing unit is not restricted by time and coherence, that is, this computing unit is not restricted by the usage duration and is available at any time. In addition, in a silicon chip, the number of such computing units is also sufficient. Currently, the number of computing units in a classical processor 161 is in the thousands. The sufficient number of computing units and the fixed computing logic available for CMOS transistors, for example: AND logic. When operating with CMOS transistors, a large number of CMOS transistors are combined with limited logic functions to achieve the operation effect.

[0045] The basic computing unit of the quantum processor 171 in the quantum computing unit 170 is a qubit. The input of a qubit is restricted by coherence and also by the coherence time, that is, a qubit is restricted by the usage duration and is not available at any time. Making full use of qubits within their available usage duration is a key problem in quantum computing. In addition, the number of qubits in a quantum computer is one of the representative indicators of the performance of a quantum computer. Each qubit realizes the computing function through the logic function configured on demand. Given the limited number of qubits, and the logic functions in the field of quantum computing are diverse, for example: Hadamard gate (H gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), X gate, RY gate, RZ gate, CNOT gate, CR gate, iSWAP gate, Toffoli gate, etc. When performing quantum computing, it is necessary to combine a limited number of qubits with diverse logic function combinations to achieve the operation effect.

[0046] Based on these differences, the design of classical logic functions acting on CMOS transistors is significantly and essentially different from the design of quantum logic functions acting on qubits; the design of classical logic functions acting on CMOS transistors does not need to consider the individuality of CMOS transistors, such as the individual identification of which CMOS transistor it is in the silicon chip, its location, and the available duration of each CMOS transistor. Therefore, the classical algorithms composed of classical logic functions only express the operational relationship of the algorithms and do not express the dependence of the algorithms on the individuality of CMOS transistors.

[0047] However, the design of quantum logic functions acting on qubits needs to consider the individuality of qubits, such as the individual identification of which qubit it is in the quantum chip, its location, the relationship with surrounding qubits, and the available duration of each qubit. Therefore, the quantum algorithms composed of quantum logic functions not only express the operational relationship of the algorithms but also express the dependence of the algorithms on the individuality of qubits.

[0048] Exemplarily:

[0049] Quantum algorithm one: H1, H2, CNOT(1,3), H3, CNOT(2,3);

[0050] Quantum algorithm two: H1, H2, CNOT(1,2), H3, CNOT(2,3);

[0051] Quantum algorithm one and quantum algorithm two use the method of adding Arabic numerals to quantum logic gates to represent the qubits on which the quantum logic gates act. The Arabic numerals 1, 2, and 3 therein can represent three sequentially connected qubits Q1, Q2, Q3 or interconnected qubits Q1, Q2, Q3;

[0052] An exemplary explanation of the influence of quantum algorithms on the coherence time of qubits is as follows:

[0053] Define the execution duration of a single qubit logic gate as t, and the execution time of 1 two-qubit logic gate acting on adjacent qubits as 2t; then:

[0054] When Q1, Q2, and Q3 are interconnected with each other, the calculation of quantum algorithm one requires 6t and is carried out in 4 time periods. The required duration of each time period is t, 2t, t, and 2t respectively. The operations performed within each time period are: H1, H2; CNOT(1,3); H3; CNOT(2,3);

[0055] The calculation of quantum algorithm one requires 5t and is carried out in 3 time periods. The required duration of each time period is t, 2t, and 2t respectively. The operations performed within each time period are: H1, H2, H3; CNOT(1,2); CNOT(2,3);

[0056] When Q1, Q2, and Q3 are connected in sequence, Quantum Algorithm 1 needs to be equivalent to: H1, H2; swap(1,2), CNOT(2,3), swap(1,2); H3; CNOT(2,3). The calculation of the equivalent Quantum Algorithm 1 requires 10t, which is divided into 4 time periods, and the duration required for each time period is t, 6t, t, and 2t respectively. The operations executed within each time period are: H1, H2; swap(1,2), CNOT(2,3), swap(1,2); H3; CNOT(2,3).

[0057] Therefore, the design of quantum logic functions acting on qubits (including the design of whether to use qubits and the design of the usage efficiency of each qubit) is the key to improving the computing performance of quantum computers, and special designs are required. This is also the uniqueness of quantum algorithms based on quantum logic functions, which is essentially and significantly different from classical algorithms based on classical logic functions. The above-mentioned design for qubits is a technical problem that ordinary computing devices do not need to consider and do not need to face. This application proposes a quantum processor for calculating the two-norm of lattice vectors to achieve the calculation of the two-norm of lattice vectors using a quantum computer.

[0058] An embodiment of this application provides a quantum processor for calculating the two-norm of lattice vectors. The quantum processor may include a square operator, a division operator, a first register, and a second register;

[0059] The first register is used to store the quantum states corresponding to the components of the lattice vector;

[0060] The square operator and the division operator act on the second register alternately. After the square operator superimposes the square operation result of any component of the lattice vector stored in the first register to the second register, the division operator cyclically exchanges the quantum states of the qubits in the second register in ascending order from the low bit to the high bit p times, until the square operation results of each component of the lattice vector are superimposed to the second register to generate the two-norm of the lattice vector, where p is the maximum value among the components of the lattice vector.

[0061] In the embodiment of this application, for a d-dimensional lattice vector u, u can be expressed as u = (u1, u2,..., u d ), and the calculation of its two-norm can be expressed as:

[0062]

[0063] The above-mentioned first register is used to store the quantum states corresponding to the respective components u1, u2,..., u d of the lattice vector.

[0064] In one implementation, each component of the lattice vector u can be converted into a binary number and encoded onto the qubits of the first register.

[0065] For example, if the lattice vector is (3, 2), then in the first register, the lattice vector can be stored as the quantum state |11, 10>, where the component 3 of the lattice vector corresponds to the quantum state |11> and the component 2 corresponds to the quantum state |10>.

[0066] The second register mentioned above is a quantum register for storing the second norm of the lattice vector, and the initial quantum state of the qubits in the second register is |0>.

[0067] The square operation unit and the division operation unit act on the second register alternately. The square operation unit is used to perform a square operation on the quantum state corresponding to each component of the lattice vector stored in the first register, and superimpose the result of the square operation on the second register. After each superimposition of the result of the square operation on the second register and before the next superimposition of the result of the square operation, the division operation unit cyclically exchanges the qubits of the second register in the order from the highest bit to the lowest bit times of quantum states, for performing times of division-by-2 operations on the superimposed result of the square operation in the second register.

[0068] For example, for the lattice vector (3, 2), the maximum value of each component of the lattice vector (3, 2) is p = 3,

[0069] The square operation unit acts on the first register, performs a square operation on the quantum state |11> corresponding to the component 3, and obtains the result of the square operation |01001>. The result of the square operation is superimposed on the second register, and the quantum state of the second register is |01001>. Before superimposing the result of the square operation of the quantum state |10> corresponding to the component 2 on the second register, the division operation unit cyclically exchanges the qubits of the second register in the order from the highest bit to the lowest bit times of quantum states, that is, the quantum state |01001> is shifted from left to right in turn, and the last bit on the right is moved to the first bit on the left, evolving into the quantum state |10100>.

[0070] As Figure 2 shown, Figure 2 is a schematic diagram of the quantum circuit of a quantum processor for calculating the second norm of a lattice vector provided by an embodiment of the present application, Figure 2 which shows the first register, the second register and the auxiliary register. Among them, the first register is used to store the respective components u0, u1,..., u d , Figure 2The Sqr shown represents a squaring operator. The squaring operator performs squaring operations on each component u0, u1, …, u of the lattice vector in sequence by means of the auxiliary register aux0, and superimposes the results of the squaring operations onto the second register aux. d This is a simplified quantum circuit diagram, omitting the division operator acting on the second register aux. The division operator and the squaring operator will be introduced in the following embodiments. Figure 2 This application provides a quantum processor for calculating the two-norm of a lattice vector. The quantum processor includes a squaring operator, a division operator, a first register, and a second register. The first register is used to store the quantum states corresponding to each component of the lattice vector. The squaring operator and the division operator act on the second register alternately. After the squaring operator superimposes the result of the squaring operation of any component of the lattice vector stored in the first register onto the second register, the division operator cyclically exchanges the quantum states of the qubits in the second register in the order from the highest bit to the lowest bit

[0071] p times, until the results of the squaring operations of each component of the lattice vector are superimposed onto the second register to generate the two-norm of the lattice vector, where p is the maximum value among the components of the lattice vector. Through the quantum states corresponding to each component of the lattice vector stored in the first register, and using the squaring operator and the division operator to act on the second register alternately, so that the results of the squaring operations of each component of the lattice vector are superimposed onto the second register, this application realizes the solution of the two-norm of the lattice vector using a quantum computer. Next, the specific operating principle of the squaring operator in the above embodiment will be introduced. In another embodiment of this application, the above squaring operator may include an adder and a multiplier.

[0072] Among them, the adder acts on the first register and the second register, and superimposes the quantum states corresponding to each component of the lattice vector onto the second register in sequence according to the order from the highest bit to the lowest bit of the bit positions.

[0073] In an embodiment of this application, a component of the lattice vector can be represented as the quantum state |x

[0074] x n-1 x n-2 …x0>. Then the adder will sequentially superimpose x n-1 x n-2 …x0 onto the second register, where x i takes values of 0 or 1, and i ∈ [0, n - 1].

[0075] For example, for the lattice vector (3, 2), the quantum state corresponding to its component 2 is |10>. The adder first superimposes 1 onto the second register, and then superimposes 0 onto the second register.

[0076] Specifically, the adder described above is a controlled adder. The quantum processor includes a first auxiliary qubit, and the squaring operator includes a first CNOT gate.

[0077] For each component of the lattice vector, the control qubit positions of the first CNOT gate are successively each qubit position from the highest bit to the lowest bit of the quantum state corresponding to this component. The target qubit position includes the first auxiliary qubit; the initial quantum state of the first auxiliary qubit is |0>.

[0078] The controlled adder is used to, after the action of the first CNOT gate and when the quantum state of the first auxiliary qubit is the target quantum state, superimpose the quantum state of the control qubit positions of the first CNOT gate onto the second register.

[0079] It should be noted that the CNOT gate is one of the commonly used gates in quantum computing and is used to implement the controlled flip operation between quantum bits. The CNOT gate acts on two quantum bits, one as the control qubit and the other as the target qubit. When the control qubit is 1, the state of the target qubit will be flipped; when the control qubit is 0, the state of the target qubit remains unchanged.

[0080] The specific principle of action is as follows:

[0081] Initial state: Before the CNOT gate acts, the initial states of the two qubits are |a>|b>, where |a> represents the state of the control qubit and |b> represents the state of the target qubit.

[0082] Control operation: The CNOT gate will detect the state of the control qubit. If the control qubit is 1, a flip operation is performed; if the control qubit is 0, no operation is performed.

[0083] Flip operation: When the control qubit is 1, the CNOT gate will perform a flip operation on the target qubit, that is, change the state of the target qubit from |0> to |1> or from |1> to |0>.

[0084] Result output: After the CNOT gate acts, the states of the two qubits become |a>|b xor a>, where xor represents the logical exclusive OR operation, indicating the result after the exclusive OR operation between the control qubit and the target qubit.

[0085] In summary, the CNOT gate can implement the flip operation of the state of the target qubit by the control qubit, thus realizing the control operation between quantum bits. This is very important in quantum computing and can be used to construct more complex quantum logic gates and quantum algorithms.

[0086] The first CNOT gate is a controlled-NOT gate. When the quantum state of the control bit of the first CNOT gate is |1>, the first CNOT gate flips the quantum state of the first auxiliary bit of the target bit; when the quantum state of the control bit of the first CNOT gate is |0>, the first CNOT gate does not flip the quantum state of the first auxiliary bit of the target bit, and the quantum state of the first auxiliary bit remains unchanged.

[0087] The above-mentioned controlled adder is controlled by the first auxiliary bit, and the target quantum state is |1>. When the quantum state of the first auxiliary bit is |1>, the controlled adder superimposes the quantum state of the control bit of the first CNOT gate onto the second register. Through the action of the first CNOT gate, the quantum state corresponding to any component of the lattice vector can control the flipping of the quantum state of the first auxiliary bit in sequence according to the order of the bits from high to low. The initial quantum state of the first auxiliary bit is |0>. When the quantum state of the control bit is |1>, the quantum state of the first auxiliary bit flips to the target quantum state |1>.

[0088] Further, the squaring operator may further include a second CNOT gate;

[0089] The second CNOT gate is used to restore the quantum state of the first auxiliary bit to the initial quantum state with the control bit of the first CNOT gate as the control bit and the first auxiliary bit as the target bit after the controlled adder superimposes the quantum state of the control bit of the first CNOT gate onto the second register.

[0090] The multiplier is used to act on the second register after the adder superimposes the quantum state of any bit corresponding to each component onto the second register, and perform a double multiplication operation on the superimposed result stored in the second register.

[0091] As Figure 3 shown, Figure 3 This is a quantum circuit of a squaring operator provided by an embodiment of the present application. Figure 3 It also shows a division operator ( / 2 n-1 ) acting on the second register. |x n-1 >|x n-2 >…|x1>|x0> represents a component x of the lattice vector u stored in the first register. Figure 3The black dots indicate being controlled. The first CNOT gate is before the controlled adder (+), and the second CNOT gate is after the controlled adder (+). The first qubit is the first auxiliary qubit with an initial quantum state of |0>, and the last qubit is the second auxiliary qubit. The second auxiliary qubit is used to assist the multiplier (*2) in performing a doubling multiplication operation. |y> represents the superposed quantum state in the second register.

[0092] Among them, the above quantum processor includes a second auxiliary qubit. The multiplier includes a SWAP gate. The SWAP gate acts on the qubits in the second register and the second auxiliary qubit, and cyclically exchanges the quantum states of each qubit in the order from the low bit to the high bit.

[0093] The multiplier in the embodiment of the present application is used to perform a single 2-fold multiplication operation on the superposed result in the second register, corresponding to the times of dividing by 2 operations performed by the above divider.

[0094] As Figure 4 shown, Figure 4 This is the quantum circuit of the multiplier provided by the embodiment of the present application, including n qubits in the second register for representing the superposed result and the second auxiliary qubit. The swap gate acts on adjacent qubits and can cyclically exchange the quantum states of each qubit in the order from the low bit to the high bit, that is, exchange the quantum states of each qubit in the order from |x0>|x1>…|x n-2 >|x n-1 >. The initial quantum state of the second auxiliary qubit is |0>. After the exchange, the quantum states of |x1>…|x n-2 >|x n-1 > correspond one-to-one to the quantum states of |x0>|x1>…|x n-2 > before the exchange. The quantum state of the second auxiliary qubit after the exchange corresponds to the quantum state of |x n-1 > before the exchange.

[0095] Continuing the example in the above embodiment, first, the square operation result of the quantum state corresponding to the component 3 of the lattice vector (3, 2) is superimposed on the second register. After obtaining the quantum state of the second register as |01001>, the quantum state |01001> is moved from left to right in turn by using the divider. During the movement of the rightmost bit to the leftmost bit, the quantum state of the second register evolves into |10100>.

[0096] Then, square the quantum state |10> corresponding to component 2 of the lattice vector (3, 2). For the highest bit |1> of the quantum state |10> corresponding to component 2, the control bit of the first CNOT gate is |1>, and the initial quantum state of the first auxiliary bit of the target bit is flipped from |0> to |1>. The control bit of the controlled adder is the quantum state |1> of the first auxiliary bit. Then, the controlled adder superimposes the highest bit |1> onto the second register, evolving the quantum state of the second register from |10100> to |10110>. Then, use the multiplier to cyclically exchange the quantum states of each bit of the quantum state |10110> of the second register in the order from the lowest bit to the highest bit. The quantum state of the second register is evolved to |01101>. At the same time, use the second CNOT gate to reset the quantum state of the first auxiliary bit to |0>.

[0097] Then, for the lowest bit |0> of the quantum state |10> corresponding to component 2, the control bit of the first CNOT gate is |0>, the target bit, the first auxiliary bit, maintains its initial quantum state |0> unchanged. The control bit of the controlled adder is the quantum state |0> of the first auxiliary bit. Then, the controlled adder does not superimpose the lowest bit |0>. The final quantum state of the second register is |01101>, which is converted to the decimal number 2 3 +2 2 +2 0 = 13, that is, the two-norm of (3, 2) of the required lattice vector is obtained as 3 2 +2 2 = 13.

[0098] It can be seen from the above embodiments that the controlled adder only superimposes the part of the quantum state bit corresponding to the lattice vector component that is |1> onto the second register, and does not perform the superimposition operation on the part that is |0>, which can reduce the number of operations and improve the operation efficiency.

[0099] In the embodiment of the present application, the above first CNOT gate, controlled adder, second CNOT gate, and multiplier constitute a square operation unit. By superimposing the quantum states corresponding to each component of the lattice vector stored in the first register onto the second register bit by bit, and using the divider to cyclically exchange the quantum states of each bit of the superimposed result of the second register in the order from the highest bit to the lowest bit, and repeating the above process until each component of the lattice vector is superimposed onto the second register, the calculation result of the two-norm of the lattice vector is obtained, realizing the calculation of the two-norm of the lattice vector using a quantum computer.

[0100] The embodiment of the present application also provides a method for calculating the two-norm of a lattice vector, as Figure 5 shown. The method includes:

[0101] S501. Construct a quantum processor as described in the above embodiment.

[0102] The quantum circuit of the quantum processor is consistent with the description in the above embodiments. For details, please refer to the description in the above embodiments and will not be elaborated here.

[0103] S502. Encode the lattice vector to be calculated into the first register of the quantum processor and run the quantum processor.

[0104] In one implementation, each component of the lattice vector can be converted into a binary number and encoded onto the qubits of the first register.

[0105] S503. Determine the second norm of the lattice vector to be calculated according to the quantum state of the second register of the quantum processor.

[0106] After the quantum processor finishes running, the quantum state of the second register can be measured, and the obtained binary measurement result can be converted into a decimal number to obtain the second norm of the lattice vector to be calculated.

[0107] In the embodiment of the present application, by constructing a quantum processor for calculating the second norm of a lattice vector, encoding the lattice vector to be calculated into the first register of the quantum processor, running the quantum processor, and determining the second norm of the lattice vector to be calculated according to the quantum state of the second register of the quantum processor, the calculation of the second norm of the lattice vector by using a quantum computer is realized, and further the acceleration of the quantum Grover search algorithm is realized.

[0108] Based on the same inventive concept, the embodiment of the present application further provides a device for calculating the second norm of a lattice vector, as Figure 6 shown. The device includes:

[0109] A construction module 601, configured to construct a quantum processor as described in the above embodiments;

[0110] An operation module 602, configured to encode the lattice vector to be calculated into the first register of the quantum processor and run the quantum processor;

[0111] A determination module 603, configured to determine the second norm of the lattice vector to be calculated according to the quantum state of the second register of the quantum processor.

[0112] For the specific functions and effects achieved by the device for calculating the second norm of a lattice vector, please refer to other embodiments of this specification for comparison and explanation, and will not be elaborated here. Each module in the device for calculating the second norm of a lattice vector can be implemented in whole or in part by software, hardware, and their combination. The modules can be embedded in the processor of the computer device in hardware form or be independent of it, or can be stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to the above modules.

[0113] Please refer to Figure 7 Figure 7 . The embodiments of this specification also provide a computer device, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the method for calculating the two-norm of a lattice vector in any of the above embodiments. Please refer to Figure 7 . The computer device may be a classical computer. The computer device may also be a quantum computer.

[0114] The embodiments of this specification also provide a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a computer, the computer implements the method for calculating the two-norm of a lattice vector in any of the above embodiments.

[0115] The embodiments of this specification also provide a computer program product including instructions. When the instructions are executed by a computer, the computer implements the method for calculating the two-norm of a lattice vector in any of the above embodiments.

[0116] The embodiments of this specification also provide a quantum computer operating system, and the quantum computer operating system calculates the two-norm of a lattice vector according to the method in the above embodiments.

[0117] It can be understood that the specific examples in this specification are only to help those skilled in the art better understand the embodiments of this specification, rather than limiting the scope of this application.

[0118] It can be understood that in various embodiments of this specification, the magnitude of the sequence numbers of the processes does not mean the order of execution is prior or subsequent. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of this specification.

[0119] It can be understood that the various embodiments described in this specification can be implemented alone or in combination, and the embodiments of this specification do not limit this.

[0120] Unless otherwise specified, all technical and scientific terms used in the embodiments of this specification have the same meaning as commonly understood by those skilled in the technical field of this specification. The terms used in this specification are only for the purpose of describing specific embodiments, and are not intended to limit the scope of this specification. The term "and / or" used in the embodiments of this specification includes any and all combinations of one or more of the related listed items. The singular forms of "a", "the above", and "the" used in the embodiments of this specification and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0121] It can be understood that the processor in the embodiments of this specification can be an integrated circuit chip with signal processing capabilities. In the implementation process, the steps of the above method embodiments can be completed by the integrated logic circuit in the hardware of the processor or instructions in the form of software. The above-mentioned processor can be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of this specification. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of this specification can be directly embodied as being executed by a hardware decoding processor, or completed by a combination of hardware and software modules in the decoding processor. The software module can be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. This storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the above method.

[0122] It can be understood that the memory in the embodiments of this specification can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM) or a flash memory. The volatile memory can be a random access memory (RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0123] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or by a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professionals can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of this specification.

[0124] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0125] In the several embodiments provided in this specification, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there can be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces, and the indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0126] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0127] In addition, in each embodiment of this specification, the functional units can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit.

[0128] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this specification, in essence, or the part that contributes to the prior art or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of this specification. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0129] The above is only the specific embodiment of this specification, but the protection scope of this application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this specification, and all should be covered by the protection scope of this specification. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. A quantum processor for calculating the two-norm of lattice vectors, characterized in that The quantum processor includes a squaring operator, a division operator, a first register, and a second register; The first register is used to store the quantum states corresponding to the components of the lattice vector; The square calculator and the division calculator alternately act on the second register. After the square calculator superimposes the square operation result of any component of the lattice vector stored in the first register on the second register, the division calculator cyclically exchanges the qubits of the second register in the order from the high bit to the low bit times of quantum states until the square operation results of each component of the lattice vector are superimposed on the second register to generate the two-norm of the lattice vector, where p is the maximum value among the components of the lattice vector.

2. The quantum processor according to claim 1, characterized in that, The squaring operator includes an adder and a multiplier; The adder acts on the first register and the second register, and sequentially superimposes the quantum states corresponding to each component of the lattice vector onto the second register in the order from the highest bit to the lowest bit of the bit positions; The multiplier is used to, after the adder superimposes the quantum state of any bit position corresponding to each component onto the second register, act on the second register to perform a double multiplication operation on the superimposed result stored in the second register.

3. The quantum processor according to claim 2, wherein The adder is a controlled adder, the quantum processor further includes a first auxiliary bit, and the squaring operator further includes a first CNOT gate; For each component of the lattice vector, the control bit positions of the first CNOT gate are sequentially each bit position from the highest bit to the lowest bit of the quantum state corresponding to this component, and the target bit position includes the first auxiliary bit; the initial quantum state of the first auxiliary bit is |0>; The controlled adder is used to, after the first CNOT gate acts and the quantum state of the first auxiliary bit is the target quantum state, superimpose the quantum state of the control bit position of the first CNOT gate onto the second register.

4. The quantum processor according to claim 3, wherein The squaring operator further includes a second CNOT gate; The second CNOT gate is used to, after the controlled adder superimposes the quantum state of the control bit position of the first CNOT gate onto the second register, use the control bit position of the first CNOT gate as the control bit position and the first auxiliary bit as the target bit to restore the quantum state of the first auxiliary bit to the initial quantum state.

5. The quantum processor according to claim 2, characterized in that, The quantum processor further includes a second auxiliary bit, the multiplier includes a SWAP gate, and the SWAP gate acts on the quantum bits of the second register and the second auxiliary bit to cyclically exchange the quantum states of each bit in the order from the lowest bit to the highest bit.

6. A method for calculating the two-norm of a lattice vector, characterized in that, The method includes: Constructing a quantum processor as described in any one of claims 1-5; Encoding the lattice vector to be calculated into the first register of the quantum processor and running the quantum processor; Determining the two-norm of the lattice vector to be calculated according to the quantum state of the second register of the quantum processor.

7. An apparatus for calculating the two-norm of a lattice vector, characterized in that, The device includes: A construction module for constructing a quantum processor as described in any one of claims 1-5; An operation module for encoding the lattice vector to be calculated into the first register of the quantum processor and running the quantum processor; A determination module for determining the two-norm of the lattice vector to be calculated according to the quantum state of the second register of the quantum processor.

8. A storage medium, characterized in that, A computer program is stored in the storage medium, wherein the computer program is set to execute the method described in claim 6 when running.

9. An electronic device, comprising a memory and a processor, characterized in that, A computer program is stored in the memory, and the processor is set to run the computer program to execute the method described in claim 6.

10. A quantum computer operating system, characterized in that, The quantum computer operating system implements the calculation of the two-norm of the lattice vector according to the method described in claim 6 above.

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