Optimization method of Shor algorithm based on controlled swap gate

Abstract

The invention discloses an optimization method of a Shor algorithm based on a controlled swap gate. The method comprises the steps of determining an initial quantum circuit according to a to-be-processed target problem based on a Shor algorithm; next, a modular exponential operator in the initial quantum line is converted into a controlled swap gate to determine a first quantum line. And finally, grouping and merging the controlled swap gates in the first quantum circuit, and determining a first target quantum circuit so as to optimize the Shor algorithm. Therefore, the quantum circuit depth and the required quantum bit number of the Shor algorithm are reduced by replacing modular index operators with the controlled swap gates and performing grouping and merging processing on the controlled swap gates, so that the performance limitation of a current quantum computer is broken through, and the development of a larger-scale Shor algorithm real machine experiment is promoted.

Description

Technical Field

[0001] This application relates to the field of quantum computing, and more particularly, to an optimization method for Shor's algorithm based on a controlled swap gate. Background Art

[0002] Based on the unique physical properties of qubits such as quantum superposition and quantum entanglement, quantum computing exhibits significant theoretical advantages over classical computing paradigms when dealing with specific complex problems. In related technologies, Shor's algorithm transforms prime factorization into a periodicity detection problem through quantum computing, and uses quantum Fourier transform to accelerate the solution of the period exponentially. However, due to the performance limitations of current quantum computers, it is often difficult to use Shor's algorithm to solve prime factorization problems with higher complexity. Summary of the Invention

[0003] This application provides an optimization method for Shor's algorithm based on a controlled swap gate.

[0004] An embodiment of this application provides an optimization method for Shor's algorithm based on a controlled swap gate, and the method includes: Based on the Shor's algorithm, determine an initial quantum circuit according to the target problem to be processed; Convert the modular exponentiation operator in the initial quantum circuit into a controlled swap gate to determine a first quantum circuit; Perform grouping and merging processing on the controlled swap gates in the first quantum circuit to determine a first target quantum circuit, so as to optimize the Shor's algorithm.

[0005] In this way, based on the Shor's algorithm, the computer device determines an initial quantum circuit according to the target problem to be processed. Then, the computer device converts the modular exponentiation operator in the initial quantum circuit into a controlled swap gate to determine a first quantum circuit. Finally, the computer device performs grouping and merging processing on the controlled swap gates in the first quantum circuit to determine a first target quantum circuit, so as to optimize the Shor's algorithm. In this way, by replacing the modular exponentiation operator with a controlled swap gate and performing grouping and merging processing on the controlled swap gates, the quantum circuit depth and the number of qubits required by the Shor's algorithm are reduced, thereby breaking through the performance limitations of current quantum computers and promoting the development of larger-scale real machine experiments of the Shor's algorithm.

[0006] In some embodiments, the determining an initial quantum circuit based on the Shor's algorithm and according to the target problem to be processed includes: Based on the Shor's algorithm, determine a base according to the target problem, where the base is relatively prime to the integer to be factored in the target problem and less than the integer to be factored; Determine the number of phase qubits according to the target problem, where the number of phase qubits is used to record the phase information generated by running the Shor's algorithm; Determine the number of operation qubits according to the target problem, where the number of operation qubits is used to record the quantum state information generated by running the modular exponentiation operator; Determine the initial quantum circuit according to the basis, the number of phase qubits, and the number of operation qubits.

[0007] In this way, the computer device determines the basis according to the target problem, where the basis is relatively prime to the integer to be factored in the target problem and less than the integer to be factored. Then, the computer device determines the number of phase qubits according to the target problem, where the number of phase qubits is used to record the phase information generated by running the Shor's algorithm. Next, the computer device determines the number of operation qubits according to the target problem, where the number of operation qubits is used to record the quantum state information generated by running the modular exponentiation operator. Finally, the computer device determines the initial quantum circuit according to the basis, the number of phase qubits, and the number of operation qubits. In this way, the quantization mapping of the Shor's algorithm is realized through parametric design. While ensuring mathematical correctness, the resource consumption is controlled within the range that can be tolerated by the quantum computer, and a foundation for subsequent optimization is laid.

[0008] In some embodiments, the determining the initial quantum circuit according to the basis, the number of phase qubits, and the number of operation qubits includes: Determine the modular exponentiation operator according to the basis, the number of phase qubits, and the integer to be factored; Determine the initial quantum circuit according to the basis, the number of phase qubits, the number of operation qubits, and the modular exponentiation operator.

[0009] In this way, the computer device determines the modular exponentiation operator according to the basis, the number of phase qubits, and the integer to be factored. Then, the computer device determines the initial quantum circuit according to the basis, the number of phase qubits, the number of operation qubits, and the modular exponentiation operator. In this way, through rigorous number theory transformation, it is ensured that the initial quantum circuit correctly maps the theoretical framework of the Shor's algorithm mathematically, avoiding decomposition anomalies caused by parameter errors.

[0010] In some embodiments, the performing grouped merging processing on the controlled swap gates in the first quantum circuit to determine the first target quantum circuit includes: Based on a preset grouping rule, perform grouping processing on the controlled swap gates in the first quantum circuit to determine a first temporary quantum circuit, where the first temporary quantum circuit includes at least one group of target controlled swap gates with different control bits and the same controlled bits; Determine target quantum gate information and a second temporary quantum circuit according to the first temporary quantum circuit, where the target quantum gate information includes a controlled swap gate, relevant information of the controlled swap gate, a controlled NOT gate, and relevant information of the controlled NOT gate; Determine the first target quantum circuit according to the target quantum gate information and the second temporary quantum circuit.

[0011] In this way, based on a preset grouping rule, a computer device performs grouping processing on the controlled swap gates in the first quantum circuit to determine a first temporary quantum circuit, where the first temporary quantum circuit includes at least one group of target controlled swap gates with different control bits and the same controlled bits. Then, the computer device determines target quantum gate information and a second temporary quantum circuit according to the first temporary quantum circuit, where the target quantum gate information includes a controlled swap gate, relevant information of the controlled swap gate, a controlled NOT gate, and relevant information of the controlled NOT gate. Finally, the computer device determines the first target quantum circuit according to the target quantum gate information and the second temporary quantum circuit. In this way, by grouping and merging the controlled swap gates, redundant operations in the quantum circuit are reduced, and the requirements for quantum bit resources and the number of quantum gate operations are lowered, thereby improving the execution efficiency of the Shor algorithm.

[0012] In some embodiments, the determining target quantum gate information and a second temporary quantum circuit according to the first temporary quantum circuit includes: Based on a preset merging rule, perform merging processing on the target controlled swap gates to determine the target quantum gate information and the second temporary quantum circuit.

[0013] In this way, based on a preset merging rule, a computer device performs merging processing on the target controlled swap gates to determine target quantum gate information and a second temporary quantum circuit. In this way, the merged quantum circuit disassembles the global operations into independent groups, and the gates within each group can be independently optimized, facilitating cross-group parallelism.

[0014] In some embodiments, the determining the first target quantum circuit according to the target quantum gate information and the second temporary quantum circuit includes: Based on a preset decomposition rule, perform decomposition processing on the quantum gates in the target quantum gate information to determine the first target quantum circuit.

[0015] In this way, based on a preset decomposition rule, a computer device performs decomposition processing on the quantum gates in the target quantum gate information to determine the first target quantum circuit. In this way, the complex controlled swap gates are decomposed and transformed into a combination of basic gates, which is convenient for implementation on quantum hardware.

[0016] In some embodiments, the method further includes: Perform an identification process on the first target quantum circuit to determine the existence of the first circuit property of the first target quantum circuit; Determine a second quantum circuit according to the existence of the first circuit property; Determine a second target quantum circuit according to the second quantum circuit to optimize the Shor algorithm.

[0017] In this way, the computer device performs an identification process on the first target quantum circuit to determine the existence of the first circuit property of the first target quantum circuit. Then, the computer device determines a second quantum circuit according to the existence of the first circuit property. Finally, the computer device determines a second target quantum circuit according to the second quantum circuit to optimize the Shor algorithm. In this way, through the processes of identifying circuit properties, targeted optimization, and global integration, and utilizing the mathematical properties of the first target quantum circuit, the efficiency of the modular exponentiation operation module of the Shor algorithm is achieved.

[0018] In some embodiments, the first circuit property includes controlled-NOT gate symmetry, controlled-bit mutual exclusivity, operation commutativity, and operation determinacy. The determining of the second quantum circuit according to the existence of the first circuit property includes: When the first target quantum circuit has the controlled-NOT gate symmetry, controlled-bit mutual exclusivity, and operation commutativity, based on the controlled-NOT gate symmetry, controlled-bit mutual exclusivity, and operation commutativity, adjust the controlled-NOT gates in the first target quantum circuit to determine the second quantum circuit; or When the first target quantum circuit has the operation determinacy, based on the operation determinacy, optimize the first target quantum circuit to determine the second quantum circuit.

[0019] In this way, when the first target quantum circuit has the controlled-NOT gate symmetry, controlled-bit mutual exclusivity, and operation commutativity, based on the controlled-NOT gate symmetry, controlled-bit mutual exclusivity, and operation commutativity, the computer device adjusts the controlled-NOT gates in the first target quantum circuit to determine the second quantum circuit. Or, when the first target quantum circuit has the operation determinacy, based on the operation determinacy, the computer device optimizes the first target quantum circuit to determine the second quantum circuit. In this way, by clarifying the first circuit property and optimizing the first target quantum circuit based on the first circuit property, the consumption of quantum gate resources can be reduced, thereby reducing the accumulation of quantum gate errors, improving the accuracy of cycle measurement, and further accelerating the large integer factorization speed.

[0020] In some embodiments, the determining of the second quantum circuit according to the existence of the first circuit property includes: In the case where the first circuit property does not exist, determine the first target quantum circuit as the second target quantum circuit.

[0021] In this way, in the case where the first circuit property does not exist, the computer device determines the first target quantum circuit as the second target quantum circuit. Thus, when the first target quantum circuit does not satisfy any optimizable circuit properties, forcibly applying the optimization rules may lead to circuit logic errors or introduce additional noise. At this time, directly retaining the original circuit can avoid damaging the circuit function due to blind optimization and ensure the correctness and stability of the Shor algorithm.

[0022] In some embodiments, the determining the second target quantum circuit according to the second quantum circuit to optimize the Shor algorithm includes: Perform an identification process on the second quantum circuit to determine the existence of the second circuit property of the second quantum circuit; Determine the second quantum circuit according to the existence of the second circuit property; Determine the second target quantum circuit according to the second quantum circuit to optimize the Shor algorithm.

[0023] In this way, the computer device performs an identification process on the second quantum circuit to determine the existence of the second circuit property of the second quantum circuit. Then, the computer device determines the second quantum circuit according to the existence of the second circuit property. Finally, the computer device determines the second target quantum circuit according to the second quantum circuit to optimize the Shor algorithm. In this way, through multi-level identification, continuous improvement of the quantum circuit is achieved, so that the Shor algorithm meets the standard in terms of performance indicators such as the number of quantum gates, the depth of the quantum circuit, and the fidelity of the quantum circuit.

[0024] Additional aspects and advantages of the embodiments of the present application will be given in part in the following description, become apparent in part from the following description, or be understood through the practice of the embodiments of the present application. Description of the Drawings

[0025] The above and / or additional aspects and advantages of the present application will become apparent and be easily understood from the description of the embodiments in conjunction with the following drawings, where: Figure 1 is one of the flow diagrams of the optimization method of the Shor algorithm according to the embodiments of the present application; Figure 2 is a schematic diagram of a controlled swap gate according to the embodiments of the present application; Figure 3 is one of the schematic diagrams of the quantum circuit of the Shor algorithm according to the embodiments of the present application; Figure 4It is the second schematic diagram of the quantum circuit of the Shor algorithm according to the embodiment of the present application; Figure 5 It is the first schematic diagram of the quantum circuit according to the embodiment of the present application; Figure 6 It is the first schematic diagram of the target quantum circuit according to the embodiment of the present application; Figure 7 It is the second schematic diagram of the flow of the optimization method of the Shor algorithm according to the embodiment of the present application; Figure 8 It is the third schematic diagram of the flow of the optimization method of the Shor algorithm according to the embodiment of the present application; Figure 9 It is the fourth schematic diagram of the flow of the optimization method of the Shor algorithm according to the embodiment of the present application; Figure 10 It is the schematic diagram of the controlled NOT gate according to the embodiment of the present application; Figure 11 It is the fifth schematic diagram of the flow of the optimization method of the Shor algorithm according to the embodiment of the present application; Figure 12 It is the schematic diagram of the merging process according to the embodiment of the present application; Figure 13 It is the sixth schematic diagram of the flow of the optimization method of the Shor algorithm according to the embodiment of the present application; Figure 14(a) is the first schematic diagram of the decomposition of the controlled swap gate according to the embodiment of the present application; Figure 14(b) is the second schematic diagram of the decomposition of the controlled swap gate according to the embodiment of the present application; Figure 15 It is the schematic diagram of the Toffoli gate decomposition according to the embodiment of the present application; Figure 16 It is the seventh schematic diagram of the flow of the optimization method of the Shor algorithm according to the embodiment of the present application; Figure 17 It is the eighth schematic diagram of the flow of the optimization method of the Shor algorithm according to the embodiment of the present application; Figure 18 It is the third schematic diagram of the quantum circuit of the Shor algorithm according to the embodiment of the present application; Figure 19 It is the fourth schematic diagram of the quantum circuit of the Shor algorithm according to the embodiment of the present application; Figure 20 It is the schematic diagram of the Bell state preparation circuit according to the embodiment of the present application; Figure 21 It is the fifth schematic diagram of the quantum circuit of the Shor algorithm according to the embodiment of the present application; Figure 22 It is the sixth schematic diagram of the quantum circuit of the Shor algorithm according to the embodiment of the present application; Figure 23This is the seventh quantum circuit diagram of the Shor algorithm in the implementation mode of the present application; Figure 24 This is the ninth flow chart of the optimization method of the Shor algorithm in the implementation mode of the present application; Figure 25 This is the tenth flowchart of the optimization method of the Shor algorithm in the implementation mode of the present application. DETAILED DESCRIPTION

[0026] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions from beginning to end. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of the present application, and cannot be understood as limiting the embodiments of the present application.

[0027] Based on the unique physical properties of quantum bits - quantum superposition and quantum entanglement, quantum computing has shown theoretical advantages that significantly surpass the classical computing paradigm when dealing with specific complex problems. Unlike classical bits that can only represent two discrete states, 0 or 1, a single quantum bit can be in and The entanglement between multiple quantum bits can form a high-dimensional correlated state, which makes quantum computing have a natural parallel information processing capability. In the field of classical computing, the computational complexity of many complex problems, such as the prime factorization of large integers, increases exponentially with the increase of the value, making it difficult for classical computers to solve them within a reasonable time. Quantum computing, with its unique physical properties, has shown great potential in solving prime factorization problems.

[0028] Among the related technologies, Shor's algorithm is an important achievement in the field of quantum computing and has a milestone significance. It cleverly transforms the prime factorization problem, which is extremely challenging in classical computing, into a periodicity detection problem. Specifically, for a given integer N to be factored, Shor's algorithm first randomly selects an integer a that is coprime with N, and then solves the function through quantum computing. Once the period r is found, the prime factors of N can be efficiently decomposed using number theory.

[0029] In this process, the inverse quantum Fourier transform (IQFT) plays a key role, which can exponentially accelerate the periodic solution process. The classical algorithm solution cycle often needs to traverse a large number of possible values, which has extremely high time complexity. The quantum Fourier transform, with the help of quantum superposition and entanglement characteristics, can process a large amount of information at the quantum state level at the same time, thereby greatly shortening the calculation time.

[0030] However, although Shor's algorithm has great theoretical advantages, limited by the performance of current quantum computers, its practical application still faces many challenges, and it is often difficult to use Shor's algorithm to solve the prime factorization problem with a relatively high complexity. Current quantum computers, especially noisy intermediate-scale quantum (NISQ) devices, have problems such as a limited number of qubits, short coherence times, and high gate operation error rates. These factors make it difficult for quantum computers to precisely maintain the superposition and entanglement characteristics of quantum states when running Shor's algorithm, and they are easily affected by noise interference, resulting in incorrect calculation results.

[0031] For example, Shor's algorithm requires a large number of qubits to construct phase registers and operation registers to achieve high-precision period detection. When facing prime factorization problems with relatively high complexity, the number of qubits required increases linearly according to logN, while the number of qubits in current quantum computers far from meets the requirements. At the same time, the entanglement operation between qubits requires extremely high precision, and any tiny error may be amplified during the calculation process, leading to the failure of the final result.

[0032] Based on the above problems, please refer to Figure 1 , the embodiments of the present application provide an optimization method for Shor's algorithm based on controlled-swap gates, and the method includes: 01: Based on Shor's algorithm, determine an initial quantum circuit according to the target problem to be processed; 02: Convert the modular exponentiation operator in the initial quantum circuit into a controlled-swap gate to determine a first quantum circuit; 03: Perform grouping and merging processing on the controlled-swap gates in the first quantum circuit to determine a first target quantum circuit to optimize Shor's algorithm.

[0033] The embodiments of the present application also provide a computer device, including a memory and a processor. The optimization method for Shor's algorithm based on controlled-swap gates in the embodiments of the present application can be implemented by the computer device in the embodiments of the present application. Specifically, a computer program is stored in the memory, and the processor is used to determine an initial quantum circuit based on Shor's algorithm according to the target problem to be processed. And convert the modular exponentiation operator in the initial quantum circuit into a controlled-swap gate to determine a first quantum circuit. And perform grouping and merging processing on the controlled-swap gates in the first quantum circuit to determine a first target quantum circuit to optimize Shor's algorithm.

[0034] Embodiments of the present application also provide a quantum circuit optimization device. The optimization method of the Shor algorithm based on the controlled-swap gate in the embodiments of the present application can be implemented by the quantum circuit optimization device in the embodiments of the present application. Specifically, the quantum circuit simulation device includes a determination module. The determination module is configured to determine an initial quantum circuit based on the Shor algorithm according to the target problem to be processed. And convert the modular exponentiation operator in the initial quantum circuit into a controlled-swap gate to determine a first quantum circuit. And perform grouped merging processing on the controlled-swap gates in the first quantum circuit to determine a first target quantum circuit to optimize the Shor algorithm.

[0035] Specifically, the Shor algorithm refers to a classical algorithm in the field of quantum computing, which can utilize the characteristics of quantum computing to solve the problem of large integer prime factorization that is difficult for classical computers to efficiently complete. The key of the Shor algorithm is to transform the prime factorization problem into a periodicity detection problem and achieve exponential acceleration by means of quantum superposition and inverse quantum Fourier transform (IQFT) of quantum computing.

[0036] A quantum circuit is a tool for quantum computing, which is used to transform an abstract quantum algorithm into a sequence of physical operations that can be executed on quantum computing hardware. Its essence is a graphical model that describes the evolution process of qubits (Qubits), similar to the logic circuit in a classical computer, but the operating object is qubits with the characteristics of quantum superposition and quantum entanglement.

[0037] A qubit (Qubit) refers to the basic unit of a quantum circuit and is the carrier of quantum information. It can be in 、 and its superposition state.

[0038] Quantum gates (Quantum Gates) refer to the basic operation units in quantum computing. They are mathematical operations that perform specific transformations on the states of qubits. Their essence is a unitary transformation acting on quantum states, satisfying reversibility and probability conservation, and are used to construct quantum circuits to realize the logical functions of quantum algorithms.

[0039] The controlled-swap gate (Controlled-Swap Gate, CSWAP) is an important quantum gate in quantum computing and belongs to the category of controlled gates. It determines whether to perform a swap operation by introducing a control bit. The controlled-swap gate usually acts on 3 qubits, including 1 control bit and 2 target bits. Among them, the control bit refers to the qubit in a quantum logic gate that is used to control the states of other qubits (controlled bits). Only when the control bit is in a specific state (usually the ground state ), the state of the controlled bit will change. The control bit itself does not change its state during the operation. It only determines whether to perform an operation on the controlled bit. The controlled bit is the qubit in the quantum logic gate that is affected by the control bit. When the control bit is in a specific state, the controlled bit will perform specific quantum operations, such as bit flipping, phase flipping, etc. The state change of the controlled bit depends on the state of the control bit and the specific quantum logic gate operation. Suppose the controlled swap gate is 1-controlled, then the logic of the controlled swap gate can be described as: when the control bit is ), swap the quantum states of the two target bits; when the control bit is ), the quantum states of the two target bits remain unchanged. Please refer to Figure 2 , Figure 2 for the schematic diagram of the controlled swap gate. Among them, the controlled swap gate is a 1-controlled controlled swap gate. The solid dot above is the control bit, and the crossed lines below are the target bits.

[0040] The target problem refers to the computational problem that the Shor algorithm aims at, that is, the problem of factoring large integers into prime factors. That is, given a large integer N (usually the product of two prime numbers), find its prime factors p and q (i.e., N = p×q, and p, q≠1 or N). In the traditional method, the steps to solve the target problem using the Shor algorithm are as follows: First, input the composite number N to be factored. Then, select a random integer a that satisfies 1 < a < N and gcd(a, N) = 1. Then, solve the period r of the function , that is, the smallest positive integer r that satisfies . If the period r is even and , then and are very likely to be non-trivial factors (i.e., prime factors) of N. In the process of solving the function , the superposition state can be prepared through the quantum register, where x can take multiple integer values at the same time (such as 0, 1, 2, and , etc.) to realize the parallel calculation of all possible values of f(x). And, the superposition state can also be operated through the inverse quantum Fourier transform to convert the period information of the function from the time domain to the frequency domain, so as to quickly extract the probability amplitude information of the period r. Finally, after obtaining the estimated value of the period r through quantum computing, use classical algorithms (such as continued fraction expansion) to accurately calculate r and combine number theory methods to factorize the prime factors of N.

[0041] The initial quantum circuit is a combination of quantum gates designed based on the principle of the Shor algorithm to solve the problem of factoring large integers into prime factors (the target problem). It directly corresponds to the mathematical logic of the algorithm and is the starting point for subsequent optimization. The initial quantum circuit includes a quantum register, an inverse quantum Fourier transform module, and a modular exponentiation module.

[0042] Among them, the quantum register includes a phase register and an operation register. The phase register is used to store the phase information of the inverse quantum Fourier transform. In the Shor algorithm, by performing the inverse Fourier transform operation on the phase register, the target information in the phase register can be transformed from the phase to the basis vector, thereby converting the period information encoded in the phase register into a measurable probability distribution for subsequent processing. When performing the controlled modular exponentiation operation, each bit of the phase register serves as a control bit to control the modular exponentiation operation on the operation register. Through the combination of different bits, the modular operation control of different exponential powers of the data in the operation register is achieved. The operation register is used to store the intermediate and final results of the modular exponentiation operation. Its initial state is usually set to a specific value, which is (i.e., the binary representation of ). During the execution of the Shor algorithm, the operation register will continuously update the data stored therein according to the control of the phase register. During the controlled modular exponentiation stage, according to the control of each bit of the phase register, the data in the operation register will perform the corresponding modular exponentiation operation. The inverse quantum Fourier transform module is used to extract the period information. The modular exponentiation module is used to calculate .

[0043] The modular exponentiation operator refers to the quantum circuit module that implements the function , which is the core component of the initial quantum circuit and essentially converts the classical modular exponentiation operation into a quantum reversible operation.

[0044] The first quantum circuit is the circuit structure obtained by replacing the modular exponentiation operator in the initial quantum circuit with a controlled swap gate, which is an optimized intermediate link. The core of the modular exponentiation operator is controlled multiplication, and multiplication can be achieved through the combination of addition and swap operations (such as the multiplication circuit based on a quantum adder). Therefore, by decomposing the multiplication steps in the modular exponentiation operator, some complex operations can be replaced with controlled swap gates.

[0045] The first target quantum circuit is the optimized circuit obtained by grouping and merging the controlled swap gates in the first quantum circuit.

[0046] First, the computer device constructs a basic quantum circuit for solving the target problem to be processed according to the mathematical principle of the Shor algorithm, that is, the initial quantum circuit.

[0047] Subsequently, the computer device locates the sub-circuit that implements in the initial quantum circuit and, using mathematical equivalence, replaces the modular exponentiation operator with a controlled swap gate, that is, by decomposing the multiplication steps in the modular exponentiation module, some complex operations are replaced with controlled swap gates. In this way, the multi-level modular exponentiation operation can be transformed into a more basic swap operation, reducing the circuit complexity.

[0048] Finally, the computer device performs grouped merging processing on the controlled swap gates in the first quantum circuit to determine the first target quantum circuit for optimizing the Shor algorithm.

[0049] The following takes the integer factorization of 21 = 3×7 as an example to illustrate the optimization method of the Shor algorithm based on controlled swap gates provided by the embodiments of the present application. Please refer to Figure 3 , Figure 3 which is a schematic diagram of the quantum circuit of the Shor algorithm. Among them, to are quantum bits. The horizontal lines folded below are operation registers for storing the intermediate and final results of modular exponentiation operations. Their initial states are usually set to specific values, and in most cases, they are . IQFT refers to the inverse quantum Fourier transform module. U represents the controlled U gate. In a quantum circuit, modular exponentiation operations are usually implemented through a series of controlled U gates, and each controlled U gate corresponds to operations. The t in the superscript of U represents the number of qubits in the phase register. M identifies the measurement operation.

[0050] It can be seen from Figure 3 that in quantum computing, modular exponentiation operations (i.e., calculating , corresponding to the exponential operation of the U gate) are the core steps of quantum algorithms such as the Shor algorithm. For the exponent x (assuming it is an n - qubit number), each of its bits (a total of t = n bits) needs to control the execution of the modular operation, and the processing of each qubit bit involves two multiplication operations. Therefore, the total number of multiplications for t operations is approximately 4n^2 (including additional operations such as modular reduction). Since the quantum circuit complexity of a single multiplication operation is O(n^2) (such as a multiplier based on Toffoli gates), the total arithmetic operation complexity is O(n^4).

[0051] Please refer to Figure 4 , Figure 4 which is a schematic diagram of the quantum circuit of the Shor algorithm. Since Figure 3 the controlled modular exponentiation operations in it are commutative with each other, we can move the controlled modular exponentiation operations forward and backward arbitrarily to form a quantum circuit as shown in Figure 4 . The quantum circuits shown in Figure 3 and Figure 4 are equivalent.

[0052] First, the computer device constructs an initial quantum circuit for solving the integer factorization of 21 = 3×7 according to the mathematical principle of the Shor algorithm.

[0053] Next, please refer to Figure 5 , Figure 5The first quantum circuit schematic diagram for solving the integer factorization of 21 = 3×7. The computer device locates and implements in the initial quantum circuit of the sub-circuit, and using mathematical equivalence, replaces the controlled-U gate with a controlled-swap gate. It should be noted that for demonstration purposes, in this example, the phase register takes 5 bits instead of 2n - 2 bits, and the controlled-SWAP gate with the control bit acting on the same bit is equivalent to a controlled-U operation. Also, the operation register should be 5 qubits, but since the 2nd and 4th bits have not been involved in the relevant operations of the controlled-SWAP gate, they are omitted here, leaving only 3 qubits.

[0054] Finally, please refer to Figure 6 , Figure 6 The first target quantum circuit schematic diagram for solving the integer factorization of 21 = 3×7. The computer device performs grouping and merging processing on the controlled-swap gates in the first quantum circuit to determine the first target quantum circuit for optimizing the Shor algorithm.

[0055] In summary, in the optimization method of the Shor algorithm based on the controlled-swap gate provided by the embodiments of the present application, based on the Shor algorithm, the computer device determines the initial quantum circuit according to the target problem to be processed. Then, the computer device converts the modular exponentiation operator in the initial quantum circuit into a controlled-swap gate to determine the first quantum circuit. Finally, the computer device performs grouping and merging processing on the controlled-swap gates in the first quantum circuit to determine the first target quantum circuit for optimizing the Shor algorithm. In this way, by replacing the modular exponentiation operator with a controlled-swap gate and performing grouping and merging processing on the controlled-swap gate, the quantum circuit depth and the required number of qubits of the Shor algorithm are reduced, thereby breaking through the performance limitations of current quantum computers and promoting the development of larger-scale Shor algorithm real machine experiments.

[0056] Please refer to Figure 7 ,in some embodiments, step 01 (based on the Shor algorithm, according to the target problem to be processed, determine the initial quantum circuit), includes: 011: Based on the Shor algorithm, determine the base according to the target problem; 012: Determine the number of phase qubits according to the target problem; 013: Determine the number of operation qubits according to the target problem; 014: Determine the initial quantum circuit according to the base, the number of phase qubits, and the number of operation qubits.

[0057] In some embodiments, the determination module is further configured to determine a basis based on the Shor algorithm according to the target problem, and determine the number of phase qubits according to the target problem. The determination module is further configured to determine the number of operation qubits according to the target problem, and determine an initial quantum circuit according to the basis, the number of phase qubits, and the number of operation qubits.

[0058] In some embodiments, the processor is further configured to determine a basis based on the Shor algorithm according to the target problem, and determine the number of phase qubits according to the target problem. The processor is further configured to determine the number of operation qubits according to the target problem, and determine an initial quantum circuit according to the basis, the number of phase qubits, and the number of operation qubits.

[0059] Specifically, in the Shor algorithm, the basis refers to a positive integer a that is relatively prime to the integer N to be factored and less than N (i.e., 1 < a < N and gcd(a, N) = 1). The basis is the core input of the modular exponentiation operation and is used to construct a periodic function. . The Shor algorithm analyzes the period r of this function through the inverse quantum Fourier transform (IQFT), and then uses number theory knowledge to factor N. It should be noted that the randomness of the basis affects the algorithm efficiency. In practical applications, multiple bases are usually randomly selected to ensure successful factorization.

[0060] The number of phase qubits refers to the number of qubits used to store the phase information of the period measurement result in the Shor algorithm, usually denoted as t. These qubits form a phase register. In the quantum circuit, the phase qubits are initialized to a superposition state through Hadamard gates, then entangled with the operation qubits through the modular exponentiation circuit, and finally the period information is encoded as a phase (i.e., the argument of the quantum state) through QFT. Moreover, the number t of phase qubits directly determines the accuracy of the period measurement: the larger t is, the higher the resolution of the measurement result, and the easier it is to deduce the true period r through classical algorithms.

[0061] The number of operation qubits refers to the number of qubits used to perform the modular exponentiation operation (i.e., calculate . It forms an operation register, usually denoted as n (n is the number of bits of the integer N to be factored, i.e., ). The operation qubits are used to store the intermediate results of the modular exponentiation operation (such as the value of ), and their quantum states evolve step by step along with the modular exponentiation circuit. Moreover, each operation qubit corresponds to a binary digit of the value, and iterative calculations of the value are realized through operations such as controlled gates (such as controlled multiplication gates) and SWAP gates.

[0062] It should be noted that the base is an input parameter of the algorithm and determines the periodic function to be analyzed; the number of phase qubits t and the number of operation qubits n are hardware parameters for circuit design, corresponding to the phase measurement accuracy and numerical representation accuracy respectively. In the initial quantum circuit design, n needs to be determined according to the size of N, t needs to be determined according to the expected period r, and a suitable base a needs to be selected. The three together determine the scale of the quantum circuit and the feasibility of the algorithm.

[0063] In this way, the computer device determines the base according to the target problem. The base is relatively prime to the integer to be factored in the target problem and is less than the integer to be factored. Then, the computer device determines the number of phase qubits according to the target problem. The number of phase qubits is used to record the phase information generated by running the Shor's algorithm. Next, the computer device determines the number of operation qubits according to the target problem. The number of operation qubits is used to record the quantum state information generated by running the modular exponentiation operator. Finally, the computer device determines the initial quantum circuit according to the base, the number of phase qubits, and the number of operation qubits. In this way, through parametric design, the quantization mapping of the Shor's algorithm is realized. While ensuring mathematical correctness, the resource consumption is controlled within the range that can be tolerated by the quantum computer, and it lays a foundation for subsequent optimization.

[0064] Please refer to Figure 8 , in some embodiments, step 014 (determine the initial quantum circuit according to the base, the number of phase qubits, and the number of operation qubits) includes: 0141: Determine the modular exponentiation operator according to the base, the number of phase qubits, and the integer to be factored; 0142: Determine the initial quantum circuit according to the base, the number of phase qubits, the number of operation qubits, and the modular exponentiation operator.

[0065] In some embodiments, the determination module is further configured to determine the modular exponentiation operator according to the base, the number of phase qubits, and the integer to be factored, and determine the initial quantum circuit according to the base, the number of phase qubits, the number of operation qubits, and the modular exponentiation operator.

[0066] In some embodiments, the processor is further configured to determine the modular exponentiation operator according to the base, the number of phase qubits, and the integer to be factored, and determine the initial quantum circuit according to the base, the number of phase qubits, the number of operation qubits, and the modular exponentiation operator.

[0067] Specifically, the construction of the modular exponentiation operator depends on the base a, the number of phase qubits t, and the integer to be factored N. The modular exponentiation operator is equivalent to the modular exponentiation operation in the classical algorithm (such as the fast power algorithm), but realizes parallel computing through quantum gate operations. It can utilize the quantum superposition state and can calculate corresponding to multiple x simultaneously , which is the key to the exponential acceleration achieved by Shor's algorithm.

[0068] After determining the modular exponentiation operator, the computer device determines an initial quantum circuit based on the base, the number of phase qubits, the number of operation qubits, and the modular exponentiation operator.

[0069] In this way, the computer device determines the modular exponentiation operator based on the base, the number of phase qubits, and the integer to be factored. Then, the computer device determines the initial quantum circuit based on the base, the number of phase qubits, the number of operation qubits, and the modular exponentiation operator. In this way, through rigorous number-theoretic transformations, it is ensured that the initial quantum circuit correctly maps the theoretical framework of Shor's algorithm mathematically, avoiding decomposition anomalies caused by parameter errors.

[0070] Please refer to Figure 9 , in some embodiments, step 03 (performing grouped merging processing on the controlled swap gates in the first quantum circuit to determine the first target quantum circuit) includes: 031: Grouping the controlled swap gates in the first quantum circuit based on a preset grouping rule to determine a first temporary quantum circuit; 032: Determining target quantum gate information and a second temporary quantum circuit according to the first temporary quantum circuit; 033: Determining the first target quantum circuit according to the target quantum gate information and the second temporary quantum circuit.

[0071] In some embodiments, the determination module is further configured to group the controlled swap gates in the first quantum circuit based on a preset grouping rule to determine a first temporary quantum circuit. And determine target quantum gate information and a second temporary quantum circuit according to the first temporary quantum circuit. And determine the first target quantum circuit according to the target quantum gate information and the second temporary quantum circuit.

[0072] In some embodiments, the processor is further configured to group the controlled swap gates in the first quantum circuit based on a preset grouping rule to determine a first temporary quantum circuit. And determine target quantum gate information and a second temporary quantum circuit according to the first temporary quantum circuit. And determine the first target quantum circuit according to the target quantum gate information and the second temporary quantum circuit.

[0073] Specifically, the grouped merging process refers to the process of grouping quantum gates with similar structures or shareable resources (such as controlled swap gates) in quantum circuit optimization, merging repeated or redundant operations to reduce circuit complexity and resource consumption.

[0074] The preset grouping rule refers to a preset grouping logic or strategy used to determine which controlled swap gates can be grouped into the same group. In some embodiments, the preset grouping rule includes: 1. Controlled swap gates with only different control bits and the same controlled bits can be grouped; 2. On the premise that the order of quantum gate operations does not affect the result (such as satisfying the commutation property), the order of quantum gates is allowed to be reorganized; 3. The grouped gates can share intermediate calculation results.

[0075] The first temporary quantum circuit refers to an intermediate state circuit obtained by preliminarily grouping the controlled swap gates in the original circuit (the first quantum circuit) after applying the preset grouping rule, providing a basis for subsequent extraction of target quantum gate information and generation of the final optimized circuit. The first temporary quantum circuit includes at least one group of target controlled swap gates with different control bits and the same controlled bits.

[0076] The target controlled swap gate refers to the grouped controlled swap gate in the first temporary quantum circuit. Please refer to Figure 5 , Figure 5 The quantum gates in region A in

[0077] The target quantum gate information refers to the key gate operation information extracted from the first temporary quantum circuit, used to describe the optimizable gate structure after grouping, including the controlled swap gate and its related information, the controlled NOT gate (CNOT gate) and its related information, providing clear operation objects and parameters for subsequent circuit optimization. For example, by reorganizing the control logic through the CNOT gate, the merging of multiple controlled swap gates can be achieved. Among them, the controlled swap gate and its related information include the specific qubit numbers of the control bit and the controlled bit, etc. The controlled NOT gate (CNOT gate) and its related information include the auxiliary CNOT gates introduced or to be adjusted during the grouping process, etc., used to realize the conversion of control logic.

[0078] The controlled NOT gate is a basic quantum logic gate in quantum computing, which is a two-qubit gate, where one qubit serves as the control bit and the other as the controlled bit. The control logic of the controlled NOT gate is: when the control bit is , the controlled bit remains unchanged. When the control bit is , the state of the controlled bit flips (i.e., becomes , becomes ). Please refer to Figure 10 , Figure 10 for the schematic diagram of the controlled NOT gate. Among them, the solid dot acting on the qubit q1 is the control bit; the small circle with a cross is the controlled bit, acting on the qubit q2.

[0079] The second temporary quantum circuit refers to an intermediate circuit obtained by preliminarily optimizing the first temporary quantum circuit after extracting the target quantum gate information.

[0080] First, divide the controlled swap gates in the first quantum circuit into different groups according to preset rules (such as different control bits and the same controlled bits) to generate a first temporary quantum circuit.

[0081] Next, further adjust the first temporary quantum circuit and extract the target quantum gate information to obtain a second temporary quantum circuit.

[0082] Finally, optimize the second temporary quantum circuit according to the scalar quantum gate information to finally generate the first target quantum circuit.

[0083] In this way, based on the preset grouping rules, the computer device groups the controlled swap gates in the first quantum circuit to determine the first temporary quantum circuit, and the first temporary quantum circuit includes at least one group of target controlled swap gates with different control bits and the same controlled bits. Next, the computer device determines the target quantum gate information and the second temporary quantum circuit according to the first temporary quantum circuit, and the target quantum gate information includes controlled swap gates, relevant information of the controlled swap gates, controlled NOT gates, and relevant information of the controlled NOT gates. Finally, the computer device determines the first target quantum circuit according to the target quantum gate information and the second temporary quantum circuit. In this way, by grouping and combining the controlled swap gates, the redundant operations in the quantum circuit are reduced, and the requirements for qubit resources and the number of quantum gate operations are reduced, thereby improving the execution efficiency of the Shor algorithm.

[0084] Please refer to Figure 11 , in some embodiments, step 032 (determine the target quantum gate information and the second temporary quantum circuit according to the first temporary quantum circuit) includes: 0321: Based on the preset merging rules, perform a merging process on the target controlled swap gates to determine the target quantum gate information and the second temporary quantum circuit.

[0085] In some embodiments, the determination module is further configured to perform a merging process on the target controlled swap gates based on the preset merging rules to determine the target quantum gate information and the second temporary quantum circuit.

[0086] In some embodiments, the processor is further configured to perform a merging process on the target controlled swap gates based on the preset merging rules to determine the target quantum gate information and the second temporary quantum circuit.

[0087] Specifically, the preset merging rules refer to predefined logical rules for determining which controlled swap gates can be merged into an equivalent single operation or a smaller combination to reduce the complexity of the quantum circuit. In some embodiments, the preset merging rules include the same controlled bits and different control bits.

[0088] The merging process refers to an optimization process in which multiple controlled swap gates are replaced with an equivalent but more streamlined combination of quantum gates based on a preset merging rule.

[0089] Please refer to Figure 12 , Figure 12 for the schematic diagram of the merging process. Among them, Figure 12 on the left is the target controlled swap gate, including two CSWAP gates. The control bit of the first CSWAP gate is , and the controlled bits are and . The control bit of the second CSWAP gate is , and the controlled bits are and . Figure 12 On the right is a composite operation controlled by and .

[0090] In this way, based on the preset merging rule, the computer device performs a merging process on the target controlled swap gate to determine the target quantum gate information and the second temporary quantum circuit. In this way, the merged quantum circuit disassembles the global operation into independent groups, and the gates within each group can be independently optimized, facilitating the implementation of cross-group parallelism.

[0091] Please refer to Figure 13 , in some embodiments, step 033 (determining the first target quantum circuit according to the target quantum gate information and the second temporary quantum circuit) includes: 0331: Based on a preset decomposition rule, decompose the quantum gates in the target quantum gate information to determine the first target quantum circuit.

[0092] In some embodiments, the determination module is further configured to decompose the quantum gates in the target quantum gate information based on a preset decomposition rule to determine the first target quantum circuit.

[0093] In some embodiments, the processor is further configured to decompose the quantum gates in the target quantum gate information based on a preset decomposition rule to determine the first target quantum circuit.

[0094] Specifically, the preset decomposition rule refers to a predefined conversion rule for decomposing complex quantum gates (such as controlled swap gates) into a set of basic gates that can be directly implemented by quantum hardware, such as controlled NOT gates and controlled-controlled-NOT gates (Toffoli gates).

[0095] The decomposition process refers to the specific implementation process of converting complex quantum gate operations in the target quantum gate information into a sequence of basic gates based on a preset decomposition rule. Please refer to FIGS. 14(a) and 14(b). FIGS. 14(a) and 14(b) show two ways of decomposing the controlled-swap gate. The two decomposition methods of the controlled-swap gate are functionally equivalent. The difference lies in the different bit positions of the Ry gates after the subsequent approximate decomposition of the Toffoli gate, as well as the resulting differences in the CNOT gate symmetry and circuit optimization potential.

[0096] Please refer to Figure 15 , Figure 15 FIG. 14(a) is a schematic diagram of the decomposition of the Toffoli gate obtained according to the decomposition method shown in FIG. 14(a). In this way, 4 Ry gates and 3 controlled-NOT gates are obtained. Among them, the 4 Ry gates all act on the middle bit of the operation register (i.e., the common bit where the controlled bit is located), and the angles of the 4 Ry gates are +45°, +45°, -45°, and -45°, respectively.

[0097] Please refer to Figure 6 , for the integer decomposition of 21 = 3×7, after determining the target quantum gate information and the second temporary quantum circuit, based on the preset decomposition rule, the computer device performs a decomposition process on the target quantum gate information to determine the first target quantum circuit (as Figure 6 shown, the decomposition of the controlled-SWAP gate here all adopts the decomposition method shown in FIG. 14(b)).

[0098] In this way, based on the preset decomposition rule, the computer device performs a decomposition process on the target quantum gate information to determine the first target quantum circuit. In this way, the complex controlled-swap gate is decomposed and converted into a combination of basic gates, which is convenient to implement on quantum hardware.

[0099] Please refer to Figure 16 , in some embodiments, the method further includes: 04: Performing an identification process on the first target quantum circuit to determine the existence of the first circuit property of the first target quantum circuit; 05: Determining a second quantum circuit according to the existence of the first circuit property; 06: Determining a second target quantum circuit according to the second quantum circuit to optimize the Shor algorithm.

[0100] In some embodiments, the determining module is further configured to perform an identification process on the first target quantum circuit to determine the existence of the first circuit property of the first target quantum circuit. And determining a second quantum circuit according to the existence of the first circuit property. And determining a second target quantum circuit according to the second quantum circuit to optimize the Shor algorithm.

[0101] In some embodiments, the processor is further configured to perform identification processing on the first target quantum circuit to determine the presence of the first circuit property of the first target quantum circuit. And based on the presence of the first circuit property, determine the second quantum circuit. And based on the second quantum circuit, determine the second target quantum circuit to optimize the Shor algorithm.

[0102] Specifically, the first circuit property is the core basis for triggering optimization, including properties such as CNOT gate symmetry, controlled-bit mutual exclusivity, operation determinacy, and operation commutativity.

[0103] Among them, CNOT gate symmetry refers to the fact that in the quantum circuit structure after the decomposition of the controlled SWAP gate, the arrangement of CNOT gates exhibits a symmetric characteristic that can be adjusted in direction or order. When there is CNOT gate symmetry, the function of the quantum circuit remains unchanged after adjustment. For example, please refer again to Figure 6 , Figure 6 In region A, the two controlled NOT gates with the controlled bit q1 have CNOT gate symmetry. The control bits of these two controlled NOT gates are both q0, the controlled bits are both q1, and they are symmetric based on the Toffoli gate in region A.

[0104] Controlled-bit mutual exclusivity means that the controlled bits (i.e., the qubits actually performing the operation) of two identical controlled gates (such as CSWAP gate, Toffoli gate) are distributed on different qubits, and the control bit acts on the same qubit.

[0105] Operation determinacy means that the result of a quantum gate operation does not depend on the measurement result or other random factors. For example, certain operation sequences can be proven to necessarily produce specific results without additional verification.

[0106] Operation commutativity means that two quantum gates A and B satisfy AB = BA, that is, the operation order can be exchanged without affecting the final quantum state. For example, two single-qubit gates acting on different qubits are necessarily commutative.

[0107] The second quantum circuit is an intermediate product after preliminary optimization based on the first circuit property.

[0108] The second target quantum circuit is the quantum circuit that finally adapts to the hardware, completing the full-process optimization from theoretical design to physical execution.

[0109] First, scan the first target quantum circuit to identify the first circuit properties present therein. Then, based on the identified properties, optimize the first target quantum circuit. Finally, the computer device determines the second target quantum circuit based on the second quantum circuit to optimize the Shor algorithm.

[0110] In this way, the computer device identifies and processes the first target quantum circuit to determine the presence of the first circuit property of the first target quantum circuit. Then, the computer device determines the second quantum circuit based on the presence of the first circuit property. Finally, the computer device determines the second target quantum circuit based on the second quantum circuit to optimize the Shor algorithm. In this way, through the process of identifying circuit properties, targeted optimization, and global integration, the mathematical properties of the first target quantum circuit are utilized to achieve the high efficiency of the modular exponentiation operation module of the Shor algorithm.

[0111] Please refer to Figure 17 , in some embodiments, the first circuit property includes controlled-NOT gate symmetry, controlled-bit mutual exclusivity, operation commutativity, and operation determinacy. Step 05 (determining the second quantum circuit based on the presence of the first circuit property) includes: 051: When the first target quantum circuit has controlled-NOT gate symmetry, controlled-bit mutual exclusivity, and operation commutativity, based on the controlled-NOT gate symmetry, controlled-bit mutual exclusivity, and operation commutativity, adjust the controlled-NOT gates in the first target quantum circuit to determine the second quantum circuit; or 052: When the first target quantum circuit has operation determinacy, based on the operation determinacy, optimize the first target quantum circuit to determine the second quantum circuit.

[0112] In some embodiments, the determination module is further configured to, when the first target quantum circuit has controlled-NOT gate symmetry, controlled-bit mutual exclusivity, and operation commutativity, based on the controlled-NOT gate symmetry, controlled-bit mutual exclusivity, and operation commutativity, adjust the controlled-NOT gates in the first target quantum circuit to determine the second quantum circuit. Or, it is configured to, when the first target quantum circuit has operation determinacy, based on the operation determinacy, optimize the first target quantum circuit to determine the second quantum circuit.

[0113] In some embodiments, the processor is further configured to, when the first target quantum circuit has controlled-NOT gate symmetry, controlled-bit mutual exclusivity, and operation commutativity, based on the controlled-NOT gate symmetry, controlled-bit mutual exclusivity, and operation commutativity, adjust the controlled-NOT gates in the first target quantum circuit to determine the second quantum circuit. Or, it is configured to, when the first target quantum circuit has operation determinacy, based on the operation determinacy, optimize the first target quantum circuit to determine the second quantum circuit.

[0114] Specifically, when the first target quantum circuit has controlled-NOT gate symmetry, controlled-bit mutual exclusivity, and operation commutativity, based on the controlled-NOT gate symmetry, controlled-bit mutual exclusivity, and operation commutativity, the computer device adjusts the controlled-NOT gates in the first target quantum circuit to determine the second quantum circuit. Please refer to Figure 6 , Figure 6Among the three SWAP sub-circuits in Region B, there are adjacent SWAP gates. After decomposition, the resulting circuit contains multiple CNOT gates and Ry gates, and there is an intersection between the control bits of the CNOT gates and the acting bits of the Ry gates, resulting in non-parallel operations and a relatively high circuit depth. By swapping the directions of the CNOT gates in Region B (i.e., converting from Figure 14(b) to Figure 14(a)), without changing the overall function of the circuit, the outer CNOT gates of adjacent controlled SWAP operations can form a commutation ability between the control bits, obtaining a quantum circuit as shown in Figure 18 As shown. As Figure 18 shown, the control bits of the two CNOT gates in the solid-line box of Region C commute on a common qubit. Since the Toffoli gates use an approximate circuit (as shown in Figure 15 ); therefore, the Ry gates decomposed from these Toffoli gates are not on the middle qubits of the operation register (control-bit mutual exclusivity), which enables the two CNOT gates in each Region C to be parallel to the Ry gates decomposed from the Toffoli gates of the other side after adjusting the order, thereby reducing the circuit depth.

[0115] Please refer to Figure 19 , there is operational determinacy in the first target quantum circuit. Based on the operational determinacy, the computer device optimizes the first target quantum circuit to determine the second quantum circuit. As Figure 19 shown in Region D, since the two H gates output a uniform superposition state and the subsequent CNOT does not change the output, the CNOT gate can be omitted. As Figure 19 shown in Region E, since the control bit of the CNOT gate is a definite 1, the middle qubit of the operation register must also be 1. This circuit can be replaced by two direct-product X gates. And it can be found that the control bit of the Toffoli gate in the next time step of this circuit on the middle qubit of the operation register is also a definite 1. Therefore, whether this Toffoli gate is executed depends entirely on a control bit above, thus degenerating into a CNOT gate, and the circuit depth is reduced from 7 to 1. The circuit after simplification using operational determinacy is as shown in Figure 20 As shown.

[0116] In addition, please refer to Figure 21 , it can be found that new operational determinacy may also appear in the optimized circuit, such as the CNOT gate in Figure 21 Region F. Since the control bit of this CNOT gate is constantly 0, this CNOT gate can also be omitted.

[0117] Please refer to Figure 21, the CNOT at the second time step of the circuit and the control bits (or controlled bits) of the subsequent CNOT gates are not on the same qubit, so commutation operations cannot be used. However, it can be found that the circuit in region G is actually a circuit for preparing Bell states. Then, swapping the operations of the two qubits of this circuit does not affect the result of quantum state evolution and also belongs to the category of operation determinacy, as Figure 22 shows the equivalence of the two ( Figure 22 is a Bell state preparation circuit).

[0118] Please refer to Figure 23 , finally, after properties such as CNOT gate symmetry, controlled bit mutual exclusivity, operation determinacy, and operation commutation are considered, the first target quantum circuit is optimized in multiple rounds (in some embodiments, after identifying the circuit properties in one round, the circuit properties are identified again, and after multiple iterations, the second target quantum circuit is determined). The resulting second quantum circuit is as Figure 23 shown. In this way, it can be found that when reaching the last Ry gate on the right, the depth of the quantum circuit is reduced from Figure 18 19 time steps to 8 time steps. At the same time, this circuit structure allows the maximum parallelism of two-qubit gates and single-qubit gates, while avoiding the parallelism between two-qubit gates in close proximity, effectively suppressing the impact of qubit crosstalk on the output result.

[0119] Thus, in the case where the first target quantum circuit has control-NOT gate symmetry, controlled bit mutual exclusivity, and operation commutation, based on the control-NOT gate symmetry, controlled bit mutual exclusivity, and operation commutation, the computer device adjusts the control-NOT gates in the first target quantum circuit to determine the second quantum circuit. Or, in the case where the first target quantum circuit has operation determinacy, based on the operation determinacy, the computer device optimizes the first target quantum circuit to determine the second quantum circuit. In this way, by clarifying the first circuit property and optimizing the first target quantum circuit based on this first circuit property, the consumption of quantum gate resources can be reduced, thereby reducing the accumulation of quantum gate errors, improving the accuracy of periodic measurements, and further accelerating the speed of large integer factorization.

[0120] Please refer to Figure 24 , in some embodiments, step 05 (determining the second quantum circuit according to the presence or absence of the first circuit property) includes: 053: When the first circuit property does not exist, determining the first target quantum circuit as the second target quantum circuit.

[0121] In some embodiments, the confirmation module is further configured to determine the first target quantum circuit as the second target quantum circuit when the first circuit property does not exist.

[0122] In some embodiments, the processor is further configured to determine the first target quantum circuit as the second target quantum circuit in the absence of the first circuit property.

[0123] Specifically, in the absence of the first circuit property, the computer device determines the first target quantum circuit as the second target quantum circuit.

[0124] In this way, in the absence of the first circuit property, the computer device determines the first target quantum circuit as the second target quantum circuit. Thus, when the first target quantum circuit does not satisfy any optimizable circuit properties, forcibly applying the optimization rules may lead to circuit logic errors or introduce additional noise. At this time, directly retaining the original circuit can avoid damaging the circuit function due to blind optimization and ensure the correctness and stability of the Shor algorithm.

[0125] Please refer to Figure 25 , in some embodiments, step 06 (determining the second target quantum circuit according to the second quantum circuit to optimize the Shor algorithm) includes: 061: Perform an identification process on the second quantum circuit to determine the presence or absence of the second circuit property of the second quantum circuit; 062: Determine the second quantum circuit according to the presence or absence of the second circuit property; Determine the second target quantum circuit according to the second quantum circuit to optimize the Shor algorithm.

[0126] In some embodiments, the determination module is further configured to perform an identification process on the second quantum circuit to determine the presence or absence of the second circuit property of the second quantum circuit. And determine the second quantum circuit according to the presence or absence of the second circuit property. And determine the second target quantum circuit according to the second quantum circuit to optimize the Shor algorithm.

[0127] In some embodiments, the processor is further configured to perform an identification process on the second quantum circuit to determine the presence or absence of the second circuit property of the second quantum circuit. And determine the second quantum circuit according to the presence or absence of the second circuit property. And determine the second target quantum circuit according to the second quantum circuit to optimize the Shor algorithm.

[0128] Specifically, after obtaining the second quantum circuit, further identify the second circuit property in the second quantum circuit and generate the final second target quantum circuit based on these properties to achieve in-depth optimization of the Shor algorithm. In this way, by repeatedly identifying the circuit properties of the quantum circuit and gradually optimizing, an efficient implementation of the Shor algorithm is finally generated.

[0129] In this way, the computer device identifies and processes the second quantum circuit to determine the existence of the second circuit property of the second quantum circuit. Then, the computer device determines the second quantum circuit according to the existence of the second circuit property. Finally, the computer device determines the second target quantum circuit according to the second quantum circuit to optimize the Shor algorithm. In this way, through multi-level identification, continuous improvement of the quantum circuit is achieved, so that the Shor algorithm meets the standard in terms of performance indicators such as the number of quantum gates, the depth of the quantum circuit, and the fidelity of the quantum circuit.

[0130] The present application also provides a computer-readable storage medium containing a computer program. When the computer program is executed by one or more processors, one or more processors are caused to execute the method of the present application.

[0131] It can be understood that the computer program includes computer program code. The computer program code can be in the form of source code, object code, executable file or some intermediate form, etc. The computer-readable storage medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disc, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), and software distribution media, etc.

[0132] In the description of this specification, the descriptions referring to the terms "specifically", "further", "specially", "understandably", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0133] Any process or method description shown in the flowchart or described in other ways herein can be understood to represent a module, segment or part of code including one or more executable instructions for implementing a specific logical function or process, and the scope of the preferred embodiments of the present application includes additional implementations, where the functions can be executed in a substantially simultaneous manner or in the reverse order according to the functions involved, rather than in the order shown or discussed, which should be understood by those skilled in the art of the embodiments of the present application.

[0134] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. An optimization method for Shor's algorithm based on controlled swap gates, characterized in that, The method includes: Based on the Shor algorithm, determine an initial quantum circuit according to the target problem to be processed; Convert the modular exponentiation operator in the initial quantum circuit into a controlled-swap gate to determine a first quantum circuit; Perform grouping and merging processing on the controlled-swap gates in the first quantum circuit to determine a first target quantum circuit so as to optimize the Shor algorithm.

2. The method according to claim 1, wherein The step of based on the Shor algorithm, determining an initial quantum circuit according to the target problem to be processed includes: Based on the Shor algorithm, determine a base according to the target problem, where the base is relatively prime to the integer to be factored in the target problem and less than the integer to be factored; According to the target problem, determine the number of phase qubits, where the number of phase qubits is used to record the phase information generated by running the Shor algorithm; According to the target problem, determine the number of operation qubits, where the number of operation qubits is used to record the quantum state information generated by running the modular exponentiation operator; Determine the initial quantum circuit according to the base, the number of phase qubits, and the number of operation qubits.

3. The method according to claim 2, wherein The step of determining the initial quantum circuit according to the base, the number of phase qubits, and the number of operation qubits includes: Determine the modular exponentiation operator according to the base, the number of phase qubits, and the integer to be factored; Determine the initial quantum circuit according to the base, the number of phase qubits, the number of operation qubits, and the modular exponentiation operator.

4. The method according to claim 1, wherein The step of performing grouping and merging processing on the controlled-swap gates in the first quantum circuit to determine a first target quantum circuit includes: Based on a preset grouping rule, perform grouping processing on the controlled-swap gates in the first quantum circuit to determine a first temporary quantum circuit, where the first temporary quantum circuit includes at least one group of target controlled-swap gates with different control bits and the same controlled bits; Determine target quantum gate information and a second temporary quantum circuit according to the first temporary quantum circuit; Determine the first target quantum circuit according to the target quantum gate information and the second temporary quantum circuit.

5. The method according to claim 4, characterized in that, The step of determining target quantum gate information and a second temporary quantum circuit according to the first temporary quantum circuit includes: Based on a preset merging rule, perform merging processing on the target controlled-swap gates to determine the target quantum gate information and the second temporary quantum circuit.

6. The method according to claim 4, wherein The step of determining the first target quantum circuit according to the target quantum gate information and the second temporary quantum circuit includes: Based on a preset decomposition rule, perform decomposition processing on the quantum gates in the target quantum gate information to determine the first target quantum circuit.

7. The method according to claim 1, characterized in that, The method further includes: Perform identification processing on the first target quantum circuit to determine the existence situation of the first circuit property of the first target quantum circuit; Determine a second quantum circuit according to the existence situation of the first circuit property; Determine a second target quantum circuit according to the second quantum circuit so as to optimize the Shor algorithm.

8. The method according to claim 7, wherein The first circuit property includes the symmetry of the controlled NOT gate, the mutual exclusivity of the controlled bits, the commutativity of operations, and the determinacy of operations. Determining the second quantum circuit according to the presence of the first circuit property includes: When the first target quantum circuit has the symmetry of the controlled NOT gate, the mutual exclusivity of the controlled bits, and the commutativity of operations, adjusting the controlled NOT gates in the first target quantum circuit based on the symmetry of the controlled NOT gate, the mutual exclusivity of the controlled bits, and the commutativity of operations to determine the second quantum circuit; or When the first target quantum circuit has the determinacy of operations, optimizing the first target quantum circuit based on the determinacy of operations to determine the second quantum circuit.

9. The method according to claim 7, characterized in that Determining the second quantum circuit according to the presence of the first circuit property includes: When the first circuit property does not exist, determining the first target quantum circuit as the second target quantum circuit.

10. The method according to claim 7, characterized in that Determining the second target quantum circuit according to the second quantum circuit to optimize the Shor algorithm includes: Performing an identification process on the second quantum circuit to determine the presence of the second circuit property of the second quantum circuit; Determining the second quantum circuit according to the presence of the second circuit property; Determining the second target quantum circuit according to the second quantum circuit to optimize the Shor algorithm.

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