Shift register reinforced circuit structure capable of resisting single event upset

Abstract

The invention provides an anti-single event upset shift register reinforced circuit structure, and relates to the field of integrated circuit reliability design, the circuit comprises an enable control module, a shift register circuit and an output control selection module; the enabling control module can be configured to be in a redundancy mode or a single-group activation mode, when the enabling control module is in the single-group activation mode, enabling signals drive all the triggers one to one, and data are shifted and transmitted step by step in the shifting register circuit; when the shift register circuit is in a redundancy mode, the triggers correspond to each other in pairs to form a group of main triggers and backup triggers, enable signals drive each group of main triggers and backup triggers to work at the same time, the same data is written into the main triggers and the backup triggers synchronously, and the output control selection module is used for monitoring the data flow state of the shift register circuit in real time. And the state of the trigger is verified, and if single event upset or time sequence deviation is detected, an error correction mechanism is triggered immediately to ensure data integrity.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit reliability design, and particularly to a shift register hardening circuit structure against single-event upsets. Background Art

[0002] Single-Event Upset (SEU) is a transient fault phenomenon in integrated circuits caused by high-energy charged particles. When high-energy particles penetrate the sensitive area of the chip, their ionization effect may cause the state of memory cells or logic circuits to flip unexpectedly. As semiconductor processes evolve towards the nanoscale, the critical charge of devices decreases, and the sensitivity to SEU increases significantly, becoming a key threat to high-reliability electronic systems.

[0003] A shift register is a basic storage device in digital circuits, composed of multiple flip-flops cascaded together, capable of shifting stored binary data bit by bit in a specific direction (left shift or right shift). Its core function is to control the sequential movement of data through a clock signal, and it is widely used in fields such as data format conversion, timing control, and arithmetic processing. With its flexible data movement ability, the shift register has become a fundamental component for implementing serial-to-parallel conversion, timing control, and data processing in digital systems.

[0004] However, in the aerospace application environment, due to its cascaded structure and timing dependence, the shift register is extremely vulnerable to the combined effects of the space radiation environment, leading to multiple reliability problems. When high-energy charged particles penetrate the device, they may trigger single-event upsets, causing the state of a certain flip-flop in the register to flip abnormally, and the error will propagate step by step with the shift operation, forming data chain contamination.

[0005] In the prior art, the mitigation strategies for SEU mainly include fault-tolerant designs such as triple modular redundancy, error detection and correction, and also include methods of hardening with radiation-resistant processes such as using silicon-on-insulator (SOI) or silicon carbide (SiC) materials: Conventional fault-tolerant design methods have problems such as doubled area, power consumption, voting delay, additional storage overhead, and limited real-time performance; The cost of process hardening design is high, and it is difficult to be compatible with commercial design processes.

[0006] However, as the application scenarios expand to extreme environments such as deep space exploration and high-density integration, the existing solutions face bottlenecks in terms of energy efficiency ratio, multi-bit flip tolerance, and dynamic recovery efficiency. Especially under the constraints of high frequency and low power consumption, traditional static redundancy and verification mechanisms are difficult to balance the reliability and performance requirements. Therefore, there is an urgent need for a new type of hardening architecture that can achieve high-efficiency SEU immunity with limited resources and be compatible with mainstream design methods to cope with the severe reliability challenges of next-generation electronic systems. Summary of the Invention

[0007] In order to effectively reduce the area overhead of traditional reinforcement design and conform to the commercial process design flow as much as possible, the present invention designs a shift register reinforcement circuit structure that utilizes the characteristics of the shift register itself and is flexibly configurable to resist single-event upsets, realizing the error detection function without sacrificing performance.

[0008] Specifically, the present invention provides a shift register reinforcement circuit structure for resisting single-event upsets, including: an enable control module, a shift register circuit, and an output control selection module; wherein, the enable control module is used to form different enable signals through decoding of the external address signal terminal according to the external control and enable signals, so as to be configured into different enable modes, and the enable modes include a redundant mode or a single-group activation mode; The shift register circuit is a configurable shift register array composed of multi-stage flip-flops. When in the single-group activation mode, the enable signal drives all flip-flops one by one, and data is shifted and transmitted step by step in the shift register circuit; when in the redundant mode, the flip-flops are paired in pairs to form a group of master flip-flops and backup flip-flops, and the enable signal drives each group of master flip-flops and backup flip-flops to work simultaneously, so that the same data is synchronously written into the master flip-flops and backup flip-flops to form a dual-copy redundant storage; The output control selection module is used to monitor the data flow state of the shift register circuit in real time and perform logical determination; when in the single-group activation mode, the output control selection module directly outputs the data output by the shift register circuit; when in the redundant mode, the output control selection module compares the data output by the master flip-flop and the backup flip-flop in real time. If the data is consistent, the current valid group of data is output. If the data is inconsistent, no data is output.

[0009] As a further description of the present invention, a clock signal terminal, a reset signal terminal, a control signal terminal, an external enable signal terminal, an address signal terminal, and an enable control network output terminal are provided on the enable control module, and an address decoder is included in the enable control module; after receiving the clock signal, the reset signal, and the control signal, the enable control module selects the address signal terminal through the address decoder to generate different enable signals for output, so as to realize the configuration of the redundant mode or the single-group activation mode.

[0010] As a further description of the present invention, when the control signal is at a low level, the enable control module is configured into the single-group activation mode, and when the control signal is at a high level, the enable control module is configured into the redundant mode.

[0011] As a further description of the present invention, each flip-flop includes a standard input terminal, a clock terminal, an output terminal, and an enable control terminal, wherein the standard input terminal is used to receive external input data; The output end is connected to the standard input end of the next-stage flip-flop, which is used to directly output data or shift and transmit data to the next-stage flip-flop under the drive of a clock. The enable control end is connected to a single enable end among the corresponding external enable signal end and the enable control network output end in the enable control module, and is used to receive the enable signal output by the enable control module.

[0012] As a further description of the present invention, the single enable end of the enable control network output end is simultaneously connected to the enable control ends of two flip-flops, so that the flip-flops are paired up to form a group of master flip-flops and backup flip-flops.

[0013] As a further description of the present invention, the output control selection module includes a control selector and an error judgment module, and the data output end of the shift register circuit is simultaneously connected to the control selector and the error judgment module; When in the single-group activation mode, the error judgment module is turned off, and the data output by the shift register circuit is directly output by the control selector; when in the redundant mode, the control selector is turned off, and the error judgment module compares the data output by the master flip-flop and the backup flip-flop in real time. If the data is consistent, the current valid group data is output. If the data is inconsistent, no data is output.

[0014] As a further description of the present invention, the output control selection module switches the data output path through a selection enable signal. The selection enable signal is respectively connected to the control selector and the error judgment module. When in the single-group activation mode, the selection enable signal remains high level, thereby activating the control selector and turning off the error judgment module; when in the redundant mode, the selection enable signal remains low level, thereby activating the error judgment module and turning off the control selector.

[0015] As a further description of the present invention, the error judgment module includes a plurality of exclusive-OR gate circuits and a plurality of two-to-one selectors. The output ends of the master flip-flop and the backup flip-flop in the same group are connected to the same exclusive-OR gate circuit, and the output end of each master flip-flop is connected to a two-to-one selector. The exclusive-OR gate circuit and the two-to-one selector connected to the output end of the same master flip-flop are connected to each other; When in the redundant mode, the exclusive-OR gate circuit compares the data output by the master flip-flop and the backup flip-flop in real time. If the data is consistent, the data output by the master flip-flop is output by the two-to-one selector. If the data is inconsistent, the output signal of the two-to-one selector is turned off.

[0016] As a further illustration of the present invention, the exclusive - OR gate circuit controls the state of the multiplexer through the error indication signal output therefrom; if the data is consistent, the error indication signal remains at a low level, and the data output from the master flip - flop is output by the multiplexer; if the data is inconsistent, the error indication signal remains at a high level, and the output signal of the multiplexer is turned off.

[0017] As a further illustration of the present invention, if the data is consistent, the error indication signal is also transmitted to the upper - level processor, and the upper - level processor controls discarding the error data and re - sending the relevant correct data to the standard data input terminal of the corresponding flip - flop.

[0018] Compared with the prior art, the present invention has the following beneficial technical effects: The anti - single - event - upset shift register reinforcement circuit structure provided by the present invention realizes efficient fault tolerance while reducing hardware overhead through dynamic enable control, redundant data synchronous writing, and intelligent switching mechanisms, and is applicable to high - reliability application scenarios.

[0019] Other features and advantages of this technical solution will be described in the subsequent specification, and, in part, will become apparent from the specification, or will be understood by implementing this technical solution. The objectives and other advantages of this technical solution can be realized and obtained through the structures specifically pointed out in the written specification and the drawings.

[0020] The following further describes the technical solution of this technical solution in detail through the drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings are used to provide a further understanding of this technical solution, and constitute a part of the specification. Together with the embodiments of this technical solution, they are used to explain this technical solution, and do not constitute a limitation to this technical solution. In the drawings: Figure 1 It is the overall architecture of the anti - single - event - upset shift register reinforcement circuit structure provided by the present invention.

[0022] Figure 2 It is the structural diagram of the enable control module in the present invention.

[0023] Figure 3 It is the core structural diagram of the shift register circuit in the present invention.

[0024] Figure 4 It is the core structural diagram of the output control selection module in the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] The following describes the preferred embodiments of this technical solution with reference to the drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain this technical solution, and are not used to limit this technical solution.

[0026] As Figure 1 shown, the present invention provides a hardened circuit structure for a shift register against single event upset, comprising: an enable control module, a shift register circuit and an output control selection module; wherein, the enable control module is configured to form different enable signals after decoding through an external address signal terminal according to an external control and an enable signal, so as to be configured into different enable modes, and the enable modes include a redundant mode or a single-group activation mode; the shift register circuit is a configurable shift register array composed of multi-stage flip-flops. When in the single-group activation mode, the enable signal drives all flip-flops one by one, and data is shifted and transmitted step by step in the shift register circuit; when in the redundant mode, the flip-flops are paired two by two to form a group of master flip-flops and backup flip-flops, and the enable signal drives each group of master flip-flops and backup flip-flops to work simultaneously, so that the same data is synchronously written into the master flip-flops and backup flip-flops to form a dual-copy redundant storage; the output control selection module is configured to monitor the data flow state of the shift register circuit in real time and perform a logical determination; when in the single-group activation mode, the output control selection module directly outputs the data output by the shift register circuit; when in the redundant mode, the output control selection module compares the data output by the master flip-flops and backup flip-flops in real time. If the data is consistent, the current valid group of data is output; if the data is inconsistent, no data is output.

[0027] Specifically, as Figure 2As shown, the enable control module is provided with a clock signal terminal (CK), a reset signal terminal (RST), a control signal terminal (CTRL), an external enable signal terminal (EN[0:31]), an address signal terminal (ADDR), and an enable control network output terminal (EN[0:15]); the enable control module contains an address decoder that dynamically allocates enable signals after receiving a control signal (CTRL). When CTRL = 0 (single-group activation mode), the external enable signals EN[0:31] are directly connected to 32 flip-flops; when CTRL = 1 (redundancy mode), the address decoder maps EN[0:15] to 16 groups of enable signals (E0 - E15), and each group simultaneously drives a master flip-flop (such as flip-flop 0) and a backup flip-flop (such as flip-flop 16) to achieve synchronous writing of double copies. After receiving the clock signal, the reset signal, and the control signal, the enable control module selects the address signal terminal through the address decoder to generate different enable signal outputs to achieve the configuration of the redundancy mode or the single-group activation mode. When the control signal is at a low level, the enable control module is in the single-group activation mode, and the external enable signals (EN[0:31]) drive the enable signals of all flip-flops one-to-one (EN[0] corresponds to flip-flop 0, and so on, EN

[31] corresponds to flip-flop 31), and data is input through the D terminal of the flip-flop and shifted and transmitted step by step under the drive of the clock. When the control signal is at a high level, the enable control module is configured in the redundancy mode, and the enable signals of the enable control module are dynamically allocated to multiple groups through the address decoder. For example, the EN[0] signal is connected to Figure 3 the E0 signal in, activating the master flip-flop (such as trigger 0) and the backup flip-flop (such as flip-flop 16) to work simultaneously, corresponding to each other in pairs to form a group, achieving synchronous writing of the same data, and forming a double-copy redundant storage. The reset signal (RST) forces all enable signals to be set to zero to ensure that the system initialization state is controllable.

[0028] Specifically, such as Figure 3As shown, the core structure of the shift register circuit is that multiple stages of flip-flops are connected end to end in a cascaded manner to form a configurable shift register array, which is used to implement the function of transmitting data bit by bit. It has serial loading and segmented control functions, and is suitable for flexible switching between high-speed data processing and fault tolerance performance. The specific circuit structure consists of a D flip-flop chain structure and an enable control network connected thereto. The D flip-flop chain structure is mainly composed of D flip-flops with different numbers. Each flip-flop contains a standard input terminal (D), a clock terminal (CLK), an output terminal (Q), and an enable control terminal (E). Among them, the standard input terminal is used to receive external input data; the output terminal is connected to the standard input terminal of the next-stage flip-flop, which is used to directly output data or shift and transmit data to the next-stage flip-flop under the drive of the clock; the enable control terminal is connected to a single enable terminal among the corresponding external enable signal terminals in the enable control module and the output terminal of the enable control network, which is used to receive the enable signal output by the enable control module. Specifically, the enable control network controls the activation states of different flip-flops through E0 - E15 signal lines to realize dynamic selection of the data path and facilitate the implementation of the function of information redundant storage.

[0029] More specifically, a single enable terminal at the output of the enable control network is simultaneously connected to the enable control terminals of two flip-flops, so that the flip-flops are paired up to form a group of master flip-flops and backup flip-flops. As Figure 3 shown, the master group of flip-flops includes flip-flops 0 - 15, and the backup group of flip-flops includes flip-flops 16 - 31. The D terminals of each group of flip-flops are cascaded with the Q terminals of the previous-stage flip-flops to form a serial shift link. For example, the D terminal of flip-flop 0 in the master group receives external input data, and its Q terminal outputs to the D terminal of flip-flop 1, and so on. The backup group is cascaded in the same way. The enable control terminal (E) of the flip-flop is bound to the corresponding enable signal (such as E0 controls flip-flop 0 and flip-flop 16). When the enable signal is valid, data is input from the first-stage flip-flop and transmitted step by step. In the redundant mode, the master and backup groups of flip-flops receive data synchronously and store independently. The master and backup groups shift in parallel, and data is synchronously written into the master and backup flip-flops of the same group through the same enable signal (such as E0). Any single event upset only affects a single group of shift registers (such as flip-flop 0 being abnormal), and the other group (flip-flop 16) still maintains data integrity.

[0030] Specifically, as Figure 4 shown, the output control selection module includes a control selector and an error judgment module. The data output terminal of the shift register circuit is simultaneously connected to the control selector and the error judgment module; when in the single-group activation mode, the error judgment module is turned off, and the control selector directly outputs the data output by the shift register circuit; when in the redundant mode, the control selector is turned off, and the error judgment module compares the data output by the master flip-flop and the backup flip-flop in real time. If the data is consistent, the current valid group data is output; if the data is inconsistent, no data is output.

[0031] Specifically, the output control selection module switches the data output path by means of a selection enable signal (SELEN) (for example, selects Q0 - Q15 or Q0 - Q31 as the currently valid output segment). The selection enable signal is connected to the control selector and the error judgment module respectively. When in the single - group activation mode, the selection enable signal remains high, thereby activating the control selector and turning off the error judgment module; when in the redundant mode, the selection enable signal remains low, thereby activating the error judgment module and turning off the control selector.

[0032] Specifically, the error judgment module includes a plurality of exclusive - OR gate circuits and a plurality of two - to - one selectors. The output terminals of the master flip - flop and the backup flip - flop in the same group are connected to the same exclusive - OR gate circuit. The output terminal of each master flip - flop is connected to a two - to - one selector, and the exclusive - OR gate circuit and the two - to - one selector connected to the output terminal of the same master flip - flop are interconnected. When in the redundant mode, the exclusive - OR gate circuit compares the data output by the master flip - flop and the backup flip - flop in real time. If the data is consistent, the two - to - one selector outputs the data output by the master flip - flop. If the data is inconsistent, the output signal of the two - to - one selector is turned off.

[0033] Furthermore, the exclusive - OR gate circuit combines the error indication signal to verify the state of the flip - flop: if a single - event upset or timing deviation is detected, the error - correction mechanism is immediately triggered to ensure data integrity. Specifically, the exclusive - OR gate circuit controls the state of the two - to - one selector through its output error indication signal; if the data is consistent, the error indication signal remains low, and the two - to - one selector outputs the data output by the master flip - flop; if the data is inconsistent, the error indication signal remains high, and the output signal of the two - to - one selector is turned off. If the data is consistent, the error indication signal is also transmitted to the upper - level processor, and the upper - level processor controls the discarding of the error data and re - sends the relevant correct data to the standard data input terminal of the corresponding flip - flop.

[0034] The working process of the output control selection module is as follows: After the SELEN signal is decoded, the currently valid flip - flop group is selected and the result is output (such as Q0 - Q15 in the redundant mode or Q0 - Q31 in the single - group activation mode), and the Q - end data of the corresponding flip - flop is output to the downstream circuit. If the circuit is in the single - group activation mode, the SELEN signal remains high. As the enable terminal of the control selector, it turns on the control selector, and the exclusive - OR gate circuit for comparison is not activated, and Q0 - Q31 is output; when the circuit is in the redundant mode, the SELEN signal remains low, the control selector is turned off, and the exclusive - OR gate circuit is activated through the SELEN signal to compare the redundant data output by the master and backup group flip - flops in real time (such as Q0 and Q16). If the data is consistent, the error indication signal remains low, and the data of the currently valid group is output; if inconsistency is detected (such as the states of Q0 and Q16 are abnormal, such as Figure 4As shown by the "error indication signal 1" and "error indication signal 16" in [reference], the error indication signal is transmitted to the upper processor, indicating that data is in error at that time. The upper processor recognizes the error and performs further processing, such as controlling the discarding of data and retransmitting relevant data to restore its correct state. At the same time, the error indication signal serves as the enabling signal for the multiplexer. When the error indication signal is at a low level, the data output by the main group flip-flop (such as Q0) of the multiplexer is output. If the error indication signal is at a high level, the multiplexer will not output any value until the system value is restored and the system operates normally.

[0035] In summary, the overall working process of the above-mentioned hardened shift register circuit structure against single-event upsets is divided into three stages: the initialization stage, where the reset signal of the enabling control module clears all flip-flops (such as the initial states of each group of flip-flops in [reference]), the enabling control module is configured in the redundant mode or the single-group activation mode, and the main and backup group flip-flops are synchronously loaded with the initial data. Figure 3 During the normal operation stage, the control signal of the enabling control module is switched to the single-group activation mode, that is, all enabling signals are connected to EN[0:31], and each flip-flop is enabled by a separate enabling signal. The data is shifted and transmitted as needed, and the error comparison logic does not work. When the task needs to operate in the redundant mode, it is configured in the redundant mode. In this stage, after an error is detected, the XOR gate circuit triggers the error indication signal to prompt that there is an error in the register chain of the upper processor. The multiplexer will turn off the signal output through the error indication signal. At the same time, after the upper processor recognizes the error, it turns off the enabling of the non-faulty flip-flops, holds the data in the relevant flip-flops, then turns on the enabling signal of the faulty flip-flop, rewrites the correct data, and after completing the error recovery, turns on the signal enabling, and the register chain continues to operate normally. This design realizes efficient fault tolerance while reducing the hardware overhead through dynamic enabling control, redundant data synchronous writing, and intelligent switching mechanisms, and is applicable to high-reliability application scenarios.

[0036] Obviously, those skilled in the art can make various changes and modifications to this technical solution without departing from the spirit and scope of this technical solution. Thus, if these modifications and variations of this technical solution fall within the scope of the claims of this technical solution and its equivalent technologies, then this technical solution is also intended to include these changes and modifications.

Claims

1. An anti-single event upset shift register reinforcement circuit structure, characterized in that Including: An enable control module, a shift register circuit, and an output control selection module; wherein, The enable control module is used to form different enable signals through decoding of an external address signal terminal according to an external control and enable signal, so as to be configured into different enable modes, and the enable modes include a redundant mode or a single-group activation mode; The shift register circuit is a configurable shift register array composed of multi-stage flip-flops. When in the single-group activation mode, the enable signal drives all flip-flops one by one, and data is shifted and transmitted step by step in the shift register circuit; when in the redundant mode, the flip-flops are paired two by two to form a group of master flip-flops and backup flip-flops, and the enable signal drives each group of master flip-flops and backup flip-flops to work simultaneously, so that the same data is synchronously written into the master flip-flops and backup flip-flops to form a dual-copy redundant storage; The output control selection module is used to monitor the data flow state of the shift register circuit in real time and perform logical judgment; when in the single-group activation mode, the output control selection module directly outputs the data output by the shift register circuit; when in the redundant mode, the output control selection module compares the data output by the master flip-flops and backup flip-flops in real time. If the data is consistent, the current valid group of data is output. If the data is inconsistent, no data is output.

2. The anti-single event upset shift register reinforcement circuit structure according to claim 1, characterized in that A clock signal terminal, a reset signal terminal, a control signal terminal, an external enable signal terminal, an address signal terminal, and an enable control network output terminal are arranged on the enable control module, and an address decoder is included in the enable control module; after receiving the clock signal, the reset signal, and the control signal, the enable control module selects the address signal terminal through the address decoder to generate different enable signals for output, so as to realize the configuration of the redundant mode or the single-group activation mode.

3. The anti-single event upset shift register hardening circuit structure according to claim 2, wherein When the control signal is at a low level, the enable control module is configured into the single-group activation mode. When the control signal is at a high level, the enable control module is configured into the redundant mode.

4. The anti-single event upset shift register reinforcement circuit structure according to claim 2, characterized in that Each flip-flop includes a standard input terminal, a clock terminal, an output terminal, and an enable control terminal, wherein, The standard input terminal is used to receive external input data; The output terminal is connected to the standard input terminal of the next-stage flip-flop, and is used to directly output data or shift and transmit the data to the next-stage flip-flop under the drive of a clock; The enable control terminal is connected to a single enable terminal among the corresponding external enable signal terminal and the enable control network output terminal in the enable control module, and is used to receive the enable signal output by the enable control module.

5. The anti-single event upset shift register hardening circuit structure according to claim 4, wherein The single enable terminal of the enable control network output terminal is simultaneously connected to the enable control terminals of two flip-flops, so that the flip-flops are paired two by two to form a group of master flip-flops and backup flip-flops.

6. The anti-single event upset shift register reinforcement circuit structure according to claim 1, characterized in that The output control selection module includes a control selector and an error judgment module, and the data output terminal of the shift register circuit is simultaneously connected to the control selector and the error judgment module; When in the single-group activation mode, the error judgment module is turned off, and the data output by the shift register circuit is directly output by the control selector; when in the redundant mode, the control selector is turned off, and the error judgment module compares the data output by the master flip-flop and the backup flip-flop in real time. If the data is consistent, the current valid group data is output; if the data is inconsistent, no data is output.

7. The anti-single event upset shift register reinforcement circuit structure according to claim 6, characterized in that The output control selection module switches the data output path through the selection enable signal. The selection enable signal is respectively connected to the control selector and the error judgment module. When in the single-group activation mode, the selection enable signal remains high level, thereby activating the control selector and turning off the error judgment module; when in the redundant mode, the selection enable signal remains low level, thereby activating the error judgment module and turning off the control selector.

8. The anti-single event upset shift register reinforcement circuit structure according to claim 6, characterized in that The error judgment module includes a plurality of exclusive-OR gate circuits and a plurality of two-to-one selectors. The output terminals of the master flip-flop and the backup flip-flop in the same group are connected to the same exclusive-OR gate circuit. The output terminal of each master flip-flop is connected to a two-to-one selector, and the exclusive-OR gate circuit and the two-to-one selector connected to the output terminal of the same master flip-flop are connected to each other; When in the redundant mode, the exclusive-OR gate circuit compares the data output by the master flip-flop and the backup flip-flop in real time. If the data is consistent, the data output by the master flip-flop is output by the two-to-one selector; if the data is inconsistent, the output signal of the two-to-one selector is turned off.

9. The anti-single event upset shift register reinforcement circuit structure according to claim 8, characterized in that The exclusive-OR gate circuit controls the state of the two-to-one selector through the error indication signal output by it; if the data is consistent, the error indication signal remains low level, and the data output by the master flip-flop is output by the two-to-one selector; if the data is inconsistent, the error indication signal remains high level, and the output signal of the two-to-one selector is turned off.

10. The anti-single event upset shift register reinforcement circuit structure according to claim 9, characterized in that, If the data is consistent, the error indication signal is also transmitted to the upper processor, and the upper processor controls to discard the error data and retransmit the relevant correct data to the standard data input terminal of the corresponding flip-flop.

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