Frequency set point function test method, device, equipment and medium

Abstract

The present application relates to the field of testing technology, and more particularly to a method, apparatus, device, and medium for testing a frequency set point function. The method comprises: setting a target memory to use a first frequency setting operating point, writing a binary data array into a target storage unit in the target memory; setting the target memory to use a second frequency setting operating point, reading data from the target storage unit to obtain first read data, and writing the binary data array into the storage unit; setting the target memory to use the first frequency setting operating point, again reading data from the target storage unit to obtain second read data; and determining a test result based on the first read data, the second read data, and a preset expected read data. Thus, the present application can solve the problem of slow speed and poor timeliness of frequency set point function testing methods in memory chips.

Description

Technical Field

[0001] The present application relates to the field of testing technology, and in particular to a frequency set point function testing method, device, equipment and medium. Background Art

[0002] The Frequency Set Point (FSP) feature allows memory chips to maintain normal operation after changing key parameters without requiring new training. With FSP enabled, LPDDR (Low Power Double Data Rate SDRAM) can switch its command bus (CA bus) between two different operating frequencies based on voltage swings and termination resistances.

[0003] In the prior art, the test method for the frequency set point function in the memory chip has high test time complexity and is difficult to meet the timeliness requirements of mass production testing. Summary of the Invention

[0004] In view of this, the embodiments of the present application provide a frequency set point function test method, device, equipment and medium, which can effectively solve the problems of slow speed and poor timeliness of the frequency set point function test method in the memory chip.

[0005] In a first aspect, an embodiment of the present application provides a frequency set point function testing method, comprising:

[0006] Enabling read and write functions of a first group of mode registers in a target memory, setting the target memory to use a first frequency setting operating point, and writing a binary data array into a target storage unit in the target memory;

[0007] enabling read and write functions of a second set of mode registers in the target memory, setting the target memory to use a second frequency setting operating point, reading data in the target storage unit to obtain first read data, and writing the binary data array into the storage unit;

[0008] Enabling the read and write functions of the first group of mode registers in the target memory, setting the target memory to use a first frequency setting operating point, and reading the data in the target storage unit again to obtain second read data;

[0009] A test result is determined according to the first read data, the second read data, and preset expected read data.

[0010] In some embodiments, before enabling the read and write functions of the first set of mode registers in the target memory, setting the target memory to use a first frequency setting operating point, and writing the binary data array into the target storage unit in the target memory, the method further includes:

[0011] Initializing and setting each group of mode registers specifically includes: when the target memory is powered on and the target memory is set to use a first frequency setting operating point, setting the first group of mode registers using first parameter data;

[0012] During the power-on process of the target memory, and when the target memory is set to adopt a second frequency setting operating point, the second group of mode registers is set using second parameter data.

[0013] In some embodiments, the method further includes: setting an operating point using a frequency adopted by the target memory, encapsulating codes corresponding to initializing and setting each group of mode registers, thereby obtaining a first sub-vector module and a second sub-vector module; setting the first group of mode registers using the first sub-vector module; and setting the second group of mode registers using the second sub-vector module.

[0014] In some embodiments, enabling the read and write functions of the first group of mode registers in the target memory and setting the target memory to use a first frequency setting operating point includes:

[0015] During power-on of the target memory, first configuration data is written into a target register in the target memory through a register write instruction to implement setting an operating point using the first frequency and enabling read and write functions of the first group of mode registers, and executing an impedance calibration command and a latch command on the target memory;

[0016] The enabling of the read and write functions of the second group of mode registers in the target memory and setting the target memory to adopt a second frequency setting operating point includes:

[0017] During the power-on process of the target memory, the second configuration data is written into the target register in the target memory through a register write instruction to realize the use of the second frequency to set the operating point and enable the read and write functions of the second group of mode registers, and execute the impedance calibration command and the latch command on the target memory.

[0018] In some embodiments, the first configuration data and the second configuration data both include: an operation code for enabling frequency setting point read and write functions, an operation code for controlling the switching frequency setting operating point, and an operation code for setting the reference voltage pin level.

[0019] In some embodiments, reading the data in the target storage unit includes:

[0020] Using automatic test equipment to measure the level of each data input and output pin on the target memory data bus;

[0021] The determining a test result according to the first read data, the second read data, and preset expected read data includes:

[0022] The levels of each digit in the first read data and the second read data are compared with a reference level respectively; if they are lower than the reference level, a first result is obtained, and if they are higher than the reference level, a second result is obtained; wherein the expected read data includes the reference level of the corresponding digit, and the reference level is determined by the power supply voltage.

[0023] In some embodiments, the test frequency corresponding to the first frequency setting operating point is 3200 Mbps; the test frequency corresponding to the second frequency setting operating point is 4266 Mbps.

[0024] In a second aspect, an embodiment of the present application provides a frequency set point function testing device, comprising:

[0025] a data writing module, configured to enable read and write functions of a first group of mode registers in a target memory, set the target memory to adopt a first frequency setting operating point, and write a binary data array into a target storage unit in the target memory;

[0026] a data reading and writing module, configured to enable the reading and writing functions of the second group of mode registers in the target memory, set the target memory to adopt a second frequency setting operating point, read the data in the target storage unit to obtain first read data, and write the binary data array into the storage unit;

[0027] a data reading module, configured to enable the read and write functions of the first group of mode registers in the target memory, set the target memory to operate at the first frequency setting operating point, and read the data in the target storage unit again to obtain second read data;

[0028] A test result determination module is used to determine a test result according to the first read data, the second read data and preset expected read data.

[0029] In a third aspect, an embodiment of the present application provides a terminal device, comprising a processor and a memory, wherein the memory stores a computer program, and the processor is configured to execute the computer program to implement a frequency set point function test method provided in the first aspect of the present application.

[0030] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium storing a computer program. When the computer program is executed on a processor, it implements a frequency set point function test method provided in the first aspect of the present application.

[0031] The embodiments of the present application have the following beneficial effects:

[0032] The present application enables the read and write functions of the first set of mode registers in the target memory, sets the target memory to use a first frequency setting operating point, and writes a binary data array to a target storage unit in the target memory; enables the read and write functions of the second set of mode registers in the target memory, sets the target memory to use a second frequency setting operating point, reads the data in the target storage unit to obtain first read data, and writes the binary data array to the storage unit; enables the read and write functions of the first set of mode registers in the target memory, sets the target memory to use the first frequency setting operating point, reads the data in the target storage unit again to obtain second read data; and determines a test result based on the first read data, the second read data, and the preset expected read data. The present application enables the corresponding mode register group at one frequency setting operating point and writes data to the storage unit, and enables another mode register group at another frequency setting operating point and reads the data in the storage unit. The test result is obtained by comparing the expected read data with the read data to verify whether the data is damaged by frequency switching. The implementation method of the present application is simple, the test speed is fast, and the applicability is relatively high. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 A schematic diagram of the structure of a replicable mode register involved in the frequency set point function test method according to an embodiment of the present application is shown;

[0035] Figure 2 Another schematic diagram of parameter settings of a replicable mode register in a frequency set point function test method according to an embodiment of the present application is shown;

[0036] Figure 3 A flow chart showing a frequency set point function test method according to an embodiment of the present application is shown;

[0037] Figure 4A data schematic diagram of a binary data array involved in the frequency set point function test method according to an embodiment of the present application is shown;

[0038] Figure 5 A structural schematic diagram of a frequency setting point function testing device according to an embodiment of the present application is shown.

[0039] Description of main component symbols:

[0040] 510 - data writing module; 520 - data reading and writing module; 530 - data reading module; 540 - test result determination module. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0042] The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but rather merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.

[0043] Hereinafter, the terms "including", "having" and their cognates used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the aforementioned items, and should not be understood as excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the aforementioned items or adding the possibility of one or more features, numbers, steps, operations, elements, components or combinations of the aforementioned items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and should not be understood as indicating or implying relative importance.

[0044] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as in the context of the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present application.

[0045] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0046] The present application provides an automatic testing system. Exemplarily, the automatic testing system includes an automatic testing device and a target memory. The automatic testing device is communicatively connected to the target memory to automatically test the target memory. The target memory includes a replicable mode register and a memory cell. The target memory includes, but is not limited to, LPDDR4.

[0047] Frequency Set Point (FSP) is a new media feature introduced with LPDDR4. It allows memory chips to maintain normal operation after switching key parameters without requiring new training. Enabling FSP allows LPDDR to switch between two different operating frequencies of the CA bus as voltage swings and termination resistors change. When parameters such as supply voltage, termination resistors, and register data change, the memory chip requires new training to ensure the accuracy of the drive frequency and data sampling points during testing, preventing the chip from being left in an untrained state and potentially losing communication with the host controller. Enabling FSP allows the memory chip to operate normally by copying all CA bus mode register parameters, as well as other mode registers that change with the operating frequency, eliminating the need for new training. Changing the FSP-WR bit allows the MR (Mode Register) parameters to be changed for an alternate frequency set point without affecting current operation. Once all necessary parameters are written to the alternate set point, changing the FSP operation bit switches operation to use all new parameters simultaneously (within tFC), eliminating the possibility of communication loss caused by partial configuration changes. Here, tFC is the transition time, which refers to the time required from the FSP operation bit (FSP-OP) changing to the new frequency set point taking full effect. Furthermore, tFC is a timing parameter related to DRAM chip operation, specifically representing the delay time during the FSP (frequency set point) switching process. It is a critical time constraint to ensure the proper functioning of the FSP function. The replicable mode register has two sets of physical registers. Assume that they are Group A (the first set of mode registers) and Group B (the second set of mode registers). Figure 1 As shown in FIG. 1 , the registers that can be copied are mode registers MR1, MR2, MR3, MR11, MR12, MR14, and MR22. These copied registers use the same mode register address.

[0048] The frequency set point function testing method in this embodiment primarily includes four steps: mode register initialization, frequency point storage sequence design, memory matrix test algorithm, and test result data analysis. In this embodiment, the frequency set point (FSP) enables the CA bus to switch between two different operating frequencies as voltage and impedance matching change. For example, the first frequency set point corresponds to an operating frequency of 3200 Mbps; the second frequency set point corresponds to an operating frequency of 4266 Mbps.

[0049] The frequency setting point function test method is described below with reference to some specific embodiments.

[0050] Exemplarily, the frequency set point function test method includes the following steps:

[0051] S000, mode register initialization.

[0052] In the present embodiment, read / write access to each set of mode registers is controlled by bit FSP-WR (Frequency Set Point Write / Read) of mode register 13 (abbreviated as MR13), and the operating point is controlled by bit FSP-OP (Frequency Set Point Operation Mode) of MR13. Exemplarily, MR13 includes eight data bits, namely OP[0]-OP[7].

[0053] For FSP-OP operation, FSP-OP stands for frequency setting operating point. It is mainly enabled by MR13 OP[7], and the data bit defaults to 0. DRAM (Dynamic Random Access Memory) uses mode register N to set FSP operation [0], that is, the mode register of group A is switched to frequency point 0 (the first frequency setting operating point). If the data bit of MR13OP[7] is written to 1, DRAM uses mode register N to set FSP operation [1], that is, the mode register of group B is switched to frequency point 1 (the second frequency setting operating point). When FSP-OP changes from 0 to 1, the reference voltage pin (VRCG) must change from normal current to high current. This operation is achieved by setting MR13 OP[3] to 1. When FSP-OP changes from 1 to 0, VRCG must change from high current to normal current. This operation is achieved by setting MR13 OP[3] to 0.

[0054] Among them, in the FSP-WR operation, FSP-WR stands for frequency set point read / write. It is mainly enabled by MR13 OP[6]. The data bit defaults to 0. The data is written to the mode register N of FSP operation[0] through the MRW command, that is, the mode register of group A is written. If the data bit of MR13 OP[6] is written to 1, the data is written to the mode register N of FSP operation[1] through the MRW command, that is, the mode register of group B is written. The MRW (Mode Register Write) instruction is a command used to write data to the mode register. The mode register is an important component used to store and configure the working parameters of the memory chip. Through the MRW instruction, these parameters can be flexibly set and modified to meet different working requirements.

[0055] Initialize each group of mode registers, including:

[0056] S010 , during a power-on process of the target memory, and when the target memory is set to operate at a first frequency setting operating point, a first set of mode registers is set using first parameter data.

[0057] S020 , during the power-on process of the target memory, and when the target memory is set to operate at a second frequency setting operating point, use second parameter data to set a second group of mode registers.

[0058] For example, this application mainly uses 3200 / 4266Mpbs to complete the fixed-point frequency switching verification, such as Figure 2 As shown in the figure, during the target memory power-up process, the corresponding parameters of the mode registers MR1, MR2, MR3, MR11, MR12, MR14, and MR22 are set to D1A, D1B, D1C, D1E, D1F, D1G, and D1H, respectively, at a test frequency of 3200 Mbps. At a test frequency of 4266 Mbps, the corresponding parameters of the mode registers are set to D2A, D2B, D2C, D2E, D2F, D2G, and D2H. This operation configures the timing and characteristic parameters according to the chip datasheet during the particle's power-up process. By writing the corresponding frequency register using the MRW instruction, this sequence can be defined at the ATE code level and instantiated as the sub-vector module MRSET.

[0059] As can be understood, based on the target memory's operating point frequency, the code for initializing each set of mode registers is packaged separately, resulting in a first sub-vector module MRSET1 and a second sub-vector module MRSET2. The first sub-vector module is used to set the first set of mode registers, while the second sub-vector module is used to set the second set of mode registers.

[0060] The mode register 13 (abbreviated as MR13) of this application includes 8 digits, namely OP[0]-OP[7]. Among them, OP[7] is used to control the selection of the frequency setting operating point to be used, and OP[6] is used to control which group of mode registers to read and write. OP[7]=0 means that the first frequency setting operating point is used, and the corresponding test frequency is 3200Mbps; OP[6]=0 means that the read and write functions of the first group of mode registers are enabled. The following describes the control method for switching the frequency setting operating point and the control method for enabling the read and write functions of each group of mode registers:

[0061] Step 1: Write #00 (corresponding to binary 00000000) to mode register 13. The data on each digit is shown in Table 1. After the particle receives a similar master control signal from ATE, it writes the configuration via MRW, thereby selecting group A mode registers and switching to frequency point 0. This step is equivalent to the frequency information storage stage of 3200.

[0062] Table 1 Digits in MR13 (I)

[0063]

[0064] Step 2: Store the frequency information of 3200 into the mode register of group A. Therefore, the write operation can be completed in sequence through the initialization setting sub-vector module MRSET1, strictly set to the default value that matches the current frequency. At this time, after the MRSET1 module completes the configuration of the mode register of group A, the 3200 frequency point information is stored.

[0065] Step 3: Execute the ZQCAL and ZQLatch commands, and the memory chip (target memory) completes data calibration and latching. In LPDDR4 chips, the ZQCAL and ZQLatch commands are commonly used for data calibration and latching. Specifically, the ZQCAL command is used for impedance calibration. The output driver of the LPDDR4 chip needs to adjust its impedance based on external conditions (such as temperature and voltage) to ensure signal transmission quality. The ZQCAL command triggers the chip to automatically adjust impedance parameters to ensure signal integrity. The ZQLatch command is used to latch the calibrated impedance parameters. After calibration is complete, the ZQLatch command fixes the calibrated impedance value for subsequent read and write operations.

[0066] Step 4: Storing the frequency point information for 4266 is similar to Steps 1-2. Switch the data in MR13 to #C8 (corresponding to 11001000 in binary). The write configuration uses the B group mode registers, frequency point 1. Note that when switching frequency point 0 to 1, VRCG must be set high simultaneously. The data written to MR13 is shown in Table 2. OP[7] = 0 indicates that the first frequency setting operating point is used, corresponding to a test frequency of 3200 Mbps. OP[6] = 0 indicates that the read and write functions of the first group of mode registers are enabled.

[0067] Table 2: Digits in MR13 (II)

[0068]

[0069] Step 5: After completing the 4266 frequency configuration, execute the ZQCAL and ZQLatch commands. The memory chip (target memory) completes data calibration and latching.

[0070] The frequency setting point function testing method of the embodiment of the present application is described below based on the above-mentioned control method for switching the frequency to set the operating point and the control method for enabling the read and write functions of each group of mode registers.

[0071] Figure 3 A flow chart of a frequency set point function test method according to an embodiment of the present application is shown. Exemplarily, the frequency set point function test method includes the following steps:

[0072] S100 , enabling the read and write functions of a first group of mode registers in a target memory, setting the target memory to adopt a first frequency setting operating point, and writing a binary data array into a target storage unit in the target memory.

[0073] S200 , enabling the read and write functions of the second set of mode registers in the target memory, setting the target memory to adopt a second frequency setting operating point, reading data in the target storage unit to obtain first read data, and writing the binary data array into the storage unit.

[0074] S300 , enabling the read and write functions of the first group of mode registers in the target memory, setting the target memory to operate at a first frequency setting working point, and reading the data in the target storage unit again to obtain second read data.

[0075] S400 , determining a test result according to the first read data, the second read data, and preset expected read data.

[0076] The present application has no restrictions on the reading and writing order of the first group of mode registers and the second group of mode registers. Data is written at one frequency setting operating point and data is read at another frequency setting operating point.

[0077] In one embodiment, enabling the read and write functions of a first group of mode registers in a target memory and setting the target memory to use a first frequency setting operating point includes:

[0078] During the target memory power-up process, a register write instruction is used to write first configuration data to a target register within the target memory, thereby adopting a first frequency setting operating point and enabling read and write functions of a first set of mode registers. Furthermore, an impedance calibration command and a latch command are executed on the target memory. For example, the ZQCAL command (impedance calibration command) and the ZQLatch command (latch command) are executed to complete data calibration and latching. Then, after the target memory power-up is complete, the binary data array is written to the target memory cell within the target memory.

[0079] Enabling the read and write functions of the second set of mode registers in the target memory and setting the target memory to adopt the second frequency setting operating point includes:

[0080] During the target memory power-up process, a register write instruction is used to write second configuration data to a target register within the target memory, thereby adopting a second frequency setting operating point and enabling read and write functions of a second set of mode registers. Furthermore, an impedance calibration command and a latch command are executed on the target memory. For example, the ZQCAL command (impedance calibration command) and the ZQLatch command (latch command) are executed to complete data calibration and latching. Subsequently, after the target memory power-up is complete, the binary data array is written to the target memory cell within the target memory.

[0081] It can be understood that the target register includes multiple data bits; the first and second configuration data both include: an opcode enabling the frequency setpoint read / write function, an opcode controlling the switching frequency setting operating point, and an opcode setting the reference voltage pin voltage level. The opcode enabling the frequency setpoint read / write function (corresponding to binary 0 / 1) controls the read / write function of the first or second set of mode registers; the opcode controlling the switching frequency setting operating point (corresponding to binary 0 / 1) controls the selection of the first or second frequency setting operating point. The opcode setting the reference voltage pin voltage level (corresponding to binary 0 / 1) controls the reference voltage pin voltage level. The target register is MR13, the first configuration data is #00, and the second configuration data is #C8.

[0082] In one embodiment, reading data in a target storage unit includes:

[0083] The voltage levels of each data input and output pin (DQ pin) on the target memory data bus are acquired by automated test equipment. For example, ATE acquires the high and low voltage levels of each DQ pin on the target memory data bus.

[0084] Determining a test result based on the first read data, the second read data, and the preset expected read data includes:

[0085] The levels of each digit in the first read data and the second read data are compared with the reference level respectively; if they are lower than the reference level, a first result is obtained, and if they are higher than the reference level, a second result is obtained; wherein, the expected read data includes the reference level of the corresponding digit, and the reference level is determined by the power supply voltage.

[0086] For example, the voltage level of each bit in the first read data is compared with a reference voltage level. Set the reference voltage level to 0.5*VDDQ. If the value of the bit in the first read data is lower than the reference voltage level, it is judged as "0"; if it is higher than the reference voltage level, it is judged as "1." Therefore, by comparing the collected data bits, if they do not match, it is judged as a failure; if they match, it is judged as a pass.

[0087] The following describes the frequency set point function test method of this application based on LPDDR4:

[0088] S510, configure the test environment. Ensure the ATE equipment is properly connected, check the power supply and signal integrity. Set the room temperature to 27°C and humidity to 50%, avoiding any environmental interference.

[0089] S520, loading the test program. Load the test program into the ATE system to ensure that the program can execute FSP-related commands.

[0090] S530: Initialize memory control parameters.

[0091] Set basic memory control parameters such as address mapping, timing configuration, and voltage settings; ensure that the selected initial frequency meets the LPDDR4 specifications.

[0092] S540, at a test frequency of 3200Mbps, uses a register write instruction to write #00 (binary 00000000) to the MR13 register during the target memory power-up process to configure it. This is a call to the A group mode register. When the target memory is powered on and stable, a binary data array is written to the memory cell at a frequency of 3200. The binary data array format is as follows: Figure 4 shown.

[0093] At S550, at a test frequency of 4266 Mbps, during the target memory power-up process, a register write instruction is used to write #C8 to the MR13 mode register for configuration. This is a call to the group B mode register. After the target memory is powered on and stabilized, a read operation is performed at a frequency of 4266 Mbps to read the data within the memory cell, obtaining the first read data.

[0094] At S560, at a test frequency of 4266 Mbps, during the target memory power-up process, a register write instruction is used to write register #C8 to register MR13 for configuration, i.e., to call registers in group B. After the target memory is powered on and stabilized, a write operation is performed at a test frequency of 4266 Mbps to write the binary data array to the memory cells.

[0095] At S570, at a test frequency of 3200 Mbps, during the target memory power-up process, a register write instruction is used to write #00 to the MR13 mode register for configuration. This is a call to the group A mode register. After the target memory stabilizes after power-up, a read operation is performed at a frequency of 3200 Mbps to read the data within the memory cell, obtaining the second read data.

[0096] S580 , comparing the first read data with the expected data, and comparing the second read data with the expected data, to obtain a result of whether the test passes.

[0097] In the prior art, mode registers are usually used for static configuration (such as fixed frequency / voltage), while this application simulates frequency hopping in real scenarios by dynamically switching MR groups. In this application, the first time: the first frequency (first frequency setting operating point) is written → the second frequency (second frequency setting operating point) is read to detect the residual interference of high-frequency data at low frequency; the second time: the first frequency is restored → read again to verify whether the data is damaged by frequency switching. This application can not only accurately locate transient data errors caused by frequency switching, but also improve test coverage, and is especially suitable for reliability verification of high-frequency memories (such as LPDDR5, HBM).

[0098] In summary, compared with the prior art, this application has the following advantages:

[0099] (1) Improved testing efficiency:

[0100] Traditional testing has high time complexity and is difficult to meet the timeliness requirements of mass production testing. The test method in this application shortens the test time by more than 40%, increases the coverage of the fault modes that can be checked, and is suitable for mass production testing.

[0101] (2) Strong compatibility:

[0102] It can be widely used in mass production testing of memory chips, quality verification of various generations of DDR and LPDDR4 / 4X / 5 / 5X, reliability evaluation, and failure analysis of memory products.

[0103] Figure 5 A schematic diagram of a frequency setting point function test device according to an embodiment of the present application is shown. Exemplarily, the frequency setting point function test device includes: a data writing module 510 , a data reading and writing module 520 , a data reading module 530 and a test result determination module 540 .

[0104] a data writing module 510 configured to enable read and write functions of a first set of mode registers in a target memory, set the target memory to use a first frequency setting operating point, and write a binary data array into a target storage unit in the target memory;

[0105] a data reading and writing module 520 configured to enable the reading and writing functions of the second set of mode registers in the target memory, set the target memory to use a second frequency setting operating point, read the data in the target storage unit to obtain first read data, and write the binary data array into the storage unit;

[0106] a data reading module 530 configured to enable the read and write functions of the first set of mode registers in the target memory, set the target memory to operate at the first frequency setting operating point, and read the data in the target memory cell again to obtain second read data;

[0107] The test result determination module 540 is configured to determine a test result according to the first read data, the second read data, and preset expected read data.

[0108] It can be understood that the device of this embodiment corresponds to the frequency setting point function testing method of the above embodiment, and the options in the above embodiment are also applicable to this embodiment, so they will not be described again here.

[0109] The present application also provides a terminal device. Exemplarily, the terminal device includes a processor and a memory, wherein the memory stores a computer program. The processor executes the computer program, thereby causing the terminal device to execute the functions of the various modules in the aforementioned frequency set point function testing method or the aforementioned frequency set point function testing apparatus. The terminal device is an automated testing device.

[0110] The processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor, etc., and can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this application.

[0111] The memory may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM). The memory is used to store computer programs, and the processor can execute the computer programs accordingly after receiving an execution instruction.

[0112] This application also provides a computer-readable storage medium for storing the computer program used in the terminal device. For example, the computer-readable storage medium may include, but is not limited to, various media capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0113] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or flowchart, and the combination of boxes in the structure diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0114] In addition, the functional modules or units in the various embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0115] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a smart phone, personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application.

[0116] The above is only a specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the scope of protection of the present application.

Claims

1. A frequency set point function test method, characterized in that: include: Enabling read and write functions of a first set of mode registers in a target memory, setting the target memory to use a first frequency to set an operating point, and writing a binary data array into a target storage unit in the target memory; wherein, enabling the read and write functions of the first set of mode registers in the target memory and setting the target memory to use the first frequency to set an operating point includes: during a power-on process of the target memory, writing first configuration data into a target register in the target memory through a register write instruction to implement the use of the first frequency to set an operating point and enable the read and write functions of the first set of mode registers, and executing an impedance calibration command and a latch command on the target memory; enabling read and write functions of a second set of mode registers in the target memory, setting the target memory to use a second frequency setting operating point, reading data in the target memory cell to obtain first read data, and writing the binary data array into the target memory cell; Enabling the read and write functions of the first group of mode registers in the target memory, setting the target memory to use a first frequency setting operating point, and reading the data in the target storage unit again to obtain second read data; A test result is determined according to the first read data, the second read data, and preset expected read data.

2. The frequency set point function test method according to claim 1, characterized in that: Before enabling the read and write functions of the first group of mode registers in the target memory, setting the target memory to use a first frequency setting operating point, and writing the binary data array into the target storage unit in the target memory, the method further includes: Initializing and setting each group of mode registers specifically includes: when the target memory is powered on and the target memory is set to use a first frequency setting operating point, setting the first group of mode registers using first parameter data; During the power-on process of the target memory, and when the target memory is set to adopt a second frequency setting operating point, the second group of mode registers is set using second parameter data.

3. The frequency set point function test method according to claim 2, characterized in that: Also includes: Based on the frequency setting operating point adopted by the target memory, the codes corresponding to initializing and setting each group of mode registers are respectively encapsulated to obtain a first sub-vector module and a second sub-vector module. The first sub-vector module is used to set the first group of mode registers; and the second sub-vector module is used to set the second group of mode registers.

4. The frequency set point function test method according to claim 1, characterized in that: The enabling of the read and write functions of the second group of mode registers in the target memory and setting the target memory to adopt a second frequency setting operating point includes: During the power-on process of the target memory, the second configuration data is written into the target register in the target memory through a register write instruction to realize the use of the second frequency to set the operating point and enable the read and write functions of the second group of mode registers, and execute the impedance calibration command and the latch command on the target memory.

5. The frequency set point function test method according to claim 4, characterized in that: The first configuration data and the second configuration data both include: an operation code for enabling the frequency setting point read and write function, an operation code for controlling the switching frequency setting operating point, and an operation code for setting the reference voltage pin level.

6. The frequency set point function test method according to claim 1, characterized in that: The reading of data in the target storage unit includes: Using automatic test equipment to measure the level of each data input and output pin on the target memory data bus; The determining a test result according to the first read data, the second read data, and preset expected read data includes: The levels of each digit in the first read data and the second read data are compared with a reference level respectively; if they are lower than the reference level, a first result is obtained, and if they are higher than the reference level, a second result is obtained; wherein the expected read data includes the reference level of the corresponding digit, and the reference level is determined by the power supply voltage.

7. The frequency set point function testing method according to any one of claims 1 to 6, characterized in that: The test frequency corresponding to the first frequency setting working point is 3200 Mbps; the test frequency corresponding to the second frequency setting working point is 4266 Mbps.

8. A frequency set point function test device, characterized in that: include: a data write module, configured to enable read and write functions of a first set of mode registers in a target memory, set the target memory to use a first frequency setting operating point, and write a binary data array into a target storage unit in the target memory; wherein, enabling the read and write functions of the first set of mode registers in the target memory and setting the target memory to use the first frequency setting operating point comprises: during power-on of the target memory, writing first configuration data into a target register in the target memory via a register write instruction, so as to adopt the first frequency setting operating point and enable the read and write functions of the first set of mode registers, and executing an impedance calibration command and a latch command on the target memory; a data reading and writing module, configured to enable the reading and writing functions of the second group of mode registers in the target memory, set the target memory to adopt a second frequency setting operating point, read the data in the target storage unit to obtain first read data, and write the binary data array into the target storage unit; a data reading module, configured to enable the read and write functions of the first group of mode registers in the target memory, set the target memory to operate at the first frequency setting operating point, and read the data in the target storage unit again to obtain second read data; A test result determination module is used to determine a test result according to the first read data, the second read data and preset expected read data.

9. A terminal device, characterized in that: The terminal device includes a processor and a memory, wherein the memory stores a computer program, and the processor is configured to execute the computer program to implement the frequency set point function test method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The computer program is stored therein, and when the computer program is executed on a processor, the computer program implements the frequency set point function test method according to any one of claims 1 to 7.

Images