Semiconductor deep silicon etching method and application thereof

Abstract

The invention discloses a semiconductor deep silicon etching method and application thereof. The semiconductor deep silicon etching method comprises the following steps: providing a structure to be etched, wherein the structure comprises a silicon structure and a silicon oxide layer; patterning etching is carried out; growing silicon oxide as a filling layer which comprises a side surface part and a bottom surface part, filling the first inner wall to form a second inner wall, and enabling the second inner wall and the bottom surface to be closer to 90 degrees; performing secondary etching to expose the silicon structure again; and forming a deep silicon etching structure by adopting a deep silicon etching process. According to the method, the opening width and the opening side wall morphology of the hard mask are adjusted by utilizing a transverse growth method, on one hand, the width of the mask opening can be accurately adjusted by controlling the transverse growth condition, and high-precision photoetching equipment is not needed; and on the other hand, the deep silicon etching quality can be remarkably improved by adjusting the shape of the side wall of the opening, and various abnormities of the deep silicon etching groove can be avoided without complex procedures and expensive equipment.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a method for deep silicon etching of semiconductors and its applications. Background Art

[0002] Micro-nano deep groove structures are widely used in semiconductor processes, but usually require high-precision lithography equipment to achieve. However, the cost differences between lithography and etching equipment with different precisions are huge. For example, the price differences of lithography machines with 0.7 / 0.3um precision are very obvious. How to use equipment with lower precision to achieve high-precision etching linewidth control is a problem worthy of research.

[0003] In addition, there are many abnormalities in the etching morphology of conventional deep groove etching processes, such as bowing (sidewall bowing) / undercut (side etching) / tapered (angle inclination), etc. In addition, the size of the scallop pattern near the opening after etching can reach about 100nm. The step coverage in subsequent processes and the tip discharge phenomenon generated during device operation seriously affect the electrical performance of the device. To solve these problems, many processes have been developed, but all use complex processes and expensive equipment to assist optimization. Thus, how to achieve deep groove etching in a more simple way and avoid defects on the groove wall is also an urgent technical problem to be solved. Summary of the Invention

[0004] Aiming at the deficiencies of the prior art, the purpose of the present invention is to provide a method for deep silicon etching of semiconductors and its applications, to solve the problems of low-cost precise control of the grooving linewidth and easy appearance of defective morphologies on the groove wall in the prior art.

[0005] To achieve the foregoing invention purpose, the technical solutions adopted by the present invention include: In a first aspect, the present invention provides a method for deep silicon etching of semiconductors, which includes: Providing a structure to be etched, the structure to be etched includes a silicon structure and a silicon oxide layer covering the surface of the silicon structure; Performing patterned etching on the silicon oxide layer in a selected area to form a first opening, the depth of the first opening reaches at least the silicon structure, the first opening has a first inner wall and a bottom surface, and the normal direction of the first inner wall forms a first intersection angle with the normal direction of the bottom surface; Growing silicon oxide as a filling layer in the first opening by LPCVD process, the filling layer includes a side portion covering the side of the first inner wall and a bottom portion covering the bottom surface, and the side portion fills the first inner wall to form a second inner wall, the normal direction of the second inner wall forms a second intersection angle with the normal direction of the bottom surface, and the second intersection angle is closer to 90° than the first intersection angle; Perform secondary etching on the bottom surface portion to expose the silicon structure again and form a second opening; Use a deep silicon etching process to etch the silicon structure with the second opening as an etching window to form a deep silicon etching structure.

[0006] In a second aspect, the present invention also provides an application of the above semiconductor deep silicon etching method in the fields of manufacturing silicon capacitors, manufacturing memory chips, and realizing 3D packaging.

[0007] Based on the above technical solutions, compared with the prior art, the beneficial effects of the present invention at least include: The semiconductor deep silicon etching method provided by the present invention uses a lateral growth method to adjust the opening width and the sidewall morphology of the hard mask. On the one hand, it can accurately adjust the width of the mask opening by controlling the conditions of lateral growth without high-precision lithography equipment; on the other hand, it can significantly improve the quality of deep silicon etching by adjusting the sidewall morphology of the opening, and avoid various abnormalities in the deep silicon etching groove without complex processes and expensive equipment; the overall process steps are simple, suitable for batch processing, and significantly improve the cost and performance, especially in the fields of silicon capacitors / memory chips / 3D packaging, etc., which is of great significance.

[0008] The above description is only an overview of the technical solutions of the present invention. In order to enable those skilled in the art to understand the technical means of the present application more clearly and implement it according to the content of the specification, the following is described with reference to the preferred embodiments of the present invention and detailed drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of a semi-finished product structure of a part of the process of the semiconductor deep silicon etching method provided by a typical embodiment of the present invention; Figure 2 is a schematic diagram of a semi-finished product structure of another part of the process of the semiconductor deep silicon etching method provided by a typical embodiment of the present invention; Figure 3 is a schematic diagram of a semi-finished product structure of yet another part of the process of the semiconductor deep silicon etching method provided by a typical embodiment of the present invention; Figure 4 is a SEM photo of a partial cross-sectional structure of the finished product of the semiconductor deep silicon etching method provided by a typical comparative case of the present invention; Figure 5 is a SEM photo of a partial cross-sectional structure of the finished product of the semiconductor deep silicon etching method provided by a typical embodiment of the present invention; Figure 6 is a SEM photo of the overall cross-sectional structure of the finished product of the semiconductor deep silicon etching method provided by a typical embodiment of the present invention Figure 7It is a SEM photo of the scallop pattern feature near the opening of the finished deep silicon etching groove of the semiconductor deep silicon etching method provided by a typical embodiment of the present invention; Figure 8 It is a high-magnification SEM photo of the scallop pattern feature near the opening of the finished deep silicon etching groove of the semiconductor deep silicon etching method provided by a typical embodiment of the present invention; Figure 9 It is a high-magnification SEM photo of the scallop pattern feature near the opening of the finished deep silicon etching groove of the semiconductor deep silicon etching method provided by another typical embodiment of the present invention. Detailed implementation manners

[0010] In view of the deficiencies in the prior art, the inventors of this case have proposed the technical solution of the present invention through long-term research and a large number of practices. The following will further explain the technical solution, its implementation process, principle, etc.

[0011] Many specific details are set forth in the following description in order to provide a thorough understanding of the present invention. However, the present invention may be practiced in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited by the specific embodiments disclosed below.

[0012] Moreover, relational terms such as "first" and "second" are only used to distinguish one component or method step with the same name from another, and do not necessarily require or imply any actual relationship or order between these components or method steps.

[0013] An embodiment of the present invention provides a semiconductor deep silicon etching method, which includes the following steps: Provide a structure to be etched, where the structure to be etched includes a silicon structure and a silicon oxide layer covering the surface of the silicon structure; Perform patterned etching on the silicon oxide layer in a selected area to form a first opening, the depth of the first opening reaches at least the silicon structure, the first opening has a first inner wall and a bottom surface, and the normal direction of the first inner wall forms a first crossing angle with the normal direction of the bottom surface; Use the LPCVD process to grow silicon oxide in the first opening as a filling layer. The filling layer includes a side portion covering the side of the first inner wall and a bottom portion covering the bottom surface, and the side portion fills the first inner wall to form a second inner wall. The normal direction of the second inner wall forms a second crossing angle with the normal direction of the bottom surface, and the second crossing angle is closer to 90° than the first crossing angle; Perform secondary etching on the bottom portion to expose the silicon structure again, and form a second opening surrounded by the second inner wall and the surface of the silicon structure; Using a deep silicon etching process, the silicon structure is etched with the second opening as the etching window to form a deep silicon etching structure.

[0014] In the above technical solution, deep silicon etching can be performed on a silicon substrate, or on any semiconductor structure composed of other processed silicon materials. For example, when the substrate material is silicon, the etched structure can be a deep trench, a through-silicon via (TSV), or a deep blind hole in silicon, etc., which is mainly realized through photolithography + semiconductor etching processes. In the present invention, it is particularly applicable to the scale of micro-nano structures, and the main core is realized through photolithography opening, lateral growth process (LPCVD process), secondary etching, and deep silicon etching.

[0015] In the above technical solution, the lateral growth process adopted can control the CD (line width) value of the opening, and small line width openings and precise control of the line width size can be achieved without using high-precision photolithography equipment; moreover, the lateral growth process also has the function of adjusting the opening inclination angle. This is because the LPCVD process has a good step coverage rate, which can compensate for the inclined sidewall morphology of the opening, making the sidewall morphology of the second opening have better verticality, avoiding the influence of the inclined sidewall on the subsequent deep silicon etching, especially avoiding the generation of many abnormal morphologies.

[0016] For specific application cases, reference can be made to Figures 1-3 As shown in Figure 1 , the first opening is formed by using photoresist plus dry etching, and then as shown in Figure 2 , it is filled through the lateral growth process. The state after removing the thin layer of sediment at the bottom of the opening is as shown in Figure 3 , and at this time, deep silicon etching can be performed.

[0017] By this method, not only can the deposition thickness be calculated according to the required grooving line width value to adjust the deposition time or deposition conditions to control the opening size, but also the inclination angle caused by directly etching the hard mask can be repaired. This morphology is very unfavorable for the subsequent deep silicon etching, especially in etched products with structures such as deep grooves. Due to plasma etching to sidewall sputtering and electron aggregation effects, abnormal morphologies such as bowing appear on the silicon sidewalls.

[0018] In addition, in order to better achieve the functions of width control and vertical filling, the width ratio of the first opening and the second opening should be appropriately controlled. According to the width dimension of the target second opening (corresponding to the designed width of the desired deep silicon etch groove), the width dimension range of the appropriate first opening should be matched. The width of the mouth of the first opening is 1.2 - 1.4 times the bottom width within this range, and generally the average width of the first opening is about 0.6 μm wider than the second opening, such as 0.4 - 0.8 μm. After filling, a relatively vertical sidewall morphology can be formed, but it does not mean that the improvement effect cannot be achieved at all beyond this size range.

[0019] For example, if it is desired to form a deep trench with a 1um CD, the opening size of the mouth of the first opening can be 1.8um, and the opening size of the bottom can be 1.4um. The sidewall opening angle is about 83 - 85°. Through lateral growth, a relatively vertical sidewall angle morphology can be obtained. An inclined opening angle greater than 85° poses new difficulties for the process; an angle less than 83° cannot meet the subsequent process. After filling and lateral growth, an almost vertical opening morphology can usually be formed.

[0020] More specifically, in some embodiments, the average width range of the first opening can be 1 - 2 μm.

[0021] Of course, since the sidewalls of the first opening are substantially inclined, the width referred to here is the average width. Taking the trapezoidal cross-sectional shape as an example, it can be the average value of the upper opening width and the lower opening width.

[0022] A key point of the present invention lies in the LPCVD process. In some embodiments, the temperature of the LPCVD process is 700 - 900 °C, the pressure of the process gas is 0.2 - 0.5 torr, the deposition rate is 2 - 4 nm / min, and the flow rate of the process gas is 70 - 200 sccm.

[0023] In some embodiments, the process gas includes a silicon source and an oxygen source. The silicon source includes SiH2Cl2, and the oxygen source includes N2O.

[0024] In some embodiments, the volume ratio of the silicon source to the oxygen source is 1:2 to 1:4.

[0025] The feasible deposition method is not limited to this. For example, PECVD plasma vapor deposition can also be used, with TEOS source + O2 as the reaction medium, and the deposition temperature is 100 - 250 °C. The specific growth method and process conditions can be set by oneself as long as lateral growth is satisfied.

[0026] In addition, for the etching of the first opening and the bottom surface portion, conventional etching processes can be employed. For example, in some embodiments, the patterned etching and / or the secondary etching use an ICP etching process; the etching gas for the ICP etching process includes CHF3 and Ar with a volume ratio of 5:1 to 3:1, the total flow rate of the etching gas is 20 - 40 sccm, the plasma power is 600 - 1000 W, the microwave power is 300 - 500 W, and the pressure is 3 - 10 mtorr.

[0027] Of course, the specific etching process may not be limited to the scope of the above examples, as long as it can achieve equivalent functions.

[0028] As a specific example, a conventional PECVD process can be used to deposit a layer of silicon oxide on a silicon substrate or other silicon structures as a hard mask to improve the etch selectivity for silicon etching. Then, patterning is achieved through a photolithography process, which involves process steps such as spin coating, pre-baking, exposure, and development. The specific process does not need to be elaborated in detail. After patterning the photoresist layer, an ICP dry etching process for opening holes can be used to etch away the silicon oxide at the position of the first opening, exposing the silicon etching area. Then, after removing the remaining photoresist on the surface, the above-mentioned lateral growth process is carried out. And because the LPCVD process has good filling ability, a thin layer of silicon oxide will also be deposited on the bottom surface of the first opening. Therefore, in the present invention, after the lateral growth deposition of silicon oxide, an ICP secondary etching process (or other equivalent etching processes) is also required to remove the silicon oxide deposition at the bottom to re-expose the silicon body. The specific etching process and time can be appropriately adjusted to adapt to different bottom deposition thicknesses.

[0029] Regarding the deep silicon etching step, an ICP device can be used for Bosch cycle etching. In some embodiments, the deep silicon etching process includes multiple sequentially cyclic passivation stages, bombardment stages, main etching stages, and buffer stages, and the pressure for each stage is 15 - 40 mtorr; the passivation gas for the passivation step is selected from C4F8, the flow rate of the passivation gas is 200 - 100 sccm, the upper electrode power is 2000 - 3000 W, the lower electrode power is 0, and the time is 1 - 3 s; the bombardment gas for the bombardment stage is selected from SF6, the flow rate of the bombardment gas is 150 - 100 sccm, the upper electrode power is 2000 - 3000 W, the lower electrode power is 50 - 200 W, and the time is 1 - 1.5 s; the etching gas for the main etching stage is selected from SF6, the flow rate range of the etching gas is 200 - 400 sccm, the upper electrode power is 2000 - 3000 W, and the lower electrode power is 30 - 80 W; no etching gas is added in the buffer stage, the lower electrode is not loaded, and only the upper electrode power of 2000 - 3000 W is loaded, and the time is 0.1 - 0.5 s.

[0030] In the above deep silicon etching process, the pressure preferably changes gradually over time. The core of this process is the fourth step: the buffer stage, which can ensure that all the volatile substances generated during the formation of the deep trench structure are exhausted, without affecting the etching effect of the next cycle. Thus, a highly controllable topography can be achieved, and the aspect ratio can reach 50 / 1. The specific number of etching cycles is calculated according to the designed etching depth. Combining with the excellent topography and dimensional accuracy of the second opening mentioned in the previous steps, high-quality deep silicon etching trenches can be formed.

[0031] The above technical solution can mainly solve problems such as bowing (sidewall bowing), undercut (side etching), and tapered (angle inclination), and can also reduce the size of the scallops near the opening of the deep silicon trench to a certain extent. However, if a smaller scallop size is desired, a higher flatness requirement for the deep trench wall surface is needed. On the basis of the above technical solution, the present invention also provides a better implementation method, that is: In some embodiments, after the deep silicon etching process, the following steps are further included: a step of trimming the scallop topography of the inner wall near the port of the deep silicon etching trench formed by the deep silicon etching process using a steady-state etching process; the temperature of the steady-state etching process is 0 - 20°C, the etching gas is selected from fluorine-based gases, the fluorine-based gases include any one or a combination of two or more of SF6, CF4, CHF3, and C4F8, the flow rate of the etching gas is 30 - 60 sccm, the etching ICP power is 600 - 1500 W, the microwave power is 200 - 600 W, and the pressure is 2 - 10 mtorr.

[0032] The above process weakens the size of the scallop topography of the sidewall near the opening (for example, the thickness of the scallop topography in the direction perpendicular to the sidewall is 60 - 100 nm) through an additional steady-state etching process, and the roughness can reach within 20 nm, greatly improving the performance of subsequent products.

[0033] In some embodiments, the deep silicon etching method may further include, for example, a step of removing the remaining silicon oxide layer and filling layer using a wet etching process, specifically, for example, removing the remaining silicon oxide hard mask through an HF solution.

[0034] The second aspect of the embodiments of the present invention also provides applications of the above semiconductor deep silicon etching method in the fields of manufacturing silicon capacitors, manufacturing memory chips, and realizing 3D packaging.

[0035] The technical solution of the present invention will be further described in detail below through several embodiments in combination with the drawings. However, the selected embodiments are only used to illustrate the present invention and do not limit the scope of the present invention.

[0036] Comparative Example 1 This comparative example performs the etching of a silicon substrate using a conventional deep silicon etching process. The specific etching process is as follows: Openings with inclined sidewalls are directly formed in the silicon oxide hard mask; then deep holes are formed by deep silicon etching.

[0037] The experimental range of the condition parameters is as follows: Opening: Any one of SF6, CF4, and CHF3 is used as the etching gas. The flow rate of the etching gas is 20 - 50 sccm, the etching ICP power is 600 - 1500 W, the microwave power is 200 - 600 W, and the pressure is 2 - 10 mtorr.

[0038] Deep silicon etching: Simple passivation + etching cycles, without considering the relationship between the etching morphology and the gradient parameters.

[0039] Passivation step: C4F8: 100 - 200 sccm, SF6: 10 - 20 sccm, upper electrode power 1500 - 2500 W, lower electrode power 50 - 100 W; the pressure is 20 - 40 mtorr.

[0040] Etching step: SF6: 100 - 200 sccm, C4F8: 10 - 20 sccm, upper electrode power 1500 - 2500 W, lower electrode power 50 - 100 W; pressure: 20 - 40 mtorr.

[0041] The obtained typically representative samples are as Figure 4 shown. It can be found that the deep grooves have a curved necking morphology, and the quality of the deep grooves is not ideal. No matter how the process conditions are adjusted, this etching method is similar to Figure 4 the following.

[0042] Example 1 In this example, a deep trench structure with a line width CD of 0.8 μm and an aspect ratio greater than 40 / 1 is fabricated.

[0043] First, a 1.5 - μm - thick silicon oxide is deposited on the silicon substrate using a conventional PECVD process with SiH4 gas.

[0044] After the deposition of the silicon oxide hard mask layer, lithography patterning is performed to make patterns, involving processes such as photoresist coating, pre - baking, exposure, and development. The MA8 lithography machine is used, with a line width accuracy of 1 μm. The opening size of the photoresist is 1.6 μm. After the silicon oxide opening, the upper CD is close to 1.6 μm, the lower CD is 1.2 μm, and through lateral growth of 0.22 μm on one side, the final bottom CD is 0.8 μm.

[0045] After patterning, an ICP dry etching process is used to open holes. The gas mixture is CHF3 and Ar with a volume ratio of 4:1, the flow rate range is 30 sccm, the ICP etching power is 800 W, the RF power is 400 W, and the pressure is 5 mtorr.

[0046] After that, a wet process is used to remove the remaining PR mask.

[0047] Lateral growth is carried out on the inner wall of the opening, and a silicon oxide filling layer with a thickness of 100 nm is grown on both sides. The process conditions of LPCVD are as follows: temperature 800 °C, the gas is SiH2Cl2 and N2O with a volume ratio of 1:2, the gas pressure is 0.3 torr, the gas flow rate is 150 sccm, and the deposition time is 30 min.

[0048] After the hard mask growth is completed, a secondary etching process of the thin silicon oxide deposited at the bottom is carried out. The etching gas is CHF3 and Ar, the flow rate range is 35 sccm, the ICP etching power is 1000 W, the RF power is 400 W, the pressure is 6 mtorr, and the etching time is 40 s.

[0049] Then, deep etching of the silicon substrate is carried out through a deep silicon etching process, with 4 steps in a cycle. It is realized by the passivation + bombardment + main etching + buffer steps. The APC pressure during etching gradually increases from 20 mtorr to 40 mtorr. Passivation step: The passivation gas is C4F8, the flow rate is 200 sccm, the upper electrode power is 2500 W, the lower electrode power is 0, and the time ranges from 1 - 2.5 s, gradually increasing with the number of cycles; Bombardment step: The etching gas is SF6, the flow rate range is 120 sccm, the upper electrode power is 2300 W, the lower electrode power is 150 W, and the time is 1.2 s; Main etching step: The etching gas is SF6, the flow rate is 350 sccm, the upper electrode power is 3000 W, the lower electrode power is 60 W; Buffer step: No etching gas is added, the lower electrode is not loaded, only the upper electrode power is loaded: 2500 W, and the time ranges from 0.1 - 0.5 s, gradually increasing with the number of cycles. The total number of cycles is 300 rounds.

[0050] The morphology of the finally obtained sample is as Figure 5 and Figure 6 shown. It can be seen that the side walls of the deep grooves are vertical and the morphology is excellent.

[0051] Example 2 As Figure 7 and 8 shown, after magnifying and observing the opening of the deep groove (generally called "head") in the above Example 1, a wavy and serrated side wall can still be observed, which is generally called scallop morphology in the industry.

[0052] Based on Embodiment 1, in this embodiment, through one-step steady-state etching, the obvious sidewall scallop morphology within the range of the head depth of 1 - 2 μm is eliminated.

[0053] The specific steady-state etching process is as follows: using SF6 / or CF4 gas, with a gas flow rate of 40 sccm, an etching ICP power of 1000 W, an RF power of 300 W, a pressure of 6 mtorr, and an etching time of 30 S, to complete the trimming of the trench structure with smooth sidewalls, perpendicular angles, and an aspect ratio that can reach 40 / 1.

[0054] After the repair is completed, soak it in an HF solution using a wet process for 10 min to complete the removal of the silicon oxide hard mask.

[0055] The final product structure is as Figure 9 shown. It can be observed that the scallop morphology at the head has disappeared, and the remaining silicon oxide hard mask has been removed. Therefore, in this embodiment, a product with better deep trench quality is obtained.

[0056] Embodiment 3 This embodiment is generally the same as Embodiment 1, with the main difference being the adjustment of the photoresist opening size and the width size of the target deep trench. The photoresist opening width is adjusted to 1.2 μm, and the width of the target deep trench is adjusted to 0.6 μm. The corresponding filling thickness is calculated based on the difference between the two.

[0057] Using the dimensions of this embodiment, deep silicon etching trenches with equally excellent quality can still be obtained.

[0058] Embodiment 4 This embodiment is generally the same as Embodiment 1, with the main difference being the adjustment of the photoresist opening size and the width size of the target deep trench. The photoresist opening width is adjusted to 1 μm, and the width of the target deep trench is adjusted to 0.4 μm. The corresponding filling thickness is calculated based on the difference between the two.

[0059] Using the dimensions of this embodiment, deep silicon etching trenches with equally excellent quality can still be obtained.

[0060] Control Example 2 This control example is generally the same as Embodiment 1, with the main difference being that the ratio of the designed first opening and the second opening is too large, and the CD ratio of the upper and lower openings is greater than 1.4. For example, the upper CD is 1 μm and the lower CD is 0.5 μm, and the inclination angle is too large, resulting in the sidewall being unable to reach a relatively perpendicular angle, thus leading to the problem of poor deep silicon etching bowing and ultimately resulting in poor deep silicon etching trenches.

[0061] Control Example 3 This comparative example is generally the same as Example 1, and the main difference is that the ratio of the designed first opening and second opening is too small, and the CD ratio of the upper and lower openings is less than 1.2. For example, the upper CD is 1.5um and the lower CD is 1.35um. Through lateral growth, it is easy for the upper CD head to grow fast and seal easily, thus affecting the etching rate and morphology.

[0062] Example 5 This example is generally the same as Example 1, and the main difference is that the process conditions of LPCVD are adjusted as follows: temperature 700°C, gas is SiH2Cl2 and N2O with a volume ratio of 1:3, gas pressure is 0.5 torr, gas flow rate is 200 sccm, and deposition time is 20 min.

[0063] This example can still obtain deep silicon etching grooves with the same excellent quality.

[0064] Example 6 This example is generally the same as Example 1, and the main difference is that the process conditions of LPCVD are adjusted as follows: temperature 900°C, gas is SiH2Cl2 and N2O with a volume ratio of 1:4, gas pressure is 0.2 torr, gas flow rate is 70 sccm, and deposition time is 5 min.

[0065] This example can still obtain deep silicon etching grooves with the same excellent quality.

[0066] Based on the above examples and comparative examples, it can be clarified that the semiconductor deep silicon etching method provided by the embodiments of the present invention uses the method of lateral growth to adjust the opening width and the sidewall morphology of the hard mask. On the one hand, it can accurately adjust the width of the mask opening by controlling the conditions of lateral growth without high-precision lithography equipment; on the other hand, it can significantly improve the quality of deep silicon etching by adjusting the sidewall morphology of the opening, and can avoid various abnormalities in the deep silicon etching groove without complex processes and expensive equipment; the overall process steps are simple, suitable for process batch production, and significantly improve the cost and performance. It is of great significance especially in the fields of silicon capacitors / memory chips / 3D packaging, etc.

[0067] It should be understood that the above examples are only used to illustrate the technical concept and characteristics of the present invention, and their purpose is to enable those who are familiar with this technology to understand the content of the present invention and implement it accordingly, and cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit and essence of the present invention should be covered within the protection scope of the present invention.

Claims

1. A semiconductor deep silicon etching method, characterized in that, Comprising: Providing an etching structure to be etched, the etching structure to be etched including a silicon structure and a silicon oxide layer covering the surface of the silicon structure; Performing patterned etching on the silicon oxide layer in a selected area to form a first opening, the depth of the first opening reaching at least the silicon structure, the first opening having a first inner wall and a bottom surface, the normal of the first inner wall and the normal of the bottom surface forming a first intersection angle; Growing silicon oxide in the first opening as a filling layer by LPCVD process, the filling layer including a side portion covering the side of the first inner wall and a bottom portion covering the bottom surface, and the side portion filling the first inner wall to form a second inner wall, the normal of the second inner wall and the normal of the bottom surface forming a second intersection angle, the second intersection angle being closer to 90° than the first intersection angle; Performing secondary etching on the bottom portion to expose the silicon structure again, forming a second opening; Performing deep silicon etching on the silicon structure with the second opening as an etching window by deep silicon etching process to form a deep silicon etching structure.

2. The semiconductor deep silicon etching method according to claim 1, wherein The width of the mouth of the first opening is 1.2 - 1.4 times the width of the bottom.

3. The semiconductor deep silicon etching method according to claim 2, wherein The average width of the first opening is 1 - 2 μm.

4. The semiconductor deep silicon etching method according to claim 1, wherein The temperature of the LPCVD process is 700 - 900 °C, the pressure of the process gas is 0.2 - 0.5 torr, the deposition rate is 2 - 4 nm / min, and the flow rate of the process gas is 70 - 200 sccm.

5. The semiconductor deep silicon etching method according to claim 4, characterized in that The process gas includes a silicon source and an oxygen source, the silicon source includes SiH2Cl2, and the oxygen source includes N2O; And / or, the volume ratio of the silicon source to the oxygen source is 1:2 to 1:

4.

6. The semiconductor deep silicon etching method according to claim 1, wherein The patterned etching and / or secondary etching adopt ICP etching process; The etching gas of the ICP etching process includes CHF3 and Ar with a volume ratio of 5:1 to 3:1, the total flow rate of the etching gas is 20 - 40 sccm, the plasma power is 600 - 1000 W, the microwave power is 300 - 500 W, and the pressure is 3 - 10 mtorr.

7. The semiconductor deep silicon etching method according to claim 1, characterized in that The deep silicon etching process includes multiple rounds of sequentially cycled passivation stage, bombardment stage, main etching stage, and buffer stage, and the pressure of each stage is 15 - 40 mtorr; The passivation gas of the passivation step is selected from C4F8, the flow rate of the passivation gas is 200 - 100 sccm, the upper electrode power is 2000 - 3000 W, the lower electrode power is 0, and the time is 1 - 3 s; The bombardment gas of the bombardment stage is selected from SF6, the flow rate of the bombardment gas is 150 - 100 sccm, the upper electrode power is 2000 - 3000 W, the lower electrode power is 50 - 200 W, and the time is 1 - 1.5 s; The etching gas of the main etching stage is selected from SF6, the flow rate range of the etching gas is 200 - 400 sccm, the upper electrode power is 2000 - 3000 W, and the lower electrode power is 30 - 80 W; No etching gas is added in the buffer stage, the lower electrode is not loaded, only the upper electrode power of 2000 - 3000 W is loaded, and the time is 0.1 - 0.5 s.

8. The semiconductor deep silicon etching method according to claim 1, characterized in that, After the deep silicon etching process, it further includes the step of using a steady-state etching process to trim the inner wall scallop morphology near the port of the deep silicon etching groove formed by the deep silicon etching process; The temperature of the steady-state etching process is 0-20°C, the etching gas is selected from fluorine-based gases, the fluorine-based gases include any one or a combination of two or more of SF6, CF4, CHF3, and C4F8, the flow rate of the etching gas is 30-60 sccm, the etching ICP power is 600-1500 W, the microwave power is 200-600 W, and the pressure is 2-10 mtorr.

9. The semiconductor deep silicon etching method according to claim 1, wherein It further includes: The step of removing the remaining silicon oxide layer and filling layer by a wet etching process.

10. Application of the semiconductor deep silicon etching method according to any one of claims 1-9 in the fields of manufacturing silicon capacitors, manufacturing memory chips, and realizing 3D packaging.

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